Compare commits
2
Commits
| Author | SHA1 | Date | |
|---|---|---|---|
 jens
|
2818178863 | ||
|
jens
|
1e0d84d989 |
@@ -1,2 +0,0 @@
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VHDL/lib/emac/emac_jb.vhd
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@@ -1,8 +0,0 @@
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VHDL/lib/emac/sim/tb_emac_jb.fdo
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VHDL/lib/emac/sim/tb_serdes.fdo
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VHDL/lib/emac/sim/tb_emac_jb.wdo
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VHDL/lib/emac/sim/tb_serdes.wdo
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VHDL/lib/emac/sim/tb_serdes.fdo
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VHDL/lib/emac/sim/tb_serdes.wdo
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@@ -1,14 +0,0 @@
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## NOTE: Do not edit this file.
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## Autogenerated by ProjNav (creatfdo.tcl) on Thu Jul 06 20:49:07 Westeuropäische Sommerzeit 2006
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##
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vlib work
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vcom -explicit -93 "../../misc/utils_pkg.vhd"
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vcom -explicit -93 "../src/crc32.vhd"
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vcom -explicit -93 "../src/tb_crc32.vhd"
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vsim -t 1ps -lib work tb_crc32
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view wave
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do {tb_crc32.wdo}
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view structure
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view signals
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run 1 us
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@@ -1,25 +0,0 @@
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onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate -format Logic /tb_crc32/clk
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add wave -noupdate -format Logic /tb_crc32/rst
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add wave -noupdate -format Logic /tb_crc32/din_vld
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add wave -noupdate -format Literal -radix hexadecimal /tb_crc32/din
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add wave -noupdate -format Literal -radix hexadecimal /tb_crc32/crc32
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add wave -noupdate -format Logic /tb_crc32/crc32_vld
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add wave -noupdate -format Literal -radix hexadecimal /tb_crc32/test_data
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 1} {667016 ps} 0}
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configure wave -namecolwidth 150
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configure wave -valuecolwidth 100
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configure wave -justifyvalue left
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configure wave -signalnamewidth 1
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configure wave -snapdistance 10
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configure wave -datasetprefix 0
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configure wave -rowmargin 4
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configure wave -childrowmargin 2
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configure wave -gridoffset 0
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configure wave -gridperiod 100
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configure wave -griddelta 40
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configure wave -timeline 1
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update
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WaveRestoreZoom {0 ps} {1050 ns}
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@@ -1,15 +0,0 @@
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## NOTE: Do not edit this file.
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## Autogenerated by ProjNav (creatfdo.tcl) on Thu Jul 06 20:49:07 Westeuropäische Sommerzeit 2006
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##
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vlib work
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vcom -explicit -93 "../../misc/utils_pkg.vhd"
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vcom -explicit -93 "../src/piso.vhd"
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vcom -explicit -93 "../src/sipo.vhd"
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vcom -explicit -93 "../src/tb_serdes.vhd"
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vsim -t 1ps -lib work tb_serdes
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view wave
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do {tb_serdes.wdo}
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view structure
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view signals
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run 20 us
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@@ -1,58 +0,0 @@
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onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate -format Logic /tb_serdes/clk
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add wave -noupdate -format Logic /tb_serdes/rst
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add wave -noupdate -divider PiSo
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add wave -noupdate -format Logic /tb_serdes/clk
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add wave -noupdate -format Logic /tb_serdes/piso_din_vld
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add wave -noupdate -format Logic /tb_serdes/piso_din_rdy
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add wave -noupdate -format Literal /tb_serdes/piso_din_be
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add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/piso_din
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add wave -noupdate -format Logic /tb_serdes/piso_dout_vld
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add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/piso_dout
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add wave -noupdate -format Logic /tb_serdes/piso_dout_en
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add wave -noupdate -divider SiPo
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add wave -noupdate -format Logic /tb_serdes/clk
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add wave -noupdate -format Logic /tb_serdes/sipo_enable
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add wave -noupdate -format Logic /tb_serdes/sipo_rst
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add wave -noupdate -format Logic /tb_serdes/sipo_din_vld
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add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/sipo_din
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add wave -noupdate -format Logic /tb_serdes/sipo_dout_vld
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add wave -noupdate -format Logic /tb_serdes/sipo_dout_en
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add wave -noupdate -format Literal /tb_serdes/sipo_dout_be
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add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/sipo_dout
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add wave -noupdate -divider PiSo
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add wave -noupdate -format Logic /tb_serdes/clk
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add wave -noupdate -format Logic /tb_serdes/piso2_din_vld
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add wave -noupdate -format Logic /tb_serdes/piso2_din_rdy
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add wave -noupdate -format Literal /tb_serdes/piso2_din_be
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add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/piso2_din
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add wave -noupdate -format Logic /tb_serdes/piso2_dout_vld
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add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/piso2_dout
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add wave -noupdate -format Logic /tb_serdes/piso2_dout_en
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add wave -noupdate -divider SiPo
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add wave -noupdate -format Logic /tb_serdes/clk
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add wave -noupdate -format Logic /tb_serdes/sipo2_enable
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add wave -noupdate -format Logic /tb_serdes/sipo2_rst
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add wave -noupdate -format Logic /tb_serdes/sipo2_din_vld
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add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/sipo2_din
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add wave -noupdate -format Logic /tb_serdes/sipo2_dout_vld
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add wave -noupdate -format Logic /tb_serdes/sipo2_dout_en
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add wave -noupdate -format Literal /tb_serdes/sipo2_dout_be
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add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/sipo2_dout
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 1} {19757882 ps} 0} {{Cursor 2} {49999912163 ps} 0} {{Cursor 3} {49999529250 ps} 0}
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configure wave -namecolwidth 150
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configure wave -valuecolwidth 100
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configure wave -justifyvalue left
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configure wave -signalnamewidth 1
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configure wave -snapdistance 10
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configure wave -datasetprefix 0
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configure wave -rowmargin 4
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configure wave -childrowmargin 2
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configure wave -gridoffset 0
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configure wave -gridperiod 100
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configure wave -griddelta 40
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configure wave -timeline 1
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update
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WaveRestoreZoom {0 ps} {21 us}
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@@ -1,34 +0,0 @@
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## NOTE: Do not edit this file.
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## Autogenerated by ProjNav (creatfdo.tcl) on Thu Jul 06 20:49:07 Westeuropäische Sommerzeit 2006
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##
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vlib work
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vcom -explicit -93 "../../misc/utils_pkg.vhd"
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vcom -explicit -93 "../../rams/dpram_1w1r2c_ra_sim.vhd"
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vcom -explicit -93 "../../rams/dpram_2w2r2c_ra_sim.vhd"
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vcom -explicit -93 "../../rams/dpram_1w1r2c_ro_sim.vhd"
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vcom -explicit -93 "../../rams/dpram_2w2r2c_ro_sim.vhd"
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vcom -explicit -93 "../../FIFO/src/fifo_ctrl_pkg.vhd"
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vcom -explicit -93 "../../FIFO/src/fifo_sync_ctrl.vhd"
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vcom -explicit -93 "../../FIFO/src/fifo_sync.vhd"
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vcom -explicit -93 "../../FIFO/src/gray_counter.vhd"
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vcom -explicit -93 "../../FIFO/src/fifo_async_ctrl.vhd"
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vcom -explicit -93 "../../FIFO/src/fifo_async.vhd"
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vcom -explicit -93 "../../JBUS/src/busmaster_types.vhd"
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vcom -explicit -93 "../../JBUS/src/busmaster_sync.vhd"
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vcom -explicit -93 "../../JBUS/src/dmac.vhd"
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vcom -explicit -93 "../src/piso.vhd"
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vcom -explicit -93 "../src/sipo.vhd"
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vcom -explicit -93 "../src/crc32.vhd"
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vcom -explicit -93 "../src/emac_types.vhd"
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vcom -explicit -93 "../src/emac_rx.vhd"
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vcom -explicit -93 "../src/emac_tx.vhd"
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vcom -explicit -93 "../src/emac_top_jb.vhd"
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vcom -explicit -93 "../src/pkt_gen.vhd"
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vcom -explicit -93 "../src/tb_emac_top_jb.vhd"
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vsim -t 1ps -lib work tb_emac_top_jb
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view wave
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do {tb_emac_top_jb.wdo}
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view structure
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view signals
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run 16000 us
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@@ -1,236 +0,0 @@
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onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate -divider {Ethernet MAC}
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/clk_i
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/rst_i
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/ram64
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add wave -noupdate -divider Slave
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add wave -noupdate -format Logic -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/int_o
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/cyc_i
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/stb_i
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add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/sel_i
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/we_i
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/ack_o
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/srdy_o
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mrdy_i
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/addr_i
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/dat_i
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/dat_o
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||||
add wave -noupdate -divider Master
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add wave -noupdate -format Logic /tb_emac_top_jb/cyc_o
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add wave -noupdate -format Logic /tb_emac_top_jb/stb_o
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add wave -noupdate -format Logic /tb_emac_top_jb/we_o
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add wave -noupdate -format Literal /tb_emac_top_jb/sel_o
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||||
add wave -noupdate -format Logic /tb_emac_top_jb/ack_i
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||||
add wave -noupdate -format Logic /tb_emac_top_jb/mrdy_o
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||||
add wave -noupdate -format Logic /tb_emac_top_jb/srdy_i
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/addr_o
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add wave -noupdate -format Literal /tb_emac_top_jb/mdat_i
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||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/mdat_o
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||||
add wave -noupdate -divider MII
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||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_rx_clk
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_rx_dv
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_rx_er
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/mii_rx
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_tx_clk
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_tx_en
|
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_tx_er
|
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/mii_tx
|
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_gtx_clk
|
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_crs
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_col
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/status_reg
|
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/size_reg
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/dat_o_reg
|
||||
add wave -noupdate -format Literal /tb_emac_top_jb/emac_action
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/dat_o_cnt_rst
|
||||
add wave -noupdate -format Literal /tb_emac_top_jb/dat_o_cnt
|
||||
add wave -noupdate -format Literal /tb_emac_top_jb/pkt_count
|
||||
add wave -noupdate -divider {Packet generator}
|
||||
add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/tx_packets
|
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add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/tx_bytes
|
||||
add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_pkt_gen/pkt_nbytes
|
||||
add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_pkt_gen/pkt_nwords
|
||||
add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/host_s
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_emac_top_jb/inst_pkt_gen/tx_ctrl_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_emac_top_jb/inst_pkt_gen/tx_ctrl_out
|
||||
add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/tx_bytes
|
||||
add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/tx_packets
|
||||
add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_pkt_gen/fill_size
|
||||
add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_pkt_gen/fill_cnt
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_pkt_gen/fill_rdy
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_pkt_gen/fill_set
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_pkt_gen/fill_en
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_pkt_gen/tx_din
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_pkt_gen/tx_din_vld
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/pktgen_tx
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/pktgen_tx_en
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/pktgen_tx_er
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/pktgen_en
|
||||
add wave -noupdate -divider RX-DMA
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/master_req
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/master_gnt
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/dma_start
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/dma_active
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/dma_end
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/req_rdy
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/req_en
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/req_rw
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/req_addr_start
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/req_num_xfers
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/req_addr_auto_inc
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/req_complete
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/req_complete_ack
|
||||
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/s
|
||||
add wave -noupdate -divider RX
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/clk
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/rst
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/dout_re
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/dout
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ctrl_in
|
||||
add wave -noupdate -format Literal -radix unsigned -expand /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ctrl_out
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_rx_clk
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_rx_dv
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_rx_er
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_rx
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_crs
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_col
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_dout
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_we
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_re
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_empty
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_full
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/host_ptr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/host_ram_limit
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/host_ram_base
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/commit_en
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_ram_limit
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_ram_full
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_base
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_ptr
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_en_a
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_we_a
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_addr_a
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_din_a
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_en_b
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_addr_b
|
||||
add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/byte_count
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_din
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_din_vld
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_dout
|
||||
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_dout_be
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_dout_vld
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_dout_en
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_en
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_rst
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo8_dout
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo8_rst
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo8_dout_vld
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo8_dout_en
|
||||
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/host_s
|
||||
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_s
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/preamble_bsy
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/preamble_ok
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/preamble_rdy
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_rdy
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_ok
|
||||
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_num_ok
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_addr
|
||||
add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_cnt
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/fcs_vld
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/fcs_din_vld
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/fcs
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/fcs_chk_ok
|
||||
add wave -noupdate -divider TX
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/clk
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/rst
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/din_vld
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ctrl_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ctrl_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_dout
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_we
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_re
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_empty
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_full
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_pre_rdy
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_bsy
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_set
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_en
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_cnt_en
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_base
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_size
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_cnt
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_ptr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_remain
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/alloc_ok
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/alloc_req
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/alloc_ack
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/nwords_free
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/alloc_size
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mem_alloc_en
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mem_free_en
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/commit_en
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/uncommit_en
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_bsy
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_size
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_ptr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_cnt
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_cnt_en
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_en
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_set
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_en_a
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_we_a
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_addr_a
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_din_a
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_en_b
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_addr_b
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_dout_b
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_din
|
||||
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_din_be
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_din_rdy
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_din_vld
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_dout
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_dout_vld
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_dout_en
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_we
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_re
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_full
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_empty
|
||||
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_re_dly
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_din_vld
|
||||
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_din
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_dout_vld
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_din_rdy
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_dout
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fcs_rst
|
||||
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fcs_en
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fcs_din_vld
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fcs_vld
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fcs
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_tx_clk
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_tx_en
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_tx_er
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_tx
|
||||
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/host_s
|
||||
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_s
|
||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mem_free_req
|
||||
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mem_free_ack
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {15999470765 ps} 0} {{Cursor 2} {49999967706 ps} 0} {{Cursor 3} {42725669958 ps} 0} {{Cursor 4} {10461803096 ps} 0} {{Cursor 5} {10000 ps} 0}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 100
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 1
|
||||
update
|
||||
WaveRestoreZoom {0 ps} {379173 ps}
|
||||
@@ -1,8 +0,0 @@
|
||||
VHDL/lib/emac/emac_jb.vhd
|
||||
VHDL/lib/emac/src/emac_jb.vhd
|
||||
VHDL/lib/emac/src/emac_jb.vhd
|
||||
|
||||
VHDL/lib/emac/src/tb_emac_jb.vhd
|
||||
VHDL/lib/emac/src/tb_serdes.vhd
|
||||
VHDL/lib/emac/src/tb_serdes.vhd
|
||||
|
||||
@@ -1,64 +0,0 @@
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
use std.textio.all; -- Imports the standard textio package.
|
||||
|
||||
use work.utils_pkg.all; -- Imports the standard textio package.
|
||||
|
||||
ENTITY crc32 IS
|
||||
Generic
|
||||
(
|
||||
crc32_init : unsigned(31 downto 0) := X"00000000"
|
||||
);
|
||||
Port
|
||||
(
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
din_vld : in STD_LOGIC;
|
||||
din : in unsigned(7 downto 0);
|
||||
crc32_vld : out STD_LOGIC;
|
||||
crc32_out : out unsigned(31 downto 0)
|
||||
|
||||
);
|
||||
END crc32;
|
||||
|
||||
ARCHITECTURE behavior OF crc32 IS
|
||||
|
||||
type crc_table_t is array (0 to 15) of unsigned(31 downto 0);
|
||||
|
||||
constant crc_table : crc_table_t :=
|
||||
(
|
||||
X"4DBDF21C", X"500AE278", X"76D3D2D4", X"6B64C2B0",
|
||||
X"3B61B38C", X"26D6A3E8", X"000F9344", X"1DB88320",
|
||||
X"A005713C", X"BDB26158", X"9B6B51F4", X"86DC4190",
|
||||
X"D6D930AC", X"CB6E20C8", X"EDB71064", X"F0000000"
|
||||
);
|
||||
|
||||
signal crc0 : unsigned(31 downto 0);
|
||||
signal crc1 : unsigned(31 downto 0);
|
||||
signal crc2 : unsigned(31 downto 0);
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
begin
|
||||
|
||||
crc1 <= X"0" & crc0(31 downto 4) xor crc_table(to_integer(crc0(3 downto 0) xor din(3 downto 0)));
|
||||
crc2 <= X"0" & crc1(31 downto 4) xor crc_table(to_integer(crc1(3 downto 0) xor din(7 downto 4)));
|
||||
|
||||
crc32_out <= crc0;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
crc0 <= crc32_init;
|
||||
crc32_vld <= '0';
|
||||
elsif din_vld = '1' then
|
||||
crc0 <= crc2;
|
||||
crc32_vld <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
end behavior;
|
||||
@@ -1,561 +0,0 @@
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
use std.textio.all; -- Imports the standard textio package.
|
||||
|
||||
use work.emac_types.all;
|
||||
use work.utils_pkg.all;
|
||||
|
||||
ENTITY emac_rx IS
|
||||
Generic
|
||||
(
|
||||
f_sysclk : real := 100.0;
|
||||
RAM_SIZE : natural := 2048
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk : in STD_LOGIC;
|
||||
rst : in STD_LOGIC;
|
||||
dout_re : in STD_LOGIC;
|
||||
dout : out unsigned(31 downto 0);
|
||||
ctrl_in : in rx_ctrl_in_t;
|
||||
ctrl_out : out rx_ctrl_out_t;
|
||||
mii_rx_clk : in STD_LOGIC;
|
||||
mii_rx_dv : in STD_LOGIC;
|
||||
mii_rx_er : in STD_LOGIC;
|
||||
mii_rx : in unsigned(7 downto 0);
|
||||
mii_crs : in STD_LOGIC;
|
||||
mii_col : in STD_LOGIC
|
||||
|
||||
);
|
||||
END emac_rx;
|
||||
|
||||
ARCHITECTURE behavior OF emac_rx IS
|
||||
|
||||
constant RAM_ADDR_WIDTH : natural := NextExpBaseTwo(RAM_SIZE);
|
||||
|
||||
subtype word_ptr_t is unsigned(RAM_ADDR_WIDTH-1 downto 0);
|
||||
|
||||
-- Signals for EMAC connections
|
||||
signal cmd_fifo_din : unsigned(2*word_ptr_t'length+2 downto 0);
|
||||
signal cmd_fifo_dout : unsigned(2*word_ptr_t'length+2 downto 0);
|
||||
signal cmd_fifo_we : std_logic;
|
||||
signal cmd_fifo_re : std_logic;
|
||||
signal cmd_fifo_empty : std_logic;
|
||||
signal cmd_fifo_full : std_logic;
|
||||
|
||||
signal reset_en : std_logic;
|
||||
|
||||
signal host_ptr : word_ptr_t;
|
||||
signal host_ptr_next : word_ptr_t;
|
||||
signal host_ram_limit : word_ptr_t;
|
||||
signal host_ram_base : word_ptr_t;
|
||||
|
||||
signal commit_en : std_logic;
|
||||
|
||||
signal xfer_ram_limit : word_ptr_t;
|
||||
signal xfer_ram_full : std_logic;
|
||||
signal xfer_base : word_ptr_t;
|
||||
signal xfer_ptr : word_ptr_t;
|
||||
signal xfer_en : std_logic;
|
||||
signal xfer_set : std_logic;
|
||||
signal xfer_vld : std_logic;
|
||||
signal xfer_promiscious : std_logic;
|
||||
|
||||
signal ram_en_a : std_logic;
|
||||
signal ram_we_a : std_logic;
|
||||
signal ram_addr_a : word_ptr_t;
|
||||
signal ram_din_a : unsigned(31 downto 0);
|
||||
signal ram_dout_b : unsigned(31 downto 0);
|
||||
signal ram_en_b : std_logic;
|
||||
signal ram_addr_b : word_ptr_t;
|
||||
|
||||
signal sipo32_din : unsigned(7 downto 0);
|
||||
signal sipo32_din_vld : std_logic;
|
||||
signal sipo32_dout : unsigned(31 downto 0);
|
||||
signal sipo32_dout_be : unsigned(3 downto 0);
|
||||
signal sipo32_dout_vld : std_logic;
|
||||
signal sipo32_dout_en : std_logic;
|
||||
signal sipo32_en : std_logic;
|
||||
signal sipo32_rst : std_logic;
|
||||
|
||||
signal sipo8_dout : unsigned(7 downto 0);
|
||||
signal sipo8_rst : std_logic;
|
||||
signal sipo8_dout_vld : std_logic;
|
||||
signal sipo8_dout_en : std_logic;
|
||||
signal sipo8_en : std_logic;
|
||||
|
||||
signal byte_count_rst : std_logic;
|
||||
signal byte_count : word_ptr_t;
|
||||
|
||||
signal reset_pipe : unsigned(31 downto 0);
|
||||
|
||||
signal preamble_en : std_logic;
|
||||
signal preamble_rdy : std_logic;
|
||||
signal preamble_bsy : std_logic;
|
||||
signal preamble_OK : std_logic;
|
||||
|
||||
signal mac_chk_rdy : std_logic;
|
||||
signal mac_chk_BC : std_logic;
|
||||
signal mac_chk_OK : std_logic;
|
||||
signal mac_chk_num_OK : natural range 0 to 6;
|
||||
signal mac_chk_num_BC : natural range 0 to 6;
|
||||
signal mac_chk_cnt : natural range 0 to 5;
|
||||
signal mac_addr : mac_addr_t;
|
||||
signal mac_chk_addr : mac_addr_t;
|
||||
|
||||
signal Gbps_en : std_logic;
|
||||
signal fcs_chk_en : std_logic;
|
||||
signal rx_en : std_logic;
|
||||
|
||||
signal fcs_vld : std_logic;
|
||||
signal fcs_din_vld : std_logic;
|
||||
signal fcs_din : unsigned(7 downto 0);
|
||||
signal fcs : unsigned(31 downto 0);
|
||||
signal fcs_chk_OK : std_logic;
|
||||
|
||||
type host_state_t is (host_init, host_flush, host_idle);
|
||||
signal host_s, host_sn : host_state_t;
|
||||
|
||||
type xfer_state_t is (xfer_init, xfer_idle, xfer_preamble, xfer_setup, xfer_active, xfer_finish, xfer_commit);
|
||||
signal xfer_s, xfer_sn : xfer_state_t;
|
||||
|
||||
alias cmd_mac_ok_in is cmd_fifo_din(cmd_fifo_din'left);
|
||||
alias cmd_bcast_in is cmd_fifo_din(cmd_fifo_din'left-1);
|
||||
alias cmd_pkt_valid_in is cmd_fifo_din(cmd_fifo_din'left-2);
|
||||
alias cmd_nbytes_in is cmd_fifo_din(word_ptr_t'length-1 downto 0);
|
||||
alias cmd_base_in is cmd_fifo_din(2*word_ptr_t'length-1 downto word_ptr_t'length);
|
||||
|
||||
alias cmd_mac_ok_out is cmd_fifo_dout(cmd_fifo_dout'left);
|
||||
alias cmd_bcast_out is cmd_fifo_dout(cmd_fifo_dout'left-1);
|
||||
alias cmd_pkt_valid_out is cmd_fifo_dout(cmd_fifo_dout'left-2);
|
||||
alias cmd_nbytes_out is cmd_fifo_dout(word_ptr_t'length-1 downto 0);
|
||||
alias cmd_base_out is cmd_fifo_dout(2*word_ptr_t'length-1 downto word_ptr_t'length);
|
||||
|
||||
begin
|
||||
|
||||
ctrl_out.rx_size <= resize(cmd_nbytes_out, 16);
|
||||
ctrl_out.pkt_avail <= not cmd_fifo_empty;
|
||||
ctrl_out.pkt_valid <= cmd_pkt_valid_out;
|
||||
ctrl_out.pkt_bcast <= cmd_bcast_out;
|
||||
ctrl_out.pkt_mac_match <= cmd_mac_ok_out;
|
||||
ctrl_out.reset_busy <= reset_en;
|
||||
|
||||
dout <= ram_dout_b;
|
||||
|
||||
ram_en_b <= '1';
|
||||
ram_addr_b <= host_ptr_next;
|
||||
|
||||
ram_en_a <= '1';
|
||||
ram_din_a <= sipo32_dout;
|
||||
ram_addr_a <= xfer_ptr;
|
||||
ram_we_a <= xfer_en and sipo32_dout_vld;
|
||||
|
||||
xfer_vld <= (mac_chk_OK or mac_chk_BC or xfer_promiscious) and (not fcs_chk_en or fcs_chk_OK);
|
||||
cmd_fifo_we <= commit_en and xfer_vld;
|
||||
cmd_fifo_re <= ctrl_in.pkt_free_en;
|
||||
|
||||
cmd_pkt_valid_in <= fcs_chk_OK;
|
||||
cmd_mac_ok_in <= mac_chk_OK;
|
||||
cmd_bcast_in <= mac_chk_BC;
|
||||
cmd_nbytes_in <= byte_count;
|
||||
cmd_base_in <= xfer_base;
|
||||
|
||||
|
||||
reset_en <= reset_pipe(reset_pipe'left);
|
||||
|
||||
------------------------------------------------------------------
|
||||
reset_gen:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' or ctrl_in.reset = '1' then
|
||||
reset_pipe <= (others => '1');
|
||||
else
|
||||
reset_pipe <= reset_pipe(reset_pipe'left-1 downto 0) & '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
-- Fill stuff
|
||||
------------------------------------------------------------------
|
||||
fill_pointer:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if ctrl_in.pkt_req_en = '1' then
|
||||
host_ptr <= cmd_base_out;
|
||||
elsif dout_re = '1' then
|
||||
host_ptr <= host_ptr_next;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
host_ptr_next <= host_ptr + 1 when dout_re = '1' else host_ptr;
|
||||
|
||||
------------------------------------------------------------------
|
||||
-- Transfer stuff
|
||||
------------------------------------------------------------------
|
||||
host2xfer_sync_register:
|
||||
process(mii_rx_clk)
|
||||
begin
|
||||
if rising_edge(mii_rx_clk) then
|
||||
xfer_promiscious <= ctrl_in.promiscious;
|
||||
Gbps_en <= ctrl_in.Gbps_en;
|
||||
fcs_chk_en <= ctrl_in.fcs_chk_en;
|
||||
mac_addr <= ctrl_in.mac_addr;
|
||||
xfer_ram_limit <= host_ram_limit;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
host_limit_register:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
host_ram_base <= xfer_base;
|
||||
if cmd_fifo_empty = '1' then
|
||||
host_ram_limit <= host_ram_base - 1;
|
||||
else
|
||||
host_ram_limit <= cmd_base_out - 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
xfer_ram_full_detect:
|
||||
process(mii_rx_clk)
|
||||
begin
|
||||
if rising_edge(mii_rx_clk) then
|
||||
if xfer_set = '1' or reset_en = '1' then
|
||||
xfer_ram_full <= '0';
|
||||
elsif xfer_en = '1' and sipo32_dout_vld = '1' then
|
||||
if xfer_ptr = xfer_ram_limit then
|
||||
xfer_ram_full <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
xfer_base_logic:
|
||||
process(mii_rx_clk)
|
||||
begin
|
||||
if rising_edge(mii_rx_clk) then
|
||||
if reset_en = '1' then
|
||||
xfer_base <= (others => '0');
|
||||
elsif commit_en = '1' and xfer_vld = '1' then
|
||||
xfer_base <= xfer_ptr;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
xfer_pointer:
|
||||
process(mii_rx_clk)
|
||||
begin
|
||||
if rising_edge(mii_rx_clk) then
|
||||
if xfer_set = '1' then
|
||||
xfer_ptr <= xfer_base;
|
||||
elsif xfer_en = '1' and sipo32_dout_vld = '1' then
|
||||
xfer_ptr <= xfer_ptr + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
byte_counter:
|
||||
process(mii_rx_clk)
|
||||
begin
|
||||
if rising_edge(mii_rx_clk) then
|
||||
if byte_count_rst = '1' then
|
||||
if fcs_chk_en = '0' then
|
||||
byte_count <= to_unsigned(0, RAM_ADDR_WIDTH);
|
||||
else
|
||||
byte_count <= unsigned(to_signed(-4, RAM_ADDR_WIDTH));
|
||||
end if;
|
||||
elsif sipo32_en = '1' and sipo32_din_vld = '1' then
|
||||
byte_count <= byte_count + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
preamble_sync_logic:
|
||||
process(mii_rx_clk)
|
||||
begin
|
||||
if rising_edge(mii_rx_clk) then
|
||||
if preamble_en = '0' then
|
||||
preamble_rdy <= '0';
|
||||
preamble_bsy <= '0';
|
||||
preamble_OK <= '0';
|
||||
elsif sipo32_din_vld = '1' then
|
||||
if preamble_bsy = '1' then
|
||||
if sipo32_din = X"D5" then
|
||||
preamble_OK <= '1';
|
||||
end if;
|
||||
end if;
|
||||
if sipo32_din /= X"55" then
|
||||
preamble_bsy <= '0';
|
||||
preamble_rdy <= preamble_bsy;
|
||||
else
|
||||
preamble_bsy <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
mac_check_logic:
|
||||
process(mii_rx_clk)
|
||||
begin
|
||||
if rising_edge(mii_rx_clk) then
|
||||
if byte_count_rst = '1' then
|
||||
mac_chk_rdy <= '0';
|
||||
mac_chk_OK <= '0';
|
||||
mac_chk_BC <= '0';
|
||||
mac_chk_cnt <= 0;
|
||||
mac_chk_num_OK <= 0;
|
||||
mac_chk_num_BC <= 0;
|
||||
mac_chk_addr <= mac_addr;
|
||||
elsif mac_chk_rdy = '1' then
|
||||
if mac_chk_num_OK = 6 then
|
||||
mac_chk_OK <= '1';
|
||||
end if;
|
||||
if mac_chk_num_BC = 6 then
|
||||
mac_chk_BC <= '1';
|
||||
end if;
|
||||
elsif sipo32_din_vld = '1' and sipo32_en = '1' then
|
||||
if sipo32_din = mac_chk_addr(mac_chk_cnt) then
|
||||
mac_chk_num_OK <= mac_chk_num_OK + 1;
|
||||
end if;
|
||||
if sipo32_din = X"FF" then
|
||||
mac_chk_num_BC <= mac_chk_num_BC + 1;
|
||||
end if;
|
||||
if mac_chk_cnt /= 5 then
|
||||
mac_chk_cnt <= mac_chk_cnt + 1;
|
||||
else
|
||||
mac_chk_rdy <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
xfer_state_next:
|
||||
process(mii_rx_clk)
|
||||
begin
|
||||
if rising_edge(mii_rx_clk) then
|
||||
if reset_en = '1' then
|
||||
xfer_s <= xfer_init;
|
||||
else
|
||||
xfer_s <= xfer_sn;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
xfer_state:
|
||||
process(xfer_s, rx_en, sipo32_dout_en, preamble_bsy, preamble_OK, xfer_ram_full)
|
||||
begin
|
||||
|
||||
commit_en <= '0';
|
||||
xfer_set <= '0';
|
||||
xfer_en <= '0';
|
||||
sipo32_rst <= '0';
|
||||
sipo32_en <= '0';
|
||||
byte_count_rst <= '0';
|
||||
preamble_en <= '0';
|
||||
|
||||
xfer_sn <= xfer_s;
|
||||
|
||||
case xfer_s is
|
||||
|
||||
when xfer_init =>
|
||||
sipo32_rst <= '1';
|
||||
if rx_en = '0' then
|
||||
xfer_sn <= xfer_idle;
|
||||
end if;
|
||||
|
||||
when xfer_idle =>
|
||||
preamble_en <= rx_en;
|
||||
if preamble_bsy = '1' then
|
||||
xfer_sn <= xfer_preamble;
|
||||
end if;
|
||||
|
||||
when xfer_preamble =>
|
||||
preamble_en <= rx_en;
|
||||
byte_count_rst <= preamble_bsy;
|
||||
sipo32_en <= rx_en and not preamble_bsy;
|
||||
if preamble_bsy = '0' then
|
||||
xfer_sn <= xfer_init;
|
||||
if preamble_OK = '1' then
|
||||
xfer_sn <= xfer_setup;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when xfer_setup =>
|
||||
xfer_set <= '1';
|
||||
sipo32_en <= rx_en;
|
||||
xfer_en <= sipo32_dout_en;
|
||||
xfer_sn <= xfer_active;
|
||||
|
||||
when xfer_active =>
|
||||
xfer_en <= sipo32_dout_en;
|
||||
sipo32_en <= rx_en;
|
||||
if xfer_ram_full = '1' then
|
||||
xfer_sn <= xfer_init;
|
||||
elsif rx_en = '0' then
|
||||
xfer_sn <= xfer_finish;
|
||||
end if;
|
||||
|
||||
when xfer_finish =>
|
||||
xfer_en <= sipo32_dout_en;
|
||||
if sipo32_dout_en = '0' then
|
||||
xfer_sn <= xfer_commit;
|
||||
end if;
|
||||
|
||||
when xfer_commit =>
|
||||
commit_en <= '1';
|
||||
xfer_sn <= xfer_init;
|
||||
|
||||
when others =>
|
||||
xfer_sn <= xfer_init;
|
||||
end case;
|
||||
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
-- Instantiate synchronous FIFO
|
||||
inst_cmd_fifo: entity work.fifo_async
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => NextExpBaseTwo(RAM_SIZE) - 4, -- RAMSIZE(words)/MIN_PACKET_LEN(words)
|
||||
data_width => cmd_fifo_din'length,
|
||||
do_last_read_update => false
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => reset_en,
|
||||
clk_w => mii_rx_clk,
|
||||
clk_r => clk,
|
||||
we => cmd_fifo_we,
|
||||
re => cmd_fifo_re,
|
||||
fifo_full => cmd_fifo_full,
|
||||
fifo_empty => cmd_fifo_empty,
|
||||
fifo_afull => open,
|
||||
fifo_aempty => open,
|
||||
data_w => cmd_fifo_din,
|
||||
data_r => cmd_fifo_dout
|
||||
);
|
||||
|
||||
inst_ram : entity work.dpram_1w1r2c_ro
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => RAM_ADDR_WIDTH,
|
||||
data_width => 32
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
clk_a => mii_rx_clk,
|
||||
clk_b => clk,
|
||||
en_a => ram_en_a,
|
||||
en_b => ram_en_b,
|
||||
we_a => ram_we_a,
|
||||
addr_a => ram_addr_a,
|
||||
addr_b => ram_addr_b,
|
||||
din_a => ram_din_a,
|
||||
dout_b => ram_dout_b
|
||||
);
|
||||
|
||||
inst_sipo32 : entity work.sipo
|
||||
GENERIC MAP
|
||||
(
|
||||
data_width_in => 8,
|
||||
data_width_out => 32,
|
||||
msb_first => true
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => sipo32_rst,
|
||||
clk => mii_rx_clk,
|
||||
din_vld => sipo32_din_vld,
|
||||
din_en => sipo32_en,
|
||||
din => sipo32_din,
|
||||
dout_be => sipo32_dout_be,
|
||||
dout_vld => sipo32_dout_vld,
|
||||
dout => sipo32_dout,
|
||||
dout_en => sipo32_dout_en
|
||||
|
||||
);
|
||||
|
||||
inst_fcs: entity work.crc32
|
||||
GENERIC MAP
|
||||
(
|
||||
crc32_init => X"00000000"
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => byte_count_rst,
|
||||
clk => mii_rx_clk,
|
||||
din_vld => fcs_din_vld,
|
||||
din => fcs_din,
|
||||
crc32_vld => fcs_vld,
|
||||
crc32_out => fcs
|
||||
|
||||
);
|
||||
|
||||
fcs_din <= sipo32_din;
|
||||
fcs_din_vld <= sipo32_en and sipo32_din_vld;
|
||||
|
||||
fcs_chk_register:
|
||||
process(mii_rx_clk)
|
||||
begin
|
||||
if rising_edge(mii_rx_clk) then
|
||||
if fcs_vld = '1' then
|
||||
fcs_chk_OK <= '0';
|
||||
if fcs = X"2144DF1C" then
|
||||
fcs_chk_OK <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
mii_input_register:
|
||||
process(mii_rx_clk)
|
||||
begin
|
||||
if rising_edge(mii_rx_clk) then
|
||||
if Gbps_en = '1' then
|
||||
sipo32_din <= mii_rx;
|
||||
sipo32_din_vld <= not mii_rx_er;
|
||||
rx_en <= mii_rx_dv;
|
||||
else
|
||||
sipo32_din <= sipo8_dout;
|
||||
sipo32_din_vld <= sipo8_dout_vld;
|
||||
rx_en <= sipo8_dout_en;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
inst_sipo_8bit : entity work.sipo
|
||||
GENERIC MAP
|
||||
(
|
||||
data_width_in => 4,
|
||||
data_width_out => 8,
|
||||
msb_first => false
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => sipo8_rst,
|
||||
clk => mii_rx_clk,
|
||||
din_vld => mii_rx_dv,
|
||||
din_en => mii_rx_dv,
|
||||
din => mii_rx(3 downto 0),
|
||||
dout_be => open,
|
||||
dout_vld => sipo8_dout_vld,
|
||||
dout => sipo8_dout,
|
||||
dout_en => sipo8_dout_en
|
||||
|
||||
);
|
||||
|
||||
sipo8_rst <= reset_en or not (mii_rx_dv or sipo8_dout_en);
|
||||
sipo8_en <= not mii_rx_er;
|
||||
|
||||
end behavior;
|
||||
@@ -1,503 +0,0 @@
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
use std.textio.all; -- Imports the standard textio package.
|
||||
|
||||
use work.emac_types.all;
|
||||
use work.utils_pkg.all;
|
||||
use work.busmaster_types.all;
|
||||
|
||||
ENTITY emac_top_jb IS
|
||||
Generic
|
||||
(
|
||||
f_sysclk : real := 100.0;
|
||||
TX_RAM_SIZE : natural := 2048;
|
||||
RX_RAM_SIZE : natural := 2048
|
||||
);
|
||||
Port
|
||||
(
|
||||
-- JBUS Slave
|
||||
CLK_I : in STD_LOGIC;
|
||||
RST_I : in STD_LOGIC;
|
||||
INT_O : out STD_LOGIC;
|
||||
CYC_I : in STD_LOGIC;
|
||||
STB_I : in STD_LOGIC;
|
||||
SEL_I : in unsigned(3 downto 0);
|
||||
WE_I : in STD_LOGIC;
|
||||
ACK_O : out STD_LOGIC;
|
||||
SRDY_O : out STD_LOGIC;
|
||||
MRDY_I : in STD_LOGIC;
|
||||
ADDR_I : in unsigned(31 downto 0);
|
||||
DAT_I : in unsigned(31 downto 0);
|
||||
DAT_O : out unsigned(31 downto 0);
|
||||
|
||||
-- JBUS Master
|
||||
ACK_I : in std_logic;
|
||||
SRDY_I : in std_logic;
|
||||
MDAT_I : in unsigned(31 downto 0);
|
||||
MDAT_O : out unsigned(31 downto 0);
|
||||
ADDR_O : out unsigned(31 downto 0);
|
||||
SEL_O : out unsigned(3 downto 0);
|
||||
WE_O : out std_logic;
|
||||
CYC_O : out std_logic;
|
||||
STB_O : out std_logic;
|
||||
MRDY_O : out std_logic;
|
||||
|
||||
-- MII
|
||||
mii_rx_clk : in STD_LOGIC;
|
||||
mii_rx_dv : in STD_LOGIC;
|
||||
mii_rx_er : in STD_LOGIC;
|
||||
mii_rx : in unsigned(7 downto 0);
|
||||
mii_tx_clk : in STD_LOGIC;
|
||||
mii_tx_en : out STD_LOGIC;
|
||||
mii_tx_er : out STD_LOGIC;
|
||||
mii_tx : out unsigned(7 downto 0);
|
||||
mii_gtx_clk : out STD_LOGIC;
|
||||
mii_crs : in STD_LOGIC;
|
||||
mii_col : in STD_LOGIC
|
||||
|
||||
);
|
||||
END emac_top_jb;
|
||||
|
||||
ARCHITECTURE behavior OF emac_top_jb IS
|
||||
|
||||
-- Constants
|
||||
constant DMA_NUM_CHANNEL : integer := 2;
|
||||
constant DMA_CH_WRITE : integer := 0;
|
||||
constant DMA_CH_READ : integer := 1;
|
||||
constant DMA_RW_CONF : unsigned(DMA_NUM_CHANNEL-1 downto 0) := "01";
|
||||
|
||||
-- Signals for EMAC connections
|
||||
signal tx_ctrl_in : tx_ctrl_in_t;
|
||||
signal tx_ctrl_out : tx_ctrl_out_t;
|
||||
signal tx_din : unsigned(31 downto 0);
|
||||
signal tx_din_vld : std_logic;
|
||||
|
||||
signal rx_ctrl_in : rx_ctrl_in_t;
|
||||
signal rx_ctrl_out : rx_ctrl_out_t;
|
||||
|
||||
signal rx_dout : unsigned(31 downto 0);
|
||||
signal rx_dout_re : std_logic;
|
||||
|
||||
signal rx_int_en : std_logic;
|
||||
signal tx_int_en : std_logic;
|
||||
signal irq_rx : std_logic;
|
||||
signal irq_tx : std_logic;
|
||||
|
||||
signal ready : std_logic;
|
||||
|
||||
signal read : std_logic;
|
||||
signal write : std_logic;
|
||||
signal rx_read_en_CPU : std_logic;
|
||||
signal rx_req_en_CPU : std_logic;
|
||||
signal rx_free_en_CPU : std_logic;
|
||||
signal tx_write_en_CPU : std_logic;
|
||||
signal reg_read : std_logic;
|
||||
signal reg_write : std_logic;
|
||||
|
||||
signal reg_addr : unsigned(3 downto 0);
|
||||
|
||||
-- DMA Controller
|
||||
signal dma_master_req : unsigned(DMA_NUM_CHANNEL-1 downto 0);
|
||||
signal dma_master_gnt : unsigned(DMA_NUM_CHANNEL-1 downto 0) := (others => '0');
|
||||
signal dma_req_rdy : unsigned(DMA_NUM_CHANNEL-1 downto 0);
|
||||
signal dma_req_en : unsigned(DMA_NUM_CHANNEL-1 downto 0) := (others => '0');
|
||||
signal dma_req_addr_auto_inc : unsigned(DMA_NUM_CHANNEL-1 downto 0);
|
||||
type array32_t is array (0 to DMA_NUM_CHANNEL-1) of unsigned(31 downto 0);
|
||||
signal dma_req_addr : array32_t;
|
||||
signal dma_req_num_xfers : array32_t;
|
||||
|
||||
signal dma_req_complete : unsigned(DMA_NUM_CHANNEL-1 downto 0);
|
||||
signal dma_req_complete_ack : unsigned(DMA_NUM_CHANNEL-1 downto 0) := (others => '0');
|
||||
|
||||
signal dma_start : unsigned(DMA_NUM_CHANNEL-1 downto 0);
|
||||
signal dma_active : unsigned(DMA_NUM_CHANNEL-1 downto 0);
|
||||
signal dma_end : unsigned(DMA_NUM_CHANNEL-1 downto 0);
|
||||
signal dma_bus_cmd_cycle_finished : unsigned(DMA_NUM_CHANNEL-1 downto 0);
|
||||
signal dma_bus_cmd_cycle_en : unsigned(DMA_NUM_CHANNEL-1 downto 0) := (others => '0');
|
||||
signal dma_bus_cmd_rdy : unsigned(DMA_NUM_CHANNEL-1 downto 0);
|
||||
signal dma_bus_cmd_we : unsigned(DMA_NUM_CHANNEL-1 downto 0) := (others => '0');
|
||||
type array_bus_cmd_t is array (0 to DMA_NUM_CHANNEL-1) of bm_cmd_t;
|
||||
signal dma_bus_cmd : array_bus_cmd_t;
|
||||
|
||||
-- Busmaster arbiter
|
||||
signal arb_idx : natural range 0 to DMA_NUM_CHANNEL-1;
|
||||
|
||||
-- BUS Master controller
|
||||
signal bus_din_re : std_logic;
|
||||
signal bus_cmd_cycle_finished : std_logic;
|
||||
signal bus_cmd_cycle_en : std_logic := '0';
|
||||
signal bus_cmd_rdy : std_logic;
|
||||
signal bus_cmd_we : std_logic := '0';
|
||||
signal bus_cmd : bm_cmd_t;
|
||||
signal bus_din_rdy : std_logic;
|
||||
signal bus_din_vld : std_logic := '0';
|
||||
signal bus_din : unsigned(31 downto 0) := (others => '-');
|
||||
signal bus_dout : unsigned(31 downto 0);
|
||||
signal bus_dout_vld : std_logic;
|
||||
signal bus_dout_re : std_logic := '0';
|
||||
|
||||
begin
|
||||
|
||||
mii_gtx_clk <= '0';
|
||||
|
||||
SRDY_O <= CYC_I and ready;
|
||||
read <= STB_I and CYC_I and not WE_I;
|
||||
write <= STB_I and CYC_I and WE_I;
|
||||
rx_read_en_CPU <= read and ADDR_I(15);
|
||||
tx_write_en_CPU <= write and ADDR_I(15);
|
||||
reg_read <= read and not ADDR_I(15);
|
||||
reg_write <= write and not ADDR_I(15);
|
||||
reg_addr <= ADDR_I(5 downto 2);
|
||||
|
||||
ready <= not tx_ctrl_in.pkt_alloc_en;
|
||||
|
||||
tx_din_vld <= tx_write_en_CPU;
|
||||
tx_din <= DAT_I;
|
||||
|
||||
rx_ctrl_in.pkt_free_en <= rx_free_en_CPU or dma_end(0);
|
||||
rx_ctrl_in.pkt_req_en <= rx_req_en_CPU or dma_start(0);
|
||||
|
||||
rx_dout_re <= rx_read_en_CPU or (dma_active(DMA_CH_WRITE) and bus_din_rdy);
|
||||
|
||||
bus_din <= rx_dout;
|
||||
bus_din_vld <= dma_active(DMA_CH_WRITE);
|
||||
dma_master_gnt(0) <= SRDY_I;
|
||||
dma_req_en(0) <= rx_ctrl_out.pkt_avail;
|
||||
dma_req_num_xfers(0) <= X"0000" & "00" & rx_ctrl_out.rx_size(15 downto 2) when rx_ctrl_out.rx_size(1 downto 0) = "00" else X"0000" & "00" & rx_ctrl_out.rx_size(15 downto 2) + 1;
|
||||
dma_req_addr(0) <= X"00000800";
|
||||
dma_req_addr_auto_inc <= "11";
|
||||
|
||||
------------------------------------------------------------------
|
||||
registers_write:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
tx_ctrl_in.pkt_alloc_en <= '0';
|
||||
tx_ctrl_in.pkt_commit_en <= '0';
|
||||
tx_ctrl_in.reset <= '0';
|
||||
rx_free_en_CPU <= '0';
|
||||
rx_req_en_CPU <= '0';
|
||||
rx_ctrl_in.reset <= '0';
|
||||
if RST_I = '1' then
|
||||
rx_int_en <= '0';
|
||||
tx_int_en <= '0';
|
||||
tx_ctrl_in.tx_size <= (others => '0');
|
||||
rx_ctrl_in.mac_addr <= (X"03", X"02", X"01", X"00", X"07", X"06");
|
||||
rx_ctrl_in.promiscious <= '0';
|
||||
tx_ctrl_in.Gbps_en <= '0';
|
||||
rx_ctrl_in.Gbps_en <= '0';
|
||||
tx_ctrl_in.fcs_gen_en <= '0';
|
||||
rx_ctrl_in.fcs_chk_en <= '0';
|
||||
elsif reg_write = '1' then
|
||||
|
||||
-- 0x0000 .. 0x003C
|
||||
case reg_addr is
|
||||
|
||||
-- 0x0000
|
||||
when "0000" =>
|
||||
rx_ctrl_in.reset <= DAT_I(31);
|
||||
rx_ctrl_in.Gbps_en <= DAT_I(30);
|
||||
rx_ctrl_in.fcs_chk_en <= DAT_I(29);
|
||||
rx_ctrl_in.promiscious <= DAT_I(23);
|
||||
rx_req_en_CPU <= DAT_I(17);
|
||||
rx_free_en_CPU <= DAT_I(16);
|
||||
rx_int_en <= DAT_I(4);
|
||||
|
||||
-- 0x0004
|
||||
-- rx_size R/O
|
||||
|
||||
-- 0x0008
|
||||
when "0010" =>
|
||||
tx_ctrl_in.reset <= DAT_I(31);
|
||||
tx_ctrl_in.Gbps_en <= DAT_I(30);
|
||||
tx_ctrl_in.fcs_gen_en <= DAT_I(29);
|
||||
tx_ctrl_in.pkt_alloc_en <= DAT_I(17);
|
||||
tx_ctrl_in.pkt_commit_en <= DAT_I(16);
|
||||
tx_int_en <= DAT_I(4);
|
||||
|
||||
-- 0x000C
|
||||
when "0011" =>
|
||||
tx_ctrl_in.tx_size <= DAT_I(15 downto 0);
|
||||
|
||||
-- 0x0010
|
||||
-- Gap
|
||||
|
||||
-- 0x0014
|
||||
-- Gap
|
||||
|
||||
-- 0x0018
|
||||
when "0110" =>
|
||||
rx_ctrl_in.mac_addr(0) <= DAT_I(31 downto 24);
|
||||
rx_ctrl_in.mac_addr(1) <= DAT_I(23 downto 16);
|
||||
rx_ctrl_in.mac_addr(2) <= DAT_I(15 downto 8);
|
||||
rx_ctrl_in.mac_addr(3) <= DAT_I(7 downto 0);
|
||||
|
||||
-- 0x001C
|
||||
when "0111" =>
|
||||
rx_ctrl_in.mac_addr(4) <= DAT_I(31 downto 24);
|
||||
rx_ctrl_in.mac_addr(5) <= DAT_I(23 downto 16);
|
||||
|
||||
-- 0x0020 .. 0x003C
|
||||
-- Gap
|
||||
when others => null;
|
||||
|
||||
end case;
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
registers_read:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
ACK_O <= rx_read_en_CPU;
|
||||
DAT_O <= rx_dout;
|
||||
if reg_read = '1' then
|
||||
|
||||
-- 0x0000 .. 0x003C
|
||||
case reg_addr is
|
||||
|
||||
-- 0x0000
|
||||
when "0000" =>
|
||||
ACK_O <= ready;
|
||||
DAT_O <= (others => '0');
|
||||
DAT_O(31) <= rx_ctrl_out.reset_busy;
|
||||
DAT_O(30) <= rx_ctrl_in.Gbps_en;
|
||||
DAT_O(29) <= rx_ctrl_in.fcs_chk_en;
|
||||
DAT_O(23) <= rx_ctrl_in.promiscious;
|
||||
DAT_O(19) <= rx_ctrl_out.pkt_bcast;
|
||||
DAT_O(18) <= rx_ctrl_out.pkt_mac_match;
|
||||
DAT_O(17) <= rx_ctrl_out.pkt_valid;
|
||||
DAT_O(16) <= rx_ctrl_out.pkt_avail;
|
||||
DAT_O(4) <= rx_int_en;
|
||||
|
||||
-- 0x0004
|
||||
when "0001" =>
|
||||
ACK_O <= '1';
|
||||
DAT_O <= X"0000" & rx_ctrl_out.rx_size;
|
||||
|
||||
-- 0x0008
|
||||
when "0010" =>
|
||||
ACK_O <= ready;
|
||||
DAT_O <= (others => '0');
|
||||
DAT_O(31) <= tx_ctrl_out.reset_busy;
|
||||
DAT_O(30) <= tx_ctrl_in.Gbps_en;
|
||||
DAT_O(29) <= tx_ctrl_in.fcs_gen_en;
|
||||
DAT_O(24) <= tx_ctrl_out.pkt_done;
|
||||
DAT_O(17) <= tx_ctrl_out.pkt_alloc_req;
|
||||
DAT_O(16) <= tx_ctrl_out.pkt_armed;
|
||||
DAT_O(4) <= tx_int_en;
|
||||
|
||||
-- 0x000C
|
||||
when "0011" =>
|
||||
ACK_O <= '1';
|
||||
DAT_O <= X"0000" & tx_ctrl_out.tx_size;
|
||||
|
||||
-- 0x0010
|
||||
-- Gap
|
||||
|
||||
-- 0x0014
|
||||
-- Gap
|
||||
|
||||
-- 0x0018
|
||||
when "0110" =>
|
||||
ACK_O <= '1';
|
||||
DAT_O <= rx_ctrl_in.mac_addr(0) & rx_ctrl_in.mac_addr(1) & rx_ctrl_in.mac_addr(2) & rx_ctrl_in.mac_addr(3);
|
||||
|
||||
-- 0x001C
|
||||
when "0111" =>
|
||||
ACK_O <= '1';
|
||||
DAT_O <= rx_ctrl_in.mac_addr(4) & rx_ctrl_in.mac_addr(5) & X"0000";
|
||||
|
||||
-- 0x0020 .. 0x003C
|
||||
-- Gap
|
||||
when others => null;
|
||||
|
||||
end case;
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
irq_register:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
INT_O <= irq_rx or irq_tx;
|
||||
irq_tx <= tx_int_en and tx_ctrl_out.pkt_done;
|
||||
irq_rx <= rx_int_en and rx_ctrl_out.pkt_avail;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
inst_emac_rx : entity work.emac_rx
|
||||
GENERIC MAP
|
||||
(
|
||||
f_sysclk => f_sysclk,
|
||||
RAM_SIZE => RX_RAM_SIZE
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
clk => CLK_I,
|
||||
rst => RST_I,
|
||||
dout_re => rx_dout_re,
|
||||
dout => rx_dout,
|
||||
ctrl_in => rx_ctrl_in,
|
||||
ctrl_out => rx_ctrl_out,
|
||||
mii_rx_clk => mii_rx_clk,
|
||||
mii_rx_dv => mii_rx_dv,
|
||||
mii_rx_er => mii_rx_er,
|
||||
mii_rx => mii_rx,
|
||||
mii_crs => mii_crs,
|
||||
mii_col => mii_col
|
||||
|
||||
);
|
||||
|
||||
|
||||
inst_emac_tx : entity work.emac_tx
|
||||
GENERIC MAP
|
||||
(
|
||||
f_sysclk => f_sysclk,
|
||||
RAM_SIZE => TX_RAM_SIZE
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
clk => CLK_I,
|
||||
rst => RST_I,
|
||||
din_vld => tx_din_vld,
|
||||
din => tx_din,
|
||||
ctrl_in => tx_ctrl_in,
|
||||
ctrl_out => tx_ctrl_out,
|
||||
mii_tx_clk => mii_tx_clk,
|
||||
mii_tx_en => mii_tx_en,
|
||||
mii_tx_er => mii_tx_er,
|
||||
mii_tx => mii_tx
|
||||
|
||||
);
|
||||
|
||||
gen_dmac:
|
||||
for i in 0 to DMA_NUM_CHANNEL-1 generate
|
||||
|
||||
dma_bus_cmd_cycle_finished(i) <= bus_cmd_cycle_finished;
|
||||
dma_bus_cmd_rdy(i) <= bus_cmd_rdy;
|
||||
|
||||
inst_dmac : entity work.dmac
|
||||
Generic map
|
||||
(
|
||||
DATA_WIDTH => 32,
|
||||
XFER_CHUNK_SIZE => 32
|
||||
)
|
||||
Port map
|
||||
(
|
||||
clk => CLK_I,
|
||||
rst => RST_I,
|
||||
|
||||
master_req => dma_master_req(i),
|
||||
master_gnt => dma_master_gnt(i),
|
||||
|
||||
req_rdy => dma_req_rdy(i),
|
||||
req_en => dma_req_en(i),
|
||||
req_rw => DMA_RW_CONF(i),
|
||||
req_addr_auto_inc => dma_req_addr_auto_inc(i),
|
||||
req_addr_start => dma_req_addr(i),
|
||||
req_num_xfers => dma_req_num_xfers(i),
|
||||
|
||||
req_complete => dma_req_complete(i),
|
||||
req_complete_ack => dma_req_complete_ack(i),
|
||||
|
||||
dma_start => dma_start(i),
|
||||
dma_active => dma_active(i),
|
||||
dma_end => dma_end(i),
|
||||
|
||||
-- busmaster control
|
||||
bus_cyc_complete => dma_bus_cmd_cycle_finished(i),
|
||||
bus_cmd_rdy => dma_bus_cmd_rdy(i),
|
||||
bus_cmd_we => dma_bus_cmd_we(i),
|
||||
bus_cmd_cycle_en => dma_bus_cmd_cycle_en(i),
|
||||
|
||||
-- busmaster command
|
||||
bus_cmd_out => dma_bus_cmd(i)
|
||||
);
|
||||
|
||||
end generate;
|
||||
|
||||
inst_busmaster_sync : entity work.busmaster_sync
|
||||
GENERIC MAP
|
||||
(
|
||||
DATA_WIDTH => 32,
|
||||
FIFO_DEPTH => 4
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
-- System signals
|
||||
rst => RST_I,
|
||||
clk => CLK_I,
|
||||
|
||||
cmd_cycle_finished => bus_cmd_cycle_finished,
|
||||
cmd_cycle_en => bus_cmd_cycle_en,
|
||||
|
||||
cmd_rdy => bus_cmd_rdy,
|
||||
cmd_we => bus_cmd_we,
|
||||
cmd_in => bus_cmd,
|
||||
|
||||
din_rdy => bus_din_rdy,
|
||||
din_we => bus_din_vld,
|
||||
din => bus_din,
|
||||
|
||||
dout => bus_dout,
|
||||
dout_vld => bus_dout_vld,
|
||||
dout_re => bus_dout_re,
|
||||
|
||||
-- JBUS Master signals
|
||||
CYC_O => CYC_O,
|
||||
STB_O => STB_O,
|
||||
WE_O => WE_O,
|
||||
SEL_O => SEL_O,
|
||||
ACK_I => ACK_I,
|
||||
SRDY_I => SRDY_I,
|
||||
MRDY_O => MRDY_O,
|
||||
ADDR_O => ADDR_O,
|
||||
MDAT_I => MDAT_I,
|
||||
MDAT_O => MDAT_O
|
||||
);
|
||||
|
||||
arbiter_proc:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if RST_I = '1' then
|
||||
dma_master_gnt <= (others => '0');
|
||||
arb_idx <= 0;
|
||||
elsif dma_master_req(arb_idx) = '0' then
|
||||
if arb_idx /= DMA_NUM_CHANNEL-1 then
|
||||
arb_idx <= arb_idx + 1;
|
||||
else
|
||||
arb_idx <= 0;
|
||||
end if;
|
||||
else
|
||||
dma_master_gnt <= (others => '0');
|
||||
dma_master_gnt(arb_idx) <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
arbiter_mux:
|
||||
process(dma_master_gnt, dma_bus_cmd, dma_bus_cmd_we, dma_bus_cmd_cycle_en)
|
||||
variable v_bus_cmd_we : std_logic;
|
||||
variable v_bus_cmd_cycle_en : std_logic;
|
||||
begin
|
||||
v_bus_cmd_we := '0';
|
||||
v_bus_cmd_cycle_en := '0';
|
||||
for i in 0 to DMA_NUM_CHANNEL-1 loop
|
||||
v_bus_cmd_we := v_bus_cmd_we or dma_bus_cmd_we(i);
|
||||
v_bus_cmd_cycle_en := v_bus_cmd_cycle_en or dma_bus_cmd_cycle_en(i);
|
||||
if dma_master_gnt(i) = '1' then
|
||||
bus_cmd <= dma_bus_cmd(i);
|
||||
end if;
|
||||
end loop;
|
||||
bus_cmd_we <= v_bus_cmd_we;
|
||||
bus_cmd_cycle_en <= v_bus_cmd_cycle_en;
|
||||
end process;
|
||||
|
||||
end behavior;
|
||||
@@ -1,751 +0,0 @@
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
use std.textio.all; -- Imports the standard textio package.
|
||||
|
||||
use work.emac_types.all;
|
||||
use work.utils_pkg.all;
|
||||
|
||||
ENTITY emac_tx IS
|
||||
Generic
|
||||
(
|
||||
f_sysclk : real := 100.0;
|
||||
RAM_SIZE : natural := 2048
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk : in STD_LOGIC;
|
||||
rst : in STD_LOGIC;
|
||||
din_vld : in STD_LOGIC;
|
||||
din : in unsigned(31 downto 0);
|
||||
ctrl_in : in tx_ctrl_in_t;
|
||||
ctrl_out : out tx_ctrl_out_t;
|
||||
mii_tx_clk : in STD_LOGIC;
|
||||
mii_tx_en : out STD_LOGIC;
|
||||
mii_tx_er : out STD_LOGIC;
|
||||
mii_tx : out unsigned(7 downto 0)
|
||||
|
||||
);
|
||||
END emac_tx;
|
||||
|
||||
ARCHITECTURE behavior OF emac_tx IS
|
||||
|
||||
constant RAM_ADDR_WIDTH : natural := NextExpBaseTwo(RAM_SIZE);
|
||||
|
||||
subtype word_ptr_t is unsigned(RAM_ADDR_WIDTH-1 downto 0);
|
||||
|
||||
signal cmd_fifo_din : unsigned(2*word_ptr_t'length-1 downto 0);
|
||||
signal cmd_fifo_dout : unsigned(2*word_ptr_t'length-1 downto 0);
|
||||
signal cmd_fifo_we : std_logic;
|
||||
signal cmd_fifo_re : std_logic;
|
||||
signal cmd_fifo_empty : std_logic;
|
||||
signal cmd_fifo_full : std_logic;
|
||||
|
||||
signal reset_en : std_logic;
|
||||
|
||||
signal fill_base : word_ptr_t;
|
||||
signal fill_size : word_ptr_t;
|
||||
signal fill_cnt : word_ptr_t;
|
||||
signal fill_ptr : word_ptr_t;
|
||||
signal fill_pre_rdy : std_logic;
|
||||
signal fill_bsy : std_logic;
|
||||
signal fill_remain : unsigned(1 downto 0);
|
||||
signal fill_set : std_logic;
|
||||
signal fill_en : std_logic;
|
||||
signal fill_cnt_en : std_logic;
|
||||
|
||||
signal alloc_OK : std_logic;
|
||||
signal alloc_req : std_logic;
|
||||
signal alloc_ack : std_logic;
|
||||
signal alloc_size : word_ptr_t;
|
||||
signal alloc_remain : unsigned(1 downto 0);
|
||||
|
||||
signal commit_en : std_logic;
|
||||
signal uncommit_en : std_logic;
|
||||
signal mem_alloc_en : std_logic;
|
||||
signal mem_free_en : std_logic;
|
||||
signal nwords_free : word_ptr_t;
|
||||
signal mem_free_req : std_logic;
|
||||
signal mem_free_ack : unsigned(1 downto 0);
|
||||
|
||||
signal xfer_size : word_ptr_t;
|
||||
signal xfer_ptr : word_ptr_t;
|
||||
signal xfer_cnt : word_ptr_t;
|
||||
signal xfer_set : std_logic;
|
||||
signal xfer_en : std_logic;
|
||||
signal xfer_cnt_en : std_logic;
|
||||
signal xfer_bsy : std_logic;
|
||||
signal xfer_free_en : std_logic;
|
||||
|
||||
signal ram_en_a : std_logic;
|
||||
signal ram_we_a : std_logic;
|
||||
signal ram_addr_a : word_ptr_t;
|
||||
signal ram_din_a : unsigned(35 downto 0);
|
||||
signal ram_en_b : std_logic;
|
||||
signal ram_addr_b : word_ptr_t;
|
||||
signal ram_dout_b : unsigned(35 downto 0);
|
||||
|
||||
signal piso32_din : unsigned(31 downto 0);
|
||||
signal piso32_din_be : unsigned(3 downto 0);
|
||||
signal piso32_din_rdy : std_logic;
|
||||
signal piso32_din_vld : std_logic;
|
||||
|
||||
signal piso32_dout : unsigned(7 downto 0);
|
||||
signal piso32_dout_vld : std_logic;
|
||||
signal piso32_dout_en : std_logic;
|
||||
|
||||
signal piso8_dout_vld : std_logic;
|
||||
signal piso8_din_rdy : std_logic;
|
||||
signal piso8_din_vld : std_logic;
|
||||
signal piso8_dout : unsigned(3 downto 0);
|
||||
signal piso8_din : unsigned(7 downto 0);
|
||||
|
||||
signal reset_pipe : unsigned(31 downto 0);
|
||||
signal Gbps_en : std_logic;
|
||||
signal fcs_gen_en : std_logic;
|
||||
|
||||
signal fcs_inject_en : std_logic;
|
||||
signal fcs_rst : std_logic;
|
||||
signal fcs_en : unsigned(7 downto 0);
|
||||
signal fcs_vld : std_logic;
|
||||
signal fcs_din_vld : std_logic;
|
||||
signal fcs : unsigned(31 downto 0);
|
||||
signal fcs_rev_endian : unsigned(31 downto 0);
|
||||
|
||||
signal mii_fifo_we : std_logic;
|
||||
signal mii_fifo_re : std_logic;
|
||||
signal mii_fifo_full : std_logic;
|
||||
signal mii_fifo_empty : std_logic;
|
||||
signal mii_fifo_re_dly : unsigned(23 downto 0);
|
||||
|
||||
signal mii_bsy : std_logic;
|
||||
|
||||
type host_state_t is (host_init, host_idle, host_alloc, host_setup, host_arm, host_fill, host_commit);
|
||||
signal host_s, host_sn : host_state_t;
|
||||
|
||||
type xfer_state_t is (xfer_init, xfer_idle, xfer_start, xfer_preamble0, xfer_preamble1, xfer_active, xfer_crc, xfer_stop, xfer_finish);
|
||||
signal xfer_s, xfer_sn : xfer_state_t;
|
||||
|
||||
type piso_byte_mask_array_t is array (0 to 3) of unsigned (3 downto 0);
|
||||
constant piso_byte_mask_rom : piso_byte_mask_array_t :=
|
||||
(
|
||||
"1111",
|
||||
"1000",
|
||||
"1100",
|
||||
"1110"
|
||||
);
|
||||
|
||||
signal preamble_en : std_logic;
|
||||
signal preamble_addr : natural range 0 to 1;
|
||||
type preamble_t is array (0 to 1) of unsigned(31 downto 0);
|
||||
constant preamble : preamble_t :=
|
||||
(
|
||||
X"55555555",
|
||||
X"555555D5"
|
||||
);
|
||||
|
||||
|
||||
begin
|
||||
|
||||
ctrl_out.pkt_alloc_req <= alloc_req;
|
||||
ctrl_out.pkt_done <= cmd_fifo_empty;
|
||||
ctrl_out.reset_busy <= reset_en;
|
||||
|
||||
ram_en_a <= din_vld;
|
||||
ram_we_a <= fill_bsy;
|
||||
ram_din_a(31 downto 0) <= din;
|
||||
ram_din_a(35 downto 32) <= piso_byte_mask_rom(to_integer(fill_remain)) when fill_pre_rdy = '1' else "1111";
|
||||
ram_addr_a <= fill_ptr;
|
||||
|
||||
piso32_din <= preamble(preamble_addr) when preamble_en = '1' else fcs_rev_endian when fcs_inject_en = '1' else ram_dout_b(31 downto 0);
|
||||
piso32_din_be <= "1111" when (preamble_en = '1' or fcs_inject_en = '1') else ram_dout_b(35 downto 32);
|
||||
|
||||
cmd_fifo_we <= commit_en;
|
||||
cmd_fifo_re <= uncommit_en;
|
||||
cmd_fifo_din <= fill_size & fill_base;
|
||||
ram_en_b <= piso32_din_rdy;
|
||||
ram_addr_b <= xfer_ptr;
|
||||
|
||||
reset_en <= reset_pipe(reset_pipe'left);
|
||||
|
||||
xfer_cnt_en <= xfer_bsy and piso32_din_rdy;
|
||||
fill_cnt_en <= fill_bsy and din_vld;
|
||||
mem_free_en <= not mem_free_ack(0) and mem_free_ack(1);
|
||||
|
||||
fcs_rev_endian <= fcs(7 downto 0) & fcs(15 downto 8) & fcs(23 downto 16) & fcs(31 downto 24);
|
||||
|
||||
------------------------------------------------------------------
|
||||
reset_gen:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' or ctrl_in.reset = '1' then
|
||||
reset_pipe <= (others => '1');
|
||||
else
|
||||
reset_pipe <= reset_pipe(reset_pipe'left-1 downto 0) & '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
host_state_next:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if reset_en = '1' then
|
||||
host_s <= host_init;
|
||||
else
|
||||
host_s <= host_sn;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
host_state:
|
||||
process(host_s, alloc_OK, fill_bsy, ctrl_in.pkt_commit_en, alloc_req, mem_free_ack)
|
||||
begin
|
||||
|
||||
fill_set <= '0';
|
||||
fill_en <= '0';
|
||||
commit_en <= '0';
|
||||
alloc_ack <= '0';
|
||||
mem_alloc_en <= '0';
|
||||
|
||||
host_sn <= host_s;
|
||||
|
||||
case host_s is
|
||||
|
||||
when host_init =>
|
||||
host_sn <= host_idle;
|
||||
|
||||
when host_idle =>
|
||||
if alloc_req = '1' then
|
||||
host_sn <= host_alloc;
|
||||
end if;
|
||||
|
||||
when host_alloc =>
|
||||
if alloc_OK = '1' then
|
||||
host_sn <= host_setup;
|
||||
else
|
||||
host_sn <= host_idle;
|
||||
alloc_ack <= '1';
|
||||
end if;
|
||||
|
||||
when host_setup =>
|
||||
fill_set <= '1';
|
||||
host_sn <= host_arm;
|
||||
|
||||
when host_arm =>
|
||||
fill_en <= '1';
|
||||
alloc_ack <= '1';
|
||||
host_sn <= host_fill;
|
||||
|
||||
when host_fill =>
|
||||
fill_en <= '1';
|
||||
if alloc_req = '1' then
|
||||
host_sn <= host_alloc;
|
||||
elsif ctrl_in.pkt_commit_en = '1' then
|
||||
host_sn <= host_commit;
|
||||
end if;
|
||||
|
||||
when host_commit =>
|
||||
if mem_free_ack = "00" then
|
||||
commit_en <= '1';
|
||||
mem_alloc_en <= '1';
|
||||
host_sn <= host_idle;
|
||||
end if;
|
||||
|
||||
when others =>
|
||||
host_sn <= host_idle;
|
||||
end case;
|
||||
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
-- Allocation stuff
|
||||
------------------------------------------------------------------
|
||||
alloc_request_logic:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if reset_en = '1' then
|
||||
alloc_req <= '0';
|
||||
elsif ctrl_in.pkt_alloc_en = '1' and alloc_req = '0' then
|
||||
alloc_req <= '1';
|
||||
alloc_remain <= ctrl_in.tx_size(1 downto 0);
|
||||
alloc_size <= ctrl_in.tx_size(word_ptr_t'left+2 downto 2);
|
||||
if ctrl_in.tx_size(1 downto 0) /= "00" then
|
||||
alloc_size <= ctrl_in.tx_size(word_ptr_t'left+2 downto 2) + 1;
|
||||
end if;
|
||||
ctrl_out.tx_size <= resize(ctrl_in.tx_size(word_ptr_t'left downto 0), 16);
|
||||
elsif alloc_ack = '1' then
|
||||
alloc_req <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
host_alloc_armed_register:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if reset_en = '1' or commit_en = '1' then
|
||||
ctrl_out.pkt_armed <= '0';
|
||||
elsif alloc_ack = '1' then
|
||||
ctrl_out.pkt_armed <= alloc_OK;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
alloc_eval_logic:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
alloc_OK <= '0';
|
||||
if alloc_size < nwords_free then
|
||||
alloc_OK <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
fill_base_logic:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if reset_en = '1' then
|
||||
fill_base <= (others => '0');
|
||||
elsif commit_en = '1' then
|
||||
fill_base <= fill_ptr;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
mem_free_counter:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if reset_en = '1' then
|
||||
nwords_free <= (others => '1');
|
||||
elsif mem_alloc_en = '1' then
|
||||
nwords_free <= nwords_free - fill_size;
|
||||
elsif mem_free_en = '1' then
|
||||
nwords_free <= nwords_free + xfer_size;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
mem_free_mii:
|
||||
process(mii_tx_clk)
|
||||
begin
|
||||
if rising_edge(mii_tx_clk) then
|
||||
if reset_en = '1' then
|
||||
mem_free_req <= '0';
|
||||
elsif mem_free_ack(0) = '0' then
|
||||
if xfer_free_en = '1' then
|
||||
mem_free_req <= '1';
|
||||
end if;
|
||||
else
|
||||
mem_free_req <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
mem_free_host:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
mem_free_ack(1) <= mem_free_ack(0);
|
||||
if reset_en = '1' then
|
||||
mem_free_ack <= "00";
|
||||
elsif mem_free_req = '1' then
|
||||
if mem_alloc_en = '0' then
|
||||
mem_free_ack(0) <= '1';
|
||||
end if;
|
||||
else
|
||||
mem_free_ack(0) <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
-- Fill stuff
|
||||
------------------------------------------------------------------
|
||||
fill_counter:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if fill_set = '1' then
|
||||
fill_bsy <= '0';
|
||||
fill_pre_rdy <= '0';
|
||||
fill_cnt <= alloc_size;
|
||||
fill_size <= alloc_size;
|
||||
fill_remain <= alloc_remain;
|
||||
elsif fill_en = '1' then
|
||||
fill_bsy <= '1';
|
||||
if fill_cnt_en = '1' or fill_bsy = '0' then
|
||||
if fill_cnt /= 1 then
|
||||
fill_cnt <= fill_cnt - 1;
|
||||
else
|
||||
fill_pre_rdy <= '1';
|
||||
end if;
|
||||
if fill_pre_rdy = '1' then
|
||||
fill_bsy <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
fill_pointer:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if fill_set = '1' then
|
||||
fill_ptr <= fill_base;
|
||||
elsif fill_cnt_en = '1' then
|
||||
fill_ptr <= fill_ptr + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
-- Transfer stuff
|
||||
------------------------------------------------------------------
|
||||
host2xfer_sync_register:
|
||||
process(mii_tx_clk)
|
||||
begin
|
||||
if rising_edge(mii_tx_clk) then
|
||||
Gbps_en <= ctrl_in.Gbps_en;
|
||||
fcs_gen_en <= ctrl_in.fcs_gen_en;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
xfer_counter:
|
||||
process(mii_tx_clk)
|
||||
begin
|
||||
if rising_edge(mii_tx_clk) then
|
||||
xfer_bsy <= '0';
|
||||
if xfer_set = '1' then
|
||||
xfer_cnt <= cmd_fifo_dout(cmd_fifo_dout'left downto word_ptr_t'length);
|
||||
xfer_size <= (others => '0');
|
||||
elsif xfer_en = '1' then
|
||||
xfer_bsy <= '1';
|
||||
if xfer_cnt_en = '1' or xfer_bsy = '0' then
|
||||
if xfer_cnt /= 0 then
|
||||
xfer_cnt <= xfer_cnt - 1;
|
||||
xfer_size <= xfer_size + 1;
|
||||
else
|
||||
xfer_bsy <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
xfer_pointer:
|
||||
process(mii_tx_clk)
|
||||
begin
|
||||
if rising_edge(mii_tx_clk) then
|
||||
if xfer_set = '1' then
|
||||
xfer_ptr <= cmd_fifo_dout(xfer_ptr'left downto 0);
|
||||
elsif xfer_en = '1' then
|
||||
if xfer_bsy = '0' or xfer_cnt_en = '1' then
|
||||
xfer_ptr <= xfer_ptr + 1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
xfer_state_next:
|
||||
process(mii_tx_clk)
|
||||
begin
|
||||
if rising_edge(mii_tx_clk) then
|
||||
if reset_en = '1' then
|
||||
xfer_s <= xfer_init;
|
||||
else
|
||||
xfer_s <= xfer_sn;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
xfer_state:
|
||||
process(xfer_s, mii_bsy, cmd_fifo_empty, piso32_din_rdy, piso32_dout_vld, xfer_bsy, fcs_gen_en)
|
||||
begin
|
||||
|
||||
piso32_din_vld <= '0';
|
||||
preamble_en <= '0';
|
||||
preamble_addr <= 0;
|
||||
xfer_set <= '0';
|
||||
xfer_en <= '0';
|
||||
xfer_free_en <= '0';
|
||||
fcs_rst <= '0';
|
||||
fcs_inject_en <= '0';
|
||||
uncommit_en <= '0';
|
||||
|
||||
xfer_sn <= xfer_s;
|
||||
|
||||
case xfer_s is
|
||||
|
||||
when xfer_init =>
|
||||
xfer_sn <= xfer_idle;
|
||||
|
||||
when xfer_idle =>
|
||||
if cmd_fifo_empty = '0' and mii_bsy = '0' then
|
||||
xfer_sn <= xfer_start;
|
||||
end if;
|
||||
|
||||
when xfer_start =>
|
||||
if cmd_fifo_empty = '0' then
|
||||
xfer_sn <= xfer_preamble0;
|
||||
end if;
|
||||
|
||||
when xfer_preamble0 =>
|
||||
xfer_set <= '1';
|
||||
fcs_rst <= '1';
|
||||
preamble_addr <= 0;
|
||||
preamble_en <= '1';
|
||||
piso32_din_vld <= '1';
|
||||
if piso32_din_rdy = '1' then
|
||||
xfer_sn <= xfer_preamble1;
|
||||
end if;
|
||||
|
||||
when xfer_preamble1 =>
|
||||
preamble_addr <= 1;
|
||||
preamble_en <= '1';
|
||||
piso32_din_vld <= '1';
|
||||
if piso32_din_rdy = '1' then
|
||||
xfer_sn <= xfer_active;
|
||||
xfer_en <= '1';
|
||||
end if;
|
||||
|
||||
when xfer_active =>
|
||||
piso32_din_vld <= xfer_bsy;
|
||||
xfer_en <= '1';
|
||||
if xfer_bsy = '0' then
|
||||
xfer_sn <= xfer_stop;
|
||||
end if;
|
||||
|
||||
when xfer_stop =>
|
||||
if piso32_dout_vld = '0' then
|
||||
xfer_sn <= xfer_finish;
|
||||
if fcs_gen_en = '1' then
|
||||
xfer_sn <= xfer_crc;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when xfer_crc =>
|
||||
fcs_inject_en <= piso32_din_rdy;
|
||||
piso32_din_vld <= '1';
|
||||
if piso32_din_rdy = '1' then
|
||||
xfer_sn <= xfer_finish;
|
||||
end if;
|
||||
|
||||
when xfer_finish =>
|
||||
uncommit_en <= '1';
|
||||
xfer_free_en <= '1';
|
||||
xfer_sn <= xfer_idle;
|
||||
|
||||
when others =>
|
||||
xfer_sn <= xfer_idle;
|
||||
end case;
|
||||
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
inst_ram : entity work.dpram_1w1r2c_ro
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => RAM_ADDR_WIDTH,
|
||||
data_width => ram_din_a'length
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
clk_a => clk,
|
||||
clk_b => mii_tx_clk,
|
||||
en_a => ram_en_a,
|
||||
en_b => ram_en_b,
|
||||
we_a => ram_we_a,
|
||||
addr_a => ram_addr_a,
|
||||
addr_b => ram_addr_b,
|
||||
din_a => ram_din_a,
|
||||
dout_b => ram_dout_b
|
||||
);
|
||||
|
||||
------------------------------------------------------------------
|
||||
-- Instantiate synchronous FIFO
|
||||
inst_cmd_fifo: entity work.fifo_async
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => NextExpBaseTwo(RAM_SIZE) - 4, -- RAMSIZE(words)/MIN_PACKET_LEN(words)
|
||||
data_width => cmd_fifo_din'length,
|
||||
do_last_read_update => true
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => reset_en,
|
||||
clk_w => clk,
|
||||
clk_r => mii_tx_clk,
|
||||
we => cmd_fifo_we,
|
||||
re => cmd_fifo_re,
|
||||
fifo_full => cmd_fifo_full,
|
||||
fifo_empty => cmd_fifo_empty,
|
||||
fifo_afull => open,
|
||||
fifo_aempty => open,
|
||||
data_w => cmd_fifo_din,
|
||||
data_r => cmd_fifo_dout
|
||||
);
|
||||
|
||||
------------------------------------------------------------------
|
||||
inst_piso32 : entity work.piso
|
||||
GENERIC MAP
|
||||
(
|
||||
data_width_in => 32,
|
||||
data_width_out => 8,
|
||||
msb_first => true
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => reset_en,
|
||||
clk => mii_tx_clk,
|
||||
din_vld => piso32_din_vld,
|
||||
din_rdy => piso32_din_rdy,
|
||||
din_be => piso32_din_be,
|
||||
din => piso32_din,
|
||||
dout_vld => piso32_dout_vld,
|
||||
dout_en => piso32_dout_en,
|
||||
dout => piso32_dout
|
||||
|
||||
);
|
||||
|
||||
piso32_dout_en <= not mii_fifo_full; --'1' when Gbps_en = '1' else piso8_din_rdy;
|
||||
|
||||
------------------------------------------------------------------
|
||||
fcs_enable_gen:
|
||||
process(mii_tx_clk)
|
||||
begin
|
||||
if rising_edge(mii_tx_clk) then
|
||||
if fcs_rst = '1' then
|
||||
fcs_en <= (others => '0');
|
||||
elsif piso32_dout_vld = '1' then
|
||||
fcs_en <= fcs_en(fcs_en'left-1 downto 0) & '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
inst_fcs: entity work.crc32
|
||||
GENERIC MAP
|
||||
(
|
||||
crc32_init => X"00000000"
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => fcs_rst,
|
||||
clk => mii_tx_clk,
|
||||
din_vld => fcs_din_vld,
|
||||
din => piso32_dout,
|
||||
crc32_vld => fcs_vld,
|
||||
crc32_out => fcs
|
||||
|
||||
);
|
||||
|
||||
fcs_din_vld <= fcs_en(fcs_en'left) and piso32_dout_vld and piso32_dout_en;
|
||||
|
||||
------------------------------------------------------------------
|
||||
-- ensures continous MII-data stream and also acts as Inter Frame Gap delay
|
||||
mii_fifo_re_dly_gen:
|
||||
process(mii_tx_clk)
|
||||
begin
|
||||
if rising_edge(mii_tx_clk) then
|
||||
if mii_fifo_empty = '1' then
|
||||
if Gbps_en = '0' then
|
||||
mii_fifo_re_dly <= X"000000"; -- 100 mbps
|
||||
else
|
||||
mii_fifo_re_dly <= X"000FFF"; -- Gigabit
|
||||
end if;
|
||||
else
|
||||
mii_fifo_re_dly <= mii_fifo_re_dly(mii_fifo_re_dly'left-1 downto 0) & not mii_fifo_empty;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
mii_bsy <= mii_fifo_re_dly(mii_fifo_re_dly'left);
|
||||
|
||||
------------------------------------------------------------------
|
||||
-- Instantiate synchronous FIFO
|
||||
inst_mii_fifo: entity work.fifo_sync
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => 4,
|
||||
data_width => piso32_dout'length,
|
||||
do_last_read_update => true
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => reset_en,
|
||||
clk => mii_tx_clk,
|
||||
we => mii_fifo_we,
|
||||
re => mii_fifo_re,
|
||||
fifo_full => mii_fifo_full,
|
||||
fifo_empty => mii_fifo_empty,
|
||||
fifo_afull => open,
|
||||
fifo_aempty => open,
|
||||
data_w => piso32_dout,
|
||||
data_r => piso8_din
|
||||
);
|
||||
|
||||
mii_fifo_re <= mii_bsy when Gbps_en = '1' else (piso8_din_rdy and mii_bsy);
|
||||
mii_fifo_we <= piso32_dout_vld;
|
||||
|
||||
------------------------------------------------------------------
|
||||
inst_piso8 : entity work.piso
|
||||
GENERIC MAP
|
||||
(
|
||||
data_width_in => 8,
|
||||
data_width_out => 4,
|
||||
msb_first => false
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => reset_en,
|
||||
clk => mii_tx_clk,
|
||||
din_vld => piso8_din_vld,
|
||||
din_rdy => piso8_din_rdy,
|
||||
din_be => "11",
|
||||
din => piso8_din,
|
||||
dout_vld => piso8_dout_vld,
|
||||
dout_en => '1',
|
||||
dout => piso8_dout
|
||||
|
||||
);
|
||||
|
||||
piso8_din_vld <= not mii_fifo_empty and mii_bsy;
|
||||
|
||||
------------------------------------------------------------------
|
||||
mii_output_register:
|
||||
process(mii_tx_clk)
|
||||
begin
|
||||
if rising_edge(mii_tx_clk) then
|
||||
mii_tx_er <= '0';
|
||||
if Gbps_en = '1' then
|
||||
mii_tx_en <= piso8_din_vld;
|
||||
mii_tx <= piso8_din;
|
||||
else
|
||||
mii_tx_en <= piso8_dout_vld;
|
||||
mii_tx <= "0000" & piso8_dout;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
end behavior;
|
||||
@@ -1,63 +0,0 @@
|
||||
-- Package File Template
|
||||
--
|
||||
-- Purpose: This package defines supplemental types, subtypes,
|
||||
-- constants, and functions
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
use IEEE.MATH_REAL.ALL;
|
||||
|
||||
package emac_types is
|
||||
|
||||
-- Constants
|
||||
type mac_addr_t is array (0 to 5) of unsigned (7 downto 0);
|
||||
|
||||
-- Types
|
||||
type tx_ctrl_in_t is record
|
||||
Gbps_en : std_logic;
|
||||
reset : std_logic;
|
||||
fcs_gen_en : std_logic;
|
||||
tx_size : unsigned(15 downto 0);
|
||||
pkt_commit_en : std_logic;
|
||||
pkt_alloc_en : std_logic;
|
||||
end record;
|
||||
|
||||
type tx_ctrl_out_t is record
|
||||
tx_size : unsigned(15 downto 0);
|
||||
pkt_done : std_logic;
|
||||
pkt_alloc_req : std_logic;
|
||||
pkt_armed : std_logic;
|
||||
reset_busy : std_logic;
|
||||
end record;
|
||||
|
||||
type rx_ctrl_in_t is record
|
||||
Gbps_en : std_logic;
|
||||
reset : std_logic;
|
||||
fcs_chk_en : std_logic;
|
||||
pkt_req_en : std_logic;
|
||||
pkt_free_en : std_logic;
|
||||
mac_addr : mac_addr_t;
|
||||
promiscious : std_logic;
|
||||
end record;
|
||||
|
||||
type rx_ctrl_out_t is record
|
||||
pkt_avail : std_logic;
|
||||
pkt_valid : std_logic;
|
||||
pkt_bcast : std_logic;
|
||||
pkt_mac_match : std_logic;
|
||||
rx_size : unsigned(15 downto 0);
|
||||
reset_busy : std_logic;
|
||||
end record;
|
||||
|
||||
-- Functions
|
||||
|
||||
end emac_types;
|
||||
|
||||
|
||||
package body emac_types is
|
||||
|
||||
end emac_types;
|
||||
|
||||
|
||||
@@ -1,124 +0,0 @@
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
use std.textio.all; -- Imports the standard textio package.
|
||||
|
||||
use work.utils_pkg.all; -- Imports the standard textio package.
|
||||
|
||||
ENTITY piso IS
|
||||
Generic
|
||||
(
|
||||
data_width_in : natural := 32;
|
||||
data_width_out : natural := 8;
|
||||
msb_first : boolean := false
|
||||
);
|
||||
Port
|
||||
(
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
din_vld : in STD_LOGIC;
|
||||
din_rdy : out STD_LOGIC;
|
||||
din_be : in unsigned(data_width_in/data_width_out-1 downto 0);
|
||||
din : in unsigned(data_width_in-1 downto 0);
|
||||
dout_vld : out STD_LOGIC;
|
||||
dout_en : in STD_LOGIC;
|
||||
dout : out unsigned(data_width_out-1 downto 0)
|
||||
|
||||
);
|
||||
END piso;
|
||||
|
||||
ARCHITECTURE behavior OF piso IS
|
||||
|
||||
constant num_shifts : natural := data_width_in/data_width_out;
|
||||
signal pre_fin : STD_LOGIC;
|
||||
signal shift_cnt_pipe : unsigned(num_shifts-1 downto 0);
|
||||
signal shift_pipe : unsigned(data_width_in-1 downto 0);
|
||||
signal vld_pipe : unsigned(num_shifts-1 downto 0);
|
||||
signal din_reg : unsigned(data_width_in-1 downto 0);
|
||||
signal din_be_reg : unsigned(num_shifts-1 downto 0);
|
||||
signal din_reg_empty : STD_LOGIC;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
begin
|
||||
|
||||
pre_fin <= shift_cnt_pipe(shift_cnt_pipe'left-1);
|
||||
din_rdy <= din_reg_empty;
|
||||
dout_vld <= vld_pipe(vld_pipe'left) when msb_first else vld_pipe(0);
|
||||
dout <= shift_pipe(shift_pipe'left downto shift_pipe'left-data_width_out+1) when msb_first
|
||||
else shift_pipe(data_width_out-1 downto 0);
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
din_reg_empty <= '1';
|
||||
elsif din_reg_empty = '1' then
|
||||
if din_vld = '1' then
|
||||
din_reg_empty <= '0';
|
||||
end if;
|
||||
elsif pre_fin = '1' and dout_en = '1' then
|
||||
din_reg_empty <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if din_vld = '1' and din_reg_empty = '1' then
|
||||
din_reg <= din;
|
||||
din_be_reg <= din_be;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
shift_cnt_pipe <= (others => '1');
|
||||
elsif (pre_fin = '1' and dout_en = '1' and din_reg_empty = '0') then
|
||||
shift_cnt_pipe <= (others => '0');
|
||||
elsif dout_en = '1' then
|
||||
shift_cnt_pipe <= shift_cnt_pipe(shift_cnt_pipe'left-1 downto 0) & '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if (pre_fin = '1' and dout_en = '1' and din_reg_empty = '0') then
|
||||
shift_pipe <= din_reg;
|
||||
elsif dout_en = '1' then
|
||||
if (msb_first) then
|
||||
shift_pipe <= shift_pipe(shift_pipe'left-data_width_out downto 0) & (data_width_out-1 downto 0 => '0');
|
||||
else
|
||||
shift_pipe <= (data_width_out-1 downto 0 => '0') & shift_pipe(shift_pipe'left downto data_width_out);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
vld_pipe <= (others => '0');
|
||||
elsif (pre_fin = '1' and dout_en = '1' and din_reg_empty = '0') then
|
||||
vld_pipe <= din_be_reg;
|
||||
elsif dout_en = '1' then
|
||||
if (msb_first) then
|
||||
vld_pipe <= vld_pipe(vld_pipe'left-1 downto 0) & '0';
|
||||
else
|
||||
vld_pipe <= '0' & vld_pipe(vld_pipe'left downto 1);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
end behavior;
|
||||
@@ -1,230 +0,0 @@
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
USE IEEE.MATH_REAL.ALL;
|
||||
use std.textio.all; -- Imports the standard textio package.
|
||||
|
||||
use work.emac_types.all;
|
||||
use work.utils_pkg.all;
|
||||
|
||||
ENTITY pkt_gen IS
|
||||
Generic
|
||||
(
|
||||
f_sysclk : real := 100.0;
|
||||
TX_RAM_SIZE : natural := 2048;
|
||||
PKT_SIZE_MIN : natural := 64;
|
||||
PKT_SIZE_MAX : natural := 1518
|
||||
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk : in STD_LOGIC;
|
||||
rst : in STD_LOGIC;
|
||||
en : in STD_LOGIC;
|
||||
gigabit_en : in STD_LOGIC;
|
||||
fcs_gen_en : in STD_LOGIC;
|
||||
mii_tx_clk : in STD_LOGIC;
|
||||
mii_tx_en : out STD_LOGIC;
|
||||
mii_tx_er : out STD_LOGIC;
|
||||
mii_tx : out unsigned(7 downto 0)
|
||||
|
||||
);
|
||||
END pkt_gen;
|
||||
|
||||
ARCHITECTURE behavior OF pkt_gen IS
|
||||
|
||||
subtype word_ptr_t is unsigned(15 downto 0);
|
||||
|
||||
signal pkt_data : unsigned(31 downto 0);
|
||||
signal pkt_nbytes : word_ptr_t := X"0040";
|
||||
signal pkt_nwords : word_ptr_t := X"0010";
|
||||
|
||||
signal fill_size : word_ptr_t;
|
||||
signal fill_cnt : word_ptr_t;
|
||||
signal fill_rdy : std_logic;
|
||||
signal fill_set : std_logic;
|
||||
signal fill_en : std_logic;
|
||||
|
||||
signal tx_packets : natural;
|
||||
signal tx_bytes : natural;
|
||||
|
||||
signal tx_ctrl_in : tx_ctrl_in_t;
|
||||
signal tx_ctrl_out : tx_ctrl_out_t;
|
||||
signal tx_din : unsigned(31 downto 0);
|
||||
signal tx_din_vld : std_logic;
|
||||
|
||||
type host_state_t is (host_init, host_idle, host_alloc, host_setup, host_arm, host_fill, host_commit);
|
||||
signal host_s, host_sn : host_state_t;
|
||||
|
||||
begin
|
||||
|
||||
------------------------------------------------------------------
|
||||
host_state_next:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
host_s <= host_init;
|
||||
else
|
||||
host_s <= host_sn;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
host_state:
|
||||
process(host_s, tx_ctrl_out, pkt_nbytes, fill_rdy, en, gigabit_en, fcs_gen_en)
|
||||
begin
|
||||
|
||||
tx_ctrl_in.pkt_alloc_en <= '0';
|
||||
tx_ctrl_in.pkt_commit_en <= '0';
|
||||
tx_ctrl_in.reset <= '0';
|
||||
tx_ctrl_in.Gbps_en <= gigabit_en;
|
||||
tx_ctrl_in.fcs_gen_en <= fcs_gen_en;
|
||||
tx_ctrl_in.tx_size <= pkt_nbytes;
|
||||
fill_set <= '0';
|
||||
fill_en <= '0';
|
||||
|
||||
host_sn <= host_s;
|
||||
|
||||
case host_s is
|
||||
|
||||
when host_init =>
|
||||
if tx_ctrl_out.reset_busy = '0' then
|
||||
host_sn <= host_idle;
|
||||
end if;
|
||||
|
||||
when host_idle =>
|
||||
if tx_ctrl_out.pkt_alloc_req = '0' and en = '1' then
|
||||
tx_ctrl_in.pkt_alloc_en <= '1';
|
||||
host_sn <= host_alloc;
|
||||
end if;
|
||||
|
||||
when host_alloc =>
|
||||
if tx_ctrl_out.pkt_alloc_req = '0' then
|
||||
if tx_ctrl_out.pkt_armed = '1' then
|
||||
host_sn <= host_setup;
|
||||
else
|
||||
host_sn <= host_idle;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when host_setup =>
|
||||
fill_set <= '1';
|
||||
host_sn <= host_fill;
|
||||
|
||||
when host_fill =>
|
||||
fill_en <= '1';
|
||||
if fill_rdy = '1' then
|
||||
host_sn <= host_commit;
|
||||
end if;
|
||||
|
||||
when host_commit =>
|
||||
tx_ctrl_in.pkt_commit_en <= '1';
|
||||
host_sn <= host_idle;
|
||||
|
||||
when others =>
|
||||
host_sn <= host_idle;
|
||||
end case;
|
||||
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
pkt_generator:
|
||||
process(clk)
|
||||
variable size : word_ptr_t;
|
||||
variable krand : real;
|
||||
variable seed1 : integer;
|
||||
variable seed2 : integer;
|
||||
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
size := to_unsigned(PKT_SIZE_MIN, word_ptr_t'length);
|
||||
seed1 := 31101970;
|
||||
seed2 := 12586901;
|
||||
tx_packets <= 0;
|
||||
tx_bytes <= 0;
|
||||
elsif tx_ctrl_in.pkt_commit_en = '1' then
|
||||
uniform(seed1, seed2, krand);
|
||||
size := to_unsigned(PKT_SIZE_MIN + natural(real(PKT_SIZE_MAX-PKT_SIZE_MIN)*krand), word_ptr_t'length);
|
||||
tx_packets <= tx_packets + 1;
|
||||
tx_bytes <= tx_bytes + to_integer(pkt_nbytes);
|
||||
end if;
|
||||
pkt_nbytes <= size;
|
||||
if size(1 downto 0) = 0 then
|
||||
pkt_nwords <= "00" & size(word_ptr_t'left downto 2);
|
||||
else
|
||||
pkt_nwords <= "00" & size(word_ptr_t'left downto 2) + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
pkt_data_gen:
|
||||
process(clk)
|
||||
variable data : unsigned(7 downto 0);
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
tx_din_vld <= fill_en;
|
||||
if fill_set = '1' then
|
||||
data := X"00";
|
||||
tx_din <= X"03020100";
|
||||
elsif fill_en = '1' then
|
||||
tx_din(7 downto 0) <= data;
|
||||
data := data + 1;
|
||||
tx_din(15 downto 8) <= data;
|
||||
data := data + 1;
|
||||
tx_din(23 downto 16) <= data;
|
||||
data := data + 1;
|
||||
tx_din(31 downto 24) <= data;
|
||||
data := data + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
pkt_data_counter:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if fill_set = '1' then
|
||||
fill_size <= (others => '0');
|
||||
fill_rdy <= '0';
|
||||
fill_cnt <= pkt_nwords;
|
||||
elsif fill_en = '1' then
|
||||
if fill_cnt /= 0 then
|
||||
fill_cnt <= fill_cnt - 1;
|
||||
fill_size <= fill_size + 1;
|
||||
else
|
||||
fill_rdy <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
inst_emac_tx : entity work.emac_tx
|
||||
GENERIC MAP
|
||||
(
|
||||
f_sysclk => f_sysclk,
|
||||
RAM_SIZE => TX_RAM_SIZE
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
clk => clk,
|
||||
rst => rst,
|
||||
din_vld => tx_din_vld,
|
||||
din => tx_din,
|
||||
ctrl_in => tx_ctrl_in,
|
||||
ctrl_out => tx_ctrl_out,
|
||||
mii_tx_clk => mii_tx_clk,
|
||||
mii_tx_en => mii_tx_en,
|
||||
mii_tx_er => mii_tx_er,
|
||||
mii_tx => mii_tx
|
||||
|
||||
);
|
||||
|
||||
|
||||
end behavior;
|
||||
@@ -1,111 +0,0 @@
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
use std.textio.all; -- Imports the standard textio package.
|
||||
|
||||
use work.utils_pkg.all; -- Imports the standard textio package.
|
||||
|
||||
ENTITY shifter IS
|
||||
Generic
|
||||
(
|
||||
data_width : natural := 32;
|
||||
aggregate_size : natural := 8;
|
||||
do_pipelined : boolean := true
|
||||
);
|
||||
Port
|
||||
(
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
sa : in integer;
|
||||
din_vld : in STD_LOGIC;
|
||||
din : in unsigned(data_width-1 downto 0);
|
||||
dout_vld : out STD_LOGIC;
|
||||
dout : out unsigned(data_width-1 downto 0)
|
||||
|
||||
);
|
||||
END shifter;
|
||||
|
||||
ARCHITECTURE behavior OF shifter IS
|
||||
|
||||
constant num_rounds : natural := NextExpBaseTwo(data_width/aggregate_size);
|
||||
subtype sa_rnd_t is signed(num_rounds-1 downto 0);
|
||||
subtype word_t is unsigned(data_width-1 downto 0);
|
||||
type word_array_t is array (0 to num_rounds) of word_t;
|
||||
|
||||
signal rot_data : word_array_t;
|
||||
signal sa_rnd : sa_rnd_t;
|
||||
|
||||
type sa_rnd_array_t is array (0 to num_rounds) of sa_rnd_t;
|
||||
signal sa_rnd_pipe : sa_rnd_array_t;
|
||||
signal dout_vld_pipe : unsigned(0 to num_rounds);
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
function rol_stage(x : unsigned; en : std_logic; stage_num : natural; size : natural) return unsigned is
|
||||
variable result : unsigned(x'range);
|
||||
constant sa : natural := (2**stage_num) * size;
|
||||
begin
|
||||
if en = '1' then
|
||||
result := x(x'left-sa downto 0) & x(x'left downto x'length-sa);
|
||||
else
|
||||
result := x;
|
||||
end if;
|
||||
return result;
|
||||
end rol_stage;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
begin
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
gen_non_pipelined:
|
||||
if do_pipelined = false generate
|
||||
begin
|
||||
|
||||
rot_data(0) <= din;
|
||||
|
||||
gen_rotate_right:
|
||||
for stage in 0 to num_rounds-1 generate
|
||||
begin
|
||||
rot_data(stage+1) <= rol_stage(rot_data(stage), sa_rnd(stage), stage, aggregate_size);
|
||||
end generate;
|
||||
|
||||
sa_rnd <= to_signed(sa, num_rounds);
|
||||
dout <= rot_data(num_rounds);
|
||||
dout_vld <= din_vld;
|
||||
|
||||
end generate;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
gen_pipelined:
|
||||
if do_pipelined = true generate
|
||||
begin
|
||||
|
||||
rot_data(0) <= din;
|
||||
sa_rnd_pipe(0) <= to_signed(sa, num_rounds);
|
||||
dout_vld_pipe(0) <= din_vld;
|
||||
|
||||
gen_rotate_right:
|
||||
for stage in 0 to num_rounds-1 generate
|
||||
begin
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
dout_vld_pipe(stage+1) <= '0';
|
||||
else
|
||||
dout_vld_pipe(stage+1) <= dout_vld_pipe(stage);
|
||||
if dout_vld_pipe(stage) = '1' then
|
||||
sa_rnd_pipe(stage+1) <= sa_rnd_pipe(stage);
|
||||
rot_data(stage+1) <= rol_stage(rot_data(stage), sa_rnd_pipe(stage)(stage), stage, aggregate_size);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
dout <= rot_data(num_rounds);
|
||||
dout_vld <= dout_vld_pipe(num_rounds);
|
||||
|
||||
end generate;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
end behavior;
|
||||
@@ -1,118 +0,0 @@
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
use std.textio.all; -- Imports the standard textio package.
|
||||
|
||||
use work.utils_pkg.all; -- Imports the standard textio package.
|
||||
|
||||
ENTITY sipo IS
|
||||
Generic
|
||||
(
|
||||
data_width_in : natural := 8;
|
||||
data_width_out : natural := 32;
|
||||
msb_first : boolean := false
|
||||
);
|
||||
Port
|
||||
(
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
din_en : in STD_LOGIC;
|
||||
din_vld : in STD_LOGIC;
|
||||
din : in unsigned(data_width_in-1 downto 0);
|
||||
dout_en : out STD_LOGIC;
|
||||
dout_vld : out STD_LOGIC;
|
||||
dout : out unsigned(data_width_out-1 downto 0);
|
||||
dout_be : out unsigned(data_width_out/data_width_in-1 downto 0)
|
||||
|
||||
);
|
||||
END sipo;
|
||||
|
||||
ARCHITECTURE behavior OF sipo IS
|
||||
|
||||
constant num_shifts : natural := data_width_out/data_width_in;
|
||||
signal pre_fin : STD_LOGIC;
|
||||
signal shift_cnt_pipe : unsigned(num_shifts-1 downto 0);
|
||||
signal shift_pipe : unsigned(data_width_out-1 downto 0);
|
||||
signal out_en : STD_LOGIC;
|
||||
signal out_vld : STD_LOGIC;
|
||||
signal din_vld_r : STD_LOGIC;
|
||||
signal abort : STD_LOGIC;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
begin
|
||||
|
||||
pre_fin <= shift_cnt_pipe(shift_cnt_pipe'left) when msb_first else shift_cnt_pipe(0);
|
||||
dout_en <= out_en;
|
||||
dout_vld <= out_vld;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' or pre_fin = '1' then
|
||||
abort <= '0';
|
||||
elsif din_vld_r = '1' and din_en = '0' then
|
||||
abort <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
din_vld_r <= din_vld and din_en;
|
||||
if rst = '1' then
|
||||
out_en <= '0';
|
||||
elsif out_en = '0' then
|
||||
out_en <= pre_fin and din_en;
|
||||
elsif out_vld = '1' then
|
||||
out_en <= din_en;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
out_vld <= pre_fin;
|
||||
if pre_fin = '1' then
|
||||
dout <= shift_pipe;
|
||||
dout_be <= shift_cnt_pipe;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' or pre_fin = '1' then
|
||||
if (msb_first) then
|
||||
shift_cnt_pipe <= (shift_cnt_pipe'left downto 1 => '0') & (din_en and din_vld);
|
||||
else
|
||||
shift_cnt_pipe <= (din_en and din_vld) & (shift_cnt_pipe'left downto 1 => '0');
|
||||
end if;
|
||||
elsif din_vld = '1' or abort = '1' then
|
||||
if (msb_first) then
|
||||
shift_cnt_pipe <= shift_cnt_pipe(shift_cnt_pipe'left-1 downto 0) & din_en;
|
||||
else
|
||||
shift_cnt_pipe <= din_en & shift_cnt_pipe(shift_cnt_pipe'left downto 1);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if din_vld = '1' or abort = '1' then
|
||||
if (msb_first) then
|
||||
shift_pipe <= shift_pipe(shift_pipe'left-data_width_in downto 0) & din;
|
||||
else
|
||||
shift_pipe <= din & shift_pipe(shift_pipe'left downto data_width_in);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
end behavior;
|
||||
@@ -1,106 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: testbench for system test using Xilinx ML-402
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY tb_crc32 IS
|
||||
END tb_crc32;
|
||||
|
||||
ARCHITECTURE behavior OF tb_crc32 IS
|
||||
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
|
||||
signal CLK : std_logic := '1';
|
||||
signal RST : std_logic := '1';
|
||||
|
||||
signal din_vld : std_logic := '0';
|
||||
signal din : unsigned(7 downto 0) := (others => '-');
|
||||
signal crc32 : unsigned(31 downto 0);
|
||||
signal crc32_vld : std_logic;
|
||||
|
||||
|
||||
type byte_array_t is array (0 to 61) of unsigned(7 downto 0);
|
||||
|
||||
signal test_data : byte_array_t :=
|
||||
(
|
||||
X"00", X"0A", X"E6", X"F0", X"05", X"A3", X"00", X"12",
|
||||
X"34", X"56", X"78", X"90", X"08", X"00", X"45", X"00",
|
||||
X"00", X"30", X"B3", X"FE", X"00", X"00", X"80", X"11",
|
||||
X"72", X"BA", X"0A", X"00", X"00", X"03", X"0A", X"00",
|
||||
X"00", X"02", X"04", X"00", X"04", X"00", X"00", X"1C",
|
||||
X"89", X"4D", X"00", X"01", X"02", X"03", X"04", X"05",
|
||||
X"06", X"07", X"08", X"09", X"0A", X"0B", X"0C", X"0D",
|
||||
X"0E", X"0F", X"10", X"11", X"12", X"13"
|
||||
);
|
||||
|
||||
BEGIN
|
||||
|
||||
inst_crc32: entity work.crc32
|
||||
PORT MAP
|
||||
(
|
||||
rst => RST,
|
||||
clk => CLK,
|
||||
din_vld => din_vld,
|
||||
din => din,
|
||||
crc32_vld => crc32_vld,
|
||||
crc32_out => crc32
|
||||
|
||||
);
|
||||
|
||||
|
||||
CLK_GEN: process
|
||||
begin
|
||||
wait for CLK_PERIOD/2;
|
||||
CLK <= not CLK;
|
||||
end process;
|
||||
|
||||
|
||||
-- Master
|
||||
STIMULUS: process
|
||||
|
||||
|
||||
begin
|
||||
|
||||
wait for 6*CLK_PERIOD;
|
||||
RST <= '0';
|
||||
wait for 6*CLK_PERIOD;
|
||||
|
||||
wait until rising_edge(CLK);
|
||||
|
||||
for i in 0 to 61 loop
|
||||
din_vld <= '1';
|
||||
din <= test_data(i);
|
||||
wait until rising_edge(CLK);
|
||||
end loop;
|
||||
|
||||
din <= (others => '-');
|
||||
din_vld <= '0';
|
||||
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
END;
|
||||
@@ -1,224 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: testbench for system test using Xilinx ML-402
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY tb_serdes IS
|
||||
END tb_serdes;
|
||||
|
||||
ARCHITECTURE behavior OF tb_serdes IS
|
||||
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
|
||||
signal CLK : std_logic := '1';
|
||||
signal RST : std_logic := '1';
|
||||
|
||||
signal piso_din_vld : std_logic := '0';
|
||||
signal piso_din_rdy : std_logic;
|
||||
signal piso_din_be : unsigned(3 downto 0) := (others => '0');
|
||||
signal piso_din : unsigned(31 downto 0) := (others => '-');
|
||||
signal piso_dout_vld : std_logic;
|
||||
signal piso_dout : unsigned(7 downto 0);
|
||||
signal piso_dout_en : std_logic;
|
||||
|
||||
signal piso2_din_vld : std_logic := '0';
|
||||
signal piso2_din_rdy : std_logic;
|
||||
signal piso2_din_be : unsigned(1 downto 0) := (others => '1');
|
||||
signal piso2_din : unsigned(7 downto 0) := (others => '-');
|
||||
signal piso2_dout_vld : std_logic;
|
||||
signal piso2_dout : unsigned(3 downto 0);
|
||||
signal piso2_dout_en : std_logic;
|
||||
|
||||
signal sipo_enable : std_logic := '0';
|
||||
signal sipo_rst : std_logic := '0';
|
||||
signal sipo_din_vld : std_logic := '0';
|
||||
signal sipo_din : unsigned(7 downto 0) := (others => '-');
|
||||
signal sipo_dout_vld : std_logic;
|
||||
signal sipo_dout_en : std_logic;
|
||||
signal sipo_dout_be : unsigned(3 downto 0);
|
||||
signal sipo_dout : unsigned(31 downto 0);
|
||||
|
||||
signal sipo2_enable : std_logic := '0';
|
||||
signal sipo2_rst : std_logic := '0';
|
||||
signal sipo2_din_vld : std_logic := '0';
|
||||
signal sipo2_din : unsigned(3 downto 0) := (others => '-');
|
||||
signal sipo2_dout_vld : std_logic;
|
||||
signal sipo2_dout_en : std_logic;
|
||||
signal sipo2_dout_be : unsigned(1 downto 0);
|
||||
signal sipo2_dout : unsigned(7 downto 0);
|
||||
|
||||
|
||||
BEGIN
|
||||
|
||||
inst_piso : entity work.piso
|
||||
GENERIC MAP
|
||||
(
|
||||
data_width_in => 32,
|
||||
data_width_out => 8,
|
||||
msb_first => true
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => RST,
|
||||
clk => CLK,
|
||||
din_vld => piso_din_vld,
|
||||
din_rdy => piso_din_rdy,
|
||||
din_be => piso_din_be,
|
||||
din => piso_din,
|
||||
dout_vld => piso_dout_vld,
|
||||
dout_en => piso_dout_en,
|
||||
dout => piso_dout
|
||||
|
||||
);
|
||||
|
||||
piso_dout_en <= piso2_din_rdy;
|
||||
|
||||
inst_piso2 : entity work.piso
|
||||
GENERIC MAP
|
||||
(
|
||||
data_width_in => 8,
|
||||
data_width_out => 4,
|
||||
msb_first => true
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => RST,
|
||||
clk => CLK,
|
||||
din_vld => piso2_din_vld,
|
||||
din_rdy => piso2_din_rdy,
|
||||
din_be => piso2_din_be,
|
||||
din => piso2_din,
|
||||
dout_vld => piso2_dout_vld,
|
||||
dout_en => piso2_dout_en,
|
||||
dout => piso2_dout
|
||||
|
||||
);
|
||||
|
||||
piso2_din_vld <= piso_dout_vld;
|
||||
piso2_dout_en <= '1';
|
||||
piso2_din <= piso_dout;
|
||||
|
||||
inst_sipo : entity work.sipo
|
||||
GENERIC MAP
|
||||
(
|
||||
data_width_in => 8,
|
||||
data_width_out => 32,
|
||||
msb_first => true
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => RST,
|
||||
clk => CLK,
|
||||
din_en => sipo_enable,
|
||||
din_vld => sipo_din_vld,
|
||||
din => sipo_din,
|
||||
dout_be => sipo_dout_be,
|
||||
dout_vld => sipo_dout_vld,
|
||||
dout => sipo_dout,
|
||||
dout_en => sipo_dout_en
|
||||
|
||||
);
|
||||
sipo_din <= sipo2_dout;
|
||||
sipo_din_vld <= sipo2_dout_vld;
|
||||
sipo_enable <= sipo2_dout_en;
|
||||
sipo_rst <= RST or not piso2_dout_vld;
|
||||
|
||||
inst_sipo2 : entity work.sipo
|
||||
GENERIC MAP
|
||||
(
|
||||
data_width_in => 4,
|
||||
data_width_out => 8,
|
||||
msb_first => true
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => RST,
|
||||
clk => CLK,
|
||||
din_en => sipo2_enable,
|
||||
din_vld => sipo2_din_vld,
|
||||
din => sipo2_din,
|
||||
dout_be => sipo2_dout_be,
|
||||
dout_vld => sipo2_dout_vld,
|
||||
dout => sipo2_dout,
|
||||
dout_en => sipo2_dout_en
|
||||
|
||||
);
|
||||
sipo2_din <= piso2_dout;
|
||||
sipo2_din_vld <= piso2_dout_vld;
|
||||
sipo2_enable <= sipo2_din_vld;
|
||||
sipo_rst <= RST or not piso2_dout_vld;
|
||||
|
||||
CLK_GEN: process
|
||||
begin
|
||||
wait for CLK_PERIOD/2;
|
||||
CLK <= not CLK;
|
||||
end process;
|
||||
|
||||
|
||||
-- Master
|
||||
STIMULUS: process
|
||||
|
||||
|
||||
begin
|
||||
|
||||
wait for 600*CLK_PERIOD;
|
||||
RST <= '0';
|
||||
wait for 60*CLK_PERIOD;
|
||||
|
||||
for i in 1 to 10 loop
|
||||
|
||||
wait until rising_edge(CLK);
|
||||
piso_din_vld <= '1';
|
||||
piso_din <= X"12345678";
|
||||
piso_din_be <= "1111";
|
||||
wait until rising_edge(CLK) and piso_din_rdy = '1';
|
||||
piso_din <= piso_din + X"12345678";
|
||||
piso_din_be <= "1111";
|
||||
wait until rising_edge(CLK) and piso_din_rdy = '1';
|
||||
piso_din <= piso_din + X"12345678";
|
||||
piso_din_be <= "1111";
|
||||
wait until rising_edge(CLK) and piso_din_rdy = '1';
|
||||
piso_din <= piso_din + X"12345678";
|
||||
piso_din_be <= "1100";
|
||||
wait until rising_edge(CLK) and piso_din_rdy = '1';
|
||||
piso_din <= (others => '-');
|
||||
piso_din_vld <= '0';
|
||||
|
||||
|
||||
wait until rising_edge(CLK) and piso_dout_vld = '0';
|
||||
|
||||
-- wait until rising_edge(CLK);
|
||||
-- wait until rising_edge(CLK) and sipo_dout_vld = '1';
|
||||
--
|
||||
wait for 33*CLK_PERIOD;
|
||||
|
||||
end loop;
|
||||
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
END;
|
||||
@@ -1,761 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: testbench for system test using Xilinx ML-402
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY tb_emac_top_jb IS
|
||||
END tb_emac_top_jb;
|
||||
|
||||
ARCHITECTURE behavior OF tb_emac_top_jb IS
|
||||
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
constant MII_CLK_PERIOD : time := 37.7 ns;
|
||||
|
||||
signal CLK : std_logic := '1';
|
||||
signal RST : std_logic := '1';
|
||||
|
||||
-- Slave
|
||||
signal CYC_I : std_logic := '0';
|
||||
signal STB_I : std_logic := '0';
|
||||
signal WE_I : std_logic := '0';
|
||||
signal SEL_I : unsigned(3 downto 0) := (others => '1');
|
||||
signal ACK_O : std_logic;
|
||||
signal INT_O : std_logic;
|
||||
signal MRDY_I : std_logic := '0';
|
||||
signal SRDY_O : std_logic;
|
||||
signal ADDR_I : unsigned(31 downto 0) := (others => '-');
|
||||
signal DAT_I : unsigned(31 downto 0) := (others => '-');
|
||||
signal DAT_O : unsigned(31 downto 0) := (others => '-');
|
||||
signal DAT_O_reg : unsigned(31 downto 0) := (others => '-');
|
||||
signal status_reg : unsigned(31 downto 0) := (others => '0');
|
||||
signal size_reg : unsigned(31 downto 0) := (others => '0');
|
||||
|
||||
-- Master
|
||||
signal CYC_O : std_logic;
|
||||
signal STB_O : std_logic;
|
||||
signal WE_O : std_logic;
|
||||
signal SEL_O : unsigned(3 downto 0) := (others => '1');
|
||||
signal ACK_I : std_logic := '0';
|
||||
signal MRDY_O : std_logic := '1';
|
||||
signal SRDY_I : std_logic := '1';
|
||||
signal ADDR_O : unsigned(31 downto 0) := (others => '-');
|
||||
signal MDAT_I : unsigned(31 downto 0) := (others => '-');
|
||||
signal MDAT_O : unsigned(31 downto 0) := (others => '-');
|
||||
|
||||
-- MII signals
|
||||
signal mii_rx_clk_board : std_logic := '1';
|
||||
signal mii_tx_clk_board : std_logic := '1';
|
||||
signal mii_rx_clk : std_logic := '1';
|
||||
signal mii_tx_clk : std_logic := '1';
|
||||
signal mii_rx : unsigned(7 downto 0) := (others => '-');
|
||||
signal mii_tx : unsigned(7 downto 0);
|
||||
signal mii_rx_dv : std_logic := '0';
|
||||
signal mii_rx_er : std_logic := '0';
|
||||
signal mii_tx_en : std_logic;
|
||||
signal mii_tx_er : std_logic;
|
||||
signal mii_crs : std_logic := '0';
|
||||
signal mii_col : std_logic := '0';
|
||||
signal mii_gtx_clk : std_logic;
|
||||
|
||||
signal loop_back_en : std_logic := '0';
|
||||
|
||||
signal pktgen_tx : unsigned(7 downto 0);
|
||||
signal pktgen_tx_en : std_logic;
|
||||
signal pktgen_tx_er : std_logic;
|
||||
signal pktgen_en : std_logic := '0';
|
||||
signal pktgen_gigabit : std_logic := '0';
|
||||
signal pktgen_fcs_en : std_logic := '0';
|
||||
signal dat_o_cnt_en : std_logic := '0';
|
||||
signal dat_o_cnt_rst : std_logic := '1';
|
||||
signal dat_o_cnt : natural;
|
||||
signal pkt_count : natural;
|
||||
|
||||
type emac_action_t is (emac_idle, emac_alloc, emac_write, emac_commit, emac_wait_data, emac_read, emac_free);
|
||||
signal emac_action : emac_action_t;
|
||||
|
||||
constant RX_STATUS_REG_ADDR : unsigned(31 downto 0) := X"0000_0000";
|
||||
constant RX_SIZE_REG_ADDR : unsigned(31 downto 0) := X"0000_0004";
|
||||
constant TX_STATUS_REG_ADDR : unsigned(31 downto 0) := X"0000_0008";
|
||||
constant TX_SIZE_REG_ADDR : unsigned(31 downto 0) := X"0000_000C";
|
||||
constant DATA_REG_ADDR : unsigned(31 downto 0) := X"0000_8000";
|
||||
|
||||
|
||||
-- 64Bit RAM
|
||||
signal MDAT_I_64 : unsigned(63 downto 0) := (others => '-');
|
||||
signal MDAT_O_64 : unsigned(63 downto 0) := (others => '-');
|
||||
|
||||
type ram_t is array (0 to 511) of unsigned(63 downto 0);
|
||||
|
||||
signal ram64 : ram_t;
|
||||
|
||||
|
||||
BEGIN
|
||||
|
||||
MDAT_I <= MDAT_I_64(31 downto 0);
|
||||
MDAT_O_64 <= MDAT_O & MDAT_O;
|
||||
|
||||
process(CLK)
|
||||
variable res: unsigned(63 downto 0);
|
||||
variable ram_data : unsigned(63 downto 0);
|
||||
variable data8: unsigned(7 downto 0);
|
||||
begin
|
||||
if rising_edge(CLK) then
|
||||
if RST = '1' then
|
||||
data8 := X"00";
|
||||
for i in 0 to 255 loop
|
||||
ram_data(7 downto 0) := data8;
|
||||
data8 := data8 + 1;
|
||||
ram_data(15 downto 8) := data8;
|
||||
data8 := data8 + 1;
|
||||
ram_data(23 downto 16) := data8;
|
||||
data8 := data8 + 1;
|
||||
ram_data(31 downto 24) := data8;
|
||||
data8 := data8 + 1;
|
||||
ram_data(39 downto 32) := data8;
|
||||
data8 := data8 + 1;
|
||||
ram_data(47 downto 40) := data8;
|
||||
data8 := data8 + 1;
|
||||
ram_data(55 downto 48) := data8;
|
||||
data8 := data8 + 1;
|
||||
ram_data(63 downto 56) := data8;
|
||||
data8 := data8 + 1;
|
||||
ram64(i) <= ram_data;
|
||||
end loop;
|
||||
else
|
||||
ACK_I <= '0';
|
||||
if (CYC_O and STB_O) = '1' then
|
||||
if WE_O = '0' then
|
||||
ACK_I <= '1';
|
||||
ram_data := ram64(to_integer(ADDR_O(31 downto 3)));
|
||||
if ADDR_O(2) = '0' then
|
||||
res := ram_data;
|
||||
else
|
||||
res := ram_data(31 downto 0) & ram_data(63 downto 32);
|
||||
end if;
|
||||
else -- WE=1
|
||||
ram_data := ram64(to_integer(ADDR_O(31 downto 3)));
|
||||
-- ram_data := (others => '-');
|
||||
if ADDR_O(2) = '0' then
|
||||
if SEL_O = "11111111" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64;
|
||||
elsif SEL_O = "00001111" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O_64(31 downto 0);
|
||||
elsif SEL_O = "11110000" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(63 downto 32) & ram_data(31 downto 0);
|
||||
end if;
|
||||
else
|
||||
if SEL_O = "11111111" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(31 downto 0) & MDAT_O_64(63 downto 32);
|
||||
elsif SEL_O = "00001111" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(31 downto 0) & ram_data(31 downto 0);
|
||||
elsif SEL_O = "11110000" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O_64(63 downto 32);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
MDAT_I_64 <= res;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
inst_emac_top_jb : entity work.emac_top_jb
|
||||
GENERIC MAP
|
||||
(
|
||||
f_sysclk => 100.0,
|
||||
RX_RAM_SIZE => 2048,
|
||||
TX_RAM_SIZE => 2048
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
-- JBUS Slave signals
|
||||
CLK_I => CLK,
|
||||
RST_I => RST,
|
||||
INT_O => INT_O,
|
||||
CYC_I => CYC_I,
|
||||
STB_I => STB_I,
|
||||
SEL_I => SEL_I,
|
||||
WE_I => WE_I,
|
||||
ACK_O => ACK_O,
|
||||
SRDY_O => SRDY_O,
|
||||
MRDY_I => MRDY_I,
|
||||
ADDR_I => ADDR_I,
|
||||
DAT_I => DAT_I,
|
||||
DAT_O => DAT_O,
|
||||
|
||||
-- JBUS Master signals
|
||||
CYC_O => CYC_O,
|
||||
STB_O => STB_O,
|
||||
WE_O => WE_O,
|
||||
SEL_O => SEL_O,
|
||||
ACK_I => ACK_I,
|
||||
SRDY_I => SRDY_I,
|
||||
MRDY_O => MRDY_O,
|
||||
ADDR_O => ADDR_O,
|
||||
MDAT_I => MDAT_I,
|
||||
MDAT_O => MDAT_O,
|
||||
|
||||
mii_rx_clk => mii_rx_clk_board,
|
||||
mii_rx_dv => mii_rx_dv,
|
||||
mii_rx_er => mii_rx_er,
|
||||
mii_rx => mii_rx,
|
||||
mii_tx_clk => mii_tx_clk_board,
|
||||
mii_tx_en => mii_tx_en,
|
||||
mii_tx_er => mii_tx_er,
|
||||
mii_tx => mii_tx,
|
||||
mii_gtx_clk => mii_gtx_clk,
|
||||
mii_crs => mii_crs,
|
||||
mii_col => mii_col
|
||||
|
||||
);
|
||||
|
||||
inst_pkt_gen : entity work.pkt_gen
|
||||
GENERIC MAP
|
||||
(
|
||||
f_sysclk => 100.0,
|
||||
PKT_SIZE_MIN => 64,
|
||||
PKT_SIZE_MAX => 1512
|
||||
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
clk => CLK,
|
||||
rst => RST,
|
||||
en => pktgen_en,
|
||||
gigabit_en => pktgen_gigabit,
|
||||
fcs_gen_en => pktgen_fcs_en,
|
||||
mii_tx_clk => mii_tx_clk_board,
|
||||
mii_tx_en => pktgen_tx_en,
|
||||
mii_tx_er => pktgen_tx_er,
|
||||
mii_tx => pktgen_tx
|
||||
|
||||
);
|
||||
|
||||
|
||||
CLK_GEN: process
|
||||
begin
|
||||
wait for CLK_PERIOD/2;
|
||||
CLK <= not CLK;
|
||||
end process;
|
||||
|
||||
MII_CLK_GEN: process
|
||||
begin
|
||||
wait for MII_CLK_PERIOD/2;
|
||||
mii_rx_clk <= not mii_rx_clk;
|
||||
mii_tx_clk <= not mii_tx_clk;
|
||||
end process;
|
||||
|
||||
mii_rx_clk_board <= mii_rx_clk;
|
||||
mii_tx_clk_board <= mii_tx_clk;
|
||||
|
||||
DAT_O_register:
|
||||
process(CLK)
|
||||
begin
|
||||
if rising_edge(CLK) then
|
||||
if ACK_O = '1' then
|
||||
DAT_O_reg <= DAT_O;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
DAT_O_count_register:
|
||||
process(CLK)
|
||||
begin
|
||||
if rising_edge(CLK) then
|
||||
if dat_o_cnt_rst = '1' then
|
||||
dat_o_cnt <= 0;
|
||||
elsif ACK_O = '1' and dat_o_cnt_en = '1' then
|
||||
dat_o_cnt <= dat_o_cnt + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
mii_rx <= mii_tx when loop_back_en = '1' else pktgen_tx;
|
||||
mii_rx_dv <= mii_tx_en when loop_back_en = '1' else pktgen_tx_en;
|
||||
mii_rx_er <= mii_tx_er when loop_back_en = '1' else pktgen_tx_er;
|
||||
mii_crs <= '0';
|
||||
mii_col <= '0';
|
||||
|
||||
-- Master
|
||||
STIMULUS: process
|
||||
|
||||
procedure emac_tx_reset_100mbps is
|
||||
begin
|
||||
|
||||
CYC_I <= '1';
|
||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||
DAT_I <= X"A000_0000";
|
||||
STB_I <= '1';
|
||||
WE_I <= '1';
|
||||
ADDR_I <= TX_STATUS_REG_ADDR;
|
||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||
STB_I <= '0';
|
||||
WE_I <= '0';
|
||||
|
||||
end procedure emac_tx_reset_100mbps;
|
||||
|
||||
procedure emac_rx_reset_100mbps is
|
||||
begin
|
||||
|
||||
CYC_I <= '1';
|
||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||
DAT_I <= X"A000_0000";
|
||||
STB_I <= '1';
|
||||
WE_I <= '1';
|
||||
ADDR_I <= RX_STATUS_REG_ADDR;
|
||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||
STB_I <= '0';
|
||||
WE_I <= '0';
|
||||
|
||||
end procedure emac_rx_reset_100mbps;
|
||||
|
||||
procedure emac_tx_reset_1000mbps is
|
||||
begin
|
||||
|
||||
CYC_I <= '1';
|
||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||
DAT_I <= X"E000_0000";
|
||||
STB_I <= '1';
|
||||
WE_I <= '1';
|
||||
ADDR_I <= TX_STATUS_REG_ADDR;
|
||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||
STB_I <= '0';
|
||||
WE_I <= '0';
|
||||
|
||||
end procedure emac_tx_reset_1000mbps;
|
||||
|
||||
procedure emac_rx_reset_1000mbps is
|
||||
begin
|
||||
|
||||
CYC_I <= '1';
|
||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||
DAT_I <= X"E000_0000";
|
||||
STB_I <= '1';
|
||||
WE_I <= '1';
|
||||
ADDR_I <= RX_STATUS_REG_ADDR;
|
||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||
STB_I <= '0';
|
||||
WE_I <= '0';
|
||||
|
||||
end procedure emac_rx_reset_1000mbps;
|
||||
|
||||
procedure emac_alloc (size : natural) is
|
||||
begin
|
||||
|
||||
-- TX-ALLOCATION
|
||||
-- set TX-size
|
||||
emac_action <= emac_alloc;
|
||||
CYC_I <= '1';
|
||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||
DAT_I <= to_unsigned(size, 32);
|
||||
STB_I <= '1';
|
||||
WE_I <= '1';
|
||||
ADDR_I <= TX_SIZE_REG_ADDR;
|
||||
|
||||
check_alloc_ok:
|
||||
while(true) loop
|
||||
|
||||
-- set alloc request
|
||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||
WE_I <= '0';
|
||||
STB_I <= '1';
|
||||
ADDR_I <= TX_STATUS_REG_ADDR;
|
||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||
STB_I <= '0';
|
||||
wait until rising_edge(CLK) and ACK_O = '1';
|
||||
status_reg <= DAT_O;
|
||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||
DAT_I <= X"0002_0000" or (not X"0001_0000" and status_reg);
|
||||
STB_I <= '1';
|
||||
WE_I <= '1';
|
||||
ADDR_I <= TX_STATUS_REG_ADDR;
|
||||
|
||||
check_bsy:
|
||||
while (true) loop
|
||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||
WE_I <= '0';
|
||||
STB_I <= '1';
|
||||
ADDR_I <= TX_STATUS_REG_ADDR;
|
||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||
STB_I <= '0';
|
||||
wait until rising_edge(CLK) and ACK_O = '1';
|
||||
status_reg <= DAT_O;
|
||||
wait until rising_edge(CLK);
|
||||
if status_reg(17) = '0' then
|
||||
exit check_bsy;
|
||||
end if;
|
||||
end loop;
|
||||
if status_reg(16) = '1' then
|
||||
exit check_alloc_ok;
|
||||
end if;
|
||||
end loop;
|
||||
CYC_I <= '0';
|
||||
|
||||
emac_action <= emac_idle;
|
||||
|
||||
end procedure emac_alloc;
|
||||
|
||||
procedure emac_commit is
|
||||
begin
|
||||
|
||||
-- RX- DEALLOCATION
|
||||
emac_action <= emac_commit;
|
||||
|
||||
-- set free request
|
||||
CYC_I <= '1';
|
||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||
WE_I <= '0';
|
||||
STB_I <= '1';
|
||||
ADDR_I <= TX_STATUS_REG_ADDR;
|
||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||
STB_I <= '0';
|
||||
wait until rising_edge(CLK) and ACK_O = '1';
|
||||
status_reg <= DAT_O;
|
||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||
DAT_I <= X"0001_0000" or (not X"0002_0000" and status_reg);
|
||||
STB_I <= '1';
|
||||
WE_I <= '1';
|
||||
ADDR_I <= TX_STATUS_REG_ADDR;
|
||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||
STB_I <= '0';
|
||||
WE_I <= '0';
|
||||
|
||||
emac_action <= emac_idle;
|
||||
|
||||
end procedure emac_commit;
|
||||
|
||||
procedure emac_write (size : natural) is
|
||||
variable data : unsigned (7 downto 0);
|
||||
variable num_words : natural;
|
||||
begin
|
||||
|
||||
-- FILL TX data
|
||||
emac_action <= emac_write;
|
||||
if (size mod 4) = 0 then
|
||||
num_words := size/4;
|
||||
else
|
||||
num_words := size/4 + 1;
|
||||
end if;
|
||||
|
||||
CYC_I <= '1';
|
||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||
data := X"00";
|
||||
ADDR_I <= DATA_REG_ADDR;
|
||||
WE_I <= '1';
|
||||
for i in 1 to num_words loop
|
||||
STB_I <= '1';
|
||||
DAT_I(7 downto 0) <= data;
|
||||
data := data + 1;
|
||||
DAT_I(15 downto 8) <= data;
|
||||
data := data + 1;
|
||||
DAT_I(23 downto 16) <= data;
|
||||
data := data + 1;
|
||||
DAT_I(31 downto 24) <= data;
|
||||
data := data + 1;
|
||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||
end loop;
|
||||
|
||||
STB_I <= '0';
|
||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||
|
||||
emac_commit;
|
||||
|
||||
emac_action <= emac_idle;
|
||||
|
||||
end procedure emac_write;
|
||||
|
||||
procedure emac_read (size_in : natural) is
|
||||
variable data : unsigned (7 downto 0);
|
||||
variable size, num_words : natural;
|
||||
begin
|
||||
|
||||
return;
|
||||
emac_action <= emac_wait_data;
|
||||
|
||||
-- check if data available
|
||||
check_data_avail:
|
||||
while (true) loop
|
||||
CYC_I <= '1';
|
||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||
WE_I <= '0';
|
||||
STB_I <= '1';
|
||||
ADDR_I <= RX_STATUS_REG_ADDR;
|
||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||
STB_I <= '0';
|
||||
wait until rising_edge(CLK) and ACK_O = '1';
|
||||
status_reg <= DAT_O;
|
||||
wait until rising_edge(CLK);
|
||||
if status_reg(17) = '1' and status_reg(16) = '1' then
|
||||
exit check_data_avail;
|
||||
end if;
|
||||
end loop;
|
||||
|
||||
read_size:
|
||||
dat_o_cnt_rst <= '1';
|
||||
CYC_I <= '1';
|
||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||
WE_I <= '0';
|
||||
STB_I <= '1';
|
||||
ADDR_I <= RX_SIZE_REG_ADDR;
|
||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||
STB_I <= '0';
|
||||
wait until rising_edge(CLK) and ACK_O = '1';
|
||||
size_reg <= DAT_O;
|
||||
wait until rising_edge(CLK);
|
||||
|
||||
-- set packet request
|
||||
CYC_I <= '1';
|
||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||
WE_I <= '0';
|
||||
STB_I <= '1';
|
||||
ADDR_I <= RX_STATUS_REG_ADDR;
|
||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||
STB_I <= '0';
|
||||
wait until rising_edge(CLK) and ACK_O = '1';
|
||||
status_reg <= DAT_O;
|
||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||
DAT_I <= X"0002_0000" or (not X"0001_0000" and status_reg);
|
||||
STB_I <= '1';
|
||||
WE_I <= '1';
|
||||
ADDR_I <= RX_STATUS_REG_ADDR;
|
||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||
STB_I <= '0';
|
||||
WE_I <= '0';
|
||||
|
||||
emac_action <= emac_read;
|
||||
-- Read RX data
|
||||
size := size_in;
|
||||
if (size_in = 0) then
|
||||
size := to_integer(size_reg(15 downto 0));
|
||||
end if;
|
||||
|
||||
if (size mod 4) = 0 then
|
||||
num_words := size/4;
|
||||
else
|
||||
num_words := size/4 + 1;
|
||||
end if;
|
||||
|
||||
dat_o_cnt_rst <= '0';
|
||||
dat_o_cnt_en <= '1';
|
||||
CYC_I <= '1';
|
||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||
ADDR_I <= DATA_REG_ADDR;
|
||||
WE_I <= '0';
|
||||
STB_I <= '1';
|
||||
for i in 1 to num_words loop
|
||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||
end loop;
|
||||
STB_I <= '0';
|
||||
wait until rising_edge(CLK) and dat_o_cnt = num_words;
|
||||
dat_o_cnt_en <= '0';
|
||||
emac_action <= emac_idle;
|
||||
|
||||
end procedure emac_read;
|
||||
|
||||
procedure emac_free is
|
||||
begin
|
||||
|
||||
return;
|
||||
-- RX- DEALLOCATION
|
||||
emac_action <= emac_free;
|
||||
|
||||
-- set free request
|
||||
CYC_I <= '1';
|
||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||
WE_I <= '0';
|
||||
STB_I <= '1';
|
||||
ADDR_I <= RX_STATUS_REG_ADDR;
|
||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||
STB_I <= '0';
|
||||
wait until rising_edge(CLK) and ACK_O = '1';
|
||||
status_reg <= DAT_O;
|
||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||
DAT_I <= X"0001_0000" or (not X"0002_0000" and status_reg);
|
||||
STB_I <= '1';
|
||||
WE_I <= '1';
|
||||
ADDR_I <= RX_STATUS_REG_ADDR;
|
||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||
STB_I <= '0';
|
||||
WE_I <= '0';
|
||||
|
||||
emac_action <= emac_idle;
|
||||
|
||||
end procedure emac_free;
|
||||
|
||||
begin
|
||||
|
||||
wait for 6*MII_CLK_PERIOD;
|
||||
RST <= '0';
|
||||
wait for 60*CLK_PERIOD;
|
||||
emac_rx_reset_100mbps;
|
||||
emac_tx_reset_100mbps;
|
||||
pktgen_gigabit <= '0';
|
||||
pktgen_fcs_en <= '1';
|
||||
wait for 60*CLK_PERIOD;
|
||||
|
||||
emac_alloc (1004);
|
||||
emac_alloc (1004);
|
||||
emac_alloc (1004);
|
||||
emac_alloc (1004);
|
||||
emac_alloc (1004);
|
||||
emac_alloc (1004);
|
||||
emac_alloc (1004);
|
||||
emac_alloc (1004);
|
||||
emac_alloc (1004);
|
||||
emac_alloc (1004);
|
||||
emac_alloc (1004);
|
||||
emac_alloc (1004);
|
||||
|
||||
for i in 1 to 10 loop
|
||||
for j in 1 to 100 loop
|
||||
emac_alloc (72);
|
||||
emac_write (72);
|
||||
end loop;
|
||||
wait for 1 ms;
|
||||
end loop;
|
||||
|
||||
wait until rising_edge(mii_tx_clk) and mii_tx_en = '0';
|
||||
wait for 6000*CLK_PERIOD;
|
||||
|
||||
loop_back_en <= '1';
|
||||
|
||||
emac_alloc (74);
|
||||
emac_write (74);
|
||||
|
||||
emac_alloc (105);
|
||||
emac_write (105);
|
||||
|
||||
emac_read (0);
|
||||
emac_free;
|
||||
|
||||
emac_read (0);
|
||||
emac_free;
|
||||
|
||||
emac_alloc (103);
|
||||
emac_write (103);
|
||||
|
||||
emac_read (0);
|
||||
emac_free;
|
||||
|
||||
emac_alloc (71);
|
||||
emac_write (71);
|
||||
|
||||
emac_read (0);
|
||||
emac_free;
|
||||
|
||||
emac_alloc (82);
|
||||
emac_write (82);
|
||||
|
||||
emac_alloc (86);
|
||||
emac_write (86);
|
||||
|
||||
emac_read (0);
|
||||
emac_free;
|
||||
|
||||
emac_read (0);
|
||||
emac_free;
|
||||
|
||||
emac_alloc (77);
|
||||
emac_write (77);
|
||||
|
||||
emac_alloc (99);
|
||||
emac_write (99);
|
||||
|
||||
emac_alloc (65);
|
||||
emac_write (65);
|
||||
|
||||
emac_alloc (321);
|
||||
emac_write (321);
|
||||
|
||||
emac_read (0);
|
||||
emac_free;
|
||||
|
||||
emac_alloc (1111);
|
||||
emac_write (1111);
|
||||
|
||||
emac_read (0);
|
||||
emac_free;
|
||||
|
||||
emac_alloc (73);
|
||||
emac_write (73);
|
||||
|
||||
emac_alloc (107);
|
||||
emac_write (107);
|
||||
|
||||
emac_alloc (83);
|
||||
emac_write (83);
|
||||
|
||||
emac_read (0);
|
||||
emac_free;
|
||||
|
||||
emac_alloc (72);
|
||||
emac_write (72);
|
||||
|
||||
emac_alloc (1003);
|
||||
emac_write (1003);
|
||||
|
||||
emac_read (0);
|
||||
emac_free;
|
||||
|
||||
emac_read (0);
|
||||
emac_free;
|
||||
|
||||
emac_read (0);
|
||||
emac_free;
|
||||
|
||||
emac_read (0);
|
||||
emac_free;
|
||||
|
||||
emac_read (0);
|
||||
emac_free;
|
||||
|
||||
emac_read (0);
|
||||
emac_free;
|
||||
|
||||
emac_read (0);
|
||||
emac_free;
|
||||
|
||||
wait for 6000*CLK_PERIOD;
|
||||
|
||||
loop_back_en <= '0';
|
||||
pktgen_en <= '1';
|
||||
pkt_count <= 0;
|
||||
for i in 1 to 500 loop
|
||||
wait for 1 us;
|
||||
emac_read (0);
|
||||
emac_free;
|
||||
pkt_count <= pkt_count + 1;
|
||||
end loop;
|
||||
pktgen_en <= '0';
|
||||
emac_read (0);
|
||||
emac_free;
|
||||
|
||||
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
END;
|
||||
@@ -0,0 +1,21 @@
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/misc/pkg_template.vhd,v 1.1.2.1 2013-08-18 06:59:02 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
package template_pkg is
|
||||
|
||||
-- Constants
|
||||
|
||||
-- Types
|
||||
|
||||
-- Functions
|
||||
|
||||
end template_pkg;
|
||||
|
||||
package body template_pkg is
|
||||
|
||||
end template_pkg;
|
||||
|
||||
Reference in New Issue
Block a user