This commit was manufactured by cvs2svn to create tag 'EMAC_R0'.

git-svn-id: http://moon:8086/svn/vhdl/tags/EMAC_R0@849 cc03376c-175c-47c8-b038-4cd826a8556b
2010-03-30 10:15:25 +00:00
21 changed files with 2124 additions and 2056 deletions
@@ -1,2 +0,0 @@
-VHDL/lib/emac/emac_jb.vhd
-
@@ -0,0 +1,657 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+use std.textio.all; --  Imports the standard textio package.
+
+use work.utils_pkg.all;
+
+ENTITY emac_jb IS
+	Generic
+	(
+		f_sysclk	: real		:= 100.0;
+		TX_RAM_SIZE	: natural	:= 2048
+	);
+	Port
+	(
+		CLK_I		: in  STD_LOGIC;
+		RST_I		: in  STD_LOGIC;
+		INT_O		: out STD_LOGIC;
+		CYC_I		: in  STD_LOGIC;
+		STB_I		: in  STD_LOGIC;
+		SEL_I		: in  unsigned(3 downto 0);
+		WE_I		: in  STD_LOGIC;
+		ACK_O		: out STD_LOGIC;
+		SRDY_O		: out STD_LOGIC;
+		MRDY_I		: in  STD_LOGIC;
+		ADDR_I		: in  unsigned(31 downto 0);
+		DAT_I		: in  unsigned(31 downto 0);
+		DAT_O		: out unsigned(31 downto 0);
+		mii_rx_clk	: in  STD_LOGIC;
+		mii_rx_dv	: in  STD_LOGIC;
+		mii_rx_er	: in  STD_LOGIC;
+		mii_rx		: in unsigned(7 downto 0);
+		mii_tx_clk	: in  STD_LOGIC;
+		mii_tx_en	: out STD_LOGIC;
+		mii_tx_er	: out STD_LOGIC;
+		mii_tx		: out unsigned(7 downto 0);
+		mii_gtx_clk	: out STD_LOGIC;
+		mii_crs		: in  STD_LOGIC;
+		mii_col		: in  STD_LOGIC
+		
+	);
+END emac_jb;
+
+ARCHITECTURE behavior OF emac_jb IS
+
+	constant TX_RAM_ADDR_WIDTH	: natural := NextExpBaseTwo(TX_RAM_SIZE);
+	
+	subtype word_ptr_t is unsigned(TX_RAM_ADDR_WIDTH-1 downto 0);
+	
+	-- Signals for EMAC connections
+	signal tx_fifo_din		: unsigned(35 downto 0);
+	signal tx_fifo_dout		: unsigned(35 downto 0);
+	signal tx_fifo_we		: std_logic;
+	signal tx_fifo_re		: std_logic;
+	signal tx_fifo_empty	: std_logic;
+	signal tx_fifo_full		: std_logic;
+	signal rx_int_en		: std_logic;
+	signal tx_int_en		: std_logic;
+	signal irq_rx			: std_logic;
+	signal irq_tx			: std_logic;
+	signal tx_err			: std_logic;
+
+	signal tx_flush_en		: std_logic;
+	signal tx_flush_rdy		: std_logic;
+	signal tx_flush_ptr_set	: std_logic;
+
+	signal tx_commit_en		: std_logic;
+	signal tx_flush_ptr		: word_ptr_t;
+	
+	signal host_data_we		: std_logic;
+	signal host_data_reg	: unsigned(31 downto 0);
+	signal host_tx_size		: unsigned(15 downto 0);
+
+	signal tx_fill_size		: word_ptr_t;
+	signal tx_fill_cnt		: word_ptr_t;
+	signal tx_fill_ptr		: word_ptr_t;
+	signal tx_fill_rdy		: std_logic;
+	signal tx_fill_cnt_set	: std_logic;
+	signal tx_fill_cnt_adv	: std_logic;
+	signal tx_fill_ptr_set	: std_logic;
+	signal tx_fill_ptr_adv	: std_logic;
+
+	signal tx_alloc_OK		: std_logic;
+	signal tx_alloc_req_en	: std_logic;
+	signal tx_alloc_req		: std_logic;
+	signal tx_alloc_ack		: std_logic;
+	
+	signal tx_nwords_free	: word_ptr_t;
+	signal tx_alloc_base	: word_ptr_t;
+	signal tx_alloc_size	: word_ptr_t;
+	signal tx_alloc_en		: std_logic;
+
+	signal tx_free_en		: std_logic;
+	signal tx_uncommit_en	: std_logic;
+	signal tx_fill_remain	: unsigned(1 downto 0);
+
+	signal tx_xfer_size		: word_ptr_t;
+	signal tx_xfer_ptr		: word_ptr_t;
+	signal tx_xfer_cnt		: word_ptr_t;
+	signal tx_xfer_en		: std_logic;
+	signal tx_xfer_ptr_set	: std_logic;
+	signal tx_xfer_ptr_adv	: std_logic;
+	signal tx_xfer_cnt_set	: std_logic;
+	signal tx_xfer_cnt_adv	: std_logic;
+	signal tx_xfer_rdy		: std_logic;
+	signal xfer_tag			: unsigned(3 downto 0);
+	signal xfer_remain		: unsigned(1 downto 0);
+	signal xfer_odd			: std_logic;
+	signal xfer_remain_en	: std_logic;
+
+	signal tx_ram_en_a		: std_logic;
+	signal tx_ram_we_a		: std_logic;
+	signal tx_ram_addr_a	: unsigned(TX_RAM_ADDR_WIDTH-1 downto 0);
+	signal tx_ram_din_a		: unsigned(35 downto 0);
+	signal tx_ram_dout_a	: unsigned(35 downto 0);
+	signal tx_ram_en_b		: std_logic;
+	signal tx_ram_we_b		: std_logic;
+	signal tx_ram_addr_b	: unsigned(TX_RAM_ADDR_WIDTH-1 downto 0);
+	signal tx_ram_din_b		: unsigned(35 downto 0);
+	signal tx_ram_dout_b	: unsigned(35 downto 0);
+
+	signal piso_din_be		: unsigned(3 downto 0);
+	signal piso_din_rdy		: std_logic;
+	signal tx_data_vld		: std_logic;
+	
+	subtype inter_frame_gap_cnt_t is natural range 0 to natural(1.0*f_sysclk)-1;
+	signal inter_frame_gap_cnt	: inter_frame_gap_cnt_t;
+	signal inter_frame_gap_rdy	: std_logic;
+	
+	alias tx_ram_data_in_a is tx_ram_din_a(31 downto 0);
+	alias tx_ram_tag_in_a is tx_ram_din_a(35 downto 32);
+	alias tx_ram_data_out_a is tx_ram_dout_a(31 downto 0);
+	alias tx_ram_tag_out_a is tx_ram_dout_a(35 downto 32);
+	
+	alias tx_ram_data_in_b is tx_ram_din_b(31 downto 0);
+	alias tx_ram_tag_in_b is tx_ram_din_b(35 downto 32);
+	alias tx_ram_data_out_b is tx_ram_dout_b(31 downto 0);
+	alias tx_ram_tag_out_b is tx_ram_dout_b(35 downto 32);
+
+	type host_tx_state_t is (host_tx_init, host_tx_flush, host_tx_idle, host_tx_alloc, host_tx_setup, host_tx_arm, host_tx_fill, host_tx_commit);
+	signal host_tx_s, host_tx_sn : host_tx_state_t;
+	
+	type xfer_tx_state_t is (xfer_tx_init, xfer_tx_idle, xfer_tx_setup, xfer_wait, xfer_tx_active, xfer_tx_free);
+	signal xfer_tx_s, xfer_tx_sn : xfer_tx_state_t;
+
+
+	type piso_byte_mask_array_t is array (0 to 3) of unsigned (3 downto 0);
+	constant piso_byte_mask_rom : piso_byte_mask_array_t :=
+	(
+		"1111",
+		"0001",
+		"0011",
+		"0111"
+	);
+	
+	
+begin
+
+	SRDY_O				<= CYC_I;
+	INT_O				<= irq_rx or irq_tx;
+	mii_gtx_clk			<= '0';
+	mii_tx_er			<= tx_err;
+
+	tx_ram_tag_in_b		<= "0000";
+	tx_ram_en_b			<= '1';
+	tx_ram_we_b			<= tx_uncommit_en or tx_flush_en;
+	tx_ram_addr_b		<= tx_flush_ptr when (tx_flush_en = '1' or tx_uncommit_en = '1') else tx_xfer_ptr;
+	xfer_tag			<= tx_ram_tag_out_b;
+	
+	tx_ram_en_a			<= '1';
+	tx_ram_we_a			<= tx_commit_en or tx_fill_cnt_adv;
+	tx_ram_tag_in_a		<= tx_fill_remain & "01" when tx_commit_en = '1' else "0000";
+	tx_ram_data_in_a	<= resize(tx_fill_size, 16) & resize(tx_alloc_base, 16) when tx_commit_en = '1' else host_data_reg;
+	tx_ram_addr_a		<= tx_alloc_base when tx_commit_en = '1' else tx_fill_ptr;
+
+	piso_din_be			<= (others => '1');
+	tx_fifo_re			<= piso_din_rdy;
+	tx_data_vld			<= not tx_fifo_empty;
+	
+	tx_fifo_din(35 downto 32)	<= piso_byte_mask_rom(to_integer(xfer_remain)) when xfer_remain_en = '1' else "1111";
+	tx_fifo_din(31 downto 0)	<= tx_ram_data_out_b;
+	
+------------------------------------------------------------------
+host_tx_state_next:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				host_tx_s	<= host_tx_init;
+			else
+				host_tx_s	<= host_tx_sn;
+			end if;
+		end if;
+	end process;	
+
+host_tx_state:
+	process(host_tx_s, tx_flush_rdy, tx_alloc_req, tx_alloc_OK, tx_fill_rdy, host_data_we)
+	begin
+	
+		tx_flush_en			<= '0';
+		tx_flush_ptr_set	<= '0';
+		tx_alloc_ack		<= '0';
+		tx_fill_cnt_set		<= '0';
+		tx_fill_cnt_adv		<= '0';
+		tx_fill_ptr_set		<= '0';
+		tx_fill_ptr_adv		<= '0';
+		tx_commit_en		<= '0';
+		tx_alloc_en			<= '0';
+		
+		host_tx_sn			<= host_tx_s;
+		
+		case host_tx_s is
+		
+		when host_tx_init =>
+			tx_flush_ptr_set	<= '1';
+			host_tx_sn <= host_tx_flush;
+		
+		when host_tx_flush =>
+			tx_flush_en	<= '1';
+			if tx_flush_rdy = '1' then
+				tx_flush_en	<= '0';
+				host_tx_sn <= host_tx_idle;
+			end if;
+			
+		when host_tx_idle =>
+			if tx_alloc_req = '1' then
+				host_tx_sn	<= host_tx_alloc;
+			end if;
+
+		when host_tx_alloc =>
+			if tx_alloc_OK = '1' then
+				host_tx_sn			<= host_tx_setup;
+				tx_alloc_ack		<= '1';
+			end if;
+
+		when host_tx_setup =>
+			tx_fill_cnt_set	<= '1';
+			tx_fill_ptr_set	<= '1';
+			host_tx_sn		<= host_tx_arm;
+
+		when host_tx_arm =>
+			tx_fill_ptr_adv	<= '1';
+			tx_fill_cnt_adv	<= '1';
+			host_tx_sn		<= host_tx_fill;
+
+		when host_tx_fill =>
+			tx_fill_cnt_adv	<= host_data_we;
+			tx_fill_ptr_adv	<= not tx_fill_rdy and host_data_we;
+			if tx_alloc_req = '1' then
+				host_tx_sn	<= host_tx_alloc;
+			elsif tx_fill_rdy = '1' then
+				host_tx_sn		<= host_tx_commit;
+			end if;
+		
+		when host_tx_commit =>
+			tx_commit_en	<= '1';
+			tx_alloc_en		<= '1';
+			host_tx_sn		<= host_tx_idle;
+
+		when others => 
+			host_tx_sn	<= host_tx_idle;
+		end case;
+
+	end process;
+
+------------------------------------------------------------------
+-- Allocation stuff
+------------------------------------------------------------------
+alloc_request_logic:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				tx_alloc_req		<= '0';
+			elsif tx_alloc_req_en = '1' and tx_alloc_req = '0' then
+				tx_alloc_req		<= '1';
+				tx_fill_remain		<= host_tx_size(1 downto 0);
+				tx_fill_size		<= host_tx_size(word_ptr_t'left+2 downto 2);
+				if host_tx_size(1 downto 0) /= "00" then
+					tx_fill_size	<= host_tx_size(word_ptr_t'left+2 downto 2) + 1;
+				end if;
+			elsif tx_alloc_ack = '1' then
+				tx_alloc_req		<= '0';
+				tx_alloc_size		<= tx_fill_size;
+			end if;
+		end if;
+	end process;	
+
+------------------------------------------------------------------
+alloc_base_logic:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if tx_flush_en = '1' then
+				tx_alloc_base		<= (others => '0');
+			elsif tx_commit_en = '1' then
+				tx_alloc_base		<= tx_fill_ptr;
+			end if;
+		end if;
+	end process;	
+
+------------------------------------------------------------------
+alloc_eval_logic:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			tx_alloc_OK		<= '0';
+			if tx_alloc_req = '1' then
+				if tx_fill_size < tx_nwords_free then
+					tx_alloc_OK		<= '1';
+				end if;
+			end if;
+		end if;
+	end process;	
+
+------------------------------------------------------------------
+tx_nwords_free_counter:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if tx_flush_en = '1' then
+				tx_nwords_free		<= (others => '1');
+			elsif tx_alloc_en = '1' then
+				tx_nwords_free		<= tx_nwords_free - tx_fill_size;
+			elsif tx_free_en = '1' then
+				tx_nwords_free		<= tx_nwords_free + tx_xfer_size;
+			end if;
+		end if;
+	end process;	
+
+------------------------------------------------------------------
+tx_flush_counter:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if tx_flush_en = '0' then
+				tx_flush_rdy	<= '0';
+				if tx_flush_ptr_set = '1' then
+					tx_flush_ptr	<= (others => '1');
+				elsif tx_xfer_ptr_set = '1' then
+					tx_flush_ptr	<= tx_ram_data_out_b(tx_flush_ptr'left downto 0);
+				end if;	
+			elsif tx_flush_ptr /= 0 then
+				tx_flush_ptr	<= tx_flush_ptr - 1;
+			else
+				tx_flush_rdy	<= '1';
+			end if;
+		end if;
+	end process;	
+
+------------------------------------------------------------------
+-- Fill stuff
+------------------------------------------------------------------
+tx_fill_counter:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if tx_fill_cnt_set = '1' then	
+				tx_fill_rdy			<= '0';
+				tx_fill_cnt			<= tx_alloc_size;
+			elsif tx_fill_cnt_adv = '1' then
+				if tx_fill_cnt /= 0 then
+					tx_fill_cnt		<= tx_fill_cnt - 1;
+				else
+					tx_fill_rdy		<= '1';
+				end if;
+			end if;
+		end if;
+	end process;	
+
+tx_fill_pointer:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if tx_fill_ptr_set = '1' then
+				tx_fill_ptr		<= tx_alloc_base;
+			elsif tx_fill_ptr_adv = '1' then
+				tx_fill_ptr		<= tx_fill_ptr + 1;
+			end if;
+		end if;
+	end process;	
+
+------------------------------------------------------------------
+-- Transfer stuff
+------------------------------------------------------------------
+xfer_tx_state_next:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				xfer_tx_s	<= xfer_tx_init;
+			else
+				xfer_tx_s	<= xfer_tx_sn;
+			end if;
+		end if;
+	end process;	
+
+xfer_tx_state:
+	process(xfer_tx_s, xfer_tag, xfer_odd, tx_xfer_rdy, inter_frame_gap_rdy, tx_alloc_en, tx_fifo_full)
+	begin
+	
+		tx_xfer_cnt_set		<= '0';
+		tx_xfer_cnt_adv		<= '0';
+		tx_xfer_ptr_set		<= '0';
+		tx_xfer_ptr_adv		<= '0';
+		tx_xfer_en			<= '0';
+		xfer_remain_en		<= '0';
+		tx_free_en			<= '0';
+		tx_uncommit_en		<= '0';
+		
+		xfer_tx_sn			<= xfer_tx_s;
+		
+		case xfer_tx_s is
+		
+		when xfer_tx_init =>
+			xfer_tx_sn <= xfer_tx_idle;
+		
+		when xfer_tx_idle =>
+			if xfer_tag(0) = '1' then
+				tx_xfer_ptr_set	<= '1';
+				tx_xfer_cnt_set	<= '1';
+				xfer_tx_sn		<= xfer_wait;
+			end if;
+			
+		when xfer_wait =>
+			if inter_frame_gap_rdy = '1' then
+				xfer_tx_sn			<= xfer_tx_setup;
+			end if;			
+		
+		when xfer_tx_setup =>
+			tx_uncommit_en		<= '1';
+			tx_xfer_ptr_adv		<= '1';
+			tx_xfer_cnt_adv		<= '1';
+			xfer_tx_sn			<= xfer_tx_active;
+
+		when xfer_tx_active =>
+			tx_xfer_en			<= '1';
+			tx_xfer_cnt_adv		<= not tx_fifo_full;
+			tx_xfer_ptr_adv		<= not tx_fifo_full;
+			if tx_xfer_rdy = '1' then
+				xfer_remain_en	<= xfer_odd;
+				tx_xfer_en		<= '0';
+				tx_xfer_cnt_adv	<= '0';
+				tx_xfer_ptr_adv	<= '0';
+				xfer_tx_sn		<= xfer_tx_free;
+			end if;	
+
+		when xfer_tx_free =>
+			tx_free_en			<= not tx_alloc_en;
+			if tx_alloc_en = '0' then
+				xfer_tx_sn			<= xfer_tx_idle;
+			end if;
+
+		when others => 
+			xfer_tx_sn	<= xfer_tx_idle;
+		end case;
+
+	end process;
+
+------------------------------------------------------------------
+interframe_gap_counter:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if tx_flush_en = '1' then
+				inter_frame_gap_rdy	<= '1';
+			elsif tx_fifo_empty = '0' then
+				inter_frame_gap_rdy	<= '0';
+				inter_frame_gap_cnt <= inter_frame_gap_cnt_t'high;
+			elsif inter_frame_gap_cnt /= 0 then
+				inter_frame_gap_cnt <= inter_frame_gap_cnt - 1;
+			else
+				inter_frame_gap_rdy	<= '1';
+			end if;
+		end if;
+	end process;
+
+------------------------------------------------------------------
+tx_xfer_counter:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if tx_xfer_cnt_set = '1' then
+				tx_xfer_size	<= (others => '0');
+				tx_xfer_rdy		<= '0';
+				tx_xfer_cnt 	<= tx_ram_data_out_b(tx_xfer_ptr'left+16 downto 16);
+			elsif tx_xfer_cnt_adv = '1' then
+				if tx_xfer_cnt /= 0 then
+					tx_xfer_cnt		<= tx_xfer_cnt - 1;
+					tx_xfer_size	<= tx_xfer_size + 1;
+				else
+					tx_xfer_rdy		<= '1';
+				end if;
+			end if;
+		end if;	
+			
+	end process;	
+	
+tx_xfer_pointer:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			tx_fifo_we			<= tx_xfer_en;
+			if tx_xfer_ptr_set = '1' then
+				tx_xfer_ptr		<= tx_ram_data_out_b(tx_xfer_ptr'left downto 0);
+				xfer_remain		<= xfer_tag(3 downto 2);
+				xfer_odd 		<= '0';
+				if xfer_tag(3 downto 2) /= "00" then
+					xfer_odd <= '1';
+				end if;
+			elsif tx_xfer_ptr_adv = '1' then
+				tx_xfer_ptr		<= tx_xfer_ptr + 1;
+			end if;
+		end if;	
+			
+	end process;	
+	
+------------------------------------------------------------------
+registers_write: 
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			host_data_we	<= '0';
+			tx_alloc_req_en	<= '0';
+			if RST_I = '1' then
+				rx_int_en		<= '0';
+				tx_int_en		<= '0';
+				tx_err			<= '0';
+		elsif (STB_I and CYC_I and WE_I) = '1' then
+				case ADDR_I(5 downto 2) is
+				
+				when "0000" =>
+					tx_err				<= DAT_I(31);
+					tx_alloc_req_en		<= DAT_I(16);
+					tx_int_en			<= DAT_I(5);
+					rx_int_en			<= DAT_I(4);
+					
+				when "0001" => 
+					if tx_alloc_req = '0' then
+						host_tx_size		<= DAT_I(31 downto 16);
+					end if;	
+					
+				when "0010" =>
+					host_data_we		<= '1';
+					host_data_reg		<= DAT_I;
+					
+				when others => null;
+				end case;
+			end if;	
+		end if;	
+	end process;
+
+registers_read: 
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			ACK_O			<= '0';
+			if (STB_I and CYC_I) = '1' then
+				ACK_O		<= not WE_I;
+				DAT_O		<= (others => '0');
+				case ADDR_I(5 downto 2) is
+
+				when "0000" =>
+					DAT_O(31)	<= tx_err;
+					DAT_O(30)	<= mii_rx_er;
+					DAT_O(29)	<= mii_col;
+					DAT_O(28)	<= mii_crs;
+					DAT_O(16)	<= tx_alloc_req;
+					DAT_O(5)	<= tx_int_en;
+					DAT_O(4)	<= rx_int_en;
+
+				when "0001" => 
+					DAT_O(31 downto 16)	<= host_tx_size;
+
+				when "0010" =>
+
+				when others => null;
+				end case;
+			end if;
+		end if;	
+	end process;
+
+inst_tx_ram : entity work.dpram_2w2r
+	GENERIC MAP 
+	(
+		addr_width	=> TX_RAM_ADDR_WIDTH,
+		data_width	=> 36
+	)
+	PORT MAP 
+	(
+		clk_a	=> CLK_I,
+		clk_b	=> CLK_I,
+		en_a	=> tx_ram_en_a,
+		en_b	=> tx_ram_en_b,
+		we_a	=> tx_ram_we_a,
+		we_b	=> tx_ram_we_b,
+		addr_a	=> tx_ram_addr_a,
+		addr_b	=> tx_ram_addr_b,
+		din_a	=> tx_ram_din_a,
+		din_b	=> tx_ram_din_b,
+		dout_a	=> tx_ram_dout_a,
+		dout_b	=> tx_ram_dout_b
+	);
+
+-- Instantiate synchronous FIFO
+inst_tx_fifo: entity work.fifo_async
+	GENERIC MAP
+	(
+		addr_width			=> 5,
+		data_width			=> 36,
+		do_last_read_update	=> true
+	)
+	PORT MAP
+	(
+		rst			=>	RST_I,
+		clk_w		=>	CLK_I,
+		clk_r		=>	mii_tx_clk,
+		we			=>	tx_fifo_we,
+		re			=>	tx_fifo_re,
+		fifo_full	=>	tx_fifo_full,
+		fifo_empty	=>	tx_fifo_empty,
+		fifo_afull	=>	open,
+		fifo_aempty	=>	open,
+		data_w		=>  tx_fifo_din,
+		data_r		=>  tx_fifo_dout
+	);
+
+inst_piso : entity work.piso
+	GENERIC MAP
+	(
+		data_width_in	=> 32,
+		data_width_out	=> 8,
+		msb_first		=> false
+	)
+	PORT MAP
+	(
+		rst			=> RST_I,
+		clk			=> mii_tx_clk,
+		din_vld		=> tx_data_vld,
+		din_rdy		=> piso_din_rdy,
+		din_be		=> tx_fifo_dout(35 downto 32),
+		din			=> tx_fifo_dout(31 downto 0),
+		dout_en		=> mii_tx_en,
+		dout		=> mii_tx
+		
+	);
+
+irq_register:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			irq_tx		<= tx_int_en;
+			irq_rx		<= rx_int_en;
+		end if;
+	end process;
+
+end behavior;
@@ -1,8 +0,0 @@
-VHDL/lib/emac/sim/tb_emac_jb.fdo
-VHDL/lib/emac/sim/tb_serdes.fdo
-VHDL/lib/emac/sim/tb_emac_jb.wdo
-VHDL/lib/emac/sim/tb_serdes.wdo
-VHDL/lib/emac/sim/tb_serdes.fdo
-
-VHDL/lib/emac/sim/tb_serdes.wdo
-
@@ -1,14 +0,0 @@
-## NOTE:  Do not edit this file.
-## Autogenerated by ProjNav (creatfdo.tcl) on Thu Jul 06 20:49:07 Westeuropäische Sommerzeit 2006
-##
-vlib work
-vcom -explicit  -93 "../../misc/utils_pkg.vhd"
-vcom -explicit  -93 "../src/crc32.vhd"
-vcom -explicit  -93 "../src/tb_crc32.vhd"
-vsim -t 1ps   -lib work tb_crc32
-view wave
-do {tb_crc32.wdo}
-view structure
-view signals
-
-run 1 us
@@ -1,25 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_crc32/clk
-add wave -noupdate -format Logic /tb_crc32/rst
-add wave -noupdate -format Logic /tb_crc32/din_vld
-add wave -noupdate -format Literal -radix hexadecimal /tb_crc32/din
-add wave -noupdate -format Literal -radix hexadecimal /tb_crc32/crc32
-add wave -noupdate -format Logic /tb_crc32/crc32_vld
-add wave -noupdate -format Literal -radix hexadecimal /tb_crc32/test_data
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {667016 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {0 ps} {1050 ns}
@@ -3,12 +3,16 @@
 ##
 vlib work
 vcom -explicit  -93 "../../misc/utils_pkg.vhd"
-vcom -explicit  -93 "../src/piso.vhd"
-vcom -explicit  -93 "../src/sipo.vhd"
-vcom -explicit  -93 "../src/tb_serdes.vhd"
-vsim -t 1ps   -lib work tb_serdes
+vcom -explicit  -93 "../../misc/dpram_1w1r.vhd"
+vcom -explicit  -93 "../../FIFO/src/fifo_ctrl_pkg.vhd"
+vcom -explicit  -93 "../../FIFO/src/gray_counter.vhd"
+vcom -explicit  -93 "../../FIFO/src/fifo_async_ctrl.vhd"
+vcom -explicit  -93 "../../FIFO/src/fifo_async.vhd"
+vcom -explicit  -93 "../src/emac_jb.vhd"
+vcom -explicit  -93 "../src/tb_emac_jb.vhd"
+vsim -t 1ps   -lib work tb_emac_jb
 view wave
-do {tb_serdes.wdo}
+do {tb_emac_jb.wdo}
 view structure
 view signals

@@ -1,47 +1,33 @@
 onerror {resume}
 quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_serdes/clk
-add wave -noupdate -format Logic /tb_serdes/rst
-add wave -noupdate -divider PiSo
-add wave -noupdate -format Logic /tb_serdes/clk
-add wave -noupdate -format Logic /tb_serdes/piso_din_vld
-add wave -noupdate -format Logic /tb_serdes/piso_din_rdy
-add wave -noupdate -format Literal /tb_serdes/piso_din_be
-add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/piso_din
-add wave -noupdate -format Logic /tb_serdes/piso_dout_vld
-add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/piso_dout
-add wave -noupdate -format Logic /tb_serdes/piso_dout_en
-add wave -noupdate -divider SiPo
-add wave -noupdate -format Logic /tb_serdes/clk
-add wave -noupdate -format Logic /tb_serdes/sipo_enable
-add wave -noupdate -format Logic /tb_serdes/sipo_rst
-add wave -noupdate -format Logic /tb_serdes/sipo_din_vld
-add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/sipo_din
-add wave -noupdate -format Logic /tb_serdes/sipo_dout_vld
-add wave -noupdate -format Logic /tb_serdes/sipo_dout_en
-add wave -noupdate -format Literal /tb_serdes/sipo_dout_be
-add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/sipo_dout
-add wave -noupdate -divider PiSo
-add wave -noupdate -format Logic /tb_serdes/clk
-add wave -noupdate -format Logic /tb_serdes/piso2_din_vld
-add wave -noupdate -format Logic /tb_serdes/piso2_din_rdy
-add wave -noupdate -format Literal /tb_serdes/piso2_din_be
-add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/piso2_din
-add wave -noupdate -format Logic /tb_serdes/piso2_dout_vld
-add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/piso2_dout
-add wave -noupdate -format Logic /tb_serdes/piso2_dout_en
-add wave -noupdate -divider SiPo
-add wave -noupdate -format Logic /tb_serdes/clk
-add wave -noupdate -format Logic /tb_serdes/sipo2_enable
-add wave -noupdate -format Logic /tb_serdes/sipo2_rst
-add wave -noupdate -format Logic /tb_serdes/sipo2_din_vld
-add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/sipo2_din
-add wave -noupdate -format Logic /tb_serdes/sipo2_dout_vld
-add wave -noupdate -format Logic /tb_serdes/sipo2_dout_en
-add wave -noupdate -format Literal /tb_serdes/sipo2_dout_be
-add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/sipo2_dout
+add wave -noupdate -format Logic /tb_emac_jb/clk
+add wave -noupdate -format Logic /tb_emac_jb/rst
+add wave -noupdate -format Logic /tb_emac_jb/cyc_i
+add wave -noupdate -format Logic /tb_emac_jb/stb_i
+add wave -noupdate -format Logic /tb_emac_jb/we_i
+add wave -noupdate -format Literal /tb_emac_jb/sel_i
+add wave -noupdate -format Logic /tb_emac_jb/ack_o
+add wave -noupdate -format Logic /tb_emac_jb/int_o
+add wave -noupdate -format Logic /tb_emac_jb/mrdy_i
+add wave -noupdate -format Logic /tb_emac_jb/srdy_o
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/addr_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/dat_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/dat_o
+add wave -noupdate -format Logic /tb_emac_jb/mii_rx_clk
+add wave -noupdate -format Logic /tb_emac_jb/mii_tx_clk
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/mii_rx
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/mii_tx
+add wave -noupdate -format Logic /tb_emac_jb/mii_rx_dv
+add wave -noupdate -format Logic /tb_emac_jb/mii_rx_er
+add wave -noupdate -format Logic /tb_emac_jb/mii_tx_en
+add wave -noupdate -format Logic /tb_emac_jb/mii_tx_er
+add wave -noupdate -format Logic /tb_emac_jb/mii_crs
+add wave -noupdate -format Logic /tb_emac_jb/mii_col
+add wave -noupdate -format Logic /tb_emac_jb/mii_gtx_clk
+add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_fifo_re
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_fifo_dout
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {19757882 ps} 0} {{Cursor 2} {49999912163 ps} 0} {{Cursor 3} {49999529250 ps} 0}
+WaveRestoreCursors {{Cursor 1} {12999093 ps} 0}
 configure wave -namecolwidth 150
 configure wave -valuecolwidth 100
 configure wave -justifyvalue left
@@ -3,27 +3,21 @@
 ##
 vlib work
 vcom -explicit  -93 "../../misc/utils_pkg.vhd"
-vcom -explicit  -93 "../../rams/dpram_1w1r2c_ra_sim.vhd"
-vcom -explicit  -93 "../../rams/dpram_2w2r2c_ra_sim.vhd"
-vcom -explicit  -93 "../../rams/dpram_1w1r2c_ro_sim.vhd"
-vcom -explicit  -93 "../../rams/dpram_2w2r2c_ro_sim.vhd"
+vcom -explicit  -93 "../../misc/dpram_1w1r.vhd"
+vcom -explicit  -93 "../../misc/dpram_2w2r.vhd"
 vcom -explicit  -93 "../../FIFO/src/fifo_ctrl_pkg.vhd"
 vcom -explicit  -93 "../../FIFO/src/fifo_sync_ctrl.vhd"
 vcom -explicit  -93 "../../FIFO/src/fifo_sync.vhd"
 vcom -explicit  -93 "../../FIFO/src/gray_counter.vhd"
 vcom -explicit  -93 "../../FIFO/src/fifo_async_ctrl.vhd"
 vcom -explicit  -93 "../../FIFO/src/fifo_async.vhd"
-vcom -explicit  -93 "../../JBUS/src/busmaster_types.vhd"
-vcom -explicit  -93 "../../JBUS/src/busmaster_sync.vhd"
-vcom -explicit  -93 "../../JBUS/src/dmac.vhd"
 vcom -explicit  -93 "../src/piso.vhd"
 vcom -explicit  -93 "../src/sipo.vhd"
-vcom -explicit  -93 "../src/crc32.vhd"
+vcom -explicit  -93 "../src/shifter.vhd"
 vcom -explicit  -93 "../src/emac_types.vhd"
 vcom -explicit  -93 "../src/emac_rx.vhd"
 vcom -explicit  -93 "../src/emac_tx.vhd"
 vcom -explicit  -93 "../src/emac_top_jb.vhd"
-vcom -explicit  -93 "../src/pkt_gen.vhd"
 vcom -explicit  -93 "../src/tb_emac_top_jb.vhd"
 vsim -t 1ps   -lib work tb_emac_top_jb
 view wave
@@ -31,4 +25,4 @@ do {tb_emac_top_jb.wdo}
 view structure
 view signals

-run 16000 us
+run 250 us
@@ -3,8 +3,6 @@ quietly WaveActivateNextPane {} 0
 add wave -noupdate -divider {Ethernet MAC}
 add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/clk_i
 add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/rst_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/ram64
-add wave -noupdate -divider Slave
 add wave -noupdate -format Logic -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/int_o
 add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/cyc_i
 add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/stb_i
@@ -16,18 +14,6 @@ add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mrdy_i
 add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/addr_i
 add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/dat_i
 add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/dat_o
-add wave -noupdate -divider Master
-add wave -noupdate -format Logic /tb_emac_top_jb/cyc_o
-add wave -noupdate -format Logic /tb_emac_top_jb/stb_o
-add wave -noupdate -format Logic /tb_emac_top_jb/we_o
-add wave -noupdate -format Literal /tb_emac_top_jb/sel_o
-add wave -noupdate -format Logic /tb_emac_top_jb/ack_i
-add wave -noupdate -format Logic /tb_emac_top_jb/mrdy_o
-add wave -noupdate -format Logic /tb_emac_top_jb/srdy_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/addr_o
-add wave -noupdate -format Literal /tb_emac_top_jb/mdat_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/mdat_o
-add wave -noupdate -divider MII
 add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_rx_clk
 add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_rx_dv
 add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_rx_er
@@ -39,187 +25,127 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_
 add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_gtx_clk
 add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_crs
 add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_col
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/status_reg
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/size_reg
 add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/dat_o_reg
 add wave -noupdate -format Literal /tb_emac_top_jb/emac_action
-add wave -noupdate -format Logic /tb_emac_top_jb/dat_o_cnt_rst
-add wave -noupdate -format Literal /tb_emac_top_jb/dat_o_cnt
-add wave -noupdate -format Literal /tb_emac_top_jb/pkt_count
-add wave -noupdate -divider {Packet generator}
-add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/tx_packets
-add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/tx_bytes
-add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_pkt_gen/pkt_nbytes
-add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_pkt_gen/pkt_nwords
-add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/host_s
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_emac_top_jb/inst_pkt_gen/tx_ctrl_in
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_emac_top_jb/inst_pkt_gen/tx_ctrl_out
-add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/tx_bytes
-add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/tx_packets
-add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_pkt_gen/fill_size
-add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_pkt_gen/fill_cnt
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_pkt_gen/fill_rdy
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_pkt_gen/fill_set
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_pkt_gen/fill_en
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_pkt_gen/tx_din
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_pkt_gen/tx_din_vld
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/pktgen_tx
-add wave -noupdate -format Logic /tb_emac_top_jb/pktgen_tx_en
-add wave -noupdate -format Logic /tb_emac_top_jb/pktgen_tx_er
-add wave -noupdate -format Logic /tb_emac_top_jb/pktgen_en
-add wave -noupdate -divider RX-DMA
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/master_req
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/master_gnt
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/dma_start
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/dma_active
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/dma_end
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/req_rdy
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/req_en
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/req_rw
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/req_addr_start
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/req_num_xfers
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/req_addr_auto_inc
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/req_complete
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/req_complete_ack
-add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/gen_dmac__0/inst_dmac/s
 add wave -noupdate -divider RX
 add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/clk
 add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/rst
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/dout_re
+add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_s
+add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/host_s
 add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/dout
 add wave -noupdate -format Literal -radix hexadecimal -expand /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ctrl_in
-add wave -noupdate -format Literal -radix unsigned -expand /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ctrl_out
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_rx_clk
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_rx_dv
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_rx_er
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_rx
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_crs
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_col
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ctrl_out
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_rx_clk
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_fifo_full
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_fifo_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_fifo_din
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/clk
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_fifo_empty
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_fifo_re
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_fifo_dout
 add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_din
 add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_dout
 add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_we
 add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_re
 add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_empty
 add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_full
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/host_ptr
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/host_ram_limit
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/host_ram_base
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/commit_en
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_ram_limit
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/flush_en
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/fill_ptr
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/fill_ptr_set
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/fill_ptr_adv
 add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_ram_full
 add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_base
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_size
 add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_ptr
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_en_a
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_we_a
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_addr_a
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_din_a
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_en_b
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_cnt
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_ptr_set
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_ptr_adv
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_cnt_set
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_cnt_adv
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_rdy
+add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_tag
+add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_remain
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_odd
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_remain_en
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/byte_count
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/byte_count_reg
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/word_count
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/word_count_reg
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/word_count_set
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/word_count_clr
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/word_count_ack
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/word_count_vld
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/uncommit_en
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo_dout
+add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo_dout_be
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo_dout_vld
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_rx_dv
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_we_b
 add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_addr_b
-add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/byte_count
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_din
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_din_vld
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_dout
-add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_dout_be
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_dout_vld
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_dout_en
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_en
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_rst
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo8_dout
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo8_rst
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo8_dout_vld
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo8_dout_en
-add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/host_s
-add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_s
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/preamble_bsy
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/preamble_ok
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/preamble_rdy
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_rdy
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_ok
-add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_num_ok
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_addr
-add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_cnt
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/fcs_vld
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/fcs_din_vld
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/fcs
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/fcs_chk_ok
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_we_a
+add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_addr_a
 add wave -noupdate -divider TX
 add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/clk
 add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/rst
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/din_vld
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/din
 add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ctrl_in
 add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ctrl_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_dout
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_we
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_re
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_empty
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_full
 add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_din
 add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_dout
 add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_we
 add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_re
 add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_empty
 add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_full
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_pre_rdy
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_bsy
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_set
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_en
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_cnt_en
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_base
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/flush_en
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/commit_en
 add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_size
 add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_cnt
 add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_ptr
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_remain
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_we_a
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_addr_a
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_rdy
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_cnt_set
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_cnt_adv
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_ptr_set
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_ptr_adv
 add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/alloc_ok
 add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/alloc_req
 add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/alloc_ack
 add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/nwords_free
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_base
 add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/alloc_size
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mem_alloc_en
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mem_free_en
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/commit_en
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/alloc_en
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/free_en
 add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/uncommit_en
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_bsy
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_remain
 add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_size
 add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_ptr
 add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_cnt
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_cnt_en
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_en
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_set
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_en_a
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_we_a
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_addr_a
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_din_a
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_en_b
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_ptr_set
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_ptr_adv
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_cnt_set
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_cnt_adv
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_rdy
+add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_tag
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_remain
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_odd
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_remain_en
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_we_b
 add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_addr_b
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_dout_b
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_din
-add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_din_be
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_din_rdy
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_din_vld
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_dout
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_dout_vld
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_dout_en
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_we
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_re
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_full
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_empty
-add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_re_dly
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_din_vld
-add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_din
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_dout_vld
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_din_rdy
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_dout
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fcs_rst
-add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fcs_en
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fcs_din_vld
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fcs_vld
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fcs
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_tx_clk
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_tx_en
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_tx_er
-add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_tx
+add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso_din_be
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso_din_rdy
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/data_vld
+add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/inter_frame_gap_cnt
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/inter_frame_gap_rdy
 add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/host_s
 add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_s
-add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mem_free_req
-add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mem_free_ack
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {15999470765 ps} 0} {{Cursor 2} {49999967706 ps} 0} {{Cursor 3} {42725669958 ps} 0} {{Cursor 4} {10461803096 ps} 0} {{Cursor 5} {10000 ps} 0}
+WaveRestoreCursors {{Cursor 1} {65284974 ps} 0}
 configure wave -namecolwidth 150
 configure wave -valuecolwidth 100
 configure wave -justifyvalue left
@@ -233,4 +159,4 @@ configure wave -gridperiod 100
 configure wave -griddelta 40
 configure wave -timeline 1
 update
-WaveRestoreZoom {0 ps} {379173 ps}
+WaveRestoreZoom {0 ps} {262500 ns}
@@ -1,8 +0,0 @@
-VHDL/lib/emac/emac_jb.vhd
-VHDL/lib/emac/src/emac_jb.vhd
-VHDL/lib/emac/src/emac_jb.vhd
-
-VHDL/lib/emac/src/tb_emac_jb.vhd
-VHDL/lib/emac/src/tb_serdes.vhd
-VHDL/lib/emac/src/tb_serdes.vhd
-
@@ -1,64 +0,0 @@
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-use std.textio.all; --  Imports the standard textio package.
-
-use work.utils_pkg.all; --  Imports the standard textio package.
-
-ENTITY crc32 IS
-	Generic
-	(
-		crc32_init	: unsigned(31 downto 0) := X"00000000"
-	);
-	Port
-	(
-		rst			: in  STD_LOGIC;
-		clk			: in  STD_LOGIC;
-		din_vld		: in  STD_LOGIC;
-		din			: in  unsigned(7 downto 0);
-		crc32_vld	: out STD_LOGIC;
-		crc32_out	: out unsigned(31 downto 0)
-		
-	);
-END crc32;
-
-ARCHITECTURE behavior OF crc32 IS
-
-	type crc_table_t is array (0 to 15) of unsigned(31 downto 0);
-	
-	constant crc_table	: crc_table_t :=
-	(
-		X"4DBDF21C", X"500AE278", X"76D3D2D4", X"6B64C2B0",
-		X"3B61B38C", X"26D6A3E8", X"000F9344", X"1DB88320",
-		X"A005713C", X"BDB26158", X"9B6B51F4", X"86DC4190",
-		X"D6D930AC", X"CB6E20C8", X"EDB71064", X"F0000000"
-	);
-	
-	signal crc0		: unsigned(31 downto 0);
-	signal crc1		: unsigned(31 downto 0);
-	signal crc2		: unsigned(31 downto 0);
-	
--------------------------------------------------------------------------
-begin
-
-	crc1	<= X"0" & crc0(31 downto 4) xor crc_table(to_integer(crc0(3 downto 0) xor din(3 downto 0)));
-	crc2	<= X"0" & crc1(31 downto 4) xor crc_table(to_integer(crc1(3 downto 0) xor din(7 downto 4)));
-	
-	crc32_out	<= crc0;
-	
--------------------------------------------------------------------------
-process(clk)
-begin
-	if rising_edge(clk) then
-		if rst = '1' then
-			crc0		<= crc32_init;
-			crc32_vld	<= '0';
-		elsif din_vld = '1' then	
-			crc0		<= crc2;
-			crc32_vld	<= '1';
-		end if;
-	end if;
-end process;
-
--------------------------------------------------------------------------
-end behavior;
@@ -16,7 +16,7 @@ ENTITY emac_rx IS
 	(
 		clk				: in  STD_LOGIC;
 		rst				: in  STD_LOGIC;
-		dout_re			: in  STD_LOGIC;
+		dout_vld		: out STD_LOGIC;
 		dout			: out unsigned(31 downto 0);
 		ctrl_in			: in  rx_ctrl_in_t;
 		ctrl_out		: out rx_ctrl_out_t;
@@ -37,8 +37,15 @@ ARCHITECTURE behavior OF emac_rx IS
 	subtype word_ptr_t is unsigned(RAM_ADDR_WIDTH-1 downto 0);
 	
 	-- Signals for EMAC connections
-	signal cmd_fifo_din		: unsigned(2*word_ptr_t'length+2 downto 0);
-	signal cmd_fifo_dout	: unsigned(2*word_ptr_t'length+2 downto 0);
+	signal mii_fifo_din		: unsigned(31 downto 0);
+	signal mii_fifo_dout	: unsigned(31 downto 0);
+	signal mii_fifo_we		: std_logic;
+	signal mii_fifo_re		: std_logic;
+	signal mii_fifo_empty	: std_logic;
+	signal mii_fifo_full	: std_logic;
+
+	signal cmd_fifo_din		: unsigned(31 downto 0);
+	signal cmd_fifo_dout	: unsigned(31 downto 0);
 	signal cmd_fifo_we		: std_logic;
 	signal cmd_fifo_re		: std_logic;
 	signal cmd_fifo_empty	: std_logic;
@@ -46,123 +53,97 @@ ARCHITECTURE behavior OF emac_rx IS

 	signal reset_en			: std_logic;
 	
-	signal host_ptr			: word_ptr_t;
-	signal host_ptr_next	: word_ptr_t;
-	signal host_ram_limit	: word_ptr_t;
-	signal host_ram_base	: word_ptr_t;
+	signal fill_ptr			: word_ptr_t;

 	signal commit_en		: std_logic;

 	signal xfer_ram_limit	: word_ptr_t;
 	signal xfer_ram_full	: std_logic;
 	signal xfer_base		: word_ptr_t;
+	signal xfer_size		: word_ptr_t;
 	signal xfer_ptr			: word_ptr_t;
-	signal xfer_en			: std_logic;
-	signal xfer_set			: std_logic;
-	signal xfer_vld			: std_logic;
-	signal xfer_promiscious	: std_logic;
+	signal xfer_ptr_set		: std_logic;
+	signal xfer_ptr_adv		: std_logic;
+	signal xfer_cnt_set		: std_logic;
+	signal xfer_cnt_adv		: std_logic;
+	signal xfer_rdy			: std_logic;

 	signal ram_en_a			: std_logic;
 	signal ram_we_a			: std_logic;
 	signal ram_addr_a		: word_ptr_t;
 	signal ram_din_a		: unsigned(31 downto 0);
-	signal ram_dout_b		: unsigned(31 downto 0);
+	signal ram_dout_a		: unsigned(31 downto 0);
 	signal ram_en_b			: std_logic;
+	signal ram_we_b			: std_logic;
 	signal ram_addr_b		: word_ptr_t;
+	signal ram_din_b		: unsigned(31 downto 0);

-	signal sipo32_din		: unsigned(7 downto 0);
-	signal sipo32_din_vld	: std_logic;
-	signal sipo32_dout		: unsigned(31 downto 0);
-	signal sipo32_dout_be	: unsigned(3 downto 0);
-	signal sipo32_dout_vld	: std_logic;
-	signal sipo32_dout_en	: std_logic;
-	signal sipo32_en		: std_logic;
-	signal sipo32_rst		: std_logic;
+	signal sipo_32bit_dout		: unsigned(31 downto 0);
+	signal sipo_32bit_dout_be	: unsigned(3 downto 0);
+	signal sipo_32bit_dout_vld	: std_logic;
+	signal sipo_32bit_dout_en	: std_logic;
+	signal sipo_32bit_en		: std_logic;
+	signal sipo_32bit_rst		: std_logic;
 	
-	signal sipo8_dout		: unsigned(7 downto 0);
-	signal sipo8_rst		: std_logic;
-	signal sipo8_dout_vld	: std_logic;
-	signal sipo8_dout_en	: std_logic;
-	signal sipo8_en			: std_logic;
-	
-	signal byte_count_rst	: std_logic;
+	signal sipo_8bit_dout		: unsigned(7 downto 0);
+	signal sipo_8bit_rst		: std_logic;
+	signal sipo_8bit_dout_vld	: std_logic;
+	signal sipo_8bit_dout_en	: std_logic;
+	signal sipo_8bit_en		: std_logic;
+
+	signal byte_count_en	: std_logic;
 	signal byte_count		: word_ptr_t;
+	signal byte_count_reg	: word_ptr_t;
+
+	signal word_count		: word_ptr_t;
+	signal word_count_en	: std_logic;
+
+	signal size_fifo_full	: std_logic;
+	signal size_fifo_empty	: std_logic;
+	signal size_fifo_we		: std_logic;
+	signal size_fifo_re		: std_logic;
+	signal size_fifo_din	: unsigned(2*word_ptr_t'length-1 downto 0);
+	signal size_fifo_dout	: unsigned(2*word_ptr_t'length-1 downto 0);

 	signal reset_pipe		: unsigned(31 downto 0);

-	signal preamble_en		: std_logic;
-	signal preamble_rdy		: std_logic;
-	signal preamble_bsy		: std_logic;
-	signal preamble_OK		: std_logic;
-
-	signal mac_chk_rdy		: std_logic;
-	signal mac_chk_BC		: std_logic;
-	signal mac_chk_OK		: std_logic;
-	signal mac_chk_num_OK	: natural range 0 to 6;
-	signal mac_chk_num_BC	: natural range 0 to 6;
-	signal mac_chk_cnt		: natural range 0 to 5;
-	signal mac_addr			: mac_addr_t;
-	signal mac_chk_addr		: mac_addr_t;
-	
-	signal Gbps_en			: std_logic;
-	signal fcs_chk_en		: std_logic;
-	signal rx_en			: std_logic;
-	
-	signal fcs_vld			: std_logic;
-	signal fcs_din_vld		: std_logic;
-	signal fcs_din			: unsigned(7 downto 0);
-	signal fcs				: unsigned(31 downto 0);
-	signal fcs_chk_OK		: std_logic;
-
 	type host_state_t is (host_init, host_flush, host_idle);
 	signal host_s, host_sn : host_state_t;

-	type xfer_state_t is (xfer_init, xfer_idle, xfer_preamble, xfer_setup, xfer_active, xfer_finish, xfer_commit);
+	type xfer_state_t is (xfer_init, xfer_idle, xfer_setup, xfer_active, xfer_drop, xfer_commit, xfer_free);
 	signal xfer_s, xfer_sn : xfer_state_t;

-	alias cmd_mac_ok_in is cmd_fifo_din(cmd_fifo_din'left);
-	alias cmd_bcast_in is cmd_fifo_din(cmd_fifo_din'left-1);
-	alias cmd_pkt_valid_in is cmd_fifo_din(cmd_fifo_din'left-2);
-	alias cmd_nbytes_in is cmd_fifo_din(word_ptr_t'length-1 downto 0);
-	alias cmd_base_in is cmd_fifo_din(2*word_ptr_t'length-1 downto word_ptr_t'length);
-
-	alias cmd_mac_ok_out is cmd_fifo_dout(cmd_fifo_dout'left);
-	alias cmd_bcast_out is cmd_fifo_dout(cmd_fifo_dout'left-1);
-	alias cmd_pkt_valid_out is cmd_fifo_dout(cmd_fifo_dout'left-2);
-	alias cmd_nbytes_out is cmd_fifo_dout(word_ptr_t'length-1 downto 0);
-	alias cmd_base_out is cmd_fifo_dout(2*word_ptr_t'length-1 downto word_ptr_t'length);
+	type stream_state_t is (stream_init, stream_idle, stream_start, stream_active, stream_stop, stream_finish);
+	signal stream_s, stream_sn : stream_state_t;

 begin

-	ctrl_out.rx_size		<= resize(cmd_nbytes_out, 16);
-	ctrl_out.pkt_avail		<= not cmd_fifo_empty;
-	ctrl_out.pkt_valid		<= cmd_pkt_valid_out;
-	ctrl_out.pkt_bcast		<= cmd_bcast_out;
-	ctrl_out.pkt_mac_match	<= cmd_mac_ok_out;
-	ctrl_out.reset_busy		<= reset_en;
+	ctrl_out.rx_size	<= cmd_fifo_dout(31 downto 16);
+	ctrl_out.pkt_avail	<= not cmd_fifo_empty;
+	ctrl_out.rx_er		<= mii_rx_er;
+	ctrl_out.reset_busy	<= reset_en;
+
+	dout				<= ram_dout_a;
+
+	mii_fifo_din		<= sipo_32bit_dout;
+	mii_fifo_we			<= sipo_32bit_dout_vld;
+
+	ram_en_a			<= '1';
+	ram_din_a			<= (others => '-');
+	ram_addr_a			<= fill_ptr;
+	ram_we_a			<= '0';
+
+	ram_en_b			<= '1';
+	ram_din_b			<= mii_fifo_dout;
+	ram_addr_b			<= xfer_ptr;
+	ram_we_b			<= xfer_ptr_adv;
 	
-	dout					<= ram_dout_b;
-
-	ram_en_b				<= '1';
-	ram_addr_b				<= host_ptr_next;
-
-	ram_en_a				<= '1';
-	ram_din_a				<= sipo32_dout;
-	ram_addr_a				<= xfer_ptr;
-	ram_we_a				<= xfer_en and sipo32_dout_vld;
+	cmd_fifo_we			<= commit_en;
+	cmd_fifo_re			<= ctrl_in.pkt_free_en;
+	cmd_fifo_din		<= resize(size_fifo_dout(word_ptr_t'length-1 downto 0), 16) & resize(xfer_base, 16);
 	
-	xfer_vld				<= (mac_chk_OK or mac_chk_BC or xfer_promiscious) and (not fcs_chk_en or fcs_chk_OK);
-	cmd_fifo_we				<= commit_en and xfer_vld;
-	cmd_fifo_re				<= ctrl_in.pkt_free_en;
-
-	cmd_pkt_valid_in		<= fcs_chk_OK;
-	cmd_mac_ok_in			<= mac_chk_OK;
-	cmd_bcast_in			<= mac_chk_BC;
-	cmd_nbytes_in			<= byte_count;
-	cmd_base_in				<= xfer_base;
-	
-
-	reset_en				<= reset_pipe(reset_pipe'left);
+	size_fifo_din		<= word_count & byte_count_reg;
+	reset_en			<= reset_pipe(reset_pipe'left);
 	
 ------------------------------------------------------------------
 reset_gen:
@@ -184,166 +165,22 @@ fill_pointer:
 	process(clk)
 	begin
 		if rising_edge(clk) then
+			dout_vld			<= ctrl_in.pkt_read_en;
 			if ctrl_in.pkt_req_en = '1' then
-				host_ptr		<= cmd_base_out;
-			elsif dout_re = '1' then
-				host_ptr		<= host_ptr_next;
+				fill_ptr		<= resize(cmd_fifo_dout(15 downto 0), word_ptr_t'length);
+			elsif ctrl_in.pkt_read_en = '1' then
+				fill_ptr		<= fill_ptr + 1;
 			end if;
 		end if;
 	end process;	

-	host_ptr_next	<= host_ptr + 1 when dout_re = '1' else host_ptr;
-	
 ------------------------------------------------------------------
 -- Transfer stuff
 ------------------------------------------------------------------
-host2xfer_sync_register:
-	process(mii_rx_clk)
-	begin
-		if rising_edge(mii_rx_clk) then
-			xfer_promiscious	<= ctrl_in.promiscious;
-			Gbps_en				<= ctrl_in.Gbps_en;
-			fcs_chk_en			<= ctrl_in.fcs_chk_en;
-			mac_addr			<= ctrl_in.mac_addr;
-			xfer_ram_limit		<= host_ram_limit;
-		end if;	
-	end process;	
-
-host_limit_register:
+xfer_state_next:
 	process(clk)
 	begin
 		if rising_edge(clk) then
-			host_ram_base	<= xfer_base;
-			if cmd_fifo_empty = '1' then
-				host_ram_limit	<= host_ram_base - 1;
-			else
-				host_ram_limit	<= cmd_base_out - 1;
-			end if;
-		end if;	
-			
-	end process;	
-
-xfer_ram_full_detect:
-	process(mii_rx_clk)
-	begin
-		if rising_edge(mii_rx_clk) then
-			if xfer_set = '1' or reset_en = '1' then
-				xfer_ram_full	<= '0';
-			elsif xfer_en = '1' and sipo32_dout_vld = '1' then
-				if xfer_ptr = xfer_ram_limit then
-					xfer_ram_full <= '1';
-				end if;
-			end if;
-		end if;	
-			
-	end process;	
-
-xfer_base_logic:
-	process(mii_rx_clk)
-	begin
-		if rising_edge(mii_rx_clk) then
-			if reset_en = '1' then
-				xfer_base		<= (others => '0');
-			elsif commit_en = '1' and xfer_vld = '1' then
-				xfer_base		<= xfer_ptr;
-			end if;
-		end if;
-	end process;	
-
-xfer_pointer:
-	process(mii_rx_clk)
-	begin
-		if rising_edge(mii_rx_clk) then
-			if xfer_set = '1' then
-				xfer_ptr		<= xfer_base;
-			elsif xfer_en = '1' and sipo32_dout_vld = '1' then
-				xfer_ptr		<= xfer_ptr + 1;
-			end if;
-		end if;	
-			
-	end process;	
-	
------------------------------------------------------------------
-byte_counter:
-	process(mii_rx_clk)
-	begin
-		if rising_edge(mii_rx_clk) then
-			if byte_count_rst = '1' then
-				if fcs_chk_en = '0' then
-					byte_count		<= to_unsigned(0, RAM_ADDR_WIDTH);
-				else
-					byte_count		<= unsigned(to_signed(-4, RAM_ADDR_WIDTH));
-				end if;
-			elsif sipo32_en = '1' and sipo32_din_vld = '1' then
-				byte_count		<= byte_count + 1;
-			end if;
-		end if;
-	end process;	
-
-preamble_sync_logic:
-	process(mii_rx_clk)
-	begin
-		if rising_edge(mii_rx_clk) then
-			if preamble_en = '0' then
-				preamble_rdy	<= '0';
-				preamble_bsy	<= '0';
-				preamble_OK		<= '0';
-			elsif sipo32_din_vld = '1' then
-				if preamble_bsy = '1' then
-					if sipo32_din = X"D5" then
-						preamble_OK		<= '1';
-					end if;
-				end if;
-				if sipo32_din /= X"55" then
-					preamble_bsy	<= '0';
-					preamble_rdy	<= preamble_bsy;
-				else
-					preamble_bsy	<= '1';
-				end if;
-			end if;
-		end if;
-	end process;	
-
-mac_check_logic:
-	process(mii_rx_clk)
-	begin
-		if rising_edge(mii_rx_clk) then
-			if byte_count_rst = '1' then
-				mac_chk_rdy			<= '0';
-				mac_chk_OK			<= '0';
-				mac_chk_BC			<= '0';
-				mac_chk_cnt			<= 0;
-				mac_chk_num_OK		<= 0;
-				mac_chk_num_BC		<= 0;
-				mac_chk_addr		<= mac_addr;
-			elsif mac_chk_rdy = '1' then
-				if mac_chk_num_OK = 6 then 
-					mac_chk_OK	<= '1';
-				end if;
-				if mac_chk_num_BC = 6 then 
-					mac_chk_BC	<= '1';
-				end if;
-			elsif sipo32_din_vld = '1' and sipo32_en = '1' then
-				if sipo32_din = mac_chk_addr(mac_chk_cnt) then
-					mac_chk_num_OK	<= mac_chk_num_OK + 1;
-				end if;
-				if sipo32_din = X"FF" then
-					mac_chk_num_BC	<= mac_chk_num_BC + 1;
-				end if;
-				if mac_chk_cnt /= 5 then
-					mac_chk_cnt			<= mac_chk_cnt + 1;
-				else
-					mac_chk_rdy			<= '1';
-				end if;
-			end if;
-		end if;
-	end process;	
-
------------------------------------------------------------------
-xfer_state_next:
-	process(mii_rx_clk)
-	begin
-		if rising_edge(mii_rx_clk) then
 			if reset_en = '1' then
 				xfer_s	<= xfer_init;
 			else
@@ -353,89 +190,274 @@ xfer_state_next:
 	end process;	

 xfer_state:
-	process(xfer_s, rx_en, sipo32_dout_en, preamble_bsy, preamble_OK, xfer_ram_full)
+	process(xfer_s, size_fifo_empty, mii_fifo_empty, xfer_rdy, xfer_ram_full)
 	begin
 	
 		commit_en			<= '0';
-		xfer_set			<= '0';
-		xfer_en				<= '0';
-		sipo32_rst			<= '0';
-		sipo32_en			<= '0';
-		byte_count_rst		<= '0';
-		preamble_en			<= '0';
+		xfer_ptr_set		<= '0';
+		xfer_ptr_adv		<= '0';
+		xfer_cnt_set		<= '0';
+		xfer_cnt_adv		<= '0';
+		size_fifo_re		<= '0';
+		mii_fifo_re			<= '0';

 		xfer_sn				<= xfer_s;
 		
 		case xfer_s is
 		
 		when xfer_init =>
-			sipo32_rst			<= '1';
-			if rx_en = '0' then
-				xfer_sn 			<= xfer_idle;
-			end if;
-			
+			xfer_sn 		<= xfer_idle;
+		
 		when xfer_idle =>
-			preamble_en			<= rx_en;
-			if preamble_bsy = '1' then
-				xfer_sn 		<= xfer_preamble;
-			end if;
-
-		when xfer_preamble =>
-			preamble_en		<= rx_en;
-			byte_count_rst	<= preamble_bsy;
-			sipo32_en	<= rx_en and not preamble_bsy;
-			if preamble_bsy = '0' then
-				xfer_sn 		<= xfer_init;
-				if preamble_OK = '1' then
-					xfer_sn 		<= xfer_setup;
-				end if;
-			end if;			
+			if mii_fifo_empty = '0' then
+				xfer_sn		<= xfer_setup;
+			end if;	
 			
 		when xfer_setup =>
-			xfer_set			<= '1';
-			sipo32_en			<= rx_en;
-			xfer_en				<= sipo32_dout_en;
-			xfer_sn 			<= xfer_active;
+			xfer_cnt_set	<= '1';
+			xfer_ptr_set	<= '1';
+			xfer_sn			<= xfer_active;
 		
 		when xfer_active =>
-			xfer_en				<= sipo32_dout_en;
-			sipo32_en			<= rx_en;
+			mii_fifo_re		<= '1';
+			xfer_cnt_adv	<= not mii_fifo_empty;
+			xfer_ptr_adv	<= not mii_fifo_empty;
 			if xfer_ram_full = '1' then
-				xfer_sn 		<= xfer_init;
-			elsif rx_en = '0' then
-				xfer_sn 		<= xfer_finish;
-			end if;
+				xfer_sn		<= xfer_drop;
+			elsif size_fifo_empty = '0' then
+				if xfer_rdy = '1' then
+					xfer_sn		<= xfer_free;
+				end if;
+			end if;	

-		when xfer_finish =>
-			xfer_en				<= sipo32_dout_en;
-			if sipo32_dout_en = '0' then
-				xfer_sn 		<= xfer_commit;
-			end if;
+		when xfer_drop =>
+			mii_fifo_re		<= '1';
+			xfer_cnt_adv	<= not mii_fifo_empty;
+			if size_fifo_empty = '0' then
+				if xfer_rdy = '1' then
+					xfer_sn		<= xfer_free;
+				end if;
+			end if;			

-		when xfer_commit =>
-			commit_en		<= '1';
-			xfer_sn			<= xfer_init;
+		when xfer_free =>
+			size_fifo_re	<= '1';
+			commit_en		<= not xfer_ram_full;
+			xfer_sn			<= xfer_idle;

 		when others => 
-			xfer_sn			<= xfer_init;
+			xfer_sn				<= xfer_idle;
+		end case;
+
+	end process;
+
+------------------------------------------------------------------
+pkt_lost_register:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if reset_en = '1' then
+				ctrl_out.pkt_lost	<= '0';
+			elsif size_fifo_re = '1' and xfer_ram_full = '1' then
+				ctrl_out.pkt_lost	<= '1';
+			elsif ctrl_in.pkt_free_en = '1' then
+				ctrl_out.pkt_lost	<= '0';
+			end if;
+		end if;	
+			
+	end process;	
+
+xfer_limit_register:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if xfer_ptr_set = '1' then
+				if cmd_fifo_empty = '1' then
+					xfer_ram_limit	<= xfer_base - 1;
+				else
+					xfer_ram_limit <= resize(cmd_fifo_dout(15 downto 0), word_ptr_t'length) - 1;
+				end if;
+			end if;
+		end if;	
+			
+	end process;	
+
+xfer_ram_full_detect:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if xfer_ptr_set = '1' or reset_en = '1' then
+				xfer_ram_full	<= '0';
+			elsif xfer_ptr_adv = '1' then
+				if xfer_ptr = xfer_ram_limit then
+					xfer_ram_full <= '1';
+				end if;
+			end if;
+		end if;	
+			
+	end process;	
+
+xfer_counter:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if xfer_cnt_set = '1' then
+				xfer_rdy	<= '0';
+			elsif xfer_size = size_fifo_dout(size_fifo_dout'left downto word_ptr_t'length) then
+				xfer_rdy	<= '1';
+			end if;			
+			if xfer_cnt_set = '1' then
+				xfer_size		<= (others => '0');
+			elsif xfer_cnt_adv = '1' then
+				xfer_size	<= xfer_size + 1;
+			end if;
+		end if;	
+			
+	end process;	
+	
+xfer_pointer:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if xfer_ptr_set = '1' then
+				xfer_ptr		<= xfer_base;
+			elsif xfer_ptr_adv = '1' then
+				xfer_ptr		<= xfer_ptr + 1;
+			end if;
+		end if;	
+			
+	end process;	
+	
+xfer_base_logic:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if reset_en = '1' then
+				xfer_base		<= (others => '0');
+			elsif commit_en = '1' then
+				xfer_base		<= xfer_ptr;
+			end if;
+		end if;
+	end process;	
+
+------------------------------------------------------------------
+byte_counter:
+	process(mii_rx_clk)
+	begin
+		if rising_edge(mii_rx_clk) then
+			if sipo_8bit_rst = '1' then
+				byte_count		<= (others => '0');
+			elsif byte_count_en = '1' and sipo_8bit_dout_vld = '1' then
+				byte_count		<= byte_count + 1;
+			end if;
+		end if;
+	end process;	
+
+byte_count_register:
+	process(mii_rx_clk)
+	begin
+		if rising_edge(mii_rx_clk) then
+			if sipo_8bit_rst = '1' then
+				byte_count_reg		<= byte_count;
+			end if;
+		end if;
+	end process;	
+
+word_counter:
+	process(mii_rx_clk)
+	begin
+		if rising_edge(mii_rx_clk) then
+			if sipo_32bit_rst = '1' then
+				word_count		<= (others => '0');
+			elsif word_count_en = '1' and sipo_32bit_dout_vld = '1' then
+				word_count		<= word_count + 1;
+			end if;
+		end if;
+	end process;	
+
+------------------------------------------------------------------
+stream_state_next:
+	process(mii_rx_clk)
+	begin
+		if rising_edge(mii_rx_clk) then
+			if reset_en = '1' then
+				stream_s	<= stream_init;
+			else
+				stream_s	<= stream_sn;
+			end if;
+		end if;
+	end process;	
+
+stream_state:
+	process(stream_s, sipo_8bit_dout_en, sipo_32bit_dout_en)
+	begin
+	
+		sipo_32bit_en		<= '0';
+		sipo_32bit_rst		<= '0';
+		sipo_8bit_rst		<= '0';
+		word_count_en		<= sipo_32bit_dout_en;
+		byte_count_en		<= sipo_8bit_dout_en;
+		size_fifo_we		<= '0';
+		
+		stream_sn			<= stream_s;
+		
+		case stream_s is
+		
+		when stream_init =>
+			sipo_32bit_rst		<= '1';
+			sipo_8bit_rst	<= '1';
+			if sipo_8bit_dout_en = '0' then
+				stream_sn 		<= stream_idle;
+			end if;
+			
+		when stream_idle =>
+			sipo_32bit_en				<= sipo_8bit_dout_en;
+			if sipo_8bit_dout_en = '1' then
+				stream_sn 		<= stream_start;
+			end if;
+			
+		when stream_start =>
+			sipo_32bit_en			<= sipo_8bit_dout_en;
+			if sipo_8bit_dout_en = '1' then
+				stream_sn 		<= stream_active;
+			end if;
+
+		when stream_active =>
+			sipo_32bit_en			<= sipo_8bit_dout_en;
+			if sipo_8bit_dout_en = '0' then
+				stream_sn 		<= stream_stop;
+				sipo_8bit_rst	<= '1';
+			end if;
+
+		when stream_stop =>
+			sipo_32bit_en			<= '0';
+			if sipo_32bit_dout_en = '0' then
+				stream_sn 		<= stream_finish;
+			end if;
+
+		when stream_finish =>
+			size_fifo_we	<= '1';
+			stream_sn		<= stream_idle;
+			sipo_32bit_rst		<= '1';
+
+		when others => 
+			stream_sn		<= stream_idle;
 		end case;

 	end process;

 ------------------------------------------------------------------
 -- Instantiate synchronous FIFO
-inst_cmd_fifo: entity work.fifo_async
+inst_cmd_fifo: entity work.fifo_sync
 	GENERIC MAP
 	(
 		addr_width			=> NextExpBaseTwo(RAM_SIZE) - 4,	-- RAMSIZE(words)/MIN_PACKET_LEN(words)
 		data_width			=> cmd_fifo_din'length,
-		do_last_read_update	=> false
+		do_last_read_update	=> true
 	)
 	PORT MAP
 	(
 		rst			=>	reset_en,
-		clk_w		=>	mii_rx_clk,
-		clk_r		=>	clk,
+		clk			=>	clk,
 		we			=>	cmd_fifo_we,
 		re			=>	cmd_fifo_re,
 		fifo_full	=>	cmd_fifo_full,
@@ -446,7 +468,7 @@ inst_cmd_fifo: entity work.fifo_async
 		data_r		=>  cmd_fifo_dout
 	);

-inst_ram : entity work.dpram_1w1r2c_ro
+inst_ram : entity work.dpram_1w1r
 	GENERIC MAP 
 	(
 		addr_width	=> RAM_ADDR_WIDTH,
@@ -454,18 +476,64 @@ inst_ram : entity work.dpram_1w1r2c_ro
 	)
 	PORT MAP 
 	(
-		clk_a		=> mii_rx_clk,
-		clk_b		=> clk,
-		en_a		=> ram_en_a,
-		en_b		=> ram_en_b,
-		we_a		=> ram_we_a,
-		addr_a		=> ram_addr_a,
-		addr_b		=> ram_addr_b,
-		din_a		=> ram_din_a,
-		dout_b		=> ram_dout_b
+		clka		=> clk,
+		clkb		=> clk,
+		en_a		=> ram_en_b,
+		en_b		=> ram_en_a,
+		we_a		=> ram_we_b,
+		addr_a		=> ram_addr_b,
+		addr_b		=> ram_addr_a,
+		din_a		=> ram_din_b,
+		dout_b		=> ram_dout_a
 	);

-inst_sipo32 : entity work.sipo
+-- Instantiate synchronous FIFO
+inst_mii_fifo: entity work.fifo_async
+	GENERIC MAP
+	(
+		addr_width			=> 4,
+		data_width			=> mii_fifo_din'length,
+		do_last_read_update	=> true
+	)
+	PORT MAP
+	(
+		rst			=>	reset_en,
+		clk_w		=>	mii_rx_clk,
+		clk_r		=>	clk,
+		we			=>	mii_fifo_we,
+		re			=>	mii_fifo_re,
+		fifo_full	=>	mii_fifo_full,
+		fifo_empty	=>	mii_fifo_empty,
+		fifo_afull	=>	open,
+		fifo_aempty	=>	open,
+		data_w		=>  mii_fifo_din,
+		data_r		=>  mii_fifo_dout
+	);
+
+-- Instantiate synchronous FIFO
+inst_size_fifo: entity work.fifo_async
+	GENERIC MAP
+	(
+		addr_width			=> 1,
+		data_width			=> 2*word_ptr_t'length,
+		do_last_read_update	=> true
+	)
+	PORT MAP
+	(
+		rst			=>	reset_en,
+		clk_w		=>	mii_rx_clk,
+		clk_r		=>	clk,
+		we			=>	size_fifo_we,
+		re			=>	size_fifo_re,
+		fifo_full	=>	size_fifo_full,
+		fifo_empty	=>	size_fifo_empty,
+		fifo_afull	=>	open,
+		fifo_aempty	=>	open,
+		data_w		=>  size_fifo_din,
+		data_r		=>  size_fifo_dout
+	);
+
+inst_sipo : entity work.sipo
 	GENERIC MAP
 	(
 		data_width_in	=> 8,
@@ -474,65 +542,18 @@ inst_sipo32 : entity work.sipo
 	)
 	PORT MAP
 	(
-		rst			=> sipo32_rst,
+		rst			=> sipo_32bit_rst,
 		clk			=> mii_rx_clk,
-		din_vld		=> sipo32_din_vld,
-		din_en		=> sipo32_en,
-		din			=> sipo32_din,
-		dout_be		=> sipo32_dout_be,
-		dout_vld	=> sipo32_dout_vld,
-		dout		=> sipo32_dout,
-		dout_en		=> sipo32_dout_en
+		din_vld		=> sipo_8bit_dout_vld,
+		din_en		=> sipo_32bit_en,
+		din			=> sipo_8bit_dout,
+		dout_be		=> sipo_32bit_dout_be,
+		dout_vld	=> sipo_32bit_dout_vld,
+		dout		=> sipo_32bit_dout,
+		dout_en		=> sipo_32bit_dout_en
 		
 	);
 	
-inst_fcs: entity work.crc32
-	GENERIC MAP
-	(
-		crc32_init		=> X"00000000"
-	)
-	PORT MAP
-	(
-		rst				=> byte_count_rst,
-		clk				=> mii_rx_clk,
-		din_vld			=> fcs_din_vld,
-		din				=> fcs_din,
-		crc32_vld		=> fcs_vld,
-		crc32_out		=> fcs
-		
-	);
-	
-	fcs_din		<= sipo32_din;
-	fcs_din_vld	<= sipo32_en and sipo32_din_vld;
-	
-fcs_chk_register:
-	process(mii_rx_clk)
-	begin
-		if rising_edge(mii_rx_clk) then
-			if fcs_vld = '1' then
-				fcs_chk_OK	<= '0';
-				if fcs = X"2144DF1C" then
-					fcs_chk_OK	<= '1';
-				end if;
-			end if;
-		end if;	
-	end process;	
-
-mii_input_register:
-	process(mii_rx_clk)
-	begin
-		if rising_edge(mii_rx_clk) then
-			if Gbps_en = '1' then
-				sipo32_din		<= mii_rx;
-				sipo32_din_vld	<= not mii_rx_er;
-				rx_en			<= mii_rx_dv;
-			else
-				sipo32_din		<= sipo8_dout;
-				sipo32_din_vld	<= sipo8_dout_vld;
-				rx_en			<= sipo8_dout_en;
-			end if;			
-		end if;	
-	end process;	

 inst_sipo_8bit : entity work.sipo
 	GENERIC MAP
@@ -543,19 +564,17 @@ inst_sipo_8bit : entity work.sipo
 	)
 	PORT MAP
 	(
-		rst			=> sipo8_rst,
+		rst			=> sipo_8bit_rst,
 		clk			=> mii_rx_clk,
 		din_vld		=> mii_rx_dv,
-		din_en		=> mii_rx_dv,
+		din_en		=> sipo_8bit_en,
 		din			=> mii_rx(3 downto 0),
 		dout_be		=> open,
-		dout_vld	=> sipo8_dout_vld,
-		dout		=> sipo8_dout,
-		dout_en		=> sipo8_dout_en
+		dout_vld	=> sipo_8bit_dout_vld,
+		dout		=> sipo_8bit_dout,
+		dout_en		=> sipo_8bit_dout_en
 		
 	);
-	
-	sipo8_rst		<= reset_en or not (mii_rx_dv or sipo8_dout_en);
-	sipo8_en		<= not mii_rx_er;
+	sipo_8bit_en	<= mii_rx_dv;
 	
 end behavior;
@@ -5,7 +5,6 @@ use std.textio.all; --  Imports the standard textio package.

 use work.emac_types.all;
 use work.utils_pkg.all;
-use work.busmaster_types.all;

 ENTITY emac_top_jb IS
 	Generic
@@ -16,7 +15,6 @@ ENTITY emac_top_jb IS
 	);
 	Port
 	(
-		-- JBUS Slave
 		CLK_I		: in  STD_LOGIC;
 		RST_I		: in  STD_LOGIC;
 		INT_O		: out STD_LOGIC;
@@ -30,20 +28,6 @@ ENTITY emac_top_jb IS
 		ADDR_I		: in  unsigned(31 downto 0);
 		DAT_I		: in  unsigned(31 downto 0);
 		DAT_O		: out unsigned(31 downto 0);
-		
-		-- JBUS Master
-		ACK_I		: in std_logic;
-		SRDY_I		: in std_logic;
-		MDAT_I		: in unsigned(31 downto 0);
-		MDAT_O		: out unsigned(31 downto 0);
-		ADDR_O		: out unsigned(31 downto 0);
-		SEL_O		: out unsigned(3 downto 0);
-		WE_O		: out std_logic;
-		CYC_O		: out std_logic;
-		STB_O		: out std_logic;
-		MRDY_O		: out std_logic;
-		
-		-- MII
 		mii_rx_clk	: in  STD_LOGIC;
 		mii_rx_dv	: in  STD_LOGIC;
 		mii_rx_er	: in  STD_LOGIC;
@@ -61,12 +45,6 @@ END emac_top_jb;

 ARCHITECTURE behavior OF emac_top_jb IS

-	-- Constants
-	constant DMA_NUM_CHANNEL		: integer := 2;
-	constant DMA_CH_WRITE			: integer := 0;
-	constant DMA_CH_READ			: integer := 1;
-	constant DMA_RW_CONF			: unsigned(DMA_NUM_CHANNEL-1 downto 0) := "01";
-
 	-- Signals for EMAC connections
 	signal tx_ctrl_in		: tx_ctrl_in_t;
 	signal tx_ctrl_out		: tx_ctrl_out_t;
@@ -77,7 +55,7 @@ ARCHITECTURE behavior OF emac_top_jb IS
 	signal rx_ctrl_out		: rx_ctrl_out_t;

 	signal rx_dout			: unsigned(31 downto 0);
-	signal rx_dout_re		: std_logic;
+	signal rx_dout_vld		: std_logic;
 	
 	signal rx_int_en		: std_logic;
 	signal tx_int_en		: std_logic;
@@ -86,164 +64,53 @@ ARCHITECTURE behavior OF emac_top_jb IS

 	signal ready			: std_logic;

-	signal read				: std_logic;
-	signal write			: std_logic;
-	signal rx_read_en_CPU	: std_logic;
-	signal rx_req_en_CPU	: std_logic;
-	signal rx_free_en_CPU	: std_logic;
-	signal tx_write_en_CPU	: std_logic;
-	signal reg_read			: std_logic;
-	signal reg_write		: std_logic;
-
-	signal reg_addr			: unsigned(3 downto 0);
-
-	-- DMA Controller
-	signal dma_master_req			: unsigned(DMA_NUM_CHANNEL-1 downto 0);
-	signal dma_master_gnt			: unsigned(DMA_NUM_CHANNEL-1 downto 0) := (others => '0');
-	signal dma_req_rdy				: unsigned(DMA_NUM_CHANNEL-1 downto 0);
-	signal dma_req_en				: unsigned(DMA_NUM_CHANNEL-1 downto 0) := (others => '0');
-	signal dma_req_addr_auto_inc	: unsigned(DMA_NUM_CHANNEL-1 downto 0);
-	type array32_t is array (0 to DMA_NUM_CHANNEL-1) of unsigned(31 downto 0);
-	signal dma_req_addr				: array32_t;
-	signal dma_req_num_xfers		: array32_t;
-
-	signal dma_req_complete			: unsigned(DMA_NUM_CHANNEL-1 downto 0);
-	signal dma_req_complete_ack		: unsigned(DMA_NUM_CHANNEL-1 downto 0) := (others => '0');
-
-	signal dma_start					: unsigned(DMA_NUM_CHANNEL-1 downto 0);
-	signal dma_active					: unsigned(DMA_NUM_CHANNEL-1 downto 0);
-	signal dma_end						: unsigned(DMA_NUM_CHANNEL-1 downto 0);
-	signal dma_bus_cmd_cycle_finished	: unsigned(DMA_NUM_CHANNEL-1 downto 0);
-	signal dma_bus_cmd_cycle_en			: unsigned(DMA_NUM_CHANNEL-1 downto 0) := (others => '0');
-	signal dma_bus_cmd_rdy				: unsigned(DMA_NUM_CHANNEL-1 downto 0);
-	signal dma_bus_cmd_we				: unsigned(DMA_NUM_CHANNEL-1 downto 0) := (others => '0');
-	type array_bus_cmd_t is array (0 to DMA_NUM_CHANNEL-1) of bm_cmd_t;
-	signal dma_bus_cmd					: array_bus_cmd_t;
-
-	-- Busmaster arbiter
-	signal	arb_idx					: natural range 0 to DMA_NUM_CHANNEL-1;
-
-	-- BUS Master controller
-	signal bus_din_re				: std_logic;
-	signal bus_cmd_cycle_finished	: std_logic;
-	signal bus_cmd_cycle_en			: std_logic := '0';
-	signal bus_cmd_rdy				: std_logic;
-	signal bus_cmd_we				: std_logic := '0';
-	signal bus_cmd					: bm_cmd_t;
-	signal bus_din_rdy				: std_logic;
-	signal bus_din_vld				: std_logic := '0';
-	signal bus_din					: unsigned(31 downto 0) := (others => '-');
-	signal bus_dout					: unsigned(31 downto 0);
-	signal bus_dout_vld				: std_logic;
-	signal bus_dout_re				: std_logic := '0';
-	
 begin

-	mii_gtx_clk				<= '0';
+	SRDY_O				<= CYC_I and ready;
+	mii_gtx_clk			<= '0';

-	SRDY_O					<= CYC_I and ready;
-	read					<= STB_I and CYC_I and not WE_I;
-	write					<= STB_I and CYC_I and WE_I;
-	rx_read_en_CPU			<= read and ADDR_I(15);
-	tx_write_en_CPU			<= write and ADDR_I(15);
-	reg_read				<= read and not ADDR_I(15);
-	reg_write				<= write and not ADDR_I(15);
-	reg_addr				<= ADDR_I(5 downto 2);
-
-	ready					<= not tx_ctrl_in.pkt_alloc_en;
-	
-	tx_din_vld				<= tx_write_en_CPU;
-	tx_din					<= DAT_I;
-
-	rx_ctrl_in.pkt_free_en	<= rx_free_en_CPU or dma_end(0);
-	rx_ctrl_in.pkt_req_en	<= rx_req_en_CPU or dma_start(0);
-
-	rx_dout_re				<= rx_read_en_CPU or (dma_active(DMA_CH_WRITE) and bus_din_rdy);
-	
-	bus_din					<= rx_dout;
-	bus_din_vld				<= dma_active(DMA_CH_WRITE);
-	dma_master_gnt(0)		<= SRDY_I;
-	dma_req_en(0)			<= rx_ctrl_out.pkt_avail;
-	dma_req_num_xfers(0)	<= X"0000" & "00" & rx_ctrl_out.rx_size(15 downto 2) when rx_ctrl_out.rx_size(1 downto 0) = "00" else X"0000" & "00" & rx_ctrl_out.rx_size(15 downto 2) + 1;
-	dma_req_addr(0)			<= X"00000800";
-	dma_req_addr_auto_inc	<= "11";
+	ready				<= not tx_ctrl_in.pkt_alloc_en;
 	
 ------------------------------------------------------------------
 registers_write: 
 	process(CLK_I)
 	begin
 		if rising_edge(CLK_I) then
+			tx_din_vld					<= '0';
 			tx_ctrl_in.pkt_alloc_en		<= '0';
 			tx_ctrl_in.pkt_commit_en	<= '0';
 			tx_ctrl_in.reset			<= '0';
-			rx_free_en_CPU				<= '0';
-			rx_req_en_CPU				<= '0';
+			rx_ctrl_in.pkt_free_en		<= '0';
+			rx_ctrl_in.pkt_req_en		<= '0';
 			rx_ctrl_in.reset			<= '0';
 			if RST_I = '1' then
-				rx_int_en				<= '0';
-				tx_int_en				<= '0';
-				tx_ctrl_in.tx_size		<= (others => '0');
-				rx_ctrl_in.mac_addr		<= (X"03", X"02", X"01", X"00", X"07", X"06");
-				rx_ctrl_in.promiscious	<= '0';
-				tx_ctrl_in.Gbps_en		<= '0';
-				rx_ctrl_in.Gbps_en		<= '0';
-				tx_ctrl_in.fcs_gen_en	<= '0';
-				rx_ctrl_in.fcs_chk_en	<= '0';
-			elsif reg_write = '1' then
-			
-				-- 0x0000 .. 0x003C
-				case reg_addr is
-
-				-- 0x0000
-				when "0000" =>
-					rx_ctrl_in.reset			<= DAT_I(31);
-					rx_ctrl_in.Gbps_en			<= DAT_I(30);
-					rx_ctrl_in.fcs_chk_en		<= DAT_I(29);
-					rx_ctrl_in.promiscious		<= DAT_I(23);
-					rx_req_en_CPU				<= DAT_I(17);
-					rx_free_en_CPU				<= DAT_I(16);
-					rx_int_en					<= DAT_I(4);
-
-				-- 0x0004
-				-- rx_size R/O
-
-				-- 0x0008
-				when "0010" =>
-					tx_ctrl_in.reset			<= DAT_I(31);
-					tx_ctrl_in.Gbps_en			<= DAT_I(30);
-					tx_ctrl_in.fcs_gen_en		<= DAT_I(29);
-					tx_ctrl_in.pkt_alloc_en		<= DAT_I(17);
-					tx_ctrl_in.pkt_commit_en	<= DAT_I(16);
-					tx_int_en					<= DAT_I(4);
-
-				-- 0x000C
-				when "0011" => 
-					tx_ctrl_in.tx_size			<= DAT_I(15 downto 0);
-
-				-- 0x0010
-				-- Gap
-
-				-- 0x0014
-				-- Gap
-
-				-- 0x0018
-				when "0110" =>
-					rx_ctrl_in.mac_addr(0)		<= DAT_I(31 downto 24);
-					rx_ctrl_in.mac_addr(1)		<= DAT_I(23 downto 16);
-					rx_ctrl_in.mac_addr(2)		<= DAT_I(15 downto 8);
-					rx_ctrl_in.mac_addr(3)		<= DAT_I(7 downto 0);
-
-				-- 0x001C
-				when "0111" =>
-					rx_ctrl_in.mac_addr(4)		<= DAT_I(31 downto 24);
-					rx_ctrl_in.mac_addr(5)		<= DAT_I(23 downto 16);
-
-				-- 0x0020 .. 0x003C
-				-- Gap
-				when others => null;
-
-				end case;
+				rx_int_en			<= '0';
+				tx_int_en			<= '0';
+				tx_ctrl_in.tx_er	<= '0';
+				tx_ctrl_in.tx_size	<= (others => '0');
+			elsif (STB_I and CYC_I and WE_I) = '1' then
+				case ADDR_I(5 downto 2) is
 				
+				when "0000" =>
+					tx_ctrl_in.tx_er			<= DAT_I(31);
+					tx_ctrl_in.reset			<= DAT_I(27);
+					tx_ctrl_in.pkt_alloc_en		<= DAT_I(25);
+					tx_ctrl_in.pkt_commit_en	<= DAT_I(24);
+					rx_ctrl_in.reset			<= DAT_I(23);
+					rx_ctrl_in.pkt_free_en		<= DAT_I(17);
+					rx_ctrl_in.pkt_req_en		<= DAT_I(16);
+					tx_int_en					<= DAT_I(5);
+					rx_int_en					<= DAT_I(4);
+					
+				when "0001" => 
+					tx_ctrl_in.tx_size			<= DAT_I(31 downto 16);
+					
+				when "0010" =>
+					tx_din_vld					<= '1';
+					tx_din						<= DAT_I;
+					
+				when others => null;
+				end case;
 			end if;	
 		end if;	
 	end process;
@@ -252,71 +119,37 @@ registers_read:
 	process(CLK_I)
 	begin
 		if rising_edge(CLK_I) then
-			ACK_O					<= rx_read_en_CPU;
+			rx_ctrl_in.pkt_read_en	<= '0';
+			ACK_O					<= rx_dout_vld and CYC_I and not WE_I;
 			DAT_O					<= rx_dout;
-			if reg_read = '1' then
-				
-				-- 0x0000 .. 0x003C
-				case reg_addr is
+			if (STB_I and CYC_I) = '1' and WE_I = '0' then
+				case ADDR_I(5 downto 2) is

-				-- 0x0000
-				when "0000" =>	
+				when "0000" =>
 					ACK_O		<= ready;
 					DAT_O		<= (others => '0');
-					DAT_O(31)	<= rx_ctrl_out.reset_busy;
-					DAT_O(30)	<= rx_ctrl_in.Gbps_en;
-					DAT_O(29)	<= rx_ctrl_in.fcs_chk_en;
-					DAT_O(23)	<= rx_ctrl_in.promiscious;
-					DAT_O(19)	<= rx_ctrl_out.pkt_bcast;
-					DAT_O(18)	<= rx_ctrl_out.pkt_mac_match;
-					DAT_O(17)	<= rx_ctrl_out.pkt_valid;
+					DAT_O(31)	<= tx_ctrl_in.tx_er;
+					DAT_O(30)	<= mii_rx_er;
+					DAT_O(29)	<= mii_col;
+					DAT_O(28)	<= mii_crs;
+					DAT_O(27)	<= tx_ctrl_out.reset_busy;
+					DAT_O(26)	<= tx_ctrl_out.pkt_done;
+					DAT_O(25)	<= tx_ctrl_out.pkt_alloc_req;
+					DAT_O(24)	<= tx_ctrl_out.pkt_armed;
+					DAT_O(23)	<= rx_ctrl_out.reset_busy;
+					DAT_O(17)	<= rx_ctrl_out.pkt_lost;
 					DAT_O(16)	<= rx_ctrl_out.pkt_avail;
+					DAT_O(5)	<= tx_int_en;
 					DAT_O(4)	<= rx_int_en;
-
-				-- 0x0004
 				when "0001" => 
 					ACK_O		<= '1';
-					DAT_O		<= X"0000" & rx_ctrl_out.rx_size;
+					DAT_O		<= tx_ctrl_out.tx_size & rx_ctrl_out.rx_size;

-				-- 0x0008
 				when "0010" =>
-					ACK_O		<= ready;
-					DAT_O		<= (others => '0');
-					DAT_O(31)	<= tx_ctrl_out.reset_busy;
-					DAT_O(30)	<= tx_ctrl_in.Gbps_en;
-					DAT_O(29)	<= tx_ctrl_in.fcs_gen_en;
-					DAT_O(24)	<= tx_ctrl_out.pkt_done;
-					DAT_O(17)	<= tx_ctrl_out.pkt_alloc_req;
-					DAT_O(16)	<= tx_ctrl_out.pkt_armed;
-					DAT_O(4)	<= tx_int_en;
-
-				-- 0x000C
-				when "0011" => 
-					ACK_O		<= '1';
-					DAT_O		<= X"0000" & tx_ctrl_out.tx_size;
-
-				-- 0x0010
-				-- Gap
-
-				-- 0x0014
-				-- Gap
-
-				-- 0x0018
-				when "0110" =>
-					ACK_O		<= '1';
-					DAT_O		<= rx_ctrl_in.mac_addr(0) & rx_ctrl_in.mac_addr(1) & rx_ctrl_in.mac_addr(2) & rx_ctrl_in.mac_addr(3);
-
-				-- 0x001C
-				when "0111" =>
-					ACK_O		<= '1';
-					DAT_O		<= rx_ctrl_in.mac_addr(4) & rx_ctrl_in.mac_addr(5) & X"0000";
-
-				-- 0x0020 .. 0x003C
-				-- Gap
+					rx_ctrl_in.pkt_read_en	<= '1';
+						
 				when others => null;
-
 				end case;
-
 			end if;
 		end if;	
 	end process;
@@ -341,7 +174,7 @@ inst_emac_rx : entity work.emac_rx
 	(
 		clk			=> CLK_I,
 		rst			=> RST_I,
-		dout_re		=> rx_dout_re,
+		dout_vld	=> rx_dout_vld,
 		dout		=> rx_dout,
 		ctrl_in		=> rx_ctrl_in,
 		ctrl_out	=> rx_ctrl_out,
@@ -376,128 +209,5 @@ inst_emac_tx : entity work.emac_tx
 		
 	);

-gen_dmac:
-for i in 0 to DMA_NUM_CHANNEL-1 generate
-	
-	dma_bus_cmd_cycle_finished(i)	<= bus_cmd_cycle_finished;
-	dma_bus_cmd_rdy(i) 				<= bus_cmd_rdy;
-
-	inst_dmac : entity work.dmac
-	Generic map
-	(
-		DATA_WIDTH			=> 32,
-		XFER_CHUNK_SIZE		=> 32
-	)
-	Port map
-	(
-		clk					=> CLK_I,
-		rst					=> RST_I,
-
-		master_req			=> dma_master_req(i),
-		master_gnt			=> dma_master_gnt(i),
-
-		req_rdy				=> dma_req_rdy(i),
-		req_en				=> dma_req_en(i),
-		req_rw				=> DMA_RW_CONF(i),
-		req_addr_auto_inc	=> dma_req_addr_auto_inc(i),
-		req_addr_start		=> dma_req_addr(i),
-		req_num_xfers		=> dma_req_num_xfers(i),
-
-		req_complete		=> dma_req_complete(i),
-		req_complete_ack	=> dma_req_complete_ack(i),
-
-		dma_start			=> dma_start(i),
-		dma_active			=> dma_active(i),
-		dma_end				=> dma_end(i),
-
-		-- busmaster control
-		bus_cyc_complete	=> dma_bus_cmd_cycle_finished(i),
-		bus_cmd_rdy			=> dma_bus_cmd_rdy(i),
-		bus_cmd_we			=> dma_bus_cmd_we(i),
-		bus_cmd_cycle_en	=> dma_bus_cmd_cycle_en(i),
-
-		-- busmaster command
-		bus_cmd_out			=> dma_bus_cmd(i)
-	);
-
-end generate;
-
-inst_busmaster_sync : entity work.busmaster_sync
-	GENERIC MAP
-	(
-		DATA_WIDTH					=> 32,
-		FIFO_DEPTH					=> 4
-	)
-	PORT MAP
-	(
-		-- System signals
-		rst					=> RST_I,
-		clk					=> CLK_I,
-
-		cmd_cycle_finished	=> bus_cmd_cycle_finished,
-		cmd_cycle_en		=> bus_cmd_cycle_en,
-		
-		cmd_rdy				=> bus_cmd_rdy,
-		cmd_we				=> bus_cmd_we,
-		cmd_in				=> bus_cmd,
-		
-		din_rdy				=> bus_din_rdy,
-		din_we				=> bus_din_vld,
-		din					=> bus_din,
-
-		dout				=> bus_dout,
-		dout_vld			=> bus_dout_vld,
-		dout_re				=> bus_dout_re,
-
-		-- JBUS Master signals
-		CYC_O				=> CYC_O,
-		STB_O				=> STB_O,
-		WE_O				=> WE_O,
-		SEL_O				=> SEL_O,
-		ACK_I				=> ACK_I,
-		SRDY_I				=> SRDY_I,
-		MRDY_O				=> MRDY_O,
-		ADDR_O				=> ADDR_O,
-		MDAT_I				=> MDAT_I,
-		MDAT_O				=> MDAT_O
-	);
-
-arbiter_proc:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if RST_I = '1' then
-				dma_master_gnt	<= (others => '0');
-				arb_idx	<= 0;
-			elsif dma_master_req(arb_idx) = '0' then
-				if arb_idx /= DMA_NUM_CHANNEL-1 then
-					arb_idx	<= arb_idx + 1;
-				else
-					arb_idx	<= 0;
-				end if;
-			else	
-				dma_master_gnt	<= (others => '0');
-				dma_master_gnt(arb_idx)	<= '1';
-			end if;	
-		end if;
-	end process;
-
-arbiter_mux:
-	process(dma_master_gnt, dma_bus_cmd, dma_bus_cmd_we, dma_bus_cmd_cycle_en)
-	variable v_bus_cmd_we : std_logic;
-	variable v_bus_cmd_cycle_en : std_logic;
-	begin
-		v_bus_cmd_we := '0';
-		v_bus_cmd_cycle_en := '0';
-		for i in 0 to DMA_NUM_CHANNEL-1 loop
-			v_bus_cmd_we := v_bus_cmd_we or dma_bus_cmd_we(i);
-			v_bus_cmd_cycle_en := v_bus_cmd_cycle_en or dma_bus_cmd_cycle_en(i);
-			if dma_master_gnt(i) = '1' then
-				bus_cmd <= dma_bus_cmd(i);
-			end if;
-		end loop;
-		bus_cmd_we <= v_bus_cmd_we;
-		bus_cmd_cycle_en <= v_bus_cmd_cycle_en;
-end process;

 end behavior;
@@ -34,8 +34,15 @@ ARCHITECTURE behavior OF emac_tx IS
 	
 	subtype word_ptr_t is unsigned(RAM_ADDR_WIDTH-1 downto 0);
 	
-	signal cmd_fifo_din		: unsigned(2*word_ptr_t'length-1 downto 0);
-	signal cmd_fifo_dout	: unsigned(2*word_ptr_t'length-1 downto 0);
+	signal mii_fifo_din		: unsigned(35 downto 0);
+	signal mii_fifo_dout	: unsigned(35 downto 0);
+	signal mii_fifo_we		: std_logic;
+	signal mii_fifo_re		: std_logic;
+	signal mii_fifo_empty	: std_logic;
+	signal mii_fifo_full	: std_logic;
+
+	signal cmd_fifo_din		: unsigned(35 downto 0);
+	signal cmd_fifo_dout	: unsigned(35 downto 0);
 	signal cmd_fifo_we		: std_logic;
 	signal cmd_fifo_re		: std_logic;
 	signal cmd_fifo_empty	: std_logic;
@@ -47,12 +54,12 @@ ARCHITECTURE behavior OF emac_tx IS
 	signal fill_size		: word_ptr_t;
 	signal fill_cnt			: word_ptr_t;
 	signal fill_ptr			: word_ptr_t;
-	signal fill_pre_rdy		: std_logic;
-	signal fill_bsy			: std_logic;
+	signal fill_rdy			: std_logic;
+	signal fill_cnt_set		: std_logic;
+	signal fill_cnt_adv		: std_logic;
+	signal fill_ptr_set		: std_logic;
+	signal fill_ptr_adv		: std_logic;
 	signal fill_remain		: unsigned(1 downto 0);
-	signal fill_set			: std_logic;
-	signal fill_en			: std_logic;
-	signal fill_cnt_en		: std_logic;

 	signal alloc_OK			: std_logic;
 	signal alloc_req		: std_logic;
@@ -60,70 +67,57 @@ ARCHITECTURE behavior OF emac_tx IS
 	signal alloc_size		: word_ptr_t;
 	signal alloc_remain		: unsigned(1 downto 0);
 	
+	signal nwords_free		: word_ptr_t;
+	signal mem_alloc_en		: std_logic;
+
+	signal mem_free_en		: std_logic;
 	signal commit_en		: std_logic;
 	signal uncommit_en		: std_logic;
-	signal mem_alloc_en		: std_logic;
-	signal mem_free_en		: std_logic;
-	signal nwords_free		: word_ptr_t;
-	signal mem_free_req		: std_logic;
-	signal mem_free_ack		: unsigned(1 downto 0);

 	signal xfer_size		: word_ptr_t;
 	signal xfer_ptr			: word_ptr_t;
 	signal xfer_cnt			: word_ptr_t;
-	signal xfer_set			: std_logic;
-	signal xfer_en			: std_logic;
-	signal xfer_cnt_en		: std_logic;
-	signal xfer_bsy			: std_logic;
-	signal xfer_free_en		: std_logic;
+	signal xfer_ptr_set		: std_logic;
+	signal xfer_ptr_adv		: std_logic;
+	signal xfer_cnt_set		: std_logic;
+	signal xfer_cnt_adv		: std_logic;
+	signal xfer_rdy			: std_logic;
+	signal xfer_tag			: unsigned(3 downto 0);
+	signal xfer_remain		: unsigned(1 downto 0);
+	signal xfer_odd			: std_logic;
+	signal xfer_remain_en	: std_logic;

 	signal ram_en_a			: std_logic;
 	signal ram_we_a			: std_logic;
 	signal ram_addr_a		: word_ptr_t;
-	signal ram_din_a		: unsigned(35 downto 0);
+	signal ram_din_a		: unsigned(31 downto 0);
+	signal ram_dout_a		: unsigned(31 downto 0);
 	signal ram_en_b			: std_logic;
 	signal ram_addr_b		: word_ptr_t;
-	signal ram_dout_b		: unsigned(35 downto 0);
+	signal ram_din_b		: unsigned(31 downto 0);
+	signal ram_dout_b		: unsigned(31 downto 0);

-	signal piso32_din		: unsigned(31 downto 0);
-	signal piso32_din_be		: unsigned(3 downto 0);
-	signal piso32_din_rdy	: std_logic;
-	signal piso32_din_vld	: std_logic;
+	signal piso_din_be		: unsigned(3 downto 0);
+	signal piso_din_rdy		: std_logic;
+	signal data_vld			: std_logic;

-	signal piso32_dout		: unsigned(7 downto 0);
-	signal piso32_dout_vld	: std_logic;
-	signal piso32_dout_en	: std_logic;
+	signal piso_dout			: unsigned(7 downto 0);
+	signal piso_dout_vld		: std_logic;
+	signal piso_10mbps_din_rdy	: std_logic;
+	signal tx_en				: std_logic;
 	
-	signal piso8_dout_vld	: std_logic;
-	signal piso8_din_rdy	: std_logic;
-	signal piso8_din_vld	: std_logic;
-	signal piso8_dout		: unsigned(3 downto 0);
-	signal piso8_din		: unsigned(7 downto 0);
-	
-	signal reset_pipe		: unsigned(31 downto 0);
-	signal Gbps_en			: std_logic;
-	signal fcs_gen_en		: std_logic;
-	
-	signal fcs_inject_en	: std_logic;
-	signal fcs_rst			: std_logic;
-	signal fcs_en			: unsigned(7 downto 0);
-	signal fcs_vld			: std_logic;
-	signal fcs_din_vld		: std_logic;
-	signal fcs				: unsigned(31 downto 0);
-	signal fcs_rev_endian	: unsigned(31 downto 0);
-	
-	signal mii_fifo_we		: std_logic;
-	signal mii_fifo_re		: std_logic;
-	signal mii_fifo_full	: std_logic;
-	signal mii_fifo_empty	: std_logic;
-	signal mii_fifo_re_dly	: unsigned(23 downto 0);
+	signal reset_pipe			: unsigned(31 downto 0);

-	signal mii_bsy			: std_logic;
-
-	type host_state_t is (host_init, host_idle, host_alloc, host_setup, host_arm, host_fill, host_commit);
+	subtype ifg_cnt_t is natural range 0 to 23;		-- 10/100 mbps
+--	subtype ifg_cnt_t is natural range 0 to 11;		-- 1000 mbps
+	signal ifg_cnt	: ifg_cnt_t;
+	signal ifg_rdy	: std_logic;
+	signal ifg_idle	: std_logic;
+	
+	type host_state_t is (host_init, host_flush, host_idle, host_alloc, host_setup, host_arm, host_fill, host_commit);
 	signal host_s, host_sn : host_state_t;
 	
-	type xfer_state_t is (xfer_init, xfer_idle, xfer_start, xfer_preamble0, xfer_preamble1, xfer_active, xfer_crc, xfer_stop, xfer_finish);
+	type xfer_state_t is (xfer_init, xfer_idle, xfer_setup, xfer_arm, xfer_active, xfer_uncommit, xfer_free, xfer_wait);
 	signal xfer_s, xfer_sn : xfer_state_t;

 	type piso_byte_mask_array_t is array (0 to 3) of unsigned (3 downto 0);
@@ -135,45 +129,35 @@ ARCHITECTURE behavior OF emac_tx IS
 		"1110"
 	);
 	
-	signal preamble_en		: std_logic;
-	signal preamble_addr	: natural range 0 to 1;
-	type preamble_t is array (0 to 1) of unsigned(31 downto 0);
-	constant preamble : preamble_t :=
-	(
-		X"55555555",
-		X"555555D5"
-	);
 	
-
 begin

 	ctrl_out.pkt_alloc_req	<= alloc_req;
 	ctrl_out.pkt_done		<= cmd_fifo_empty;
 	ctrl_out.reset_busy		<= reset_en;
+	mii_tx_er				<= ctrl_in.tx_er;
+
 	
-	ram_en_a				<= din_vld;
-	ram_we_a				<= fill_bsy;
-	ram_din_a(31 downto 0)	<= din;
-	ram_din_a(35 downto 32)	<= piso_byte_mask_rom(to_integer(fill_remain)) when fill_pre_rdy = '1' else "1111";
+	ram_en_a				<= '1';
+	ram_we_a				<= fill_ptr_adv;
+	ram_din_a				<= din;
 	ram_addr_a				<= fill_ptr;
 	
-	piso32_din				<= preamble(preamble_addr) when preamble_en = '1' else fcs_rev_endian when fcs_inject_en = '1' else ram_dout_b(31 downto 0);
-	piso32_din_be			<= "1111" when (preamble_en = '1' or fcs_inject_en = '1') else ram_dout_b(35 downto 32);
-
+	piso_din_be				<= mii_fifo_dout(35 downto 32);
+	mii_fifo_re				<= piso_din_rdy;
+	data_vld				<= not mii_fifo_empty;
+	
+	mii_fifo_din(35 downto 32)	<= piso_byte_mask_rom(to_integer(xfer_remain)) when xfer_remain_en = '1' else "1111";
+	mii_fifo_din(31 downto 0)	<= ram_dout_b;
+	
 	cmd_fifo_we				<= commit_en;
 	cmd_fifo_re				<= uncommit_en;
-	cmd_fifo_din			<= fill_size & fill_base;
-	ram_en_b				<= piso32_din_rdy;
+	cmd_fifo_din			<= fill_remain & "01" & resize(fill_size, 16) & resize(fill_base, 16);
+	ram_en_b				<= not mii_fifo_full;
 	ram_addr_b				<= xfer_ptr;
+	xfer_tag				<= cmd_fifo_dout(35 downto 32);
 	
 	reset_en				<= reset_pipe(reset_pipe'left);
-	
-	xfer_cnt_en				<= xfer_bsy and piso32_din_rdy;
-	fill_cnt_en				<= fill_bsy and din_vld;
-	mem_free_en				<= not mem_free_ack(0) and mem_free_ack(1);
-	
-	fcs_rev_endian			<= fcs(7 downto 0) & fcs(15 downto 8) & fcs(23 downto 16) & fcs(31 downto 24);
-	
 ------------------------------------------------------------------
 reset_gen:
 	process(clk)
@@ -201,11 +185,13 @@ host_state_next:
 	end process;	

 host_state:
-	process(host_s, alloc_OK, fill_bsy, ctrl_in.pkt_commit_en, alloc_req, mem_free_ack)
+	process(host_s, alloc_OK, fill_rdy, din_vld, ctrl_in.pkt_commit_en, alloc_req)
 	begin
 	
-		fill_set			<= '0';
-		fill_en				<= '0';
+		fill_cnt_set		<= '0';
+		fill_cnt_adv		<= '0';
+		fill_ptr_set		<= '0';
+		fill_ptr_adv		<= '0';
 		commit_en			<= '0';
 		alloc_ack			<= '0';
 		mem_alloc_en		<= '0';
@@ -231,16 +217,18 @@ host_state:
 			end if;

 		when host_setup =>
-			fill_set		<= '1';
 			host_sn			<= host_arm;
+			fill_cnt_set	<= '1';
+			fill_ptr_set	<= '1';

 		when host_arm =>
-			fill_en			<= '1';
 			alloc_ack		<= '1';
+			fill_cnt_adv	<= '1';
 			host_sn			<= host_fill;

 		when host_fill =>
-			fill_en			<= '1';
+			fill_cnt_adv	<= din_vld;
+			fill_ptr_adv	<= not fill_rdy and din_vld;
 			if alloc_req = '1' then
 				host_sn		<= host_alloc;
 			elsif ctrl_in.pkt_commit_en = '1' then
@@ -248,11 +236,9 @@ host_state:
 			end if;
 		
 		when host_commit =>
-			if mem_free_ack = "00" then
-				commit_en		<= '1';
-				mem_alloc_en	<= '1';
-				host_sn			<= host_idle;
-			end if;
+			commit_en		<= '1';
+			mem_alloc_en	<= '1';
+			host_sn			<= host_idle;

 		when others => 
 			host_sn			<= host_idle;
@@ -279,6 +265,10 @@ alloc_request_logic:
 				ctrl_out.tx_size	<= resize(ctrl_in.tx_size(word_ptr_t'left downto 0), 16);
 			elsif alloc_ack = '1' then
 				alloc_req				<= '0';
+				if alloc_OK = '1' then
+					fill_size				<= alloc_size;
+					fill_remain				<= alloc_remain;
+				end if;
 			end if;
 		end if;
 	end process;	
@@ -322,7 +312,7 @@ fill_base_logic:
 	end process;	

 ------------------------------------------------------------------
-mem_free_counter:
+nwords_free_counter:
 	process(clk)
 	begin
 		if rising_edge(clk) then
@@ -336,41 +326,6 @@ mem_free_counter:
 		end if;
 	end process;	

------------------------------------------------------------------
-mem_free_mii:
-	process(mii_tx_clk)
-	begin
-		if rising_edge(mii_tx_clk) then
-			if reset_en = '1' then
-				mem_free_req	<= '0';
-			elsif mem_free_ack(0) = '0' then
-				if xfer_free_en = '1' then
-					mem_free_req	<= '1';
-				end if;
-			else
-				mem_free_req	<= '0';
-			end if;
-		end if;
-	end process;	
-
------------------------------------------------------------------
-mem_free_host:
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			mem_free_ack(1)	<= mem_free_ack(0);
-			if reset_en = '1' then
-				mem_free_ack	<= "00";
-			elsif mem_free_req = '1' then
-				if mem_alloc_en = '0' then
-					mem_free_ack(0)	<= '1';
-				end if;	
-			else
-				mem_free_ack(0)	<= '0';
-			end if;
-		end if;
-	end process;	
-
 ------------------------------------------------------------------
 -- Fill stuff
 ------------------------------------------------------------------
@@ -378,36 +333,26 @@ fill_counter:
 	process(clk)
 	begin
 		if rising_edge(clk) then
-			if fill_set = '1' then	
-				fill_bsy		<= '0';
-				fill_pre_rdy	<= '0';
-				fill_cnt		<= alloc_size;
-				fill_size		<= alloc_size;
-				fill_remain		<= alloc_remain;
-			elsif fill_en = '1' then
-				fill_bsy	<= '1';
-				if fill_cnt_en = '1' or fill_bsy = '0' then
-					if fill_cnt /= 1 then
-						fill_cnt	<= fill_cnt - 1;
-					else
-						fill_pre_rdy	<= '1';
-					end if;
-					if fill_pre_rdy = '1' then
-						fill_bsy	<= '0';
-					end if;
+			if fill_cnt_set = '1' then	
+				fill_rdy		<= '0';
+				fill_cnt		<= fill_size;
+			elsif fill_cnt_adv = '1' then
+				if fill_cnt /= 0 then
+					fill_cnt	<= fill_cnt - 1;
+				else
+					fill_rdy	<= '1';
 				end if;
 			end if;
 		end if;
 	end process;	

------------------------------------------------------------------
 fill_pointer:
 	process(clk)
 	begin
 		if rising_edge(clk) then
-			if fill_set = '1' then
+			if fill_ptr_set = '1' then
 				fill_ptr		<= fill_base;
-			elsif fill_cnt_en = '1' then
+			elsif fill_ptr_adv = '1' then
 				fill_ptr		<= fill_ptr + 1;
 			end if;
 		end if;
@@ -415,61 +360,11 @@ fill_pointer:

 ------------------------------------------------------------------
 -- Transfer stuff
------------------------------------------------------------------
-host2xfer_sync_register:
-	process(mii_tx_clk)
-	begin
-		if rising_edge(mii_tx_clk) then
-			Gbps_en			<= ctrl_in.Gbps_en;
-			fcs_gen_en		<= ctrl_in.fcs_gen_en;
-		end if;	
-	end process;	
-
------------------------------------------------------------------
-xfer_counter:
-	process(mii_tx_clk)
-	begin
-		if rising_edge(mii_tx_clk) then
-			xfer_bsy		<= '0';
-			if xfer_set = '1' then
-				xfer_cnt 		<= cmd_fifo_dout(cmd_fifo_dout'left downto word_ptr_t'length);
-				xfer_size		<= (others => '0');
-			elsif xfer_en = '1' then
-				xfer_bsy	<= '1';
-				if xfer_cnt_en = '1' or xfer_bsy = '0' then
-					if xfer_cnt /= 0 then
-						xfer_cnt	<= xfer_cnt - 1;
-						xfer_size	<= xfer_size + 1;
-					else
-						xfer_bsy	<= '0';
-					end if;
-				end if;
-			end if;
-		end if;	
-			
-	end process;	
-	
------------------------------------------------------------------
-xfer_pointer:
-	process(mii_tx_clk)
-	begin
-		if rising_edge(mii_tx_clk) then
-			if xfer_set = '1' then
-				xfer_ptr		<= cmd_fifo_dout(xfer_ptr'left downto 0);
-			elsif xfer_en = '1' then
-				if xfer_bsy = '0' or xfer_cnt_en = '1' then
-					xfer_ptr		<= xfer_ptr + 1;
-				end if;
-			end if;
-		end if;	
-			
-	end process;	
-	
 ------------------------------------------------------------------
 xfer_state_next:
-	process(mii_tx_clk)
+	process(clk)
 	begin
-		if rising_edge(mii_tx_clk) then
+		if rising_edge(clk) then
 			if reset_en = '1' then
 				xfer_s	<= xfer_init;
 			else
@@ -479,99 +374,152 @@ xfer_state_next:
 	end process;	

 xfer_state:
-	process(xfer_s, mii_bsy, cmd_fifo_empty, piso32_din_rdy, piso32_dout_vld, xfer_bsy, fcs_gen_en)
+	process(xfer_s, cmd_fifo_empty, xfer_odd, xfer_rdy, ifg_rdy, mem_alloc_en, mii_fifo_full)
 	begin
+	
+		xfer_cnt_set		<= '0';
+		xfer_cnt_adv		<= '0';
+		xfer_ptr_set		<= '0';
+		xfer_ptr_adv		<= '0';
+		xfer_remain_en		<= '0';
+		mii_fifo_we			<= '0';
+		mem_free_en			<= '0';
+		uncommit_en			<= '0';
 		
-		piso32_din_vld		<= '0';
-		preamble_en			<= '0';
-		preamble_addr		<= 0;
-		xfer_set			<= '0';
- 		xfer_en				<= '0';
-		xfer_free_en		<= '0';
- 		fcs_rst				<= '0';
- 		fcs_inject_en		<= '0';
- 		uncommit_en			<= '0';
-		
-		xfer_sn			<= xfer_s;
+		xfer_sn				<= xfer_s;
 		
 		case xfer_s is
 		
 		when xfer_init =>
-			xfer_sn 		<= xfer_idle;
-			
+			xfer_sn <= xfer_idle;
+		
 		when xfer_idle =>
-			if cmd_fifo_empty = '0' and mii_bsy = '0' then
-				xfer_sn 		<= xfer_start;
+			if cmd_fifo_empty = '0' then
+				xfer_sn			<= xfer_setup;
 			end if;
 			
-		when xfer_start =>
-			if cmd_fifo_empty = '0' then
-				xfer_sn 		<= xfer_preamble0;
-			end if;
+		when xfer_setup =>
+			xfer_ptr_set	<= '1';
+			xfer_cnt_set	<= '1';
+			xfer_sn				<= xfer_arm;

-		when xfer_preamble0 =>
-			xfer_set		<= '1';
- 			fcs_rst			<= '1';
-			preamble_addr	<= 0;
-			preamble_en		<= '1';
-			piso32_din_vld	<= '1';
-			if piso32_din_rdy = '1' then
-				xfer_sn 		<= xfer_preamble1;
-			end if;
-
-		when xfer_preamble1 =>
-			preamble_addr	<= 1;
-			preamble_en		<= '1';
-			piso32_din_vld	<= '1';
-			if piso32_din_rdy = '1' then
-				xfer_sn 		<= xfer_active;
- 				xfer_en			<= '1';
-			end if;
+		when xfer_arm =>
+			xfer_cnt_adv		<= '1';
+			xfer_sn				<= xfer_wait;

+		when xfer_wait =>
+			if ifg_rdy = '1' then
+				xfer_sn			<= xfer_active;
+				xfer_cnt_adv	<= '1';
+				xfer_ptr_adv		<= '1';
+			end if;			
+		
 		when xfer_active =>
-			piso32_din_vld	<= xfer_bsy;
-			xfer_en			<= '1';
-			if xfer_bsy = '0' then
-				xfer_sn 		<= xfer_stop;
+			mii_fifo_we			<= '1';
+			xfer_cnt_adv		<= not mii_fifo_full;
+			xfer_ptr_adv		<= not mii_fifo_full;
+			if xfer_rdy = '1' then
+				xfer_remain_en	<= xfer_odd;
+				xfer_cnt_adv	<= '0';
+				xfer_ptr_adv	<= '0';
+				if mii_fifo_full = '0' then
+					xfer_sn			<= xfer_uncommit;
+				end if;	
+			end if;	
+
+		when xfer_uncommit =>
+			mem_free_en			<= not mem_alloc_en;
+			if mem_alloc_en = '0' then
+				uncommit_en		<= '1';
+				xfer_sn			<= xfer_free;
 			end if;

-		when xfer_stop =>
-			if piso32_dout_vld = '0' then
-				xfer_sn 		<= xfer_finish;
-				if fcs_gen_en = '1' then
-					xfer_sn 		<= xfer_crc;
-				end if;
+		when xfer_free =>
+			if ifg_rdy = '0' then
+				xfer_sn			<= xfer_idle;
 			end if;

-		when xfer_crc =>
-			fcs_inject_en	<= piso32_din_rdy;
-			piso32_din_vld	<= '1';
-			if piso32_din_rdy = '1' then
-				xfer_sn 		<= xfer_finish;
-			end if;
-
-		when xfer_finish =>
-			uncommit_en		<= '1';
-			xfer_free_en	<= '1';
-			xfer_sn		<= xfer_idle;
-
 		when others => 
-			xfer_sn		<= xfer_idle;
+			xfer_sn				<= xfer_idle;
 		end case;

 	end process;

 ------------------------------------------------------------------
-inst_ram : entity work.dpram_1w1r2c_ro
+interframe_gap_ready:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			ifg_rdy	<= ifg_idle;
+		end if;
+	end process;
+
+------------------------------------------------------------------
+interframe_gap_counter:
+	process(mii_tx_clk)
+	begin
+		if rising_edge(mii_tx_clk) then
+			ifg_idle	<= '0';
+			if reset_en = '1' or tx_en = '1' then
+				ifg_cnt <= ifg_cnt_t'high;
+			elsif ifg_cnt /= 0 then
+				ifg_cnt		<= ifg_cnt - 1;
+			else
+				ifg_idle	<= '1';
+			end if;
+		end if;
+	end process;
+
+------------------------------------------------------------------
+xfer_counter:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if xfer_cnt_set = '1' then
+				xfer_size		<= (others => '0');
+				xfer_rdy		<= '0';
+				xfer_cnt 		<= cmd_fifo_dout(xfer_ptr'left+16 downto 16);
+			elsif xfer_cnt_adv = '1' then
+				if xfer_cnt /= 0 then
+					xfer_cnt	<= xfer_cnt - 1;
+					xfer_size	<= xfer_size + 1;
+				else
+					xfer_rdy	<= '1';
+				end if;
+			end if;
+		end if;	
+			
+	end process;	
+	
+xfer_pointer:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if xfer_ptr_set = '1' then
+				xfer_ptr		<= cmd_fifo_dout(xfer_ptr'left downto 0);
+				xfer_remain		<= xfer_tag(3 downto 2);
+				xfer_odd 		<= '0';
+				if xfer_tag(3 downto 2) /= "00" then
+					xfer_odd 	<= '1';
+				end if;
+			elsif xfer_ptr_adv = '1' then
+				xfer_ptr		<= xfer_ptr + 1;
+			end if;
+		end if;	
+			
+	end process;	
+	
+------------------------------------------------------------------
+inst_ram : entity work.dpram_1w1r
 	GENERIC MAP 
 	(
 		addr_width	=> RAM_ADDR_WIDTH,
-		data_width	=> ram_din_a'length
+		data_width	=> 32
 	)
 	PORT MAP 
 	(
-		clk_a		=> clk,
-		clk_b		=> mii_tx_clk,
+		clka		=> clk,
+		clkb		=> clk,
 		en_a		=> ram_en_a,
 		en_b		=> ram_en_b,
 		we_a		=> ram_we_a,
@@ -581,9 +529,8 @@ inst_ram : entity work.dpram_1w1r2c_ro
 		dout_b		=> ram_dout_b
 	);

------------------------------------------------------------------
 -- Instantiate synchronous FIFO
-inst_cmd_fifo: entity work.fifo_async
+inst_cmd_fifo: entity work.fifo_sync
 	GENERIC MAP
 	(
 		addr_width			=> NextExpBaseTwo(RAM_SIZE) - 4,	-- RAMSIZE(words)/MIN_PACKET_LEN(words)
@@ -593,8 +540,7 @@ inst_cmd_fifo: entity work.fifo_async
 	PORT MAP
 	(
 		rst			=>	reset_en,
-		clk_w		=>	clk,
-		clk_r		=>	mii_tx_clk,
+		clk			=>	clk,
 		we			=>	cmd_fifo_we,
 		re			=>	cmd_fifo_re,
 		fifo_full	=>	cmd_fifo_full,
@@ -605,8 +551,30 @@ inst_cmd_fifo: entity work.fifo_async
 		data_r		=>  cmd_fifo_dout
 	);

------------------------------------------------------------------
-inst_piso32 : entity work.piso
+-- Instantiate synchronous FIFO
+inst_mii_fifo: entity work.fifo_async
+	GENERIC MAP
+	(
+		addr_width			=> 4,
+		data_width			=> mii_fifo_din'length,
+		do_last_read_update	=> true
+	)
+	PORT MAP
+	(
+		rst			=>	reset_en,
+		clk_w		=>	clk,
+		clk_r		=>	mii_tx_clk,
+		we			=>	mii_fifo_we,
+		re			=>	mii_fifo_re,
+		fifo_full	=>	mii_fifo_full,
+		fifo_empty	=>	mii_fifo_empty,
+		fifo_afull	=>	open,
+		fifo_aempty	=>	open,
+		data_w		=>  mii_fifo_din,
+		data_r		=>  mii_fifo_dout
+	);
+
+inst_piso : entity work.piso
 	GENERIC MAP
 	(
 		data_width_in	=> 32,
@@ -617,98 +585,17 @@ inst_piso32 : entity work.piso
 	(
 		rst			=> reset_en,
 		clk			=> mii_tx_clk,
-		din_vld		=> piso32_din_vld,
-		din_rdy		=> piso32_din_rdy,
-		din_be		=> piso32_din_be,
-		din			=> piso32_din,
-		dout_vld	=> piso32_dout_vld,
-		dout_en		=> piso32_dout_en,
-		dout		=> piso32_dout
+		din_vld		=> data_vld,
+		din_rdy		=> piso_din_rdy,
+		din_be		=> piso_din_be,
+		din			=> mii_fifo_dout(31 downto 0),
+		dout_vld	=> piso_dout_vld,
+		dout_en		=> piso_10mbps_din_rdy,
+		dout		=> piso_dout
 		
 	);

-	piso32_dout_en	<= not mii_fifo_full; --'1' when Gbps_en = '1' else piso8_din_rdy;
-	
------------------------------------------------------------------
-fcs_enable_gen:
-	process(mii_tx_clk)
-	begin
-		if rising_edge(mii_tx_clk) then
-			if fcs_rst = '1' then
-				fcs_en	<= (others => '0');
-			elsif piso32_dout_vld = '1' then
-				fcs_en	<= fcs_en(fcs_en'left-1 downto 0) & '1';
-			end if;
-		end if;
-	end process;	
-
------------------------------------------------------------------
-inst_fcs: entity work.crc32
-	GENERIC MAP
-	(
-		crc32_init		=> X"00000000"
-	)
-	PORT MAP
-	(
-		rst				=> fcs_rst,
-		clk				=> mii_tx_clk,
-		din_vld			=> fcs_din_vld,
-		din				=> piso32_dout,
-		crc32_vld		=> fcs_vld,
-		crc32_out		=> fcs
-		
-	);
-
-	fcs_din_vld	<= fcs_en(fcs_en'left) and piso32_dout_vld and piso32_dout_en;
-
------------------------------------------------------------------
-- ensures continous MII-data stream and also acts as Inter Frame Gap delay
-mii_fifo_re_dly_gen:
-	process(mii_tx_clk)
-	begin
-		if rising_edge(mii_tx_clk) then
-			if mii_fifo_empty = '1' then
-				if Gbps_en = '0' then
-					mii_fifo_re_dly	<= X"000000";	-- 100 mbps
-				else
-					mii_fifo_re_dly	<= X"000FFF";	-- Gigabit
-				end if;
-			else
-				mii_fifo_re_dly	<= mii_fifo_re_dly(mii_fifo_re_dly'left-1 downto 0) & not mii_fifo_empty;
-			end if;
-		end if;
-	end process;	
-
-	mii_bsy			<= mii_fifo_re_dly(mii_fifo_re_dly'left);
-	
------------------------------------------------------------------
-- Instantiate synchronous FIFO
-inst_mii_fifo: entity work.fifo_sync
-	GENERIC MAP
-	(
-		addr_width			=> 4,	
-		data_width			=> piso32_dout'length,
-		do_last_read_update	=> true
-	)
-	PORT MAP
-	(
-		rst			=>	reset_en,
-		clk			=>  mii_tx_clk,
-		we			=>	mii_fifo_we,
-		re			=>	mii_fifo_re,
-		fifo_full	=>	mii_fifo_full,
-		fifo_empty	=>	mii_fifo_empty,
-		fifo_afull	=>	open,
-		fifo_aempty	=>	open,
-		data_w		=>  piso32_dout,
-		data_r		=>  piso8_din
-	);
-	
-	mii_fifo_re		<= mii_bsy when Gbps_en = '1' else (piso8_din_rdy and mii_bsy);
-	mii_fifo_we		<= piso32_dout_vld;
-
------------------------------------------------------------------
-inst_piso8 : entity work.piso
+inst_piso_10mbps : entity work.piso
 	GENERIC MAP
 	(
 		data_width_in	=> 8,
@@ -719,33 +606,17 @@ inst_piso8 : entity work.piso
 	(
 		rst			=> reset_en,
 		clk			=> mii_tx_clk,
-		din_vld		=> piso8_din_vld,
-		din_rdy		=> piso8_din_rdy,
+		din_vld		=> piso_dout_vld,
+		din_rdy		=> piso_10mbps_din_rdy,
 		din_be		=> "11",
-		din			=> piso8_din,
-		dout_vld	=> piso8_dout_vld,
+		din			=> piso_dout,
+		dout_vld	=> tx_en,
 		dout_en		=> '1',
-		dout		=> piso8_dout
+		dout		=> mii_tx(3 downto 0)
 		
 	);

-	piso8_din_vld	<= not mii_fifo_empty and mii_bsy;
-	
------------------------------------------------------------------
-mii_output_register:
-	process(mii_tx_clk)
-	begin
-		if rising_edge(mii_tx_clk) then
-			mii_tx_er		<= '0';
-			if Gbps_en = '1' then
-				mii_tx_en		<= piso8_din_vld;
-				mii_tx			<= piso8_din;
-			else
-				mii_tx_en		<= piso8_dout_vld;
-				mii_tx			<= "0000" & piso8_dout;
-			end if;			
-		end if;	
-	end process;	
+	mii_tx_en			<= tx_en;
+	mii_tx(7 downto 4)	<= "0000";

------------------------------------------------------------------
 end behavior;
@@ -12,16 +12,14 @@ use IEEE.MATH_REAL.ALL;
 package emac_types is
 	
 	-- Constants
-	type mac_addr_t is array (0 to 5) of unsigned (7 downto 0);
 	
 	-- Types
 	type tx_ctrl_in_t is record
-		Gbps_en				: std_logic;
-		reset				: std_logic;
-		fcs_gen_en			: std_logic;
+		tx_er				: std_logic;
 		tx_size				: unsigned(15 downto 0);
 		pkt_commit_en		: std_logic;
 		pkt_alloc_en		: std_logic;
+		reset				: std_logic;
 	end record;

 	type tx_ctrl_out_t is record
@@ -33,20 +31,16 @@ package emac_types is
 	end record;
 	
 	type rx_ctrl_in_t is record
-		Gbps_en				: std_logic;
 		reset				: std_logic;
-		fcs_chk_en			: std_logic;
+		pkt_read_en			: std_logic;
 		pkt_req_en			: std_logic;
 		pkt_free_en			: std_logic;
-		mac_addr			: mac_addr_t;
-		promiscious			: std_logic;
 	end record;

 	type rx_ctrl_out_t is record
+		rx_er				: std_logic;
 		pkt_avail			: std_logic;
-		pkt_valid			: std_logic;
-		pkt_bcast			: std_logic;
-		pkt_mac_match		: std_logic;
+		pkt_lost			: std_logic;
 		rx_size				: unsigned(15 downto 0);
 		reset_busy			: std_logic;
 	end record;
@@ -31,18 +31,19 @@ ARCHITECTURE behavior OF piso IS

 	constant num_shifts		: natural := data_width_in/data_width_out;
 	signal pre_fin			: STD_LOGIC;
+	signal rdy				: STD_LOGIC;
 	signal shift_cnt_pipe	: unsigned(num_shifts-1 downto 0);
 	signal shift_pipe		: unsigned(data_width_in-1 downto 0);
 	signal vld_pipe			: unsigned(num_shifts-1 downto 0);
 	signal din_reg			: unsigned(data_width_in-1 downto 0);
 	signal din_be_reg		: unsigned(num_shifts-1 downto 0);
-	signal din_reg_empty	: STD_LOGIC;
+	signal din_vld_reg		: STD_LOGIC;
 	
 --------------------------------------------------------------------------
 begin

 	pre_fin		<= shift_cnt_pipe(shift_cnt_pipe'left-1);
-	din_rdy		<= din_reg_empty;
+	din_rdy		<= rdy;
 	dout_vld	<= vld_pipe(vld_pipe'left) when msb_first else vld_pipe(0);
 	dout		<= 		shift_pipe(shift_pipe'left downto shift_pipe'left-data_width_out+1) when msb_first
 				else	shift_pipe(data_width_out-1 downto 0);
@@ -52,13 +53,11 @@ process(clk)
 begin
 	if rising_edge(clk) then
 		if rst = '1' then
-			din_reg_empty	<= '1';
-		elsif din_reg_empty = '1' then
-			if din_vld = '1' then
-				din_reg_empty	<= '0';
-			end if;
-		elsif pre_fin = '1' and dout_en = '1' then
-			din_reg_empty	<= '1';
+			rdy			<= '0';
+		elsif pre_fin = '1' and rdy = '0' then
+			rdy		<= '1';
+		elsif din_vld = '1' then
+			rdy			<= '0';
 		end if;
 	end if;
 end process;
@@ -66,7 +65,18 @@ end process;
 process(clk)
 begin
 	if rising_edge(clk) then
-		if din_vld = '1' and din_reg_empty = '1' then
+		if rst = '1' then
+			din_vld_reg	<= '0';
+		elsif (pre_fin = '1' and dout_en = '1') or din_vld_reg = '0' then
+			din_vld_reg	<= din_vld;
+		end if;
+	end if;
+end process;
+
+process(clk)
+begin
+	if rising_edge(clk) then
+		if din_vld = '1' and rdy = '1' then
 			din_reg		<= din;
 			din_be_reg	<= din_be;
 		end if;
@@ -78,10 +88,12 @@ begin
 	if rising_edge(clk) then
 		if rst = '1' then
 			shift_cnt_pipe	<= (others => '1');
-		elsif (pre_fin = '1' and dout_en = '1' and din_reg_empty = '0') then
-			shift_cnt_pipe	<= (others => '0');
 		elsif dout_en = '1' then
-			shift_cnt_pipe	<= shift_cnt_pipe(shift_cnt_pipe'left-1 downto 0)  & '1';
+			if (pre_fin = '1' and din_vld_reg = '1') or (din_vld = '1' and din_vld_reg = '0') then
+				shift_cnt_pipe	<= (others => '0');
+			else
+				shift_cnt_pipe	<= shift_cnt_pipe(shift_cnt_pipe'left-1 downto 0)  & '1';
+			end if;
 		end if;
 	end if;
 end process;
@@ -90,13 +102,15 @@ end process;
 process(clk)
 begin
 	if rising_edge(clk) then
-		if (pre_fin = '1' and dout_en = '1' and din_reg_empty = '0') then
-			shift_pipe		<= din_reg;
-		elsif dout_en = '1' then
-			if (msb_first) then
-				shift_pipe		<= shift_pipe(shift_pipe'left-data_width_out downto 0) & (data_width_out-1 downto 0 => '0');
-			else
-				shift_pipe		<= (data_width_out-1 downto 0 => '0') & shift_pipe(shift_pipe'left downto data_width_out);
+		if dout_en = '1' then
+			if pre_fin = '1' and din_vld_reg = '1' then
+				shift_pipe		<= din_reg;
+			else	
+				if (msb_first) then
+					shift_pipe		<= shift_pipe(shift_pipe'left-data_width_out downto 0) & (data_width_out-1 downto 0 => '0');
+				else
+					shift_pipe		<= (data_width_out-1 downto 0 => '0') & shift_pipe(shift_pipe'left downto data_width_out);
+				end if;
 			end if;
 		end if;
 	end if;
@@ -108,13 +122,15 @@ begin
 	if rising_edge(clk) then
 		if rst = '1' then
 			vld_pipe	<= (others => '0');
-		elsif (pre_fin = '1' and dout_en = '1' and din_reg_empty = '0') then
-			vld_pipe		<= din_be_reg;
 		elsif dout_en = '1' then
-			if (msb_first) then
-				vld_pipe		<= vld_pipe(vld_pipe'left-1 downto 0) & '0';
+			if pre_fin = '1' and din_vld_reg = '1' then
+				vld_pipe		<= din_be_reg;
 			else
-				vld_pipe		<= '0' & vld_pipe(vld_pipe'left downto 1);
+				if (msb_first) then
+					vld_pipe		<= vld_pipe(vld_pipe'left-1 downto 0) & '0';
+				else
+					vld_pipe		<= '0' & vld_pipe(vld_pipe'left downto 1);
+				end if;
 			end if;
 		end if;
 	end if;
@@ -11,7 +11,8 @@ ENTITY pkt_gen IS
 	Generic
 	(
 		f_sysclk		: real		:= 100.0;
-		TX_RAM_SIZE		: natural	:= 2048;
+		PKT_DLY_MIN		: real		:= 1.0E-6;
+		PKT_DLY_MAX		: real		:= 100.0E-6;
 		PKT_SIZE_MIN	: natural	:= 64;
 		PKT_SIZE_MAX	: natural	:= 1518
 		
@@ -20,9 +21,6 @@ ENTITY pkt_gen IS
 	(
 		clk				: in  STD_LOGIC;
 		rst				: in  STD_LOGIC;
-		en				: in  STD_LOGIC;
-		gigabit_en		: in  STD_LOGIC;
-		fcs_gen_en		: in  STD_LOGIC;
 		mii_tx_clk		: in  STD_LOGIC;
 		mii_tx_en		: out STD_LOGIC;
 		mii_tx_er		: out STD_LOGIC;
@@ -38,100 +36,152 @@ ARCHITECTURE behavior OF pkt_gen IS
 	signal pkt_data			: unsigned(31 downto 0);
 	signal pkt_nbytes		: word_ptr_t := X"0040";
 	signal pkt_nwords		: word_ptr_t := X"0010";
+	signal pkt_delay		: natural := natural(1.0*f_sysclk);
 	
-	signal fill_size		: word_ptr_t;
-	signal fill_cnt			: word_ptr_t;
-	signal fill_rdy			: std_logic;
-	signal fill_set			: std_logic;
-	signal fill_en			: std_logic;
-
 	signal tx_packets		: natural;
 	signal tx_bytes			: natural;
 	
-	signal tx_ctrl_in		: tx_ctrl_in_t;
-	signal tx_ctrl_out		: tx_ctrl_out_t;
-	signal tx_din			: unsigned(31 downto 0);
-	signal tx_din_vld		: std_logic;
+	signal mii_fifo_din		: unsigned(35 downto 0);
+	signal mii_fifo_dout	: unsigned(35 downto 0);
+	signal mii_fifo_we		: std_logic;
+	signal mii_fifo_re		: std_logic;
+	signal mii_fifo_empty	: std_logic;
+	signal mii_fifo_full	: std_logic;
+
+	signal xfer_size		: word_ptr_t;
+	signal xfer_ptr			: word_ptr_t;
+	signal xfer_cnt			: word_ptr_t;
+	signal xfer_ptr_set		: std_logic;
+	signal xfer_ptr_adv		: std_logic;
+	signal xfer_cnt_set		: std_logic;
+	signal xfer_cnt_adv		: std_logic;
+	signal xfer_rdy			: std_logic;
+	signal xfer_tag			: unsigned(3 downto 0);
+	signal xfer_remain		: unsigned(1 downto 0);
+	signal xfer_odd			: std_logic;
+	signal xfer_remain_en	: std_logic;
+	signal commit_en		: std_logic;
+
+	signal piso_din_be		: unsigned(3 downto 0);
+	signal piso_din_rdy		: std_logic;
+	signal data_vld			: std_logic;
+
+	signal piso_dout			: unsigned(7 downto 0);
+	signal piso_dout_vld		: std_logic;
+	signal piso_10mbps_din_rdy	: std_logic;
+	signal tx_en				: std_logic;
+	
+	subtype inter_frame_gap_cnt_t is natural;
+	signal inter_frame_gap_cnt	: inter_frame_gap_cnt_t;
+	signal inter_frame_gap_rdy	: std_logic;
+	
+	type xfer_state_t is (xfer_init, xfer_idle, xfer_setup, xfer_wait, xfer_active, xfer_uncommit, xfer_free);
+	signal xfer_s, xfer_sn : xfer_state_t;
+
+	type piso_byte_mask_array_t is array (0 to 3) of unsigned (3 downto 0);
+	constant piso_byte_mask_rom : piso_byte_mask_array_t :=
+	(
+		"1111",
+		"1000",
+		"1100",
+		"1110"
+	);
 	
-	type host_state_t is (host_init, host_idle, host_alloc, host_setup, host_arm, host_fill, host_commit);
-	signal host_s, host_sn : host_state_t;
 	
 begin

+	mii_tx_er				<= '0';
+
+	piso_din_be				<= mii_fifo_dout(35 downto 32);
+	mii_fifo_re				<= piso_din_rdy;
+	data_vld				<= not mii_fifo_empty;
+	
+	mii_fifo_din(35 downto 32)	<= piso_byte_mask_rom(to_integer(xfer_remain)) when xfer_remain_en = '1' else "1111";
+	mii_fifo_din(31 downto 0)	<= pkt_data;
+	
 ------------------------------------------------------------------
-host_state_next:
+-- Transfer stuff
+------------------------------------------------------------------
+xfer_state_next:
 	process(clk)
 	begin
 		if rising_edge(clk) then
 			if rst = '1' then
-				host_s	<= host_init;
+				xfer_s	<= xfer_init;
 			else
-				host_s	<= host_sn;
+				xfer_s	<= xfer_sn;
 			end if;
 		end if;
 	end process;	

-host_state:
-	process(host_s, tx_ctrl_out, pkt_nbytes, fill_rdy, en, gigabit_en, fcs_gen_en)
+xfer_state:
+	process(xfer_s, xfer_odd, xfer_rdy, inter_frame_gap_rdy, mii_fifo_full)
 	begin
 	
-		tx_ctrl_in.pkt_alloc_en		<= '0';
-		tx_ctrl_in.pkt_commit_en	<= '0';
-		tx_ctrl_in.reset			<= '0';
-		tx_ctrl_in.Gbps_en			<= gigabit_en;
-		tx_ctrl_in.fcs_gen_en		<= fcs_gen_en;
-		tx_ctrl_in.tx_size			<= pkt_nbytes;
-		fill_set					<= '0';
-		fill_en						<= '0';
+		xfer_cnt_set		<= '0';
+		xfer_cnt_adv		<= '0';
+		xfer_ptr_set		<= '0';
+		xfer_ptr_adv		<= '0';
+		xfer_remain_en		<= '0';
+		mii_fifo_we			<= '0';
+		commit_en			<= '0';
 		
-		host_sn						<= host_s;
+		xfer_sn				<= xfer_s;
 		
-		case host_s is
+		case xfer_s is
 		
-		when host_init =>
-			if tx_ctrl_out.reset_busy = '0' then
-				host_sn 		<= host_idle;
-			end if;
+		when xfer_init =>
+			xfer_sn <= xfer_idle;
 		
-		when host_idle =>
-			if tx_ctrl_out.pkt_alloc_req = '0' and en = '1' then
-				tx_ctrl_in.pkt_alloc_en		<= '1';
-				host_sn		<= host_alloc;
-			end if;
+		when xfer_idle =>
+			xfer_ptr_set	<= '1';
+			xfer_cnt_set	<= '1';
+			xfer_sn			<= xfer_wait;
+			
+		when xfer_wait =>
+			if inter_frame_gap_rdy = '1' then
+				xfer_sn			<= xfer_setup;
+				xfer_cnt_adv		<= '1';
+			end if;			
+		
+		when xfer_setup =>
+			xfer_cnt_adv		<= '1';
+			xfer_ptr_adv		<= '1';
+			xfer_sn				<= xfer_active;

-		when host_alloc =>
-			if tx_ctrl_out.pkt_alloc_req = '0' then
-				if tx_ctrl_out.pkt_armed = '1' then
-					host_sn		<= host_setup;
-				else
-					host_sn 	<= host_idle;
-				end if;
-			end if;
+		when xfer_active =>
+			mii_fifo_we			<= '1';
+			xfer_cnt_adv		<= not mii_fifo_full;
+			xfer_ptr_adv		<= not mii_fifo_full;
+			if xfer_rdy = '1' then
+				xfer_remain_en	<= xfer_odd;
+				xfer_cnt_adv	<= '0';
+				xfer_ptr_adv	<= '0';
+				if mii_fifo_full = '0' then
+					xfer_sn			<= xfer_uncommit;
+				end if;	
+			end if;	

-		when host_setup =>
-			fill_set		<= '1';
-			host_sn			<= host_fill;
+		when xfer_uncommit =>
+			commit_en		<= '1';
+			xfer_sn			<= xfer_free;

-		when host_fill =>
-			fill_en			<= '1';
-			if fill_rdy = '1' then
-				host_sn		<= host_commit;
+		when xfer_free =>
+			if inter_frame_gap_rdy = '0' then
+				xfer_sn			<= xfer_idle;
 			end if;
-		
-		when host_commit =>
-			tx_ctrl_in.pkt_commit_en	<= '1';
-			host_sn			<= host_idle;

 		when others => 
-			host_sn			<= host_idle;
+			xfer_sn				<= xfer_idle;
 		end case;

 	end process;

 ------------------------------------------------------------------
-pkt_generator:
+pkt_params:
 	process(clk)
 	variable size		: word_ptr_t;
+	variable delay		: natural;
 	variable krand		: real;
 	variable seed1		: integer;
 	variable seed2		: integer;
@@ -140,16 +190,19 @@ pkt_generator:
 		if rising_edge(clk) then
 			if rst = '1' then
 				size		:= to_unsigned(PKT_SIZE_MIN, word_ptr_t'length);
+				delay 		:= natural(1.0E6*PKT_DLY_MIN*f_sysclk);
 				seed1		:= 31101970;
 				seed2		:= 12586901;
 				tx_packets	<= 0;
 				tx_bytes	<= 0;
-			elsif tx_ctrl_in.pkt_commit_en = '1' then
+			elsif commit_en = '1' then
 				uniform(seed1, seed2, krand);
 				size		:= to_unsigned(PKT_SIZE_MIN + natural(real(PKT_SIZE_MAX-PKT_SIZE_MIN)*krand), word_ptr_t'length);
+				delay 		:= natural(1.0E6*f_sysclk*(PKT_DLY_MIN + (PKT_DLY_MAX-PKT_DLY_MIN)*krand));
 				tx_packets	<= tx_packets + 1;
 				tx_bytes	<= tx_bytes + to_integer(pkt_nbytes);
 			end if;
+			pkt_delay	<= delay;
 			pkt_nbytes	<= size;
 			if size(1 downto 0) = 0 then
 				pkt_nwords	<= "00" & size(word_ptr_t'left downto 2);
@@ -160,44 +213,53 @@ pkt_generator:
 	end process;

 ------------------------------------------------------------------
-pkt_data_gen:
+interframe_gap_counter:
+	process(mii_tx_clk)
+	begin
+		if rising_edge(mii_tx_clk) then
+			if rst = '1' then
+				inter_frame_gap_rdy	<= '1';
+			elsif tx_en = '1' then
+				inter_frame_gap_rdy	<= '0';
+				inter_frame_gap_cnt <= pkt_delay;
+			elsif inter_frame_gap_cnt /= 0 then
+				inter_frame_gap_cnt <= inter_frame_gap_cnt - 1;
+			else
+				inter_frame_gap_rdy	<= '1';
+			end if;
+		end if;
+	end process;
+
+------------------------------------------------------------------
+xfer_counter:
 	process(clk)
-	variable data : unsigned(7 downto 0);
 	begin
 		if rising_edge(clk) then
-			tx_din_vld	<= fill_en;
-			if fill_set = '1' then
-				data	:= X"00";
-				tx_din	<= X"03020100";
-			elsif fill_en = '1' then
-				tx_din(7 downto 0)		<= data;
-				data					:= data + 1;
-				tx_din(15 downto 8)		<= data;
-				data					:= data + 1;
-				tx_din(23 downto 16)	<= data;
-				data					:= data + 1;
-				tx_din(31 downto 24)	<= data;
-				data					:= data + 1;
+			if xfer_cnt_set = '1' then
+				xfer_size		<= (others => '0');
+				xfer_rdy		<= '0';
+				xfer_cnt 		<= pkt_nwords;
+			elsif xfer_cnt_adv = '1' then
+				if xfer_cnt /= 0 then
+					xfer_cnt	<= xfer_cnt - 1;
+					xfer_size	<= xfer_size + 1;
+				else
+					xfer_rdy	<= '1';
+				end if;
 			end if;
 		end if;	
 			
 	end process;	
-
------------------------------------------------------------------
-pkt_data_counter:
+	
+xfer_pointer:
 	process(clk)
 	begin
 		if rising_edge(clk) then
-			if fill_set = '1' then
-				fill_size		<= (others => '0');
-				fill_rdy		<= '0';
-				fill_cnt 		<= pkt_nwords;
-			elsif fill_en = '1' then
-				if fill_cnt /= 0 then
-					fill_cnt	<= fill_cnt - 1;
-					fill_size	<= fill_size + 1;
-				else
-					fill_rdy	<= '1';
+			if xfer_ptr_set = '1' then
+				xfer_remain		<= pkt_nbytes(1 downto 0);
+				xfer_odd 		<= '0';
+				if xfer_tag(3 downto 2) /= "00" then
+					xfer_odd 	<= '1';
 				end if;
 			end if;
 		end if;	
@@ -205,26 +267,93 @@ pkt_data_counter:
 	end process;	
 	
 ------------------------------------------------------------------
-inst_emac_tx : entity work.emac_tx
+pkt_data_gen:
+	process(clk)
+	variable data : unsigned(7 downto 0);
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				data	:= (others => '0');
+			elsif xfer_cnt_adv = '1' then
+				pkt_data(7 downto 0)	<= data;
+				data					:= data + 1;
+				pkt_data(15 downto 8)	<= data;
+				data					:= data + 1;
+				pkt_data(23 downto 16)	<= data;
+				data					:= data + 1;
+				pkt_data(31 downto 24)	<= data;
+				data					:= data + 1;
+			end if;
+		end if;	
+			
+	end process;	
+
+------------------------------------------------------------------
+-- Instantiate synchronous FIFO
+inst_mii_fifo: entity work.fifo_async
 	GENERIC MAP
 	(
-		f_sysclk	=> f_sysclk,
-		RAM_SIZE	=> TX_RAM_SIZE
+		addr_width			=> 4,
+		data_width			=> mii_fifo_din'length,
+		do_last_read_update	=> true
+	)
+	PORT MAP
+	(
+		rst			=>	rst,
+		clk_w		=>	clk,
+		clk_r		=>	mii_tx_clk,
+		we			=>	mii_fifo_we,
+		re			=>	mii_fifo_re,
+		fifo_full	=>	mii_fifo_full,
+		fifo_empty	=>	mii_fifo_empty,
+		fifo_afull	=>	open,
+		fifo_aempty	=>	open,
+		data_w		=>  mii_fifo_din,
+		data_r		=>  mii_fifo_dout
+	);
+
+inst_piso : entity work.piso
+	GENERIC MAP
+	(
+		data_width_in	=> 32,
+		data_width_out	=> 8,
+		msb_first		=> true
 	)
 	PORT MAP
 	(
-		clk			=> clk,
 		rst			=> rst,
-		din_vld		=> tx_din_vld,
-		din			=> tx_din,
-		ctrl_in		=> tx_ctrl_in,
-		ctrl_out	=> tx_ctrl_out,
-		mii_tx_clk	=> mii_tx_clk,
-		mii_tx_en	=> mii_tx_en,
-		mii_tx_er	=> mii_tx_er,
-		mii_tx		=> mii_tx
+		clk			=> mii_tx_clk,
+		din_vld		=> data_vld,
+		din_rdy		=> piso_din_rdy,
+		din_be		=> piso_din_be,
+		din			=> mii_fifo_dout(31 downto 0),
+		dout_vld	=> piso_dout_vld,
+		dout_en		=> piso_10mbps_din_rdy,
+		dout		=> piso_dout
 		
 	);

+inst_piso_10mbps : entity work.piso
+	GENERIC MAP
+	(
+		data_width_in	=> 8,
+		data_width_out	=> 4,
+		msb_first		=> false
+	)
+	PORT MAP
+	(
+		rst			=> rst,
+		clk			=> mii_tx_clk,
+		din_vld		=> piso_dout_vld,
+		din_rdy		=> piso_10mbps_din_rdy,
+		din_be		=> "11",
+		din			=> piso_dout,
+		dout_vld	=> tx_en,
+		dout_en		=> '1',
+		dout		=> mii_tx(3 downto 0)
+		
+	);
+	mii_tx_en			<= tx_en;
+	mii_tx(7 downto 4)	<= "0000";

 end behavior;
@@ -60,7 +60,7 @@ end process;
 process(clk)
 begin
 	if rising_edge(clk) then
-		din_vld_r	<= din_vld and din_en;
+		din_vld_r	<= din_vld;
 		if rst = '1' then
 			out_en <= '0';
 		elsif out_en = '0' then	
@@ -87,15 +87,15 @@ begin
 	if rising_edge(clk) then
 		if rst = '1' or pre_fin = '1' then
 			if (msb_first) then
-				shift_cnt_pipe	<= (shift_cnt_pipe'left downto 1 => '0') & (din_en and din_vld);
+				shift_cnt_pipe	<= (shift_cnt_pipe'left downto 1 => '0') & din_vld;
 			else
-				shift_cnt_pipe	<= (din_en and din_vld) & (shift_cnt_pipe'left downto 1 => '0');
+				shift_cnt_pipe	<= din_vld & (shift_cnt_pipe'left downto 1 => '0');
 			end if;
 		elsif din_vld = '1' or abort = '1' then
 			if (msb_first) then
-				shift_cnt_pipe	<= shift_cnt_pipe(shift_cnt_pipe'left-1 downto 0)  & din_en;
+				shift_cnt_pipe	<= shift_cnt_pipe(shift_cnt_pipe'left-1 downto 0)  & din_vld;
 			else
-				shift_cnt_pipe	<= din_en & shift_cnt_pipe(shift_cnt_pipe'left downto 1);
+				shift_cnt_pipe	<= din_vld & shift_cnt_pipe(shift_cnt_pipe'left downto 1);
 			end if;
 		end if;
 	end if;
@@ -1,106 +0,0 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: testbench for system test using Xilinx ML-402
-
-- Copyright (C) 2007 J. Ahrensfeld
-
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-- Lesser General Public License for more details.
-
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
-- For questions and ideas, please contact the author at jens@jayfield.org
-
-----------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-ENTITY tb_crc32 IS
-END tb_crc32;
-
-ARCHITECTURE behavior OF tb_crc32 IS 
-
-	constant CLK_PERIOD		: time := 10 ns;
-
-	signal CLK				: std_logic := '1';
-	signal RST				: std_logic := '1';
-
-	signal din_vld			: std_logic := '0';
-	signal din				: unsigned(7 downto 0) := (others => '-');
-	signal crc32			: unsigned(31 downto 0);
-	signal crc32_vld		: std_logic;
-
-
-	type byte_array_t is array (0 to 61) of unsigned(7 downto 0);
-	
-	signal test_data : byte_array_t :=
-	(
-		X"00", X"0A", X"E6", X"F0", X"05", X"A3", X"00", X"12",
-		X"34", X"56", X"78", X"90", X"08", X"00", X"45", X"00",
-		X"00", X"30", X"B3", X"FE", X"00", X"00", X"80", X"11",
-		X"72", X"BA", X"0A", X"00", X"00", X"03", X"0A", X"00",
-		X"00", X"02", X"04", X"00", X"04", X"00", X"00", X"1C",
-		X"89", X"4D", X"00", X"01", X"02", X"03", X"04", X"05",
-		X"06", X"07", X"08", X"09", X"0A", X"0B", X"0C", X"0D",
-		X"0E", X"0F", X"10", X"11", X"12", X"13"
-	);
-	
-BEGIN
-
-inst_crc32: entity work.crc32
-	PORT MAP
-	(
-		rst				=> RST,
-		clk				=> CLK,
-		din_vld			=> din_vld,
-		din				=> din,
-		crc32_vld		=> crc32_vld,
-		crc32_out		=> crc32
-		
-	);
-
-
-CLK_GEN: process
-	begin
-		wait for CLK_PERIOD/2;
-		CLK <= not CLK;
-	end process;
-
-
-- Master
-STIMULUS: process
-
-
-	begin
-
-		wait for 6*CLK_PERIOD;
-		RST <= '0';
-		wait for 6*CLK_PERIOD;
-
-		wait until rising_edge(CLK);
-
-		for i in 0 to 61 loop
-			din_vld	<= '1';
-			din		<= test_data(i);
-			wait until rising_edge(CLK);
-		end loop;
-
-		din		<= (others => '-');
-		din_vld	<= '0';
-
-		wait; 
-	
-	end process;
-	
-END;
@@ -26,58 +26,130 @@ LIBRARY ieee;
 use IEEE.STD_LOGIC_1164.ALL;
 USE ieee.numeric_std.ALL;

-ENTITY tb_serdes IS
-END tb_serdes;
+ENTITY tb_emac_jb IS
+END tb_emac_jb;

-ARCHITECTURE behavior OF tb_serdes IS 
+ARCHITECTURE behavior OF tb_emac_jb IS 

 	constant CLK_PERIOD		: time := 10 ns;
+	constant MII_CLK_PERIOD	: time := 8 ns;

 	signal CLK				: std_logic := '1';
 	signal RST				: std_logic := '1';

+	-- Slave
+	signal CYC_I			: std_logic := '0';
+	signal STB_I			: std_logic := '0';
+	signal WE_I				: std_logic := '0';
+	signal SEL_I			: unsigned(3 downto 0);
+	signal ACK_O			: std_logic;
+	signal INT_O			: std_logic;
+	signal MRDY_I			: std_logic;
+	signal SRDY_O			: std_logic;
+	signal ADDR_I			: unsigned(31 downto 0) := (others => '-');
+	signal DAT_I			: unsigned(31 downto 0) := (others => '-');
+	signal DAT_O			: unsigned(31 downto 0) := (others => '-');
+	signal DAT_O_reg		: unsigned(31 downto 0) := (others => '-');
+
+	-- MII signals
+	signal mii_rx_clk_board	: std_logic := '1';
+	signal mii_tx_clk_board	: std_logic := '1';
+	signal mii_rx_clk		: std_logic := '1';
+	signal mii_tx_clk		: std_logic := '1';
+	signal mii_rx			: unsigned(7 downto 0) := (others => '-');
+	signal mii_tx			: unsigned(7 downto 0);
+	signal mii_rx_dv		: std_logic := '0';
+	signal mii_rx_er		: std_logic := '0';
+	signal mii_tx_en		: std_logic;
+	signal mii_tx_er		: std_logic;
+	signal mii_crs			: std_logic := '0';
+	signal mii_col			: std_logic := '0';
+	signal mii_gtx_clk		: std_logic;
+
+	signal shift_sa			: integer := 0;
+	signal shift_din_vld	: std_logic := '0';
+	signal shift_din		: unsigned(31 downto 0) := (others => '-');
+	signal shift_dout_vld	: std_logic;
+	signal shift_dout		: unsigned(31 downto 0);
+
 	signal piso_din_vld		: std_logic := '0';
 	signal piso_din_rdy		: std_logic;
-	signal piso_din_be		: unsigned(3 downto 0) := (others => '0');
+	signal piso_din_be		: unsigned(7 downto 0) := (others => '0');
 	signal piso_din			: unsigned(31 downto 0) := (others => '-');
-	signal piso_dout_vld	: std_logic;
-	signal piso_dout		: unsigned(7 downto 0);
 	signal piso_dout_en		: std_logic;
-
-	signal piso2_din_vld	: std_logic := '0';
-	signal piso2_din_rdy	: std_logic;
-	signal piso2_din_be		: unsigned(1 downto 0) := (others => '1');
-	signal piso2_din		: unsigned(7 downto 0) := (others => '-');
-	signal piso2_dout_vld	: std_logic;
-	signal piso2_dout		: unsigned(3 downto 0);
-	signal piso2_dout_en	: std_logic;
+	signal piso_dout		: unsigned(3 downto 0);

 	signal sipo_enable		: std_logic := '0';
-	signal sipo_rst			: std_logic := '0';
-	signal sipo_din_vld		: std_logic := '0';
-	signal sipo_din			: unsigned(7 downto 0) := (others => '-');
+	signal sipo_din_en		: std_logic := '0';
+	signal sipo_din			: unsigned(3 downto 0) := (others => '-');
 	signal sipo_dout_vld	: std_logic;
-	signal sipo_dout_en		: std_logic;
-	signal sipo_dout_be		: unsigned(3 downto 0);
+	signal sipo_dout_be		: unsigned(7 downto 0);
 	signal sipo_dout		: unsigned(31 downto 0);

-	signal sipo2_enable		: std_logic := '0';
-	signal sipo2_rst		: std_logic := '0';
-	signal sipo2_din_vld	: std_logic := '0';
-	signal sipo2_din		: unsigned(3 downto 0) := (others => '-');
-	signal sipo2_dout_vld	: std_logic;
-	signal sipo2_dout_en	: std_logic;
-	signal sipo2_dout_be	: unsigned(1 downto 0);
-	signal sipo2_dout		: unsigned(7 downto 0);
-
+	type emac_action_t is (emac_idle, emac_alloc, emac_write, emac_read);
+	signal emac_action	: emac_action_t;
 	
 BEGIN

+inst_emac_jb : entity work.emac_jb
+	GENERIC MAP
+	(
+		f_sysclk	=> 100.0,
+		TX_RAM_SIZE	=> 2048
+	)
+	PORT MAP
+	(
+		CLK_I		=> CLK,
+		RST_I		=> RST,
+		INT_O		=> INT_O,
+		CYC_I		=> CYC_I,
+		STB_I		=> STB_I,
+		SEL_I		=> SEL_I,
+		WE_I		=> WE_I,
+		ACK_O		=> ACK_O,
+		SRDY_O		=> SRDY_O,
+		MRDY_I		=> MRDY_I,
+		ADDR_I		=> ADDR_I,
+		DAT_I		=> DAT_I,
+		DAT_O		=> DAT_O,
+		mii_rx_clk	=> mii_rx_clk_board,
+		mii_rx_dv	=> mii_rx_dv,
+		mii_rx_er	=> mii_rx_er,
+		mii_rx		=> mii_rx,
+		mii_tx_clk	=> mii_tx_clk_board,
+		mii_tx_en	=> mii_tx_en,
+		mii_tx_er	=> mii_tx_er,
+		mii_tx		=> mii_tx,
+		mii_gtx_clk	=> mii_gtx_clk,
+		mii_crs		=> mii_crs,
+		mii_col		=> mii_col
+		
+	);
+
+inst_shifter : entity work.shifter
+	GENERIC MAP
+	(
+		data_width		=> 32,
+		aggregate_size	=> 4,
+		do_pipelined	=> true
+	)
+	PORT MAP
+	(
+		rst			=> RST,
+		clk			=> CLK,
+		sa			=> shift_sa,
+		din_vld		=> shift_din_vld,
+		din			=> shift_din,
+		dout_vld	=> shift_dout_vld,
+		dout		=> shift_dout
+		
+	);
+
 inst_piso : entity work.piso
 	GENERIC MAP
 	(
 		data_width_in	=> 32,
-		data_width_out	=> 8,
+		data_width_out	=> 4,
 		msb_first		=> true
 	)
 	PORT MAP
@@ -88,43 +160,15 @@ inst_piso : entity work.piso
 		din_rdy		=> piso_din_rdy,
 		din_be		=> piso_din_be,
 		din			=> piso_din,
-		dout_vld	=> piso_dout_vld,
 		dout_en		=> piso_dout_en,
 		dout		=> piso_dout
 		
 	);

-	piso_dout_en	<= piso2_din_rdy;
-	
-inst_piso2 : entity work.piso
-	GENERIC MAP
-	(
-		data_width_in	=> 8,
-		data_width_out	=> 4,
-		msb_first		=> true
-	)
-	PORT MAP
-	(
-		rst			=> RST,
-		clk			=> CLK,
-		din_vld		=> piso2_din_vld,
-		din_rdy		=> piso2_din_rdy,
-		din_be		=> piso2_din_be,
-		din			=> piso2_din,
-		dout_vld	=> piso2_dout_vld,
-		dout_en		=> piso2_dout_en,
-		dout		=> piso2_dout
-		
-	);
-
-	piso2_din_vld	<= piso_dout_vld;
-	piso2_dout_en	<= '1';
-	piso2_din		<= piso_dout;
-	
 inst_sipo : entity work.sipo
 	GENERIC MAP
 	(
-		data_width_in	=> 8,
+		data_width_in	=> 4,
 		data_width_out	=> 32,
 		msb_first		=> true
 	)
@@ -132,44 +176,16 @@ inst_sipo : entity work.sipo
 	(
 		rst			=> RST,
 		clk			=> CLK,
-		din_en		=> sipo_enable,
-		din_vld		=> sipo_din_vld,
+		enable		=> sipo_enable,
+		din_en		=> sipo_din_en,
 		din			=> sipo_din,
 		dout_be		=> sipo_dout_be,
 		dout_vld	=> sipo_dout_vld,
-		dout		=> sipo_dout,
-		dout_en		=> sipo_dout_en
+		dout		=> sipo_dout
 		
 	);
-	sipo_din		<= sipo2_dout;
-	sipo_din_vld	<= sipo2_dout_vld;
-	sipo_enable		<= sipo2_dout_en;
-	sipo_rst		<= RST or not piso2_dout_vld;
-
-inst_sipo2 : entity work.sipo
-	GENERIC MAP
-	(
-		data_width_in	=> 4,
-		data_width_out	=> 8,
-		msb_first		=> true
-	)
-	PORT MAP
-	(
-		rst			=> RST,
-		clk			=> CLK,
-		din_en		=> sipo2_enable,
-		din_vld		=> sipo2_din_vld,
-		din			=> sipo2_din,
-		dout_be		=> sipo2_dout_be,
-		dout_vld	=> sipo2_dout_vld,
-		dout		=> sipo2_dout,
-		dout_en		=> sipo2_dout_en
-		
-	);
-	sipo2_din		<= piso2_dout;
-	sipo2_din_vld	<= piso2_dout_vld;
-	sipo2_enable	<= sipo2_din_vld;
-	sipo_rst		<= RST or not piso2_dout_vld;
+	sipo_din		<= piso_dout;
+	sipo_din_en		<= piso_dout_en;

 CLK_GEN: process
 	begin
@@ -177,42 +193,230 @@ CLK_GEN: process
 		CLK <= not CLK;
 	end process;

+MII_CLK_GEN: process
+	begin
+		wait for MII_CLK_PERIOD/2;
+		mii_rx_clk <= not mii_rx_clk;
+		mii_tx_clk <= not mii_tx_clk;
+	end process;
+
+	mii_rx_clk_board <= mii_rx_clk;
+	mii_tx_clk_board <= mii_tx_clk;
+
+DAT_O_register:
+	process(CLK)
+	begin
+		if rising_edge(CLK) then
+			if ACK_O = '1' then
+				DAT_O_reg	<= DAT_O;
+			end if;
+		end if;
+	end process;
+	

 -- Master
 STIMULUS: process

+	procedure emac_alloc (size : natural) is
+	begin
+	
+		-- TX-ALLOCATION
+		-- set TX-size
+		emac_action	<= emac_alloc;
+		CYC_I	<= '1';
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		DAT_I	<= to_unsigned(size, 16) & X"55AA";
+		STB_I	<= '1';
+		WE_I	<= '1';
+		ADDR_I	<= X"0000_0004";
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		STB_I	<= '0';
+
+		-- set alloc request
+		CYC_I	<= '1';
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		DAT_I	<= X"0001_0000";
+		STB_I	<= '1';
+		WE_I	<= '1';
+		ADDR_I	<= X"0000_0000";
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		STB_I	<= '0';
+
+		WE_I	<= '0';
+
+		-- check alloc busy
+	check_bsy:
+		while (true) loop
+			CYC_I	<= '1';
+			wait until rising_edge(CLK) and SRDY_O = '1';
+			STB_I	<= '1';
+			ADDR_I	<= X"0000_0000";
+			wait until rising_edge(CLK) and SRDY_O = '1';
+			STB_I	<= '0';
+			wait until rising_edge(CLK) and ACK_O = '1';
+			wait until rising_edge(CLK);
+			if DAT_O_reg(16) = '0' then
+				exit check_bsy;
+			end if;
+		end loop;
+		emac_action	<= emac_idle;
+
+	end procedure emac_alloc;
+	
+	procedure emac_write (size : natural) is
+	variable data : unsigned (7 downto 0);
+	variable num_words : natural;
+	begin
+
+		-- FILL TX data
+		emac_action	<= emac_write;
+		if (size mod 4) = 0 then
+			num_words	:= size/4;
+		else
+			num_words	:= size/4 + 1;
+		end if;
+		
+		CYC_I	<= '1';
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		data	:= X"00";
+		ADDR_I	<= X"0000_0008";
+		WE_I	<= '1';
+		for i in 1 to num_words loop
+			STB_I	<= '1';
+			DAT_I(7 downto 0)	<= data;
+			data				:= data + 1;
+			DAT_I(15 downto 8)	<= data;
+			data				:= data + 1;
+			DAT_I(23 downto 16)	<= data;
+			data				:= data + 1;
+			DAT_I(31 downto 24)	<= data;
+			data				:= data + 1;
+			wait until rising_edge(CLK) and SRDY_O = '1';
+		end loop;
+
+		STB_I	<= '0';
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		emac_action	<= emac_idle;
+
+	end procedure emac_write;

 	begin

-		wait for 600*CLK_PERIOD;
+		wait for 6*MII_CLK_PERIOD;
 		RST <= '0';
 		wait for 60*CLK_PERIOD;

+ 		emac_alloc (1536);
+ 		emac_write (1536);
+ 
+ 		emac_alloc (1536);
+ 		emac_write (1536);
+
+ 		emac_alloc (1536);
+ 		emac_write (1536);
+
+ 		emac_alloc (1536);
+ 		emac_write (1536);
+
+ 		emac_alloc (1536);
+ 		emac_write (1536);
+
+ 		emac_alloc (1536);
+ 		emac_write (1536);
+
+ 		emac_alloc (1536);
+ 		emac_write (1536);
+
+		emac_alloc (64);
+		emac_write (64);
+
+		emac_alloc (512);
+		emac_write (512);
+
+		emac_alloc (1536);
+		emac_write (1536);
+
+		emac_alloc (65);
+		emac_write (65);
+
+		emac_alloc (66);
+		emac_write (66);
+
+		emac_alloc (67);
+		emac_write (67);
+
+		emac_alloc (512);
+		emac_write (512);
+
+		wait for 4000*CLK_PERIOD;
+		
+		wait until rising_edge(CLK);
+		shift_din		<= X"12345678";
+		shift_sa		<= 0;
+		shift_din_vld	<= '1';
+		wait until rising_edge(CLK);
+		shift_sa		<= shift_sa + 1;
+		wait until rising_edge(CLK);
+		shift_sa		<= shift_sa + 1;
+		wait until rising_edge(CLK);
+		shift_sa		<= shift_sa + 1;
+		wait until rising_edge(CLK);
+		shift_sa		<= shift_sa + 1;
+		wait until rising_edge(CLK);
+		shift_sa		<= shift_sa + 1;
+		wait until rising_edge(CLK);
+		shift_sa		<= shift_sa + 1;
+		wait until rising_edge(CLK);
+		shift_sa		<= shift_sa + 1;
+		wait until rising_edge(CLK);
+
+		shift_sa		<= 0;
+		wait until rising_edge(CLK);
+		shift_sa		<= shift_sa - 1;
+		wait until rising_edge(CLK);
+		shift_sa		<= shift_sa - 1;
+		wait until rising_edge(CLK);
+		shift_sa		<= shift_sa - 1;
+		wait until rising_edge(CLK);
+		shift_sa		<= shift_sa - 1;
+		wait until rising_edge(CLK);
+		shift_sa		<= shift_sa - 1;
+		wait until rising_edge(CLK);
+		shift_sa		<= shift_sa - 1;
+		wait until rising_edge(CLK);
+		shift_sa		<= shift_sa - 1;
+
+		wait until rising_edge(CLK);
+		shift_din_vld	<= '0';
+
+		
 		for i in 1 to 10 loop

 			wait until rising_edge(CLK);
+			sipo_enable		<= '1';
 			piso_din_vld	<= '1';
 			piso_din		<= X"12345678";
-			piso_din_be		<= "1111";
+			piso_din_be		<= "11111111";
 			wait until rising_edge(CLK) and piso_din_rdy = '1';
 			piso_din		<= piso_din + X"12345678";
-			piso_din_be		<= "1111";
+			piso_din_be		<= "11100111";
 			wait until rising_edge(CLK) and piso_din_rdy = '1';
 			piso_din		<= piso_din + X"12345678";
-			piso_din_be		<= "1111";
+			piso_din_be		<= "11111100";
 			wait until rising_edge(CLK) and piso_din_rdy = '1';
 			piso_din		<= piso_din + X"12345678";
-			piso_din_be		<= "1100";
+			piso_din_be		<= "00111111";
 			wait until rising_edge(CLK) and piso_din_rdy = '1';
 			piso_din		<= (others => '-');
 			piso_din_vld	<= '0';


-			wait until rising_edge(CLK) and piso_dout_vld = '0';
+			wait until rising_edge(CLK) and sipo_dout_vld = '1';
+			wait until rising_edge(CLK);
+			wait until rising_edge(CLK) and sipo_dout_vld = '1';
+
+			sipo_enable		<= '0';

--			wait until rising_edge(CLK);
--			wait until rising_edge(CLK) and sipo_dout_vld = '1';
--
 			wait for 33*CLK_PERIOD;
 		
 		end loop;
@@ -32,7 +32,7 @@ END tb_emac_top_jb;
 ARCHITECTURE behavior OF tb_emac_top_jb IS 

 	constant CLK_PERIOD		: time := 10 ns;
-	constant MII_CLK_PERIOD	: time := 37.7 ns;
+	constant MII_CLK_PERIOD	: time := 40.7 ns;

 	signal CLK				: std_logic := '1';
 	signal RST				: std_logic := '1';
@@ -50,20 +50,6 @@ ARCHITECTURE behavior OF tb_emac_top_jb IS
 	signal DAT_I			: unsigned(31 downto 0) := (others => '-');
 	signal DAT_O			: unsigned(31 downto 0) := (others => '-');
 	signal DAT_O_reg		: unsigned(31 downto 0) := (others => '-');
-	signal status_reg		: unsigned(31 downto 0) := (others => '0');
-	signal size_reg			: unsigned(31 downto 0) := (others => '0');
-
-	-- Master
-	signal CYC_O					: std_logic;
-	signal STB_O					: std_logic;
-	signal WE_O						: std_logic;
-	signal SEL_O					: unsigned(3 downto 0) := (others => '1');
-	signal ACK_I					: std_logic := '0';
-	signal MRDY_O					: std_logic := '1';
-	signal SRDY_I					: std_logic := '1';
-	signal ADDR_O					: unsigned(31 downto 0) := (others => '-');
-	signal MDAT_I					: unsigned(31 downto 0) := (others => '-');
-	signal MDAT_O					: unsigned(31 downto 0) := (others => '-');

 	-- MII signals
 	signal mii_rx_clk_board	: std_logic := '1';
@@ -85,9 +71,8 @@ ARCHITECTURE behavior OF tb_emac_top_jb IS
 	signal pktgen_tx		: unsigned(7 downto 0);
 	signal pktgen_tx_en		: std_logic;
 	signal pktgen_tx_er		: std_logic;
-	signal pktgen_en		: std_logic := '0';
-	signal pktgen_gigabit	: std_logic := '0';
-	signal pktgen_fcs_en	: std_logic := '0';
+	signal pktgen_rst		: std_logic := '1';
+
 	signal dat_o_cnt_en		: std_logic := '0';
 	signal dat_o_cnt_rst	: std_logic := '1';
 	signal dat_o_cnt		: natural;
@@ -96,92 +81,8 @@ ARCHITECTURE behavior OF tb_emac_top_jb IS
 	type emac_action_t is (emac_idle, emac_alloc, emac_write, emac_commit, emac_wait_data, emac_read, emac_free);
 	signal emac_action	: emac_action_t;
 	
-	constant RX_STATUS_REG_ADDR	: unsigned(31 downto 0) := X"0000_0000";
-	constant RX_SIZE_REG_ADDR	: unsigned(31 downto 0) := X"0000_0004";
-	constant TX_STATUS_REG_ADDR	: unsigned(31 downto 0) := X"0000_0008";
-	constant TX_SIZE_REG_ADDR	: unsigned(31 downto 0) := X"0000_000C";
-	constant DATA_REG_ADDR		: unsigned(31 downto 0) := X"0000_8000";
-
-
-	-- 64Bit RAM
-	signal MDAT_I_64				: unsigned(63 downto 0) := (others => '-');
-	signal MDAT_O_64				: unsigned(63 downto 0) := (others => '-');
-
-	type ram_t  is array (0 to 511) of unsigned(63 downto 0);
-
-	signal ram64		: ram_t;
-
-	
 BEGIN

-	MDAT_I	<= MDAT_I_64(31 downto 0);
-	MDAT_O_64	<= MDAT_O & MDAT_O;
-
-	process(CLK)
-	variable res: unsigned(63 downto 0);
-	variable ram_data : unsigned(63 downto 0);
-	variable data8: unsigned(7 downto 0);
-	begin
-		if rising_edge(CLK) then
-			if RST = '1' then
-					data8 := X"00";
-				for i in 0 to 255 loop
-					ram_data(7 downto 0)	:= data8;
-					data8				:= data8 + 1;
-					ram_data(15 downto 8)	:= data8;
-					data8				:= data8 + 1;
-					ram_data(23 downto 16)	:= data8;
-					data8				:= data8 + 1;
-					ram_data(31 downto 24)	:= data8;
-					data8				:= data8 + 1;
-					ram_data(39 downto 32)	:= data8;
-					data8				:= data8 + 1;
-					ram_data(47 downto 40)	:= data8;
-					data8				:= data8 + 1;
-					ram_data(55 downto 48)	:= data8;
-					data8				:= data8 + 1;
-					ram_data(63 downto 56)	:= data8;
-					data8				:= data8 + 1;
-					ram64(i) <= ram_data;
-				end loop;
-			else
-				ACK_I	<= '0';
-				if (CYC_O and STB_O) = '1' then
-					if WE_O = '0' then
-						ACK_I	<= '1';
-						ram_data := ram64(to_integer(ADDR_O(31 downto 3)));
-						if ADDR_O(2) = '0' then
-							res			:= ram_data;
-						else
-							res			:= ram_data(31 downto 0) & ram_data(63 downto 32);
-						end if;
-					else -- WE=1
-						ram_data := ram64(to_integer(ADDR_O(31 downto 3)));
-					--	ram_data := (others => '-');
-						if ADDR_O(2) = '0' then
-							if SEL_O = "11111111" then
-								ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64;
-							elsif SEL_O = "00001111" then
-								ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O_64(31 downto 0);
-							elsif SEL_O = "11110000" then
-								ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(63 downto 32) & ram_data(31 downto 0);
-							end if;
-						else
-							if SEL_O = "11111111" then
-								ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(31 downto 0) & MDAT_O_64(63 downto 32);
-							elsif SEL_O = "00001111" then
-								ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(31 downto 0) & ram_data(31 downto 0);
-							elsif SEL_O = "11110000" then
-								ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O_64(63 downto 32);
-							end if;
-						end if;
-					end if;
-				end if;
-				MDAT_I_64	<= res;
-			end if;
-		end if;
-	end process;
-
 inst_emac_top_jb : entity work.emac_top_jb
 	GENERIC MAP
 	(
@@ -191,7 +92,6 @@ inst_emac_top_jb : entity work.emac_top_jb
 	)
 	PORT MAP
 	(
-		-- JBUS Slave signals
 		CLK_I		=> CLK,
 		RST_I		=> RST,
 		INT_O		=> INT_O,
@@ -205,19 +105,6 @@ inst_emac_top_jb : entity work.emac_top_jb
 		ADDR_I		=> ADDR_I,
 		DAT_I		=> DAT_I,
 		DAT_O		=> DAT_O,
-		
-		-- JBUS Master signals
-		CYC_O		=> CYC_O,
-		STB_O		=> STB_O,
-		WE_O		=> WE_O,
-		SEL_O		=> SEL_O,
-		ACK_I		=> ACK_I,
-		SRDY_I		=> SRDY_I,
-		MRDY_O		=> MRDY_O,
-		ADDR_O		=> ADDR_O,
-		MDAT_I		=> MDAT_I,
-		MDAT_O		=> MDAT_O,
-		
 		mii_rx_clk	=> mii_rx_clk_board,
 		mii_rx_dv	=> mii_rx_dv,
 		mii_rx_er	=> mii_rx_er,
@@ -236,6 +123,8 @@ inst_pkt_gen : entity work.pkt_gen
 	GENERIC MAP
 	(
 		f_sysclk		=> 100.0,
+		PKT_DLY_MIN		=> 1.0E-6,
+		PKT_DLY_MAX		=> 5.0E-6,
 		PKT_SIZE_MIN	=> 64,
 		PKT_SIZE_MAX	=> 1512
 		
@@ -243,10 +132,7 @@ inst_pkt_gen : entity work.pkt_gen
 	PORT MAP
 	(
 		clk			=> CLK,
-		rst			=> RST,
-		en			=> pktgen_en,
-		gigabit_en	=> pktgen_gigabit,
-		fcs_gen_en	=> pktgen_fcs_en,
+		rst			=> pktgen_rst,
 		mii_tx_clk	=> mii_tx_clk_board,
 		mii_tx_en	=> pktgen_tx_en,
 		mii_tx_er	=> pktgen_tx_er,
@@ -302,66 +188,6 @@ DAT_O_count_register:
 -- Master
 STIMULUS: process

-	procedure emac_tx_reset_100mbps  is
-	begin
-	
-		CYC_I	<= '1';
-		wait until rising_edge(CLK) and SRDY_O = '1';
-		DAT_I	<= X"A000_0000";
-		STB_I	<= '1';
-		WE_I	<= '1';
-		ADDR_I	<= TX_STATUS_REG_ADDR;
-		wait until rising_edge(CLK) and SRDY_O = '1';
-		STB_I	<= '0';
-		WE_I	<= '0';
-
-	end procedure emac_tx_reset_100mbps;
-
-	procedure emac_rx_reset_100mbps  is
-	begin
-	
-		CYC_I	<= '1';
-		wait until rising_edge(CLK) and SRDY_O = '1';
-		DAT_I	<= X"A000_0000";
-		STB_I	<= '1';
-		WE_I	<= '1';
-		ADDR_I	<= RX_STATUS_REG_ADDR;
-		wait until rising_edge(CLK) and SRDY_O = '1';
-		STB_I	<= '0';
-		WE_I	<= '0';
-
-	end procedure emac_rx_reset_100mbps;
-
-	procedure emac_tx_reset_1000mbps  is
-	begin
-	
-		CYC_I	<= '1';
-		wait until rising_edge(CLK) and SRDY_O = '1';
-		DAT_I	<= X"E000_0000";
-		STB_I	<= '1';
-		WE_I	<= '1';
-		ADDR_I	<= TX_STATUS_REG_ADDR;
-		wait until rising_edge(CLK) and SRDY_O = '1';
-		STB_I	<= '0';
-		WE_I	<= '0';
-
-	end procedure emac_tx_reset_1000mbps;
-
-	procedure emac_rx_reset_1000mbps  is
-	begin
-	
-		CYC_I	<= '1';
-		wait until rising_edge(CLK) and SRDY_O = '1';
-		DAT_I	<= X"E000_0000";
-		STB_I	<= '1';
-		WE_I	<= '1';
-		ADDR_I	<= RX_STATUS_REG_ADDR;
-		wait until rising_edge(CLK) and SRDY_O = '1';
-		STB_I	<= '0';
-		WE_I	<= '0';
-
-	end procedure emac_rx_reset_1000mbps;
-
 	procedure emac_alloc (size : natural) is
 	begin
 	
@@ -370,45 +196,36 @@ STIMULUS: process
 		emac_action	<= emac_alloc;
 		CYC_I	<= '1';
 		wait until rising_edge(CLK) and SRDY_O = '1';
-		DAT_I	<= to_unsigned(size, 32);
+		DAT_I	<= to_unsigned(size, 16) & X"55AA";
 		STB_I	<= '1';
 		WE_I	<= '1';
-		ADDR_I	<= TX_SIZE_REG_ADDR;
+		ADDR_I	<= X"0000_0004";

 	check_alloc_ok:
 		while(true) loop

 			-- set alloc request
 			wait until rising_edge(CLK) and SRDY_O = '1';
-			WE_I	<= '0';
-			STB_I	<= '1';
-			ADDR_I	<= TX_STATUS_REG_ADDR;
-			wait until rising_edge(CLK) and SRDY_O = '1';
-			STB_I	<= '0';
-			wait until rising_edge(CLK) and ACK_O = '1';
-			status_reg	<= DAT_O;
-			wait until rising_edge(CLK) and SRDY_O = '1';
-			DAT_I	<= X"0002_0000" or (not X"0001_0000" and status_reg);
+			DAT_I	<= X"0200_0000";
 			STB_I	<= '1';
 			WE_I	<= '1';
-			ADDR_I	<= TX_STATUS_REG_ADDR;
+			ADDR_I	<= X"0000_0000";

 		check_bsy:
 			while (true) loop
 				wait until rising_edge(CLK) and SRDY_O = '1';
 				WE_I	<= '0';
 				STB_I	<= '1';
-				ADDR_I	<= TX_STATUS_REG_ADDR;
+				ADDR_I	<= X"0000_0000";
 				wait until rising_edge(CLK) and SRDY_O = '1';
 				STB_I	<= '0';
 				wait until rising_edge(CLK) and ACK_O = '1';
-				status_reg	<= DAT_O;
 				wait until rising_edge(CLK);
-				if status_reg(17) = '0' then
+				if DAT_O_reg(25) = '0' then
 					exit check_bsy;
 				end if;
 			end loop;
-			if status_reg(16) = '1' then
+			if DAT_O_reg(24) = '1' then
 				exit check_alloc_ok;
 			end if;
 		end loop;
@@ -427,18 +244,10 @@ STIMULUS: process
 		-- set free request
 		CYC_I	<= '1';
 		wait until rising_edge(CLK) and SRDY_O = '1';
-		WE_I	<= '0';
-		STB_I	<= '1';
-		ADDR_I	<= TX_STATUS_REG_ADDR;
-		wait until rising_edge(CLK) and SRDY_O = '1';
-		STB_I	<= '0';
-		wait until rising_edge(CLK) and ACK_O = '1';
-		status_reg	<= DAT_O;
-		wait until rising_edge(CLK) and SRDY_O = '1';
-		DAT_I	<= X"0001_0000" or (not X"0002_0000" and status_reg);
+		DAT_I	<= X"0100_0000";
 		STB_I	<= '1';
 		WE_I	<= '1';
-		ADDR_I	<= TX_STATUS_REG_ADDR;
+		ADDR_I	<= X"0000_0000";
 		wait until rising_edge(CLK) and SRDY_O = '1';
 		STB_I	<= '0';
 		WE_I	<= '0';
@@ -463,7 +272,7 @@ STIMULUS: process
 		CYC_I	<= '1';
 		wait until rising_edge(CLK) and SRDY_O = '1';
 		data	:= X"00";
-		ADDR_I	<= DATA_REG_ADDR;
+		ADDR_I	<= X"0000_0008";
 		WE_I	<= '1';
 		for i in 1 to num_words loop
 			STB_I	<= '1';
@@ -492,7 +301,6 @@ STIMULUS: process
 	variable size, num_words : natural;
 	begin

-		return;
 		emac_action	<= emac_wait_data;

 		-- check if data available
@@ -502,13 +310,12 @@ STIMULUS: process
 			wait until rising_edge(CLK) and SRDY_O = '1';
 			WE_I	<= '0';
 			STB_I	<= '1';
-			ADDR_I	<= RX_STATUS_REG_ADDR;
+			ADDR_I	<= X"0000_0000";
 			wait until rising_edge(CLK) and SRDY_O = '1';
 			STB_I	<= '0';
 			wait until rising_edge(CLK) and ACK_O = '1';
-			status_reg	<= DAT_O;
 			wait until rising_edge(CLK);
-			if status_reg(17) = '1' and status_reg(16) = '1' then
+			if DAT_O_reg(16) = '1' then
 				exit check_data_avail;
 			end if;
 		end loop;
@@ -519,28 +326,19 @@ STIMULUS: process
 		wait until rising_edge(CLK) and SRDY_O = '1';
 		WE_I	<= '0';
 		STB_I	<= '1';
-		ADDR_I	<= RX_SIZE_REG_ADDR;
+		ADDR_I	<= X"0000_0004";
 		wait until rising_edge(CLK) and SRDY_O = '1';
 		STB_I	<= '0';
 		wait until rising_edge(CLK) and ACK_O = '1';
-		size_reg	<= DAT_O;
 		wait until rising_edge(CLK);

 		-- set packet request
 		CYC_I	<= '1';
 		wait until rising_edge(CLK) and SRDY_O = '1';
-		WE_I	<= '0';
-		STB_I	<= '1';
-		ADDR_I	<= RX_STATUS_REG_ADDR;
-		wait until rising_edge(CLK) and SRDY_O = '1';
-		STB_I	<= '0';
-		wait until rising_edge(CLK) and ACK_O = '1';
-		status_reg	<= DAT_O;
-		wait until rising_edge(CLK) and SRDY_O = '1';
-		DAT_I	<= X"0002_0000" or (not X"0001_0000" and status_reg);
+		DAT_I	<= X"0001_0000";
 		STB_I	<= '1';
 		WE_I	<= '1';
-		ADDR_I	<= RX_STATUS_REG_ADDR;
+		ADDR_I	<= X"0000_0000";
 		wait until rising_edge(CLK) and SRDY_O = '1';
 		STB_I	<= '0';
 		WE_I	<= '0';
@@ -549,7 +347,7 @@ STIMULUS: process
 		-- Read RX data
 		size := size_in;
 		if (size_in = 0) then
-			size	:= to_integer(size_reg(15 downto 0));
+			size	:= to_integer(DAT_O_reg(15 downto 0));
 		end if;
 		
 		if (size mod 4) = 0 then
@@ -562,7 +360,8 @@ STIMULUS: process
 		dat_o_cnt_en <= '1';
 		CYC_I	<= '1';
 		wait until rising_edge(CLK) and SRDY_O = '1';
-		ADDR_I	<= DATA_REG_ADDR;
+		data	:= X"00";
+		ADDR_I	<= X"0000_0008";
 		WE_I	<= '0';
 		STB_I	<= '1';
 		for i in 1 to num_words loop
@@ -578,25 +377,16 @@ STIMULUS: process
 	procedure emac_free  is
 	begin
 	
-		return;
 		-- RX- DEALLOCATION
 		emac_action	<= emac_free;

 		-- set free request
 		CYC_I	<= '1';
 		wait until rising_edge(CLK) and SRDY_O = '1';
-		WE_I	<= '0';
-		STB_I	<= '1';
-		ADDR_I	<= RX_STATUS_REG_ADDR;
-		wait until rising_edge(CLK) and SRDY_O = '1';
-		STB_I	<= '0';
-		wait until rising_edge(CLK) and ACK_O = '1';
-		status_reg	<= DAT_O;
-		wait until rising_edge(CLK) and SRDY_O = '1';
-		DAT_I	<= X"0001_0000" or (not X"0002_0000" and status_reg);
+		DAT_I	<= X"0002_0000";
 		STB_I	<= '1';
 		WE_I	<= '1';
-		ADDR_I	<= RX_STATUS_REG_ADDR;
+		ADDR_I	<= X"0000_0000";
 		wait until rising_edge(CLK) and SRDY_O = '1';
 		STB_I	<= '0';
 		WE_I	<= '0';
@@ -610,12 +400,7 @@ STIMULUS: process
 		wait for 6*MII_CLK_PERIOD;
 		RST <= '0';
 		wait for 60*CLK_PERIOD;
-		emac_rx_reset_100mbps;
-		emac_tx_reset_100mbps;
-		pktgen_gigabit	<= '0';
-		pktgen_fcs_en	<= '1';
-		wait for 60*CLK_PERIOD;
-		
+
 		emac_alloc (1004);
 		emac_alloc (1004);
 		emac_alloc (1004);
@@ -630,11 +415,11 @@ STIMULUS: process
 		emac_alloc (1004);

 		for i in 1 to 10 loop
-			for j in 1 to 100 loop
+			for j in 1 to 500 loop
 		 		emac_alloc (72);
 		 		emac_write (72);
 			end loop;
-			wait for 1 ms;
+			wait for 2 ms;
 		end loop;
 		
 		wait until rising_edge(mii_tx_clk) and mii_tx_en = '0';
@@ -642,11 +427,11 @@ STIMULUS: process
 		
 		loop_back_en	<= '1';
 		
- 		emac_alloc (74);
- 		emac_write (74);
+ 		emac_alloc (72);
+ 		emac_write (72);
 
- 		emac_alloc (105);
- 		emac_write (105);
+ 		emac_alloc (104);
+ 		emac_write (104);

 		emac_read (0);
 		emac_free;
@@ -654,14 +439,14 @@ STIMULUS: process
 		emac_read (0);
 		emac_free;

- 		emac_alloc (103);
- 		emac_write (103);
+ 		emac_alloc (104);
+ 		emac_write (104);

 		emac_read (0);
 		emac_free;

- 		emac_alloc (71);
- 		emac_write (71);
+ 		emac_alloc (72);
+ 		emac_write (72);
 
 		emac_read (0);
 		emac_free;
@@ -669,8 +454,8 @@ STIMULUS: process
 		emac_alloc (82);
 		emac_write (82);

- 		emac_alloc (86);
- 		emac_write (86);
+ 		emac_alloc (82);
+ 		emac_write (82);

 		emac_read (0);
 		emac_free;
@@ -678,44 +463,44 @@ STIMULUS: process
 		emac_read (0);
 		emac_free;

- 		emac_alloc (77);
- 		emac_write (77);
-
- 		emac_alloc (99);
- 		emac_write (99);
-
- 		emac_alloc (65);
- 		emac_write (65);
-
- 		emac_alloc (321);
- 		emac_write (321);
-
-		emac_read (0);
-		emac_free;
-
- 		emac_alloc (1111);
- 		emac_write (1111);
-
-		emac_read (0);
-		emac_free;
-
- 		emac_alloc (73);
- 		emac_write (73);
-
- 		emac_alloc (107);
- 		emac_write (107);
-
- 		emac_alloc (83);
- 		emac_write (83);
-
-		emac_read (0);
-		emac_free;
-
 		emac_alloc (72);
 		emac_write (72);

- 		emac_alloc (1003);
- 		emac_write (1003);
+ 		emac_alloc (104);
+ 		emac_write (104);
+
+ 		emac_alloc (82);
+ 		emac_write (82);
+
+ 		emac_alloc (72);
+ 		emac_write (72);
+
+		emac_read (0);
+		emac_free;
+
+ 		emac_alloc (104);
+ 		emac_write (104);
+
+		emac_read (0);
+		emac_free;
+
+ 		emac_alloc (72);
+ 		emac_write (72);
+
+ 		emac_alloc (104);
+ 		emac_write (104);
+
+ 		emac_alloc (82);
+ 		emac_write (82);
+
+		emac_read (0);
+		emac_free;
+
+ 		emac_alloc (72);
+ 		emac_write (72);
+
+ 		emac_alloc (104);
+ 		emac_write (104);

 		emac_read (0);
 		emac_free;
@@ -741,15 +526,15 @@ STIMULUS: process
 		wait for 6000*CLK_PERIOD;

 		loop_back_en	<= '0';
-		pktgen_en		<= '1';
+		pktgen_rst		<= '0';
 		pkt_count		<= 0;
 		for i in 1 to 500 loop
-			wait for 1 us;
+			wait for 7 us;
 			emac_read (0);
 			emac_free;
 			pkt_count	<= pkt_count + 1;
 		end loop;
-		pktgen_en		<= '0';
+		pktgen_rst		<= '1';
 		emac_read (0);
 		emac_free;