From ec35a40898e26f298e7b282e28b89aaaea1d2cf7 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sat, 30 May 2015 09:07:36 +0000 Subject: [PATCH] - simplified PHY control signals git-svn-id: http://moon:8086/svn/vhdl/trunk@1261 cc03376c-175c-47c8-b038-4cd826a8556b --- .../ddr_sdr_v1_5/src/sdr_phy_de0nano.vhd | 113 +++++++++--------- 1 file changed, 55 insertions(+), 58 deletions(-) diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdr_phy_de0nano.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdr_phy_de0nano.vhd index 9accd1e..79a528b 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdr_phy_de0nano.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdr_phy_de0nano.vhd @@ -61,7 +61,6 @@ end sdram_phy; architecture tech of sdram_phy is - signal drive : std_logic; signal data_reg_r : unsigned(BUS_DATA_WIDTH-1 downto 0); signal part_ctrl_reg : part_ctrl_t; signal we_reg : std_logic; @@ -76,8 +75,11 @@ architecture tech of sdram_phy is signal reset_counter : unsigned(7 downto 0) := (others => '1'); signal reset : STD_LOGIC := '1'; - type u_tag_array_t is array (natural range 0 to 4) of user_tag_t; - signal u_tag_pipe : u_tag_array_t; + signal we_cl_pipe : unsigned(TCAS-1 downto 0); + signal re_cl_pipe : unsigned(TCAS+2 downto 0); -- +2 = number of pipe registers used here + + type u_tag_array_t is array (natural range 0 to TCAS+3) of user_tag_t; + signal u_tag_pipe : u_tag_array_t; attribute KEEP : string; attribute KEEP of clk0 : signal is "TRUE"; @@ -89,6 +91,11 @@ begin clk0 <= clk0_temp after 10 ps; -- fix delta delay rst0_out <= rst0; -- clk0_rd <= clk_fb; -- no feedback pin on DE0-Nano, use shifted clk1_0_out from clock gen + + phy_out.wr_data_re <= we_cl_pipe(we_cl_pipe'left); + phy_out.rd_data_we <= re_cl_pipe(re_cl_pipe'left); + phy_out.tag_rd <= u_tag_pipe(u_tag_pipe'high); + phy_out.tag_wr <= u_tag_pipe(1); ------------------------------------------------------------------------------------------------------------------------------------------------ inst_sdram_clk : entity work.sdram_clk @@ -126,39 +133,49 @@ rst0_gen: end process; ------------------------------------------------------------------------------------------------------------------------------------------------ -utag_pipe: - process(clk0) - begin - if rising_edge(clk0) then - for i in u_tag_pipe'length-1 downto 1 loop - u_tag_pipe(i) <= u_tag_pipe(i-1); - end loop; - if phy_ctrl.utag_we = '1' then - u_tag_pipe(0) <= phy_ctrl.u_tag; - end if; - end if; +utag_pipe: + process(clk0) + begin + if rising_edge(clk0) then + for i in u_tag_pipe'length-1 downto 1 loop + u_tag_pipe(i) <= u_tag_pipe(i-1); + end loop; + if phy_ctrl.utag_we = '1' then + u_tag_pipe(0) <= phy_ctrl.u_tag; + end if; + end if; + end process; + +we_pipe: + process(clk0) + begin + if rising_edge(clk0) then + if rst0 = '1' then + we_cl_pipe <= (others => '0'); + else + for i in we_cl_pipe'length-1 downto 1 loop + we_cl_pipe(i) <= we_cl_pipe(i-1); + end loop; + we_cl_pipe(0) <= phy_ctrl.we; + end if; + end if; + end process; + +re_pipe: + process(clk0) + begin + if rising_edge(clk0) then + if rst0 = '1' then + re_cl_pipe <= (others => '0'); + else + for i in re_cl_pipe'length-1 downto 1 loop + re_cl_pipe(i) <= re_cl_pipe(i-1); + end loop; + re_cl_pipe(0) <= phy_ctrl.re; + end if; + end if; end process; - -WE_REGISTER: - process(clk0) - begin - if rising_edge(clk0) then - if rst0 = '1' then - we_reg <= '0'; - else - we_reg <= phy_ctrl.we; - end if; - end if; - end process; - -DATA_DRIVE_GEN: - process(clk0) - begin - if falling_edge(clk0) then - drive <= phy_ctrl.drive_en; - end if; - end process; - + ------------------------------------------------------------------------------------------------------------------------------------------------ -- SDRAM Clock part_clk <= clk0 after TPD_BOARD_SIM; @@ -169,7 +186,7 @@ part_clk <= clk0 after TPD_BOARD_SIM; begin if falling_edge(clk0) then part_data <= (others => 'Z') after TPD_BOARD_SIM; - if (phy_ctrl.drive_en = '1') then + if (phy_ctrl.we = '1') then part_data <= phy_in.wr_data after TPD_BOARD_SIM; end if; end if; @@ -223,31 +240,11 @@ data_sample_stage: end if; end process; -misc_flags_and_data_out: +register_data_out: process (clk0) - variable p : unsigned(3 downto 0); begin if rising_edge(clk0) then - if rst0 = '1' then - p := (others => '0'); - phy_out.rd_data_we <= '0'; - phy_out.wr_data_re <= '0'; - else - phy_out.rd_data <= data_reg_r; - if p(3) = '1' then - phy_out.tag_rd <= u_tag_pipe(4); - end if; - if phy_ctrl.we = '1' then - phy_out.tag_wr <= u_tag_pipe(0); - end if; - phy_out.wr_data_re <= phy_ctrl.drive_en; - phy_out.rd_data_we <= p(2); - if phy_ctrl.re = '1' then - p := p(p'left-1 downto 0) & '1'; - else - p := p(p'left-1 downto 0) & '0'; - end if; - end if; + phy_out.rd_data <= data_reg_r; end if; end process;