- added
git-svn-id: http://moon:8086/svn/vhdl/trunk@1414 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -0,0 +1,68 @@
|
||||
# -------------------------------------------------
|
||||
# Global options
|
||||
# -------------------------------------------------
|
||||
LANG_STD := 93c
|
||||
IEEE_STD := standard
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||||
WORK_PATH := work
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||||
SOURCE_PATH := src
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||||
LIB_PATH := ../lib
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||||
|
||||
# -------------------------------------------------
|
||||
# Target options
|
||||
# -------------------------------------------------
|
||||
TARGET := tb_cpu
|
||||
|
||||
SOURCES := $(SOURCE_PATH)/cpu_pkg.vhd \
|
||||
$(SOURCE_PATH)/stack.vhd \
|
||||
$(SOURCE_PATH)/pc.vhd \
|
||||
$(SOURCE_PATH)/reg_dual.vhd \
|
||||
$(SOURCE_PATH)/dpath_ctrl.vhd \
|
||||
$(SOURCE_PATH)/cpu.vhd \
|
||||
$(SOURCE_PATH)/alu.vhd \
|
||||
$(SOURCE_PATH)/$(TARGET).vhd
|
||||
|
||||
# -------------------------------------------------
|
||||
GHDL_OPT := --workdir=$(WORK_PATH) --std=$(LANG_STD) --ieee=$(IEEE_STD)
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||||
|
||||
# -------------------------------------------------
|
||||
all: elaborate
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||||
|
||||
.PHONY: syntax
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||||
syntax:
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||||
ghdl -s $(GHDL_OPT) $(SOURCES)
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||||
|
||||
import:
|
||||
ghdl -i $(GHDL_OPT) $(LIB_PATH)/*.vhd $(SOURCES)
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||||
|
||||
analyze:
|
||||
ghdl -a $(GHDL_OPT) $(LIB_PATH)/*.vhd $(SOURCES)
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||||
|
||||
anaborate:
|
||||
ghdl -c $(GHDL_OPT) $(LIB_PATH)/*.vhd $(SOURCES) -e $(TARGET)
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||||
|
||||
makeunit: analyze
|
||||
ghdl -m $(GHDL_OPT) $(TARGET)
|
||||
|
||||
elaborate: analyze
|
||||
ghdl -e $(GHDL_OPT) $(TARGET)
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||||
|
||||
run: elaborate
|
||||
ghdl -r $(GHDL_OPT) $(TARGET) --vcd=$(TARGET).vcd --wave=$(TARGET).ghw --assert-level=error
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||||
|
||||
show: $(TARGET).vcd
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||||
gtkwave $(TARGET).ghw $(TARGET).sav
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||||
|
||||
xref: import
|
||||
mkdir -p html
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||||
ghdl --xref-html $(SOURCES)
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||||
|
||||
tree: elaborate
|
||||
./$(TARGET) --no-run --disp-tree=inst
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||||
|
||||
# -------------------------------------------------
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||||
.PHONY: clean
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clean:
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rm -rf $(TARGET)
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cd $(WORK_PATH); rm -rf *.o *.cf
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||||
|
||||
# -------------------------------------------------
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||||
@@ -0,0 +1,284 @@
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; -------------------------------------------------
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||||
; Register definitions
|
||||
; -------------------------------------------------
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||||
include "../../../lib/jasm/cregs.inc.jsm"
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include "xregs.inc.jsm"
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||||
; -------------------------------------------------
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||||
; Constants
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; -------------------------------------------------
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CR: equ 0x0D
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LF: equ 0x0A
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report_ival: equ 0x64
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|
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; External RAM/ROM
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||||
xmem
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msg_txt: dc "J-CPU V1.", 0
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||||
|
||||
; Internal RAM
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cmem 0
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count: db 4
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||||
|
||||
cntDigit: db 8
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|
||||
count_stat: db 1
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||||
shifter: db 1
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||||
|
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ram_txt_start: db 15
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||||
ram_txt_end: db 1
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||||
ram_txt_ptr: db 1
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||||
upd_z1: db 1
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||||
page_test_var: db 1
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||||
|
||||
; -------------------------------------------------
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||||
; Program
|
||||
; -------------------------------------------------
|
||||
code
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||||
reset: org 0x000
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jmp ende
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|
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org 1023
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ende: jmp init
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||||
org 0x001
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||||
; -------------------------------------------------
|
||||
; ISR
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||||
; -------------------------------------------------
|
||||
isr: push R0
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||||
push R1
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||||
push R2
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||||
push R3
|
||||
push R4
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||||
push R5
|
||||
push R6
|
||||
push R7
|
||||
push R8
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||||
push R9
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||||
push R10
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||||
push R11
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||||
push R12
|
||||
push R13
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||||
push R14
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push R15
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xin R0, (uart_status)
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and R0, 0x10
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jz rcv_empty
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xin R0, (uart_data)
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cmp R0, 0x0D
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jeq reset_ptr
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movc R1, (ram_txt_ptr)
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movc (R1), R0
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cmp R1, ram_txt_end
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jlt inc_ptr
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reset_ptr: mov R1, ram_txt_start
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dec R1
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||||
movc (upd_z1), R1
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inc_ptr: inc R1
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movc (ram_txt_ptr), R1
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rcv_empty: call Cnt32
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||||
|
||||
pop R15
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||||
pop R14
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||||
pop R13
|
||||
pop R12
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||||
pop R11
|
||||
pop R10
|
||||
pop R9
|
||||
pop R8
|
||||
pop R7
|
||||
pop R6
|
||||
pop R5
|
||||
pop R4
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||||
pop R3
|
||||
pop R2
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||||
pop R1
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||||
pop R0
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reti
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|
||||
; -------------------------------------------------
|
||||
; Main
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||||
; -------------------------------------------------
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||||
init: ; org 0x40
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call CounterInit
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call LCD_init
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mov R0, 0x00
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movc (count_stat), R0
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xout (led_port), R0
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movc (upd_z1), R0
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xin R1, (btn_port)
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or R1, 0x80
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movc (shifter), R1
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mov R0, ram_txt_start
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movc (ram_txt_ptr), R0
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|
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mov R0, ctrl_reg
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; Enable timer
|
||||
xout (R0), 0x02
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; Enable interrupt source
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xout (R0), 0x03
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mov R0, report_ival
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movc (count_stat), R0
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|
||||
; Enable CPU interrupt
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mov R0, 0x03
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cout (cpu_int_ctrl), R0
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|
||||
; Print Hello world
|
||||
mov R0, LCD_CMD_CLEAR
|
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call LCD_writecmd
|
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mov R1, msg_txt
|
||||
call LCD_putsx
|
||||
|
||||
; Read revision reg to form version number v1.<REV>
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||||
end_txt: cin R0, (cpu_revision)
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||||
add R0, 0x30
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||||
call LCD_writechar
|
||||
|
||||
; check page sel function
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||||
mov R0, 0x00
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||||
cout (cpu_control), R0
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||||
mov R1, 0x00
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||||
movc (page_test_var), R1
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||||
|
||||
mov R0, 0x01
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||||
cout (cpu_control), R0
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||||
mov R1, 0xAA
|
||||
movc (page_test_var), R1
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||||
|
||||
mov R0, 0x00
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||||
cout (cpu_control), R0
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movc R0, (page_test_var)
|
||||
cmp R0, 0xAA
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||||
jeq error
|
||||
|
||||
mov R0, 0x01
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||||
cout (cpu_control), R0
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||||
movc R0, (page_test_var)
|
||||
cmp R0, 0xAA
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||||
jeq page_reset
|
||||
|
||||
error: jmp error
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||||
|
||||
page_reset: mov R0, 0x00
|
||||
cout (cpu_control), R0
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||||
|
||||
; -------------------------------------------------
|
||||
; Main loop
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||||
; -------------------------------------------------
|
||||
start: halt
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||||
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||||
movc R0, (count_stat)
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||||
dec R0
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||||
movc (count_stat), R0
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||||
jnz start
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||||
mov R7, report_ival
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movc R1, (cntDigit+0)
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||||
movc R2, (cntDigit+1)
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||||
swap R1
|
||||
xor R1, R2
|
||||
and R1, 0x02
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||||
jnz do_add
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||||
dec R7
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||||
mov R0, 0x2D
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||||
jmp upd_cs
|
||||
|
||||
do_add: inc R7
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||||
mov R0, 0x2B
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||||
upd_cs: movc (count_stat), R7
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||||
call sout
|
||||
|
||||
; Toggle LED
|
||||
movc R0, (shifter)
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||||
rol R0
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||||
movc (shifter), R0
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||||
|
||||
; xin R0, (led_port)
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||||
; xor R0, 0x02
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||||
xout (led_port), R0
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||||
|
||||
movc R0, (upd_z1)
|
||||
mov R1, 0x00
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||||
movc (upd_z1), R1
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||||
tst R0
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||||
jz upd_num
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||||
|
||||
mov R1, ram_txt_start
|
||||
read_ram: movc R0, (R1)
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||||
call LCD_writechar
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||||
inc R1
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||||
cmp R1, ram_txt_end
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||||
jle read_ram
|
||||
|
||||
; Write digits to LCD and serial
|
||||
upd_num: call UpdateDigits
|
||||
mov R0, LCD_CMD_Z2
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||||
call LCD_writecmd
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||||
mov R1, cntDigit+7
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||||
print_num: movc R0, (R1)
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||||
call sout
|
||||
call LCD_writechar
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||||
cmp R1, cntDigit+0
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||||
jeq sendCRLF
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||||
dec R1
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||||
jmp print_num
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||||
|
||||
sendCRLF: mov R0, CR
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||||
call sout
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||||
mov R0, LF
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||||
call sout
|
||||
|
||||
ex_print: jmp start
|
||||
|
||||
; -------------------------------------------------
|
||||
CounterInit: mov R0, 0x00
|
||||
movc (count+0), R0
|
||||
movc (count+1), R0
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||||
movc (count+2), R0
|
||||
movc (count+3), R0
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||||
ret
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||||
|
||||
; -------------------------------------------------
|
||||
Cnt32: mov R0, count+0
|
||||
cloop: movc R1, (R0)
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||||
inc R1
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||||
movc (R0), R1
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||||
jnc CountRdy
|
||||
cmp R0, count+3
|
||||
jeq CountRdy
|
||||
inc R0
|
||||
jmp cloop
|
||||
CountRdy: ret
|
||||
|
||||
; -------------------------------------------------
|
||||
UpdateDigits: mov R2, cntDigit+0
|
||||
mov R0, count+0
|
||||
dualLoop: movc R1, (R0)
|
||||
and R1, 0x0F
|
||||
cmp R1, 0x0A
|
||||
jlt isNum1
|
||||
add R1, 0x07
|
||||
isNum1: add R1, 0x30
|
||||
movc (R2), R1
|
||||
inc R2
|
||||
movc R1, (R0)
|
||||
swap R1
|
||||
and R1, 0x0F
|
||||
cmp R1, 0x0A
|
||||
jlt isNum2
|
||||
add R1, 0x07
|
||||
isNum2: add R1, 0x30
|
||||
movc (R2), R1
|
||||
cmp R0, count+3
|
||||
jeq UpdRdy
|
||||
inc R0
|
||||
inc R2
|
||||
jmp dualLoop
|
||||
UpdRdy: ret
|
||||
|
||||
; -------------------------------------------------
|
||||
include "../../../lib/jasm/uart.inc.jsm"
|
||||
include "../../../lib/jasm/lcd.inc.jsm"
|
||||
include "../../../lib/jasm/delays.inc.jsm"
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,247 @@
|
||||
######################################################################
|
||||
# Copyright (c) 2006 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# XILINX CONFIDENTIAL PROPERTY
|
||||
# This document contains proprietary information which is
|
||||
# protected by copyright. All rights are reserved. No part of
|
||||
# this document may be photocopied, reproduced or translated to
|
||||
# another program language without prior written consent of
|
||||
# XILINX Inc., San Jose, CA. 95124
|
||||
#
|
||||
# Xilinx, Inc.
|
||||
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
|
||||
# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
|
||||
# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
|
||||
# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
|
||||
# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
|
||||
# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
|
||||
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
|
||||
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
|
||||
# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
|
||||
# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
|
||||
# AND FITNESS FOR A PARTICULAR PURPOSE.
|
||||
#
|
||||
######################################################################
|
||||
|
||||
#
|
||||
# For Tcl Manual for builtin commands, see
|
||||
# http://www.tcl.tk/man/tcl8.3
|
||||
#
|
||||
#
|
||||
#
|
||||
|
||||
# Example scanning devices and ChipScope cores, in a JTAG Chain,
|
||||
# using the Cse api.
|
||||
|
||||
# Get the Cse DLL's and globals
|
||||
cd F:\\Xilinx9\\ChipScope_Pro_9_1i\\bin\\nt
|
||||
source csejtag.tcl
|
||||
|
||||
namespace import ::chipscope::*
|
||||
|
||||
# Create global variables
|
||||
|
||||
# Parallel IV Cable
|
||||
set PARALLEL_CABLE_ARGS [list "port=LPT1" \
|
||||
"frequency=200000"]
|
||||
# "frequency=5000000 | 2500000 | 200000"
|
||||
|
||||
# Platform USB Cable
|
||||
set PLATFORM_USB_CABLE_ARGS [list "port=USB2" \
|
||||
"frequency=3000000"]
|
||||
# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
|
||||
|
||||
set CABLE_NAME $CSEJTAG_TARGET_PLATFORMUSB
|
||||
set CABLE_ARGS $PLATFORM_USB_CABLE_ARGS
|
||||
set debug 0
|
||||
|
||||
proc main {argc argv} {
|
||||
global debug
|
||||
global PLATFORM_USB_CABLE_ARGS
|
||||
global CSEJTAG_TARGET_PLATFORMUSB
|
||||
global CABLE_NAME
|
||||
global CABLE_ARGS
|
||||
global CSE_MSG_INFO
|
||||
|
||||
if {[expr ($argc > 0) && [string equal "-h" [lindex $argv 0]]]} {
|
||||
writeMessage 0 $CSE_MSG_INFO "Usage: xtclsh csejtag_examplel1.tcl \[-usb\] \[-d\]\n"
|
||||
exit
|
||||
}
|
||||
|
||||
# for CseServer/CseClient use
|
||||
set serverflag_idx 0
|
||||
set serveraddress_idx 0
|
||||
|
||||
# Checks to see if usb or debug flag is set
|
||||
for {set i 0} {$i < $argc} {incr i} {
|
||||
if {[string equal "-usb" [lindex $argv $i]]} {
|
||||
set CABLE_NAME $CSEJTAG_TARGET_PLATFORMUSB
|
||||
set CABLE_ARGS $PLATFORM_USB_CABLE_ARGS
|
||||
} elseif {[string equal "-d" [lindex $argv $i]]} {
|
||||
set debug 1
|
||||
} elseif {[string equal "-server" [lindex $argv $i]]} {
|
||||
set serverflag_idx $i
|
||||
set serveraddress_idx [expr $i + 1]
|
||||
}
|
||||
}
|
||||
|
||||
# Create Session. Pass location of idcode.lst to override default.
|
||||
set handle [csejtag_session create "writeMessage" [lindex $argv $serverflag_idx] [lindex $argv $serveraddress_idx] ]
|
||||
|
||||
# Scan the JTAG chain
|
||||
scanChain $handle
|
||||
|
||||
csejtag_session destroy $handle
|
||||
}
|
||||
|
||||
proc scanChain {handle} {
|
||||
global CABLE_NAME
|
||||
global CABLE_ARGS
|
||||
global CSE_MSG_ERROR
|
||||
global CSE_MSG_INFO
|
||||
global CSEJTAG_SCAN_DEFAULT
|
||||
global CSEJTAG_LOCKED_ME
|
||||
global CSEJTAG_TEST_LOGIC_RESET
|
||||
global CSEJTAG_SHIFT_READ
|
||||
global CSEJTAG_RUN_TEST_IDLE
|
||||
|
||||
# Open cable
|
||||
csejtag_target open $handle \
|
||||
$CABLE_NAME \
|
||||
0 \
|
||||
[lindex $CABLE_ARGS 0] \
|
||||
[lindex $CABLE_ARGS 1]
|
||||
|
||||
# CseJtag_session sendMessage will call the messageRouter
|
||||
# function specified in csejtag_session create
|
||||
csejtag_session send_message $handle $CSE_MSG_INFO "Open Cable successfully\n"
|
||||
|
||||
# Need to lock cable before actually accessing JTAG chain
|
||||
set cablelock [csejtag_target lock $handle 5000]
|
||||
if {$cablelock != $CSEJTAG_LOCKED_ME} {
|
||||
csejtag_session send_message $handle $CSE_MSG_ERROR "cse_lock_target failed"
|
||||
csejtag_target close $handle
|
||||
return
|
||||
}
|
||||
|
||||
csejtag_session send_message $handle $CSE_MSG_INFO "Obtained cable lock\n"
|
||||
|
||||
# Scan the JTAG chain, reading idcodes,
|
||||
# setting IR lengths for known devices in the CseJtag
|
||||
# data structures.
|
||||
# CseJtag needs to know in order to do JTAG shifts.
|
||||
csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT
|
||||
|
||||
# Get number of devices
|
||||
set deviceCount [csejtag_tap get_device_count $handle]
|
||||
|
||||
set str [format "Found %u devices\n" $deviceCount]
|
||||
csejtag_session send_message $handle $CSE_MSG_INFO $str
|
||||
|
||||
# Get a byte array of all idcodes by scanning the JTAG chain.
|
||||
csejtag_tap navigate $handle $CSEJTAG_TEST_LOGIC_RESET 0 0
|
||||
|
||||
set idcodeBuffer [csejtag_tap shift_chain_dr $handle\
|
||||
$CSEJTAG_SHIFT_READ \
|
||||
$CSEJTAG_RUN_TEST_IDLE \
|
||||
0 \
|
||||
[expr $deviceCount * 32] \
|
||||
0 \
|
||||
-hextdimask 0 \
|
||||
-hextdomask 0]
|
||||
|
||||
for {set deviceIndex 0} {$deviceIndex < $deviceCount} {incr deviceIndex} {
|
||||
scanDevice $handle $deviceIndex $deviceCount $idcodeBuffer
|
||||
}
|
||||
|
||||
csejtag_target unlock $handle
|
||||
csejtag_target close $handle
|
||||
csejtag_session send_message $handle $CSE_MSG_INFO "Closed cable successfully\n"
|
||||
}
|
||||
|
||||
# Note that this function (with the exception of the call to
|
||||
# scanUserReg() ) does not get any information
|
||||
# which requires a new scan of the device chain.
|
||||
# It is just lookup in the 'idcode.lst' file or
|
||||
# information which CseJtag data structures already has such as:
|
||||
# deviceCount and device idcodes.
|
||||
proc scanDevice {handle deviceIndex deviceCount idcodeBuffer} {
|
||||
global CSE_MSG_INFO
|
||||
|
||||
# position of buffer
|
||||
set startofidcodeBuf [expr $deviceIndex * 8 ]
|
||||
set idcodeBuf [string range $idcodeBuffer $startofidcodeBuf [expr $startofidcodeBuf + 7] ]
|
||||
|
||||
# Get idcode without scanning the JTAG chain
|
||||
set idcodeBuffer2 [csejtag_tap get_device_idcode $handle $deviceIndex]
|
||||
|
||||
# Convert idcodeFromBuffer and idcodeFromBuffer2 to unsigned integers
|
||||
set idcodeFromBuffer [expr "0x0$idcodeBuf"]
|
||||
|
||||
set idcode [expr [format "%u" [binaryStringToInt $idcodeBuffer2] ] ]
|
||||
|
||||
# Get IR length without scanning JTAG chain
|
||||
set irLength 0
|
||||
set irLength [csejtag_db get_irlength_for_idcode $handle $idcodeBuffer2]
|
||||
|
||||
# NOTE If (irLength == 0) an application program needs to set it,
|
||||
# ( using function csejtag_tap_set_irlength $handle $deviceIndex $irLength)
|
||||
# perhaps after asking the user or looking it up someway.
|
||||
# Without irLength known for all devices in the chain,
|
||||
# JTAG communication will fail.
|
||||
|
||||
# Get device name
|
||||
set deviceName [csejtag_db get_device_name_for_idcode $handle $idcodeBuffer2]
|
||||
|
||||
# print out device info
|
||||
set str [format "\nDEVICE %u, idcode:%x, Scanned idcode:%x, IRLength:%u, %s\n" \
|
||||
$deviceIndex $idcode $idcodeFromBuffer $irLength $deviceName]
|
||||
csejtag_session send_message $handle $CSE_MSG_INFO $str
|
||||
|
||||
# Compares the two methods of obtaining the idcode,
|
||||
# prints a message if they are different.
|
||||
|
||||
if {$idcode != $idcodeFromBuffer} {
|
||||
csejtag_session send_message $handle $CSE_MSG_INFO "IDCODES ARE NOT EQUAL!!!\n"
|
||||
}
|
||||
}
|
||||
|
||||
proc writeMessage {handle msgFlags msg} {
|
||||
global debug
|
||||
global CSE_MSG_ERROR
|
||||
global CSE_MSG_WARNING
|
||||
global CSE_MSG_STATUS
|
||||
global CSE_MSG_INFO
|
||||
global CSE_MSG_NOISE
|
||||
global CSE_MSG_DEBUG
|
||||
if {[expr $debug || ($msgFlags != $CSE_MSG_DEBUG)]} {
|
||||
if {$msgFlags == $CSE_MSG_ERROR} {
|
||||
puts -nonewline "Error:"
|
||||
} elseif {$msgFlags == $CSE_MSG_WARNING} {
|
||||
puts -nonewline "Warning:"
|
||||
} elseif {$msgFlags == $CSE_MSG_INFO} {
|
||||
puts -nonewline "Info:"
|
||||
} elseif {$msgFlags == $CSE_MSG_STATUS} {
|
||||
puts -nonewline "Status:"
|
||||
} elseif {$msgFlags == $CSE_MSG_DEBUG} {
|
||||
puts -nonewline "Debug:"
|
||||
}
|
||||
puts -nonewline $msg
|
||||
flush stdout
|
||||
}
|
||||
}
|
||||
|
||||
proc binaryStringToInt {binarystring} {
|
||||
set len [string length $binarystring]
|
||||
set retval 0
|
||||
for {set i 0} {$i < $len} {incr i} {
|
||||
set retval [expr $retval << 1]
|
||||
if {[string index $binarystring $i] == "1"} {
|
||||
set retval [expr $retval | 1]
|
||||
}
|
||||
}
|
||||
return $retval
|
||||
}
|
||||
|
||||
# Start the program
|
||||
main $argc $argv
|
||||
@@ -0,0 +1,379 @@
|
||||
; -------------------------------------------------
|
||||
; Constants
|
||||
; -------------------------------------------------
|
||||
lcd_read: equ 0x20
|
||||
lcd_data: equ 0x40
|
||||
lcd_enable: equ 0x80
|
||||
|
||||
DIV10: equ 0x0A
|
||||
|
||||
CR: equ 0x0D
|
||||
LF: equ 0x0A
|
||||
|
||||
LCD_CMD_Z1: equ 0x80
|
||||
LCD_CMD_Z2: equ 0xC0
|
||||
|
||||
; I/O
|
||||
btn_port: equ 0xC0 ; RO
|
||||
led_port: equ 0xC1 ; Write
|
||||
uart_data: equ 0xC2 ; Write
|
||||
lcd_port: equ 0xC3 ; R/W
|
||||
ctrl_reg: equ 0xC4 ; R/W
|
||||
dip_port: equ 0xC5 ; RO
|
||||
uart_status: equ 0xC6 ; Read
|
||||
|
||||
; -------------------------------------------------
|
||||
; Program
|
||||
; -------------------------------------------------
|
||||
reset: jmp init
|
||||
|
||||
org 0x001
|
||||
reti
|
||||
|
||||
; -------------------------------------------------
|
||||
; Main
|
||||
; -------------------------------------------------
|
||||
init: call LCD_init
|
||||
|
||||
; Print Hello world
|
||||
call LCD_clear
|
||||
; J
|
||||
mov R0, 0x4A
|
||||
call LCD_writechar
|
||||
call sout
|
||||
; -
|
||||
mov R0, 0x2D
|
||||
call LCD_writechar
|
||||
call sout
|
||||
; C
|
||||
mov R0, 0x43
|
||||
call LCD_writechar
|
||||
call sout
|
||||
; P
|
||||
mov R0, 0x50
|
||||
call LCD_writechar
|
||||
call sout
|
||||
; U
|
||||
mov R0, 0x55
|
||||
call LCD_writechar
|
||||
call sout
|
||||
;
|
||||
mov R0, 0x20
|
||||
call LCD_writechar
|
||||
call sout
|
||||
; V
|
||||
mov R0, 0x56
|
||||
call LCD_writechar
|
||||
call sout
|
||||
; 1
|
||||
mov R0, 0x31
|
||||
call LCD_writechar
|
||||
call sout
|
||||
; .
|
||||
mov R0, 0x2E
|
||||
call LCD_writechar
|
||||
call sout
|
||||
; 0
|
||||
mov R0, 0x30
|
||||
call LCD_writechar
|
||||
call sout
|
||||
|
||||
; CRLF
|
||||
mov R0, LCD_CMD_Z2
|
||||
call LCD_writecmd
|
||||
mov R0, CR
|
||||
call sout
|
||||
mov R0, LF
|
||||
call sout
|
||||
|
||||
; R
|
||||
mov R0, 0x52
|
||||
call LCD_writechar
|
||||
call sout
|
||||
; E
|
||||
mov R0, 0x65
|
||||
call LCD_writechar
|
||||
call sout
|
||||
; A
|
||||
mov R0, 0x61
|
||||
call LCD_writechar
|
||||
call sout
|
||||
; D
|
||||
mov R0, 0x64
|
||||
call LCD_writechar
|
||||
call sout
|
||||
; Y
|
||||
mov R0, 0x79
|
||||
call LCD_writechar
|
||||
call sout
|
||||
|
||||
; CRLF
|
||||
mov R0, CR
|
||||
call sout
|
||||
mov R0, LF
|
||||
call sout
|
||||
|
||||
jjj: jmp jjj
|
||||
|
||||
; -------------------------------------------------
|
||||
; sout
|
||||
; -------------------------------------------------
|
||||
; R0 = input
|
||||
sout: push R1
|
||||
sout1: movx R1, (uart_status)
|
||||
and R1, 0x02
|
||||
jnz sout1
|
||||
movx (uart_data), R0
|
||||
pop R1
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; sin
|
||||
; -------------------------------------------------
|
||||
; R0 = output
|
||||
sin: push R1
|
||||
sin1: movx R1, (uart_status)
|
||||
and R1, 0x10
|
||||
jnz sin1
|
||||
movx R0, (uart_data)
|
||||
pop R1
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; Init LCD
|
||||
; -------------------------------------------------
|
||||
LCD_init: mov R1, lcd_port
|
||||
movx (R1), lcd_read
|
||||
|
||||
call delay10ms
|
||||
|
||||
; 0.
|
||||
mov R2, 0x00
|
||||
mov R0, 0x03
|
||||
call LCD_write_
|
||||
call delay10ms
|
||||
mov R2, 0x00
|
||||
mov R0, 0x03
|
||||
call LCD_write_
|
||||
call delay10ms
|
||||
|
||||
mov R2, 0x00
|
||||
mov R0, 0x02
|
||||
call LCD_write_
|
||||
call delay1ms
|
||||
|
||||
; 1.
|
||||
mov R0, 0x28
|
||||
call LCD_writecmd
|
||||
|
||||
; 2.
|
||||
mov R0, 0x0E
|
||||
call LCD_writecmd
|
||||
|
||||
; 3.
|
||||
mov R0, 0x06
|
||||
call LCD_writecmd
|
||||
|
||||
; 3.
|
||||
mov R0, 0x01
|
||||
call LCD_writecmd
|
||||
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; LCD_Clear
|
||||
; -------------------------------------------------
|
||||
LCD_clear: push R0
|
||||
mov R0, 0x01
|
||||
call LCD_writecmd
|
||||
pop R0
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; LCD_writecmd
|
||||
; -------------------------------------------------
|
||||
; R0 = cmd
|
||||
LCD_writecmd: call LCD_waitbsy
|
||||
push R2
|
||||
push R0
|
||||
push R0
|
||||
mov R2, 0x00
|
||||
shr R0
|
||||
shr R0
|
||||
shr R0
|
||||
shr R0
|
||||
call LCD_write_
|
||||
pop R0
|
||||
and R0, 0x0F
|
||||
call LCD_write_
|
||||
pop R0
|
||||
pop R2
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; LCD_writechar
|
||||
; -------------------------------------------------
|
||||
; R0 = char
|
||||
LCD_writechar: call LCD_waitbsy
|
||||
push R2
|
||||
push R0
|
||||
push R0
|
||||
mov R2, lcd_data
|
||||
shr R0
|
||||
shr R0
|
||||
shr R0
|
||||
shr R0
|
||||
call LCD_write_
|
||||
pop R0
|
||||
and R0, 0x0F
|
||||
call LCD_write_
|
||||
pop R0
|
||||
pop R2
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; LCD_write_
|
||||
; -------------------------------------------------
|
||||
; R0 = input
|
||||
LCD_write_: push R1
|
||||
|
||||
mov R1, R0
|
||||
or R1, R2
|
||||
movx (lcd_port), R1
|
||||
call delay1us
|
||||
|
||||
mov R1, R0
|
||||
or R1, R2
|
||||
or R1, lcd_enable
|
||||
movx (lcd_port), R1
|
||||
call delay1us
|
||||
|
||||
mov R1, R0
|
||||
or R1, R2
|
||||
movx (lcd_port), R1
|
||||
call delay1us
|
||||
|
||||
pop R1
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; LCD_read_
|
||||
; -------------------------------------------------
|
||||
; R0 = output
|
||||
LCD_read_: push R1
|
||||
|
||||
mov R1, lcd_read
|
||||
or R1, R2
|
||||
movx (lcd_port), R1
|
||||
call delay1us
|
||||
|
||||
mov R1, lcd_read
|
||||
or R1, R2
|
||||
or R1, lcd_enable
|
||||
movx (lcd_port), R1
|
||||
call delay1us
|
||||
movx R0, (lcd_port)
|
||||
|
||||
mov R1, lcd_read
|
||||
or R1, R2
|
||||
movx (lcd_port), R1
|
||||
call delay1us
|
||||
|
||||
pop R1
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; LCD_readstat
|
||||
; -------------------------------------------------
|
||||
; R0 = status
|
||||
LCD_readstat: push R2
|
||||
mov R2, 0x00
|
||||
call LCD_read_
|
||||
shl R0
|
||||
shl R0
|
||||
shl R0
|
||||
shl R0
|
||||
push R0
|
||||
call LCD_read_
|
||||
and R0, 0x0F
|
||||
pop R2
|
||||
or R0, R2
|
||||
pop R2
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; LCD_waitbsy
|
||||
; -------------------------------------------------
|
||||
LCD_waitbsy: push R0
|
||||
bsy_loop: call LCD_readstat
|
||||
and R0, 0x80
|
||||
jz ex_bsy
|
||||
call delay1us
|
||||
jmp bsy_loop
|
||||
ex_bsy: pop R0
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; Delays
|
||||
; -------------------------------------------------
|
||||
delay1s: push R15
|
||||
mov R15, DIV10
|
||||
loop1s: call delay100ms
|
||||
dec R15
|
||||
jnz loop1s
|
||||
pop R15
|
||||
ret
|
||||
|
||||
delay100ms: push R15
|
||||
mov R15, DIV10
|
||||
loop100ms: call delay10ms
|
||||
dec R15
|
||||
jnz loop100ms
|
||||
pop R15
|
||||
ret
|
||||
|
||||
delay10ms: push R15
|
||||
mov R15, DIV10
|
||||
loop10ms: call delay1ms
|
||||
dec R15
|
||||
jnz loop10ms
|
||||
pop R15
|
||||
ret
|
||||
|
||||
delay1ms: push R15
|
||||
mov R15, DIV10
|
||||
loop1ms: call delay100us
|
||||
dec R15
|
||||
jnz loop1ms
|
||||
pop R15
|
||||
ret
|
||||
|
||||
delay100us: push R15
|
||||
mov R15, DIV10
|
||||
loop100us: call delay10us
|
||||
dec R15
|
||||
jnz loop100us
|
||||
pop R15
|
||||
ret
|
||||
|
||||
delay10us: push R15
|
||||
mov R15, DIV10
|
||||
loop10us: call delay1us
|
||||
dec R15
|
||||
jnz loop10us
|
||||
pop R15
|
||||
ret
|
||||
|
||||
delay1us: push R15
|
||||
mov R15, DIV10
|
||||
loop1us: call delay100ns
|
||||
dec R15
|
||||
jnz loop1us
|
||||
pop R15
|
||||
ret
|
||||
|
||||
delay100ns: nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
ret
|
||||
@@ -0,0 +1,797 @@
|
||||
# ----------------------------------------------------------------------
|
||||
# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
# This file: The ROM file for upload to target over JTAG
|
||||
|
||||
# Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
# This library is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU Lesser General Public
|
||||
# License as published by the Free Software Foundation; either
|
||||
# version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
# This library is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
# Lesser General Public License for more details.
|
||||
|
||||
# You should have received a copy of the GNU Lesser General Public
|
||||
# License along with this library; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
# For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
# ---------------------------------------------------------------------
|
||||
|
||||
# ---------------------------------------------------------------------
|
||||
# For Chipscope 9.1
|
||||
# ---------------------------------------------------------------------
|
||||
# Source JTAG/TCL frame work
|
||||
cd $env(CHIPSCOPE)\\bin\\nt
|
||||
source csejtag.tcl
|
||||
|
||||
namespace import ::chipscope::*
|
||||
|
||||
# Platform USB Cable
|
||||
set PLATFORM_USB_CABLE_ARGS [list "port=USB2" \
|
||||
"frequency=1500000"]
|
||||
# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
|
||||
|
||||
# Create session
|
||||
set handle [::chipscope::csejtag_session create 0]
|
||||
|
||||
# Open JTAG and lock
|
||||
set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
|
||||
set lock_result [::chipscope::csejtag_target lock $handle 1000]
|
||||
|
||||
set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
|
||||
|
||||
# Get Device ID
|
||||
set devtype "Virtex-4SX"
|
||||
set devid 2
|
||||
set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
|
||||
set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
|
||||
|
||||
# ---------------------------------------------------------------
|
||||
# Shift the USER1 Instruction (b1111000010) into the Instruction Register of FPGA
|
||||
# User 1
|
||||
set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 $irlength "3C2"]
|
||||
|
||||
# Write Program
|
||||
# JASM_ROM_INSERT_HERE
|
||||
# 0x000: JMP 0x002
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "00030002"
|
||||
|
||||
# 0x001: RETI
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0007F000"
|
||||
|
||||
# 0x002: CALL 0x04A
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "000BB04A"
|
||||
|
||||
# 0x003: CALL 0x062
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "000FB062"
|
||||
|
||||
# 0x004: MOV R00, 0x4A
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "001034A0"
|
||||
|
||||
# 0x005: CALL 0x077
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0017B077"
|
||||
|
||||
# 0x006: CALL 0x03C
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "001BB03C"
|
||||
|
||||
# 0x007: MOV R00, 0x2D
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "001C32D0"
|
||||
|
||||
# 0x008: CALL 0x077
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0023B077"
|
||||
|
||||
# 0x009: CALL 0x03C
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0027B03C"
|
||||
|
||||
# 0x00A: MOV R00, 0x43
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "00283430"
|
||||
|
||||
# 0x00B: CALL 0x077
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "002FB077"
|
||||
|
||||
# 0x00C: CALL 0x03C
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0033B03C"
|
||||
|
||||
# 0x00D: MOV R00, 0x50
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "00343500"
|
||||
|
||||
# 0x00E: CALL 0x077
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "003BB077"
|
||||
|
||||
# 0x00F: CALL 0x03C
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "003FB03C"
|
||||
|
||||
# 0x010: MOV R00, 0x55
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "00403550"
|
||||
|
||||
# 0x011: CALL 0x077
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0047B077"
|
||||
|
||||
# 0x012: CALL 0x03C
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "004BB03C"
|
||||
|
||||
# 0x013: MOV R00, 0x20
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "004C3200"
|
||||
|
||||
# 0x014: CALL 0x077
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0053B077"
|
||||
|
||||
# 0x015: CALL 0x03C
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0057B03C"
|
||||
|
||||
# 0x016: MOV R00, 0x56
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "00583560"
|
||||
|
||||
# 0x017: CALL 0x077
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "005FB077"
|
||||
|
||||
# 0x018: CALL 0x03C
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0063B03C"
|
||||
|
||||
# 0x019: MOV R00, 0x31
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "00643310"
|
||||
|
||||
# 0x01A: CALL 0x077
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "006BB077"
|
||||
|
||||
# 0x01B: CALL 0x03C
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "006FB03C"
|
||||
|
||||
# 0x01C: MOV R00, 0x2E
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "007032E0"
|
||||
|
||||
# 0x01D: CALL 0x077
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0077B077"
|
||||
|
||||
# 0x01E: CALL 0x03C
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "007BB03C"
|
||||
|
||||
# 0x01F: MOV R00, 0x30
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "007C3300"
|
||||
|
||||
# 0x020: CALL 0x077
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0083B077"
|
||||
|
||||
# 0x021: CALL 0x03C
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0087B03C"
|
||||
|
||||
# 0x022: MOV R00, 0xC0
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "00883C00"
|
||||
|
||||
# 0x023: CALL 0x067
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "008FB067"
|
||||
|
||||
# 0x024: MOV R00, 0x0D
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "009030D0"
|
||||
|
||||
# 0x025: CALL 0x03C
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0097B03C"
|
||||
|
||||
# 0x026: MOV R00, 0x0A
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "009830A0"
|
||||
|
||||
# 0x027: CALL 0x03C
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "009FB03C"
|
||||
|
||||
# 0x028: MOV R00, 0x52
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "00A03520"
|
||||
|
||||
# 0x029: CALL 0x077
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "00A7B077"
|
||||
|
||||
# 0x02A: CALL 0x03C
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "00ABB03C"
|
||||
|
||||
# 0x02B: MOV R00, 0x65
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "00AC3650"
|
||||
|
||||
# 0x02C: CALL 0x077
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "00B3B077"
|
||||
|
||||
# 0x02D: CALL 0x03C
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "00B7B03C"
|
||||
|
||||
# 0x02E: MOV R00, 0x61
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "00B83610"
|
||||
|
||||
# 0x02F: CALL 0x077
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "00BFB077"
|
||||
|
||||
# 0x030: CALL 0x03C
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "00C3B03C"
|
||||
|
||||
# 0x031: MOV R00, 0x64
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "00C43640"
|
||||
|
||||
# 0x032: CALL 0x077
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "00CBB077"
|
||||
|
||||
# 0x033: CALL 0x03C
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "00CFB03C"
|
||||
|
||||
# 0x034: MOV R00, 0x79
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "00D03790"
|
||||
|
||||
# 0x035: CALL 0x077
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "00D7B077"
|
||||
|
||||
# 0x036: CALL 0x03C
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "00DBB03C"
|
||||
|
||||
# 0x037: MOV R00, 0x0D
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "00DC30D0"
|
||||
|
||||
# 0x038: CALL 0x03C
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "00E3B03C"
|
||||
|
||||
# 0x039: MOV R00, 0x0A
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "00E430A0"
|
||||
|
||||
# 0x03A: CALL 0x03C
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "00EBB03C"
|
||||
|
||||
# 0x03B: JMP 0x03B
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "00EF003B"
|
||||
|
||||
# 0x03C: PUSH R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "00F3C001"
|
||||
|
||||
# 0x03D: MOVX R01, (0xC6)
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "00F45C61"
|
||||
|
||||
# 0x03E: AND R01, 0x02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "00F99021"
|
||||
|
||||
# 0x03F: JNZ 0x03D
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "00FF203D"
|
||||
|
||||
# 0x040: MOVX (0xC2), R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "01008C20"
|
||||
|
||||
# 0x041: POP R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0107D001"
|
||||
|
||||
# 0x042: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "010BE000"
|
||||
|
||||
# 0x043: PUSH R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "010FC001"
|
||||
|
||||
# 0x044: MOVX R01, (0xC6)
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "01105C61"
|
||||
|
||||
# 0x045: AND R01, 0x10
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "01159101"
|
||||
|
||||
# 0x046: JNZ 0x044
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "011B2044"
|
||||
|
||||
# 0x047: MOVX R00, (0xC2)
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "011C5C20"
|
||||
|
||||
# 0x048: POP R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0123D001"
|
||||
|
||||
# 0x049: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0127E000"
|
||||
|
||||
# 0x04A: MOV R01, 0xC3
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "01283C31"
|
||||
|
||||
# 0x04B: MOVX (R01), 0x20
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "012C7201"
|
||||
|
||||
# 0x04C: CALL 0x0CC
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0133B0CC"
|
||||
|
||||
# 0x04D: MOV R02, 0x00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "01343002"
|
||||
|
||||
# 0x04E: MOV R00, 0x03
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "01383030"
|
||||
|
||||
# 0x04F: CALL 0x087
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "013FB087"
|
||||
|
||||
# 0x050: CALL 0x0CC
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0143B0CC"
|
||||
|
||||
# 0x051: MOV R02, 0x00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "01443002"
|
||||
|
||||
# 0x052: MOV R00, 0x03
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "01483030"
|
||||
|
||||
# 0x053: CALL 0x087
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "014FB087"
|
||||
|
||||
# 0x054: CALL 0x0CC
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0153B0CC"
|
||||
|
||||
# 0x055: MOV R02, 0x00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "01543002"
|
||||
|
||||
# 0x056: MOV R00, 0x02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "01583020"
|
||||
|
||||
# 0x057: CALL 0x087
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "015FB087"
|
||||
|
||||
# 0x058: CALL 0x0D3
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0163B0D3"
|
||||
|
||||
# 0x059: MOV R00, 0x28
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "01643280"
|
||||
|
||||
# 0x05A: CALL 0x067
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "016BB067"
|
||||
|
||||
# 0x05B: MOV R00, 0x0E
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "016C30E0"
|
||||
|
||||
# 0x05C: CALL 0x067
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0173B067"
|
||||
|
||||
# 0x05D: MOV R00, 0x06
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "01743060"
|
||||
|
||||
# 0x05E: CALL 0x067
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "017BB067"
|
||||
|
||||
# 0x05F: MOV R00, 0x01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "017C3010"
|
||||
|
||||
# 0x060: CALL 0x067
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0183B067"
|
||||
|
||||
# 0x061: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0187E000"
|
||||
|
||||
# 0x062: PUSH R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "018BC000"
|
||||
|
||||
# 0x063: MOV R00, 0x01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "018C3010"
|
||||
|
||||
# 0x064: CALL 0x067
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0193B067"
|
||||
|
||||
# 0x065: POP R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0197D000"
|
||||
|
||||
# 0x066: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "019BE000"
|
||||
|
||||
# 0x067: CALL 0x0B6
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "019FB0B6"
|
||||
|
||||
# 0x068: PUSH R02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "01A3C002"
|
||||
|
||||
# 0x069: PUSH R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "01A7C000"
|
||||
|
||||
# 0x06A: PUSH R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "01ABC000"
|
||||
|
||||
# 0x06B: MOV R02, 0x00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "01AC3002"
|
||||
|
||||
# 0x06C: SHR R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "01B1F000"
|
||||
|
||||
# 0x06D: SHR R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "01B5F000"
|
||||
|
||||
# 0x06E: SHR R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "01B9F000"
|
||||
|
||||
# 0x06F: SHR R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "01BDF000"
|
||||
|
||||
# 0x070: CALL 0x087
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "01C3B087"
|
||||
|
||||
# 0x071: POP R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "01C7D000"
|
||||
|
||||
# 0x072: AND R00, 0x0F
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "01C990F0"
|
||||
|
||||
# 0x073: CALL 0x087
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "01CFB087"
|
||||
|
||||
# 0x074: POP R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "01D3D000"
|
||||
|
||||
# 0x075: POP R02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "01D7D002"
|
||||
|
||||
# 0x076: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "01DBE000"
|
||||
|
||||
# 0x077: CALL 0x0B6
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "01DFB0B6"
|
||||
|
||||
# 0x078: PUSH R02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "01E3C002"
|
||||
|
||||
# 0x079: PUSH R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "01E7C000"
|
||||
|
||||
# 0x07A: PUSH R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "01EBC000"
|
||||
|
||||
# 0x07B: MOV R02, 0x40
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "01EC3402"
|
||||
|
||||
# 0x07C: SHR R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "01F1F000"
|
||||
|
||||
# 0x07D: SHR R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "01F5F000"
|
||||
|
||||
# 0x07E: SHR R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "01F9F000"
|
||||
|
||||
# 0x07F: SHR R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "01FDF000"
|
||||
|
||||
# 0x080: CALL 0x087
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0203B087"
|
||||
|
||||
# 0x081: POP R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0207D000"
|
||||
|
||||
# 0x082: AND R00, 0x0F
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "020990F0"
|
||||
|
||||
# 0x083: CALL 0x087
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "020FB087"
|
||||
|
||||
# 0x084: POP R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0213D000"
|
||||
|
||||
# 0x085: POP R02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0217D002"
|
||||
|
||||
# 0x086: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "021BE000"
|
||||
|
||||
# 0x087: PUSH R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "021FC001"
|
||||
|
||||
# 0x088: MOV R01, R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "02202001"
|
||||
|
||||
# 0x089: OR R01, R02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0225A021"
|
||||
|
||||
# 0x08A: MOVX (0xC3), R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "02288C31"
|
||||
|
||||
# 0x08B: CALL 0x0E8
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "022FB0E8"
|
||||
|
||||
# 0x08C: MOV R01, R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "02302001"
|
||||
|
||||
# 0x08D: OR R01, R02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0235A021"
|
||||
|
||||
# 0x08E: OR R01, 0x80
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0239B801"
|
||||
|
||||
# 0x08F: MOVX (0xC3), R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "023C8C31"
|
||||
|
||||
# 0x090: CALL 0x0E8
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0243B0E8"
|
||||
|
||||
# 0x091: MOV R01, R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "02442001"
|
||||
|
||||
# 0x092: OR R01, R02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0249A021"
|
||||
|
||||
# 0x093: MOVX (0xC3), R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "024C8C31"
|
||||
|
||||
# 0x094: CALL 0x0E8
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0253B0E8"
|
||||
|
||||
# 0x095: POP R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0257D001"
|
||||
|
||||
# 0x096: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "025BE000"
|
||||
|
||||
# 0x097: PUSH R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "025FC001"
|
||||
|
||||
# 0x098: MOV R01, 0x20
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "02603201"
|
||||
|
||||
# 0x099: OR R01, R02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0265A021"
|
||||
|
||||
# 0x09A: MOVX (0xC3), R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "02688C31"
|
||||
|
||||
# 0x09B: CALL 0x0E8
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "026FB0E8"
|
||||
|
||||
# 0x09C: MOV R01, 0x20
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "02703201"
|
||||
|
||||
# 0x09D: OR R01, R02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0275A021"
|
||||
|
||||
# 0x09E: OR R01, 0x80
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0279B801"
|
||||
|
||||
# 0x09F: MOVX (0xC3), R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "027C8C31"
|
||||
|
||||
# 0x0A0: CALL 0x0E8
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0283B0E8"
|
||||
|
||||
# 0x0A1: MOVX R00, (0xC3)
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "02845C30"
|
||||
|
||||
# 0x0A2: MOV R01, 0x20
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "02883201"
|
||||
|
||||
# 0x0A3: OR R01, R02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "028DA021"
|
||||
|
||||
# 0x0A4: MOVX (0xC3), R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "02908C31"
|
||||
|
||||
# 0x0A5: CALL 0x0E8
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0297B0E8"
|
||||
|
||||
# 0x0A6: POP R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "029BD001"
|
||||
|
||||
# 0x0A7: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "029FE000"
|
||||
|
||||
# 0x0A8: PUSH R02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "02A3C002"
|
||||
|
||||
# 0x0A9: MOV R02, 0x00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "02A43002"
|
||||
|
||||
# 0x0AA: CALL 0x097
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "02ABB097"
|
||||
|
||||
# 0x0AB: SHL R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "02ADE000"
|
||||
|
||||
# 0x0AC: SHL R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "02B1E000"
|
||||
|
||||
# 0x0AD: SHL R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "02B5E000"
|
||||
|
||||
# 0x0AE: SHL R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "02B9E000"
|
||||
|
||||
# 0x0AF: PUSH R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "02BFC000"
|
||||
|
||||
# 0x0B0: CALL 0x097
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "02C3B097"
|
||||
|
||||
# 0x0B1: AND R00, 0x0F
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "02C590F0"
|
||||
|
||||
# 0x0B2: POP R02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "02CBD002"
|
||||
|
||||
# 0x0B3: OR R00, R02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "02CDA020"
|
||||
|
||||
# 0x0B4: POP R02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "02D3D002"
|
||||
|
||||
# 0x0B5: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "02D7E000"
|
||||
|
||||
# 0x0B6: PUSH R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "02DBC000"
|
||||
|
||||
# 0x0B7: CALL 0x0A8
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "02DFB0A8"
|
||||
|
||||
# 0x0B8: AND R00, 0x80
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "02E19800"
|
||||
|
||||
# 0x0B9: JZ 0x0BC
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "02E710BC"
|
||||
|
||||
# 0x0BA: CALL 0x0E8
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "02EBB0E8"
|
||||
|
||||
# 0x0BB: JMP 0x0B7
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "02EF00B7"
|
||||
|
||||
# 0x0BC: POP R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "02F3D000"
|
||||
|
||||
# 0x0BD: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "02F7E000"
|
||||
|
||||
# 0x0BE: PUSH R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "02FBC00F"
|
||||
|
||||
# 0x0BF: MOV R15, 0x0A
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "02FC30AF"
|
||||
|
||||
# 0x0C0: CALL 0x0C5
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0303B0C5"
|
||||
|
||||
# 0x0C1: DEC R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0305501F"
|
||||
|
||||
# 0x0C2: JNZ 0x0C0
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "030B20C0"
|
||||
|
||||
# 0x0C3: POP R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "030FD00F"
|
||||
|
||||
# 0x0C4: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0313E000"
|
||||
|
||||
# 0x0C5: PUSH R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0317C00F"
|
||||
|
||||
# 0x0C6: MOV R15, 0x0A
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "031830AF"
|
||||
|
||||
# 0x0C7: CALL 0x0CC
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "031FB0CC"
|
||||
|
||||
# 0x0C8: DEC R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0321501F"
|
||||
|
||||
# 0x0C9: JNZ 0x0C7
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "032720C7"
|
||||
|
||||
# 0x0CA: POP R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "032BD00F"
|
||||
|
||||
# 0x0CB: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "032FE000"
|
||||
|
||||
# 0x0CC: PUSH R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0333C00F"
|
||||
|
||||
# 0x0CD: MOV R15, 0x0A
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "033430AF"
|
||||
|
||||
# 0x0CE: CALL 0x0D3
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "033BB0D3"
|
||||
|
||||
# 0x0CF: DEC R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "033D501F"
|
||||
|
||||
# 0x0D0: JNZ 0x0CE
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "034320CE"
|
||||
|
||||
# 0x0D1: POP R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0347D00F"
|
||||
|
||||
# 0x0D2: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "034BE000"
|
||||
|
||||
# 0x0D3: PUSH R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "034FC00F"
|
||||
|
||||
# 0x0D4: MOV R15, 0x0A
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "035030AF"
|
||||
|
||||
# 0x0D5: CALL 0x0DA
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0357B0DA"
|
||||
|
||||
# 0x0D6: DEC R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0359501F"
|
||||
|
||||
# 0x0D7: JNZ 0x0D5
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "035F20D5"
|
||||
|
||||
# 0x0D8: POP R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0363D00F"
|
||||
|
||||
# 0x0D9: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0367E000"
|
||||
|
||||
# 0x0DA: PUSH R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "036BC00F"
|
||||
|
||||
# 0x0DB: MOV R15, 0x0A
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "036C30AF"
|
||||
|
||||
# 0x0DC: CALL 0x0E1
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0373B0E1"
|
||||
|
||||
# 0x0DD: DEC R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0375501F"
|
||||
|
||||
# 0x0DE: JNZ 0x0DC
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "037B20DC"
|
||||
|
||||
# 0x0DF: POP R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "037FD00F"
|
||||
|
||||
# 0x0E0: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0383E000"
|
||||
|
||||
# 0x0E1: PUSH R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0387C00F"
|
||||
|
||||
# 0x0E2: MOV R15, 0x0A
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "038830AF"
|
||||
|
||||
# 0x0E3: CALL 0x0E8
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "038FB0E8"
|
||||
|
||||
# 0x0E4: DEC R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "0391501F"
|
||||
|
||||
# 0x0E5: JNZ 0x0E3
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "039720E3"
|
||||
|
||||
# 0x0E6: POP R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "039BD00F"
|
||||
|
||||
# 0x0E7: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "039FE000"
|
||||
|
||||
# 0x0E8: PUSH R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "03A3C00F"
|
||||
|
||||
# 0x0E9: MOV R15, 0x0A
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "03A430AF"
|
||||
|
||||
# 0x0EA: CALL 0x0EF
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "03ABB0EF"
|
||||
|
||||
# 0x0EB: DEC R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "03AD501F"
|
||||
|
||||
# 0x0EC: JNZ 0x0EA
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "03B320EA"
|
||||
|
||||
# 0x0ED: POP R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "03B7D00F"
|
||||
|
||||
# 0x0EE: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "03BBE000"
|
||||
|
||||
# 0x0EF: NOP
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "03BC0000"
|
||||
|
||||
# 0x0F0: NOP
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "03C00000"
|
||||
|
||||
# 0x0F1: NOP
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "03C40000"
|
||||
|
||||
# 0x0F2: NOP
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "03C80000"
|
||||
|
||||
# 0x0F3: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 28 "03CFE000"
|
||||
|
||||
|
||||
::chipscope::csejtag_target unlock $handle
|
||||
::chipscope::csejtag_target close $handle
|
||||
::chipscope::csejtag_session destroy $handle
|
||||
exit
|
||||
@@ -0,0 +1,51 @@
|
||||
#!/bin/sh
|
||||
|
||||
# ----------------------------------------------------------------------
|
||||
# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
# This file: rom-file generation for cpu_core
|
||||
|
||||
# Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
# This library is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU Lesser General Public
|
||||
# License as published by the Free Software Foundation; either
|
||||
# version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
# This library is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
# Lesser General Public License for more details.
|
||||
|
||||
# You should have received a copy of the GNU Lesser General Public
|
||||
# License along with this library; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
# For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
# ---------------------------------------------------------------------
|
||||
|
||||
TARGET=$2
|
||||
DSTDIR=$1
|
||||
|
||||
JASM_HOME=/cygdrive/w/vhdl/lib/CPUs/JCpu/tools
|
||||
|
||||
$JASM_HOME/jasm.rb $TARGET.jsm
|
||||
|
||||
irom_tcl_snippet="$TARGET.irom.tcl.snip"
|
||||
irom_vhdl_snippet="$TARGET.irom.vhdl.snip"
|
||||
irom_ld_vhdl_snippet="$TARGET.irom_ld.vhdl.snip"
|
||||
xrom_tcl_snippet="$TARGET.xrom.tcl.snip"
|
||||
xrom_vhdl_snippet="$TARGET.xrom.vhdl.snip"
|
||||
xrom_ld_vhdl_snippet="$TARGET.xrom_ld.vhdl.snip"
|
||||
|
||||
$JASM_HOME/insrom.rb $irom_vhdl_snippet $JASM_HOME/irom.vhd.tpl >$DSTDIR/$TARGET\_irom.vhdl
|
||||
$JASM_HOME/insrom.rb $irom_ld_vhdl_snippet $JASM_HOME/irom_ld.vhd.tpl >$DSTDIR/$TARGET\_irom_ld.vhdl
|
||||
|
||||
$JASM_HOME/insrom.rb $xrom_vhdl_snippet $JASM_HOME/xrom.vhd.tpl >$DSTDIR/$TARGET\_xrom.vhdl
|
||||
$JASM_HOME/insrom.rb $xrom_ld_vhdl_snippet $JASM_HOME/xrom_ld.vhd.tpl >$DSTDIR/$TARGET\_xrom_ld.vhdl
|
||||
|
||||
cat $irom_tcl_snippet > $TARGET.tcl.snip.snip
|
||||
cat $xrom_tcl_snippet >> $TARGET.tcl.snip.snip
|
||||
$JASM_HOME/insrom.rb $TARGET.tcl.snip.snip $JASM_HOME/rom.tcl.tpl >$TARGET.tcl
|
||||
|
||||
rm -f *.snip
|
||||
@@ -0,0 +1,773 @@
|
||||
; -------------------------------------------------
|
||||
; Register definitions
|
||||
; -------------------------------------------------
|
||||
include "../../../lib/jasm/cregs.inc.jsm"
|
||||
include "xregs.inc.jsm"
|
||||
|
||||
; -------------------------------------------------
|
||||
; Constants
|
||||
; -------------------------------------------------
|
||||
BURST_LEN: equ 8
|
||||
SD_CMD_WRITE: equ 0x06
|
||||
SD_CMD_READ: equ 0x05
|
||||
START_ADDR0: equ 0x00
|
||||
START_ADDR1: equ 0x00
|
||||
START_ADDR2: equ 0x20
|
||||
END_ADDR0: equ 0xF8
|
||||
END_ADDR1: equ 0xFF
|
||||
END_ADDR2: equ 0xFF
|
||||
PEN_TIMEOUT0: equ 0xE8
|
||||
PEN_TIMEOUT1: equ 0x03
|
||||
PEN_BUFSIZE: equ 64
|
||||
|
||||
; External RAM/ROM
|
||||
xmem
|
||||
crlf: dc 13, 10, 0
|
||||
greet_txt: dc "SDRAM Test", 0
|
||||
msg_txt0: dc "Clearing SDRAM", 0
|
||||
msg_txt1: dc "Writing SDRAM", 0
|
||||
msg_txt2: dc "Reading SDRAM", 0
|
||||
msg_txt3: dc "Reading Bitmap", 0
|
||||
verify_ok: dc "Verify OK", 0
|
||||
verify_nok: dc "Failed at ", 0
|
||||
dot: dc ".", 0
|
||||
|
||||
org 0x80
|
||||
sdram_data: db 8 ; SDRAM data window at X:0x80
|
||||
|
||||
; Internal RAM
|
||||
cmem 0
|
||||
block_cnt: db 1
|
||||
round_cnt: db 1
|
||||
bmp_offset: db 4
|
||||
pixel_buf: db 32
|
||||
|
||||
pen_rx_buf: db 128
|
||||
pen_rx_ptr_r: db 1
|
||||
pen_rx_ptr_w: db 1
|
||||
pen_timeout: db 2
|
||||
pen_bit_cnt_w: db 1
|
||||
pen_octet_w: db 1
|
||||
pen_octet_r: db 1
|
||||
pen_last_state: db 1
|
||||
pen_enable: db 1
|
||||
pen_bit_cnt_r: db 1
|
||||
|
||||
; -------------------------------------------------
|
||||
; Program
|
||||
; -------------------------------------------------
|
||||
code
|
||||
reset: org 0x000
|
||||
jmp main
|
||||
|
||||
; -------------------------------------------------
|
||||
; ISR
|
||||
; -------------------------------------------------
|
||||
org 0x001
|
||||
pen_isr: push R0
|
||||
push R1
|
||||
push R2
|
||||
|
||||
u_get_nxt: xin R1, (btn_port)
|
||||
movc R0, (pen_octet_w)
|
||||
and R1, 0x20
|
||||
shl R1
|
||||
shl R1
|
||||
shl R1
|
||||
rolc R0
|
||||
movc (pen_octet_w), R0
|
||||
movc R1, (pen_bit_cnt_w)
|
||||
inc R1
|
||||
movc (pen_bit_cnt_w), R1
|
||||
cmp R1, 8
|
||||
jne ex_uart_isr
|
||||
mov R1, 0
|
||||
movc (pen_bit_cnt_w), R1
|
||||
movc R2, (pen_rx_ptr_w)
|
||||
movc (R2), R0
|
||||
inc R2
|
||||
cmp R2, pen_rx_buf+128
|
||||
jne u_upd_nxt
|
||||
mov R2, pen_rx_buf
|
||||
u_upd_nxt: movc (pen_rx_ptr_w), R2
|
||||
ex_uart_isr: call Timer_isr
|
||||
pop R2
|
||||
pop R1
|
||||
pop R0
|
||||
reti
|
||||
|
||||
Timer_isr: xin R0, (btn_port)
|
||||
and R0, 0x20
|
||||
shr R0
|
||||
xin R1, (ctrl_reg)
|
||||
and R1, 0xEF
|
||||
or R0, R1
|
||||
xout (ctrl_reg), R0
|
||||
xin R0, (btn_port)
|
||||
and R0, 0x01
|
||||
jz btn_chk2
|
||||
mov R0, vga_read_addr
|
||||
xout (R0), 0x00
|
||||
inc R0
|
||||
xout (R0), 0x00
|
||||
inc R0
|
||||
xout (R0), 0x00
|
||||
jmp ex_t_isr
|
||||
btn_chk2: xin R0, (btn_port)
|
||||
and R0, 0x02
|
||||
jz ex_t_isr
|
||||
mov R0, vga_read_addr
|
||||
xout (R0), 0x00
|
||||
inc R0
|
||||
xout (R0), 0x00
|
||||
inc R0
|
||||
xout (R0), 0x20
|
||||
ex_t_isr: ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; Main
|
||||
; -------------------------------------------------
|
||||
main: call pen_init
|
||||
call LCD_init
|
||||
mov R0, 0x00
|
||||
xout (led_port), R0
|
||||
|
||||
mov R0, CTRL_VGA_ENABLE
|
||||
xout (ctrl_reg), R0
|
||||
|
||||
xin R0, (ctrl_reg)
|
||||
or R0, CTRL_TIMER_ENABLE
|
||||
xout (ctrl_reg), R0
|
||||
|
||||
mov R0, 0x03
|
||||
cout (cpu_int_ctrl), R0
|
||||
|
||||
; Clear LCD
|
||||
mov R0, LCD_CMD_CLEAR
|
||||
call LCD_writecmd
|
||||
|
||||
mov R0, 0
|
||||
mov R1, 0xC0
|
||||
xout (reg_color_red), R1
|
||||
xout (reg_color_grn), R1
|
||||
xout (reg_color_blu), R1
|
||||
|
||||
call cg_wait_rdy
|
||||
call cg_clr_screen
|
||||
|
||||
; Print greeting message
|
||||
mov R1, greet_txt
|
||||
call LCD_putsx
|
||||
|
||||
mov R1, greet_txt
|
||||
call cg_puts
|
||||
mov R1, crlf
|
||||
call cg_puts_clr
|
||||
|
||||
xin R0, (ctrl_reg)
|
||||
and R0, 0xCF
|
||||
xout (ctrl_reg), R0
|
||||
|
||||
mov R0, 0
|
||||
movc (round_cnt), R0
|
||||
|
||||
mov R0, 0x0F
|
||||
xout (timer_reload+0), R0
|
||||
mov R0, 0x27
|
||||
xout (timer_reload+1), R0
|
||||
mov R0, 0x00
|
||||
xout (timer_reload+2), R0
|
||||
|
||||
main_loop: call do_clear
|
||||
call write_uart_data
|
||||
ML1: call do_write
|
||||
call do_read
|
||||
movc R0, (round_cnt)
|
||||
inc R0
|
||||
movc (round_cnt), R0
|
||||
jmp ML1
|
||||
|
||||
; ----------------------------------------------------------
|
||||
; SDRAM clear
|
||||
; ----------------------------------------------------------
|
||||
do_clear:
|
||||
; Clear LCD
|
||||
mov R0, LCD_CMD_CLEAR
|
||||
call LCD_writecmd
|
||||
|
||||
; Print Clear message
|
||||
mov R1, msg_txt0
|
||||
call LCD_putsx
|
||||
|
||||
mov R1, msg_txt0
|
||||
call cg_clr_puts
|
||||
mov R1, crlf
|
||||
call cg_puts_clr
|
||||
|
||||
; Set SDRAM address register to 0
|
||||
mov R0, 0
|
||||
mov R1, 0
|
||||
mov R2, 0
|
||||
call AddrCnt_Init
|
||||
|
||||
; Fill SDR Buffer with zeros
|
||||
mov R0, sdram_data
|
||||
mov R15, 8
|
||||
buf_clr_loop: movx (R0), 0
|
||||
inc R0
|
||||
dec R15
|
||||
jnz buf_clr_loop
|
||||
|
||||
sdr_clear: mov R2, BURST_LEN
|
||||
|
||||
poll_clear_full:
|
||||
xin R0, (sdram_reg)
|
||||
xout (led_port), R0
|
||||
and R0, FIFO_STAT_WRITE_DATA_FULL
|
||||
jnz poll_clear_full
|
||||
|
||||
; Fill FIFO
|
||||
mov R0, FIFO_CTRL_IS_WRITE
|
||||
xout (sdram_reg), R0
|
||||
|
||||
sub R2, 2
|
||||
jnz poll_clear_full
|
||||
|
||||
; Start SDR write
|
||||
call wait_cmd_rdy
|
||||
mov R0, SD_CMD_WRITE
|
||||
xout (sdram_reg), R0
|
||||
|
||||
xin R0, (sdram_addr+0)
|
||||
cmp R0, END_ADDR0
|
||||
jne next_addr_c
|
||||
xin R0, (sdram_addr+1)
|
||||
cmp R0, END_ADDR1
|
||||
jne next_addr_c
|
||||
xin R0, (sdram_addr+2)
|
||||
cmp R0, END_ADDR2
|
||||
jeq clear_finished
|
||||
|
||||
; Advance address counter
|
||||
next_addr_c: mov R0, BURST_LEN
|
||||
call AddrCnt_Inc
|
||||
|
||||
jmp sdr_clear
|
||||
|
||||
clear_finished:
|
||||
call AddrCnt_Disp
|
||||
call delay1s
|
||||
ret
|
||||
|
||||
; ----------------------------------------------------------
|
||||
; SDRAM Write
|
||||
; ----------------------------------------------------------
|
||||
write_uart_data:
|
||||
; Clear LCD
|
||||
mov R0, LCD_CMD_CLEAR
|
||||
call LCD_writecmd
|
||||
|
||||
; Print Clear message
|
||||
mov R1, msg_txt3
|
||||
call LCD_putsx
|
||||
|
||||
mov R1, msg_txt3
|
||||
call cg_clr_puts
|
||||
mov R1, crlf
|
||||
call cg_puts_clr
|
||||
|
||||
|
||||
; Set SDRAM address register to 0
|
||||
; mov R0, 0xF8 ; 800x600
|
||||
; mov R1, 0x52 ; 800x600
|
||||
; mov R2, 0x07 ; 800x600
|
||||
pen_restart: mov R0, 0x00 ; 1280x1024
|
||||
mov R1, 0x00 ; 1280x1024
|
||||
mov R2, 0x00 ; 1280x1024
|
||||
call AddrCnt_Init
|
||||
call pen_init
|
||||
|
||||
chk_pen_off: xin R0, (btn_port)
|
||||
and R0, 0x20
|
||||
jnz chk_pen_off
|
||||
mov R0, 1
|
||||
chk_pen_on: xin R0, (btn_port)
|
||||
and R0, 0x20
|
||||
jz chk_pen_on
|
||||
movc R0, (pen_rx_ptr_w)
|
||||
sub R0, 5
|
||||
cmp R0, pen_rx_buf+128
|
||||
jlt set_rx_ptr
|
||||
sub R0, 128
|
||||
set_rx_ptr: movc (pen_rx_ptr_r), R0
|
||||
|
||||
|
||||
; Fill SDR Buffer
|
||||
get_pen: mov R1, pixel_buf
|
||||
wls0: call pen_getchar
|
||||
movc (R1), R0
|
||||
inc R1
|
||||
cmp R1, pixel_buf+8
|
||||
jne wls0
|
||||
|
||||
; Start SDR write
|
||||
xin R0, (sdram_addr+0)
|
||||
push R0
|
||||
xin R0, (sdram_addr+1)
|
||||
push R0
|
||||
xin R0, (sdram_addr+2)
|
||||
push R0
|
||||
|
||||
mov R15, 64
|
||||
|
||||
write_sd_block: mov R2, BURST_LEN
|
||||
mov R1, pixel_buf
|
||||
copy_sdram: mov R3, sdram_data
|
||||
copy_pixel: movc R0, (R1)
|
||||
movx (R3), R0
|
||||
inc R3
|
||||
movx (R3), R0
|
||||
inc R3
|
||||
movx (R3), R0
|
||||
inc R3
|
||||
inc R1
|
||||
cmp R3, sdram_data+6
|
||||
jne copy_pixel
|
||||
pwf: xin R0, (sdram_reg)
|
||||
xout (led_port), R0
|
||||
and R0, FIFO_STAT_WRITE_DATA_FULL
|
||||
jnz pwf
|
||||
|
||||
; Fill FIFO
|
||||
mov R0, FIFO_CTRL_IS_WRITE
|
||||
xout (sdram_reg), R0
|
||||
sub R2, 2
|
||||
jnz copy_sdram
|
||||
|
||||
call wait_cmd_rdy
|
||||
mov R0, SD_CMD_WRITE
|
||||
xout (sdram_reg), R0
|
||||
|
||||
; call AddrCnt_Disp
|
||||
xin R0, (sdram_addr+1)
|
||||
add R0, 0x05
|
||||
xout (sdram_addr+1), R0
|
||||
xin R0, (sdram_addr+2)
|
||||
addc R0, 0x00
|
||||
xout (sdram_addr+2), R0
|
||||
|
||||
dec R15
|
||||
jnz write_sd_block
|
||||
|
||||
; Advance address counter
|
||||
pop R0,
|
||||
xout (sdram_addr+2), R0
|
||||
pop R0
|
||||
xout (sdram_addr+1), R0
|
||||
pop R0
|
||||
xout (sdram_addr+0), R0
|
||||
|
||||
xin R0, (sdram_addr+0)
|
||||
cmp R0, 0xF8
|
||||
jne next_addr
|
||||
xin R0, (sdram_addr+1)
|
||||
cmp R0, 0x04
|
||||
jne next_addr
|
||||
xin R0, (sdram_addr+2)
|
||||
cmp R0, 0x00
|
||||
jeq pen_restart
|
||||
|
||||
next_addr: mov R0, BURST_LEN
|
||||
call AddrCnt_Inc
|
||||
jmp get_pen
|
||||
sdw_fin: call delay1s
|
||||
ret
|
||||
|
||||
; ----------------------------------------------------------
|
||||
; SDRAM Write
|
||||
; ----------------------------------------------------------
|
||||
do_write:
|
||||
; Clear LCD
|
||||
mov R0, LCD_CMD_CLEAR
|
||||
call LCD_writecmd
|
||||
|
||||
; Print Write message
|
||||
mov R1, msg_txt1
|
||||
call LCD_putsx
|
||||
|
||||
mov R1, msg_txt1
|
||||
call cg_clr_puts
|
||||
mov R1, crlf
|
||||
call cg_puts_clr
|
||||
|
||||
; Set SDRAM address register to 0
|
||||
mov R0, START_ADDR0
|
||||
mov R1, START_ADDR1
|
||||
mov R2, START_ADDR2
|
||||
call AddrCnt_Init
|
||||
movc R0, (round_cnt)
|
||||
movc (block_cnt), R0
|
||||
|
||||
sdr_write: mov R2, BURST_LEN
|
||||
|
||||
; Fill SDR Buffer
|
||||
sdr_burst_wr: movc R1, (block_cnt)
|
||||
mov R0, sdram_data
|
||||
mov R15, 8
|
||||
write_loop: movx (R0), R1
|
||||
inc R0
|
||||
inc R1
|
||||
dec R15
|
||||
jnz write_loop
|
||||
|
||||
poll_write_full:
|
||||
xin R0, (sdram_reg)
|
||||
xout (led_port), R0
|
||||
and R0, FIFO_STAT_WRITE_DATA_FULL
|
||||
jnz poll_write_full
|
||||
|
||||
; Fill FIFO
|
||||
mov R0, FIFO_CTRL_IS_WRITE
|
||||
xout (sdram_reg), R0
|
||||
|
||||
movc R0, (block_cnt)
|
||||
inc R0
|
||||
movc (block_cnt), R0
|
||||
|
||||
sub R2, 2
|
||||
jnz sdr_burst_wr
|
||||
|
||||
; Start SDR write
|
||||
call wait_cmd_rdy
|
||||
mov R0, SD_CMD_WRITE
|
||||
xout (sdram_reg), R0
|
||||
|
||||
xin R0, (sdram_addr+0)
|
||||
cmp R0, END_ADDR0
|
||||
jne next_addr_w
|
||||
xin R0, (sdram_addr+1)
|
||||
cmp R0, END_ADDR1
|
||||
jne next_addr_w
|
||||
xin R0, (sdram_addr+2)
|
||||
cmp R0, END_ADDR2
|
||||
jeq write_finished
|
||||
|
||||
; Advance address counter
|
||||
next_addr_w: mov R0, BURST_LEN
|
||||
call AddrCnt_Inc
|
||||
|
||||
jmp sdr_write
|
||||
|
||||
write_finished: call AddrCnt_Disp
|
||||
call delay1s
|
||||
ret
|
||||
|
||||
; ----------------------------------------------------------
|
||||
; SDRAM Verify
|
||||
; ----------------------------------------------------------
|
||||
do_read:
|
||||
; Clear LCD
|
||||
mov R0, LCD_CMD_CLEAR
|
||||
call LCD_writecmd
|
||||
|
||||
; Print Read message
|
||||
mov R1, msg_txt2
|
||||
call LCD_putsx
|
||||
|
||||
mov R1, msg_txt2
|
||||
call cg_clr_puts
|
||||
mov R1, crlf
|
||||
call cg_puts_clr
|
||||
|
||||
; Set SDRAM address register to 0
|
||||
mov R0, START_ADDR0
|
||||
mov R1, START_ADDR1
|
||||
mov R2, START_ADDR2
|
||||
call AddrCnt_Init
|
||||
movc R0, (round_cnt)
|
||||
movc (block_cnt), R0
|
||||
|
||||
; flush_data
|
||||
flush_data: xin R0, (sdram_reg)
|
||||
xout (led_port), R0
|
||||
and R0, FIFO_STAT_READ_DATA_EMPTY
|
||||
jnz sdr_read
|
||||
mov R0, FIFO_CTRL_IS_READ
|
||||
xout (sdram_reg), R0
|
||||
jmp flush_data
|
||||
|
||||
sdr_read: ; Start SDR read
|
||||
call wait_cmd_rdy
|
||||
mov R0, SD_CMD_READ
|
||||
xout (sdram_reg), R0
|
||||
|
||||
mov R3, BURST_LEN
|
||||
|
||||
; Wait last read
|
||||
poll_read_fin: xin R0, (sdram_reg)
|
||||
xout (led_port), R0
|
||||
and R0, FIFO_STAT_READ_DATA_EMPTY
|
||||
jnz poll_read_fin
|
||||
|
||||
; Verify SDR Buffer
|
||||
movc R1, (block_cnt)
|
||||
mov R0, sdram_data
|
||||
mov R15, 8
|
||||
read_loop: movx R2, (R0)
|
||||
cmp R2, R1
|
||||
jne verify_error
|
||||
inc R0
|
||||
inc R1
|
||||
dec R15
|
||||
jnz read_loop
|
||||
|
||||
; Advance Read-FIFO
|
||||
mov R0, FIFO_CTRL_IS_READ
|
||||
xout (sdram_reg), R0
|
||||
|
||||
movc R0, (block_cnt)
|
||||
inc R0
|
||||
movc (block_cnt), R0
|
||||
|
||||
sub R3, 2
|
||||
jnz poll_read_fin
|
||||
|
||||
xin R0, (sdram_addr+0)
|
||||
cmp R0, END_ADDR0
|
||||
jne next_addr_r
|
||||
xin R0, (sdram_addr+1)
|
||||
cmp R0, END_ADDR1
|
||||
jne next_addr_r
|
||||
xin R0, (sdram_addr+2)
|
||||
cmp R0, END_ADDR2
|
||||
jeq read_finished
|
||||
|
||||
; Advance address counter
|
||||
next_addr_r: mov R0, BURST_LEN
|
||||
call AddrCnt_Inc
|
||||
jmp sdr_read
|
||||
|
||||
; ----------------------------------------------------------
|
||||
wait_cmd_rdy: push R0
|
||||
wait4cmd: xin R0, (sdram_reg)
|
||||
xout (led_port), R0
|
||||
and R0, FIFO_STAT_CMD_FULL
|
||||
jnz wait4cmd
|
||||
pop R0
|
||||
ret
|
||||
|
||||
; ----------------------------------------------------------
|
||||
read_finished:
|
||||
no_error: mov R0, LCD_CMD_CLEAR
|
||||
call LCD_writecmd
|
||||
mov R1, verify_ok
|
||||
call LCD_putsx
|
||||
mov R0, LCD_CMD_Z2
|
||||
call LCD_writecmd
|
||||
call print_addr
|
||||
|
||||
mov R1, verify_ok
|
||||
call cg_clr_puts
|
||||
mov R1, crlf
|
||||
call cg_puts_clr
|
||||
|
||||
jmp ende
|
||||
|
||||
verify_error: mov R0, LCD_CMD_CLEAR
|
||||
call LCD_writecmd
|
||||
mov R1, verify_nok
|
||||
call LCD_putsx
|
||||
call print_addr
|
||||
call print_data
|
||||
mov R1, verify_nok
|
||||
call cg_clr_puts
|
||||
mov R1, crlf
|
||||
call cg_puts_clr
|
||||
xin R0, (ctrl_reg)
|
||||
or R0, 0x10
|
||||
xout (ctrl_reg), R0
|
||||
|
||||
jmp ende
|
||||
|
||||
ende: call delay1s
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
AddrCnt_Init: xout (sdram_addr+0), R0
|
||||
xout (sdram_addr+1), R1
|
||||
xout (sdram_addr+2), R2
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; Parameter
|
||||
; R0: increment value
|
||||
AddrCnt_Inc: push R1
|
||||
push R2
|
||||
push R3
|
||||
xin R1, (sdram_addr+0)
|
||||
xin R2, (sdram_addr+1)
|
||||
xin R3, (sdram_addr+2)
|
||||
add R1, R0
|
||||
addc R2, 0
|
||||
addc R3, 0
|
||||
xout (sdram_addr+0), R1
|
||||
xout (sdram_addr+1), R2
|
||||
xout (sdram_addr+2), R3
|
||||
pop R3
|
||||
pop R2
|
||||
pop R1
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; Parameter
|
||||
; R0: decrement value
|
||||
AddrCnt_Dec: push R1
|
||||
push R2
|
||||
push R3
|
||||
xin R1, (sdram_addr+0)
|
||||
xin R2, (sdram_addr+1)
|
||||
xin R3, (sdram_addr+2)
|
||||
sub R1, R0
|
||||
subc R2, 0
|
||||
subc R3, 0
|
||||
xout (sdram_addr+0), R1
|
||||
xout (sdram_addr+1), R2
|
||||
xout (sdram_addr+2), R3
|
||||
pop R3
|
||||
pop R2
|
||||
pop R1
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; Display Address counter
|
||||
AddrCnt_Disp: mov R0, LCD_CMD_Z2
|
||||
call LCD_writecmd
|
||||
call print_addr
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; PutHexByte
|
||||
; R0 : Byte value
|
||||
PutHexByte: push R1
|
||||
call bin2hex
|
||||
call LCD_writechar
|
||||
mov R0, R1
|
||||
call LCD_writechar
|
||||
pop R1
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
print_addr: push R0
|
||||
xin R0, (sdram_addr+2)
|
||||
call PutHexByte
|
||||
xin R0, (sdram_addr+1)
|
||||
call PutHexByte
|
||||
xin R0, (sdram_addr+0)
|
||||
call PutHexByte
|
||||
pop R0
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; R1 : ptr to byte array
|
||||
print_dword: push R0
|
||||
add R1, 3
|
||||
movc R0, (R1)
|
||||
call PutHexByte
|
||||
dec R1
|
||||
movc R0, (R1)
|
||||
call PutHexByte
|
||||
dec R1
|
||||
movc R0, (R1)
|
||||
call PutHexByte
|
||||
dec R1
|
||||
movc R0, (R1)
|
||||
call PutHexByte
|
||||
pop R0
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
print_data: push R0
|
||||
mov R0, LCD_CMD_Z2
|
||||
call LCD_writecmd
|
||||
movx R0, (sdram_data+7)
|
||||
call PutHexByte
|
||||
movx R0, (sdram_data+6)
|
||||
call PutHexByte
|
||||
movx R0, (sdram_data+5)
|
||||
call PutHexByte
|
||||
movx R0, (sdram_data+4)
|
||||
call PutHexByte
|
||||
movx R0, (sdram_data+3)
|
||||
call PutHexByte
|
||||
movx R0, (sdram_data+2)
|
||||
call PutHexByte
|
||||
movx R0, (sdram_data+1)
|
||||
call PutHexByte
|
||||
movx R0, (sdram_data+0)
|
||||
call PutHexByte
|
||||
pop R0
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
pen_init: push R0
|
||||
mov R0, 0
|
||||
movc (pen_enable), R0
|
||||
call delay10ms
|
||||
mov R0, pen_rx_buf
|
||||
movc (pen_rx_ptr_r), R0
|
||||
movc (pen_rx_ptr_w), R0
|
||||
mov R0, PEN_TIMEOUT0
|
||||
movc (pen_timeout+0), R0
|
||||
mov R0, PEN_TIMEOUT1
|
||||
movc (pen_timeout+1), R0
|
||||
mov R0, 0
|
||||
movc (pen_bit_cnt_w), R0
|
||||
movc (pen_octet_w), R0
|
||||
movc (pen_octet_r), R0
|
||||
mov R0, 7
|
||||
movc (pen_bit_cnt_r), R0
|
||||
pop R0
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; Params: none
|
||||
; Return:
|
||||
; R0 : received character
|
||||
pen_getchar: push R1
|
||||
push R2
|
||||
push R3
|
||||
movc R3, (pen_octet_r)
|
||||
movc R1, (pen_rx_ptr_r)
|
||||
movc R2, (pen_bit_cnt_r)
|
||||
inc R2
|
||||
cmp R2, 8
|
||||
jne u_upd_r_ptr
|
||||
mov R2, 0
|
||||
|
||||
pen_wait_rx: movc R0, (pen_rx_ptr_w)
|
||||
cmp R0, R1
|
||||
jeq pen_wait_rx
|
||||
movc R3, (R1)
|
||||
inc R1
|
||||
cmp R1, pen_rx_buf+128
|
||||
jne u_upd_r_ptr
|
||||
mov R1, pen_rx_buf
|
||||
u_upd_r_ptr: movc (pen_rx_ptr_r), R1
|
||||
movc (pen_bit_cnt_r), R2
|
||||
ex_pen_gc: mov R0, 0xFF
|
||||
shl R3
|
||||
jnc pen_is_zero
|
||||
mov R0, 0x00
|
||||
pen_is_zero: movc (pen_octet_r), R3
|
||||
pop R3
|
||||
pop R2
|
||||
pop R1
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
include "../../../lib/jasm/utils.inc.jsm"
|
||||
include "../../../lib/jasm/lcd.inc.jsm"
|
||||
include "../../../lib/jasm/cg.inc.jsm"
|
||||
include "../../../lib/jasm/delays.inc.jsm"
|
||||
include "../../../lib/jasm/uart.inc.jsm"
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,64 @@
|
||||
# ----------------------------------------------------------------------
|
||||
# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
# This file: The ROM file for upload to target over JTAG
|
||||
|
||||
# Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
# This library is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU Lesser General Public
|
||||
# License as published by the Free Software Foundation; either
|
||||
# version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
# This library is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
# Lesser General Public License for more details.
|
||||
|
||||
# You should have received a copy of the GNU Lesser General Public
|
||||
# License along with this library; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
# For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
# ---------------------------------------------------------------------
|
||||
|
||||
# Source JTAG/TCL frame work
|
||||
#cd $env(CHIPSCOPE)\bin\nt
|
||||
cd F:\\Xilinx9\\ChipScope_Pro_9_1i\\bin\\nt
|
||||
source csejtag.tcl
|
||||
|
||||
namespace import ::chipscope::*
|
||||
|
||||
# Platform USB Cable
|
||||
set PLATFORM_USB_CABLE_ARGS [list "port=USB2" \
|
||||
"frequency=6000000"]
|
||||
# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
|
||||
|
||||
set CABLE_NAME $CSEJTAG_TARGET_PLATFORMUSB
|
||||
set CABLE_ARGS $PLATFORM_USB_CABLE_ARGS
|
||||
|
||||
# Create session
|
||||
set handle [::chipscope::csejtag_session create 0]
|
||||
|
||||
# Open JTAG and lock
|
||||
set open_result [::chipscope::csejtag_target open $handle $CABLE_NAME 0 $CABLE_ARGS]
|
||||
set lock_result [::chipscope::csejtag_target lock $handle 1000]
|
||||
|
||||
set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
|
||||
|
||||
# Get Device ID
|
||||
set devtype "Virtex-4SX"
|
||||
set devid 2
|
||||
|
||||
# ---------------------------------------------------------------
|
||||
# Shift the USER1 Instruction (b1111000010) into the Instruction Register of FPGA
|
||||
# User 1
|
||||
::chipscope::csejtag_tap shift_chain_ir $handle $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 10 3C2
|
||||
|
||||
# Write Program
|
||||
# JASM_ROM_INSERT_HERE
|
||||
|
||||
::chipscope::csejtag_target unlock $handle
|
||||
::chipscope::csejtag_target close $handle
|
||||
::chipscope::csejtag_session destroy $handle
|
||||
exit
|
||||
@@ -0,0 +1,306 @@
|
||||
; -------------------------------------------------
|
||||
; Register definitions
|
||||
; -------------------------------------------------
|
||||
include "../../../lib/jasm/cregs.inc.jsm"
|
||||
include "xregs.inc.jsm"
|
||||
|
||||
; -------------------------------------------------
|
||||
; Constants
|
||||
; -------------------------------------------------
|
||||
addr_incr: equ 2
|
||||
addr_msb_max: equ 0xFF
|
||||
|
||||
; External RAM/ROM
|
||||
xmem
|
||||
greet_txt: dc "SDRAM Test", 0
|
||||
msg_txt0: dc "Clearing SDRAM", 0
|
||||
msg_txt1: dc "Writing SDRAM", 0
|
||||
msg_txt2: dc "Reading SDRAM", 0
|
||||
verify_ok: dc "Verify OK", 0
|
||||
verify_nok: dc "Verify Failed", 0
|
||||
dot: dc ".", 0
|
||||
|
||||
org 0x80
|
||||
sdram_data: db 8 ; SDRAM data window at X:0x80
|
||||
|
||||
; Internal RAM
|
||||
cmem 0
|
||||
round: db 1
|
||||
|
||||
; -------------------------------------------------
|
||||
; Program
|
||||
; -------------------------------------------------
|
||||
code
|
||||
reset: org 0x000
|
||||
jmp main
|
||||
|
||||
; -------------------------------------------------
|
||||
; ISR
|
||||
; -------------------------------------------------
|
||||
org 0x001
|
||||
reti
|
||||
|
||||
; -------------------------------------------------
|
||||
; Main
|
||||
; -------------------------------------------------
|
||||
main:
|
||||
call LCD_init
|
||||
mov R0, 0x00
|
||||
xout (led_port), R0
|
||||
|
||||
; Clear LCD
|
||||
mov R0, LCD_CMD_CLEAR
|
||||
call LCD_writecmd
|
||||
|
||||
; Wait until SDRAM ready
|
||||
poll_bsy_fin: xin R0, (sdram_reg)
|
||||
xout (led_port), R0
|
||||
and R0, SDRAM_STAT_BUSY
|
||||
jnz poll_bsy_fin
|
||||
|
||||
; Print greeting message
|
||||
mov R1, greet_txt
|
||||
call LCD_putsx
|
||||
|
||||
xin R0, (ctrl_reg)
|
||||
or R0, 0x10
|
||||
xout (ctrl_reg), R0
|
||||
call delay100ms
|
||||
or R0, 0x20
|
||||
xout (ctrl_reg), R0
|
||||
call delay100ms
|
||||
and R0, 0xEF
|
||||
xout (ctrl_reg), R0
|
||||
call delay100ms
|
||||
and R0, 0xCF
|
||||
xout (ctrl_reg), R0
|
||||
|
||||
jmp do_clear
|
||||
; ----------------------------------------------------------
|
||||
; SDRAM clear
|
||||
; ----------------------------------------------------------
|
||||
do_clear: ; Clear LCD
|
||||
mov R0, LCD_CMD_CLEAR
|
||||
call LCD_writecmd
|
||||
|
||||
; Print Clear message
|
||||
mov R1, msg_txt0
|
||||
call LCD_putsx
|
||||
|
||||
; Set SDRAM address register to 0
|
||||
call AddrCnt_Init
|
||||
|
||||
; Fill SDR Buffer with zeros
|
||||
mov R0, sdram_data
|
||||
mov R15, 8
|
||||
buf_clr_loop: movx (R0), 0
|
||||
inc R0
|
||||
dec R15
|
||||
jnz buf_clr_loop
|
||||
|
||||
sdr_clear: xin R0, (sdram_addr+2)
|
||||
cmp R0, addr_msb_max
|
||||
jeq clear_finished
|
||||
|
||||
; Wait finished last write
|
||||
poll_clear_fin: xin R0, (sdram_reg)
|
||||
xout (led_port), R0
|
||||
and R0, SDRAM_STAT_WRITE_BUSY
|
||||
|
||||
jnz poll_clear_fin
|
||||
|
||||
; Start SDR write
|
||||
mov R0, sdram_reg
|
||||
xout (R0), SDRAM_CTRL_WRITE_REQUEST
|
||||
|
||||
; Advance address counter
|
||||
mov R0, addr_incr
|
||||
call AddrCnt_Adv
|
||||
|
||||
jmp sdr_clear
|
||||
|
||||
clear_finished:
|
||||
call AddrCnt_Disp
|
||||
call delay1s
|
||||
|
||||
; ----------------------------------------------------------
|
||||
; SDRAM Write
|
||||
; ----------------------------------------------------------
|
||||
do_write: ; Clear LCD
|
||||
mov R0, LCD_CMD_CLEAR
|
||||
call LCD_writecmd
|
||||
|
||||
; Print Write message
|
||||
mov R1, msg_txt1
|
||||
call LCD_putsx
|
||||
|
||||
; Set SDRAM address register to 0
|
||||
call AddrCnt_Init
|
||||
mov R0, 0
|
||||
movc (round), R0
|
||||
|
||||
sdr_write: xin R0, (sdram_addr+2)
|
||||
cmp R0, addr_msb_max
|
||||
jeq write_finished
|
||||
|
||||
; Fill SDR Buffer
|
||||
movc R1, (round)
|
||||
; xin R0, (sdram_addr+2)
|
||||
; cmp R0, 0x7F
|
||||
; jne force_no_err
|
||||
; inc R1
|
||||
force_no_err: mov R0, sdram_data
|
||||
mov R15, 8
|
||||
write_loop: movx (R0), R1
|
||||
inc R0
|
||||
inc R1
|
||||
dec R15
|
||||
jnz write_loop
|
||||
|
||||
; Wait finished last write
|
||||
poll_write_fin: xin R0, (sdram_reg)
|
||||
xout (led_port), R0
|
||||
and R0, SDRAM_STAT_WRITE_BUSY
|
||||
jnz poll_write_fin
|
||||
|
||||
; Start SDR write
|
||||
mov R0, sdram_reg
|
||||
xout (R0), SDRAM_CTRL_WRITE_REQUEST
|
||||
|
||||
; Advance address counter
|
||||
mov R0, addr_incr
|
||||
call AddrCnt_Adv
|
||||
movc R0, (round)
|
||||
inc R0
|
||||
movc (round), R0
|
||||
|
||||
jmp sdr_write
|
||||
|
||||
write_finished: call AddrCnt_Disp
|
||||
call delay1s
|
||||
|
||||
; ----------------------------------------------------------
|
||||
; SDRAM Verify
|
||||
; ----------------------------------------------------------
|
||||
do_read: ; Clear LCD
|
||||
mov R0, LCD_CMD_CLEAR
|
||||
call LCD_writecmd
|
||||
|
||||
; Print Read message
|
||||
mov R1, msg_txt2
|
||||
call LCD_putsx
|
||||
|
||||
; Set SDRAM address register to 0
|
||||
call AddrCnt_Init
|
||||
mov R0, 0
|
||||
movc (round), R0
|
||||
|
||||
sdr_read: xin R0, (sdram_addr+2)
|
||||
cmp R0, addr_msb_max
|
||||
jeq read_finished
|
||||
|
||||
; Start SDR read
|
||||
mov R0, sdram_reg
|
||||
xout (R0), SDRAM_CTRL_READ_REQUEST
|
||||
|
||||
; Wait last read
|
||||
poll_read_fin: xin R0, (sdram_reg)
|
||||
xout (led_port), R0
|
||||
and R0, SDRAM_STAT_READ_BUSY
|
||||
jnz poll_read_fin
|
||||
|
||||
read_back_mem:
|
||||
; Verify SDR Buffer
|
||||
movc R1, (round)
|
||||
mov R0, sdram_data
|
||||
mov R15, 8
|
||||
read_loop: movx R2, (R0)
|
||||
cmp R2, R1
|
||||
jne verify_error
|
||||
inc R0
|
||||
inc R1
|
||||
dec R15
|
||||
jnz read_loop
|
||||
|
||||
; Advance address counter
|
||||
mov R0, addr_incr
|
||||
call AddrCnt_Adv
|
||||
movc R0, (round)
|
||||
inc R0
|
||||
movc (round), R0
|
||||
jmp sdr_read
|
||||
|
||||
; ----------------------------------------------------------
|
||||
read_finished:
|
||||
no_error: mov R0, LCD_CMD_Z2
|
||||
call LCD_writecmd
|
||||
mov R1, verify_ok
|
||||
call LCD_putsx
|
||||
jmp ende
|
||||
|
||||
verify_error: mov R0, LCD_CMD_Z2
|
||||
call LCD_writecmd
|
||||
mov R1, verify_nok
|
||||
call LCD_putsx
|
||||
jmp ende
|
||||
|
||||
ende: call delay1s
|
||||
jmp do_clear
|
||||
|
||||
; -------------------------------------------------
|
||||
AddrCnt_Init: push R0
|
||||
mov R0, 0x00
|
||||
xout (sdram_addr+0), R0
|
||||
xout (sdram_addr+1), R0
|
||||
xout (sdram_addr+2), R0
|
||||
pop R0
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; Parameter
|
||||
; R0: increment value
|
||||
AddrCnt_Adv: push R1
|
||||
push R2
|
||||
push R3
|
||||
xin R1, (sdram_addr+0)
|
||||
xin R2, (sdram_addr+1)
|
||||
xin R3, (sdram_addr+2)
|
||||
add R1, R0
|
||||
addc R2, 0
|
||||
addc R3, 0
|
||||
xout (sdram_addr+0), R1
|
||||
xout (sdram_addr+1), R2
|
||||
xout (sdram_addr+2), R3
|
||||
pop R3
|
||||
pop R2
|
||||
pop R1
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; Display Address counter
|
||||
AddrCnt_Disp: mov R0, LCD_CMD_Z2
|
||||
call LCD_writecmd
|
||||
|
||||
xin R0, (sdram_addr+2)
|
||||
call PutHexByte
|
||||
xin R0, (sdram_addr+1)
|
||||
call PutHexByte
|
||||
xin R0, (sdram_addr+0)
|
||||
call PutHexByte
|
||||
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; PutHexByte
|
||||
; R0 : Byte value
|
||||
PutHexByte: call bin2hex
|
||||
call LCD_writechar
|
||||
mov R0, R1
|
||||
call LCD_writechar
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
include "../../../lib/jasm/utils.inc.jsm"
|
||||
include "../../../lib/jasm/lcd.inc.jsm"
|
||||
include "../../../lib/jasm/delays.inc.jsm"
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,215 @@
|
||||
; -------------------------------------------------
|
||||
; Register definitions
|
||||
; -------------------------------------------------
|
||||
include "../../../lib/jasm/cregs.inc.jsm"
|
||||
include "xregs.inc.jsm"
|
||||
|
||||
; -------------------------------------------------
|
||||
; Constants
|
||||
; -------------------------------------------------
|
||||
addr_incr: equ 2
|
||||
addr_lsb_max: equ 0x08
|
||||
|
||||
; External RAM/ROM
|
||||
xmem
|
||||
org 0x80
|
||||
sdram_data: db 8 ; SDRAM data window at X:0x80
|
||||
|
||||
; Internal RAM
|
||||
cmem 0
|
||||
round: db 1
|
||||
|
||||
; -------------------------------------------------
|
||||
; Program
|
||||
; -------------------------------------------------
|
||||
code
|
||||
reset: org 0x000
|
||||
jmp main
|
||||
|
||||
; -------------------------------------------------
|
||||
; ISR
|
||||
; -------------------------------------------------
|
||||
org 0x001
|
||||
reti
|
||||
|
||||
; -------------------------------------------------
|
||||
; Main
|
||||
; -------------------------------------------------
|
||||
main: mov R0, 0x00
|
||||
xout (led_port), R0
|
||||
xin R0, (ctrl_reg)
|
||||
and R0, 0xCF
|
||||
xout (ctrl_reg), R0
|
||||
|
||||
; Wait until SDRAM ready
|
||||
poll_bsy_fin: xin R0, (sdram_reg)
|
||||
and R0, SDRAM_STAT_BUSY
|
||||
jnz poll_bsy_fin
|
||||
|
||||
jmp do_clear
|
||||
; ----------------------------------------------------------
|
||||
; SDRAM clear
|
||||
; ----------------------------------------------------------
|
||||
do_clear:
|
||||
; Set SDRAM address register to 0
|
||||
call AddrCnt_Init
|
||||
|
||||
; Fill SDR Buffer with zeros
|
||||
mov R0, sdram_data
|
||||
mov R15, 8
|
||||
buf_clr_loop: movx (R0), 0
|
||||
inc R0
|
||||
dec R15
|
||||
jnz buf_clr_loop
|
||||
|
||||
sdr_clear: xin R0, (sdram_addr+0)
|
||||
cmp R0, addr_lsb_max
|
||||
jeq clear_finished
|
||||
|
||||
; Wait finished last write
|
||||
poll_clear_fin: xin R0, (sdram_reg)
|
||||
and R0, SDRAM_STAT_WRITE_BUSY
|
||||
jnz poll_clear_fin
|
||||
|
||||
; Start SDR write
|
||||
mov R0, sdram_reg
|
||||
xout (R0), SDRAM_CTRL_WRITE_REQUEST
|
||||
|
||||
; Advance address counter
|
||||
mov R0, addr_incr
|
||||
call AddrCnt_Adv
|
||||
|
||||
jmp sdr_clear
|
||||
|
||||
clear_finished:
|
||||
|
||||
; ----------------------------------------------------------
|
||||
; SDRAM Write
|
||||
; ----------------------------------------------------------
|
||||
do_write:
|
||||
; Set SDRAM address register to 0
|
||||
call AddrCnt_Init
|
||||
mov R0, 0
|
||||
movc (round), R0
|
||||
|
||||
sdr_write: xin R0, (sdram_addr+0)
|
||||
cmp R0, addr_lsb_max
|
||||
jeq write_finished
|
||||
|
||||
; Fill SDR Buffer
|
||||
movc R1, (round)
|
||||
force_no_err: mov R0, sdram_data
|
||||
mov R15, 8
|
||||
write_loop: movx (R0), R1
|
||||
inc R0
|
||||
inc R1
|
||||
dec R15
|
||||
jnz write_loop
|
||||
|
||||
; Wait finished last write
|
||||
poll_write_fin: xin R0, (sdram_reg)
|
||||
and R0, SDRAM_STAT_WRITE_BUSY
|
||||
jnz poll_write_fin
|
||||
|
||||
nop
|
||||
|
||||
; Start SDR write
|
||||
mov R0, sdram_reg
|
||||
xout (R0), SDRAM_CTRL_WRITE_REQUEST
|
||||
|
||||
; Advance address counter
|
||||
mov R0, addr_incr
|
||||
call AddrCnt_Adv
|
||||
movc R0, (round)
|
||||
inc R0
|
||||
movc (round), R0
|
||||
|
||||
jmp sdr_write
|
||||
|
||||
write_finished:
|
||||
|
||||
; ----------------------------------------------------------
|
||||
; SDRAM Verify
|
||||
; ----------------------------------------------------------
|
||||
do_read:
|
||||
; Set SDRAM address register to 0
|
||||
call AddrCnt_Init
|
||||
mov R0, 0
|
||||
movc (round), R0
|
||||
|
||||
sdr_read: xin R0, (sdram_addr+0)
|
||||
cmp R0, addr_lsb_max
|
||||
jeq read_finished
|
||||
|
||||
; Start SDR read
|
||||
mov R0, sdram_reg
|
||||
xout (R0), SDRAM_CTRL_READ_REQUEST
|
||||
|
||||
; Wait last read
|
||||
poll_read_fin: xin R0, (sdram_reg)
|
||||
and R0, SDRAM_STAT_READ_BUSY
|
||||
jnz poll_read_fin
|
||||
|
||||
read_back_mem:
|
||||
; Verify SDR Buffer
|
||||
movc R1, (round)
|
||||
mov R0, sdram_data
|
||||
mov R15, 8
|
||||
read_loop: movx R2, (R0)
|
||||
cmp R2, R1
|
||||
jne verify_error
|
||||
inc R0
|
||||
inc R1
|
||||
dec R15
|
||||
jnz read_loop
|
||||
|
||||
; Advance address counter
|
||||
mov R0, addr_incr
|
||||
call AddrCnt_Adv
|
||||
movc R0, (round)
|
||||
inc R0
|
||||
movc (round), R0
|
||||
jmp sdr_read
|
||||
|
||||
; ----------------------------------------------------------
|
||||
read_finished:
|
||||
no_error: jmp ende
|
||||
|
||||
verify_error: xin R0, (ctrl_reg)
|
||||
or R0, 0x10
|
||||
xout (ctrl_reg), R0
|
||||
jmp ende
|
||||
|
||||
ende: jmp ende
|
||||
|
||||
; -------------------------------------------------
|
||||
AddrCnt_Init: push R0
|
||||
mov R0, 0x00
|
||||
xout (sdram_addr+0), R0
|
||||
xout (sdram_addr+1), R0
|
||||
xout (sdram_addr+2), R0
|
||||
pop R0
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; Parameter
|
||||
; R0: increment value
|
||||
AddrCnt_Adv: push R1
|
||||
push R2
|
||||
push R3
|
||||
xin R1, (sdram_addr+0)
|
||||
xin R2, (sdram_addr+1)
|
||||
xin R3, (sdram_addr+2)
|
||||
add R1, R0
|
||||
addc R2, 0
|
||||
addc R3, 0
|
||||
xout (sdram_addr+0), R1
|
||||
xout (sdram_addr+1), R2
|
||||
xout (sdram_addr+2), R3
|
||||
pop R3
|
||||
pop R2
|
||||
pop R1
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
|
||||
@@ -0,0 +1,542 @@
|
||||
# ----------------------------------------------------------------------
|
||||
# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
# This file: The ROM file for upload to target over JTAG
|
||||
#
|
||||
# Copyright (C) 2007 J. Ahrensfeld
|
||||
#
|
||||
# This program is free software: you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation, either version 3 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# For questions and ideas, please contact the author at jens@jayfield.org
|
||||
#
|
||||
# ---------------------------------------------------------------------
|
||||
|
||||
# ---------------------------------------------------------------------
|
||||
# For Chipscope 9.1
|
||||
# ---------------------------------------------------------------------
|
||||
# Source JTAG/TCL frame work
|
||||
cd $env(CHIPSCOPE)\\bin\\nt
|
||||
source csejtag.tcl
|
||||
|
||||
namespace import ::chipscope::*
|
||||
|
||||
# Platform USB Cable
|
||||
set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
|
||||
# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
|
||||
|
||||
# Create session
|
||||
set handle [::chipscope::csejtag_session create 0]
|
||||
|
||||
# Open JTAG and lock
|
||||
set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
|
||||
set lock_result [::chipscope::csejtag_target lock $handle 1000]
|
||||
|
||||
set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
|
||||
|
||||
# Get Device ID
|
||||
set devtype "Virtex-4SX"
|
||||
set devid 2
|
||||
set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
|
||||
set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
|
||||
|
||||
set CSE_OP $CSEJTAG_SHIFT_READWRITE
|
||||
set CSE_ES $CSEJTAG_RUN_TEST_IDLE
|
||||
|
||||
# Write Program
|
||||
# JASM_ROM_INSERT_HERE
|
||||
# Assembled from sdr_test_short.jsm
|
||||
# ---------------------------------------------------------------
|
||||
# Shift the USER2 Instruction (b1111000010) into the Instruction Register of FPGA
|
||||
# User 1
|
||||
set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C2"]
|
||||
|
||||
# 0x000: JMP 0x002
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00030002"
|
||||
|
||||
# 0x001: RETI
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0013F000"
|
||||
|
||||
# 0x002: MOV R00, 0x00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00203000"
|
||||
|
||||
# 0x003: XOUT (0x01), R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00324010"
|
||||
|
||||
# 0x004: XIN R00, (0x04)
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00428040"
|
||||
|
||||
# 0x005: AND R00, 0xCF
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00519CF0"
|
||||
|
||||
# 0x006: XOUT (0x04), R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00624040"
|
||||
|
||||
# 0x007: XIN R00, (0x07)
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00728070"
|
||||
|
||||
# 0x008: AND R00, 0x80
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00819800"
|
||||
|
||||
# 0x009: JNZ 0x007
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00932007"
|
||||
|
||||
# 0x00A: JMP 0x00B
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00A3000B"
|
||||
|
||||
# 0x00B: CALL 0x058
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00B3B058"
|
||||
|
||||
# 0x00C: MOV R00, 0x80
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00C03800"
|
||||
|
||||
# 0x00D: MOV R15, 0x08
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00D0308F"
|
||||
|
||||
# 0x00E: MOVX (R00), 0x00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00E07000"
|
||||
|
||||
# 0x00F: INC R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00F11010"
|
||||
|
||||
# 0x010: DEC R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0101501F"
|
||||
|
||||
# 0x011: JNZ 0x00E
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0113200E"
|
||||
|
||||
# 0x012: XIN R00, (0x08)
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01228080"
|
||||
|
||||
# 0x013: CMP R00, 0x08
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0130F080"
|
||||
|
||||
# 0x014: JEQ 0x01D
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0143901D"
|
||||
|
||||
# 0x015: XIN R00, (0x07)
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01528070"
|
||||
|
||||
# 0x016: AND R00, 0x02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01619020"
|
||||
|
||||
# 0x017: JNZ 0x015
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01732015"
|
||||
|
||||
# 0x018: MOV R00, 0x07
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01803070"
|
||||
|
||||
# 0x019: XOUT (R00), 0x02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01925020"
|
||||
|
||||
# 0x01A: MOV R00, 0x02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01A03020"
|
||||
|
||||
# 0x01B: CALL 0x05F
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01B3B05F"
|
||||
|
||||
# 0x01C: JMP 0x012
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01C30012"
|
||||
|
||||
# 0x01D: CALL 0x058
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01D3B058"
|
||||
|
||||
# 0x01E: MOV R00, 0x00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01E03000"
|
||||
|
||||
# 0x01F: MOVC (0x00), R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01F0D000"
|
||||
|
||||
# 0x020: XIN R00, (0x08)
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02028080"
|
||||
|
||||
# 0x021: CMP R00, 0x08
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0210F080"
|
||||
|
||||
# 0x022: JEQ 0x037
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02239037"
|
||||
|
||||
# 0x023: MOVC R01, (0x00)
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0230A001"
|
||||
|
||||
# 0x024: MOV R00, 0x80
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02403800"
|
||||
|
||||
# 0x025: MOV R15, 0x08
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0250308F"
|
||||
|
||||
# 0x026: MOVX (R01), R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02606001"
|
||||
|
||||
# 0x027: INC R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02711010"
|
||||
|
||||
# 0x028: INC R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02811011"
|
||||
|
||||
# 0x029: DEC R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0291501F"
|
||||
|
||||
# 0x02A: JNZ 0x026
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02A32026"
|
||||
|
||||
# 0x02B: XIN R00, (0x07)
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02B28070"
|
||||
|
||||
# 0x02C: AND R00, 0x02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02C19020"
|
||||
|
||||
# 0x02D: JNZ 0x02B
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02D3202B"
|
||||
|
||||
# 0x02E: NOP
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02E00000"
|
||||
|
||||
# 0x02F: MOV R00, 0x07
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02F03070"
|
||||
|
||||
# 0x030: XOUT (R00), 0x02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03025020"
|
||||
|
||||
# 0x031: MOV R00, 0x02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03103020"
|
||||
|
||||
# 0x032: CALL 0x05F
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0323B05F"
|
||||
|
||||
# 0x033: MOVC R00, (0x00)
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0330A000"
|
||||
|
||||
# 0x034: INC R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03411010"
|
||||
|
||||
# 0x035: MOVC (0x00), R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0350D000"
|
||||
|
||||
# 0x036: JMP 0x020
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03630020"
|
||||
|
||||
# 0x037: CALL 0x058
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0373B058"
|
||||
|
||||
# 0x038: MOV R00, 0x00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03803000"
|
||||
|
||||
# 0x039: MOVC (0x00), R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0390D000"
|
||||
|
||||
# 0x03A: XIN R00, (0x08)
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03A28080"
|
||||
|
||||
# 0x03B: CMP R00, 0x08
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03B0F080"
|
||||
|
||||
# 0x03C: JEQ 0x052
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03C39052"
|
||||
|
||||
# 0x03D: MOV R00, 0x07
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03D03070"
|
||||
|
||||
# 0x03E: XOUT (R00), 0x01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03E25010"
|
||||
|
||||
# 0x03F: XIN R00, (0x07)
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03F28070"
|
||||
|
||||
# 0x040: AND R00, 0x01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04019010"
|
||||
|
||||
# 0x041: JNZ 0x03F
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0413203F"
|
||||
|
||||
# 0x042: MOVC R01, (0x00)
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0420A001"
|
||||
|
||||
# 0x043: MOV R00, 0x80
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04303800"
|
||||
|
||||
# 0x044: MOV R15, 0x08
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0440308F"
|
||||
|
||||
# 0x045: MOVX R02, (R00)
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04504002"
|
||||
|
||||
# 0x046: CMP R02, R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0460E012"
|
||||
|
||||
# 0x047: JNE 0x053
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0473A053"
|
||||
|
||||
# 0x048: INC R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04811010"
|
||||
|
||||
# 0x049: INC R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04911011"
|
||||
|
||||
# 0x04A: DEC R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04A1501F"
|
||||
|
||||
# 0x04B: JNZ 0x045
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04B32045"
|
||||
|
||||
# 0x04C: MOV R00, 0x02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04C03020"
|
||||
|
||||
# 0x04D: CALL 0x05F
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04D3B05F"
|
||||
|
||||
# 0x04E: MOVC R00, (0x00)
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04E0A000"
|
||||
|
||||
# 0x04F: INC R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04F11010"
|
||||
|
||||
# 0x050: MOVC (0x00), R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0500D000"
|
||||
|
||||
# 0x051: JMP 0x03A
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0513003A"
|
||||
|
||||
# 0x052: JMP 0x057
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05230057"
|
||||
|
||||
# 0x053: XIN R00, (0x04)
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05328040"
|
||||
|
||||
# 0x054: OR R00, 0x10
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0541B100"
|
||||
|
||||
# 0x055: XOUT (0x04), R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05524040"
|
||||
|
||||
# 0x056: JMP 0x057
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05630057"
|
||||
|
||||
# 0x057: JMP 0x057
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05730057"
|
||||
|
||||
# 0x058: PUSH R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0583C000"
|
||||
|
||||
# 0x059: MOV R00, 0x00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05903000"
|
||||
|
||||
# 0x05A: XOUT (0x08), R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05A24080"
|
||||
|
||||
# 0x05B: XOUT (0x09), R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05B24090"
|
||||
|
||||
# 0x05C: XOUT (0x0A), R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05C240A0"
|
||||
|
||||
# 0x05D: POP R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05D3D000"
|
||||
|
||||
# 0x05E: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05E3E000"
|
||||
|
||||
# 0x05F: PUSH R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05F3C001"
|
||||
|
||||
# 0x060: PUSH R02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0603C002"
|
||||
|
||||
# 0x061: PUSH R03
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0613C003"
|
||||
|
||||
# 0x062: XIN R01, (0x08)
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06228081"
|
||||
|
||||
# 0x063: XIN R02, (0x09)
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06328092"
|
||||
|
||||
# 0x064: XIN R03, (0x0A)
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "064280A3"
|
||||
|
||||
# 0x065: ADD R01, R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06510001"
|
||||
|
||||
# 0x066: ADDC R02, 0x00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06613002"
|
||||
|
||||
# 0x067: ADDC R03, 0x00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06713003"
|
||||
|
||||
# 0x068: XOUT (0x08), R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06824081"
|
||||
|
||||
# 0x069: XOUT (0x09), R02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06924092"
|
||||
|
||||
# 0x06A: XOUT (0x0A), R03
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06A240A3"
|
||||
|
||||
# 0x06B: POP R03
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06B3D003"
|
||||
|
||||
# 0x06C: POP R02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06C3D002"
|
||||
|
||||
# 0x06D: POP R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06D3D001"
|
||||
|
||||
# 0x06E: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06E3E000"
|
||||
|
||||
# Assembled from sdr_test_short.jsm
|
||||
# ---------------------------------------------------------------
|
||||
# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA
|
||||
# User 2
|
||||
set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C3"]
|
||||
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0000"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0100"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0200"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0300"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0400"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0500"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0600"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0700"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0800"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0900"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0A00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0B00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0C00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0D00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0E00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0F00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1000"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1100"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1200"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1300"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1400"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1500"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1600"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1700"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1800"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1900"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1A00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1B00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1C00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1D00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1E00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1F00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2000"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2100"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2200"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2300"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2400"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2500"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2600"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2700"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2800"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2900"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2A00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2B00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2C00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2D00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2E00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2F00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3000"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3100"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3200"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3300"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3400"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3500"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3600"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3700"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3800"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3900"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3A00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3B00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3C00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3D00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3E00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3F00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4000"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4100"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4200"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4300"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4400"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4500"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4600"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4700"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4800"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4900"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4A00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4B00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4C00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4D00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4E00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4F00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5000"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5100"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5200"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5300"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5400"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5500"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5600"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5700"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5800"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5900"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5A00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5B00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5C00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5D00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5E00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5F00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6000"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6100"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6200"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6300"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6400"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6500"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6600"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6700"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6800"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6900"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6A00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6B00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6C00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6D00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6E00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6F00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7000"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7100"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7200"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7300"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7400"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7500"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7600"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7700"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7800"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7900"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7A00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7B00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7C00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7D00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7E00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7F00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8000"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8100"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8200"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8300"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8400"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8500"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8600"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8700"
|
||||
|
||||
::chipscope::csejtag_target unlock $handle
|
||||
::chipscope::csejtag_target close $handle
|
||||
::chipscope::csejtag_session destroy $handle
|
||||
exit
|
||||
@@ -0,0 +1,62 @@
|
||||
# ----------------------------------------------------------------------
|
||||
# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
# This file: The ROM file for upload to target over JTAG
|
||||
|
||||
# Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
# This library is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU Lesser General Public
|
||||
# License as published by the Free Software Foundation; either
|
||||
# version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
# This library is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
# Lesser General Public License for more details.
|
||||
|
||||
# You should have received a copy of the GNU Lesser General Public
|
||||
# License along with this library; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
# For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
# ---------------------------------------------------------------------
|
||||
|
||||
# ---------------------------------------------------------------------
|
||||
# For Chipscope 9.1
|
||||
# ---------------------------------------------------------------------
|
||||
# Source JTAG/TCL frame work
|
||||
cd $env(CHIPSCOPE)\\bin\\nt
|
||||
source csejtag.tcl
|
||||
|
||||
namespace import ::chipscope::*
|
||||
|
||||
# Platform USB Cable
|
||||
set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
|
||||
# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
|
||||
|
||||
# Create session
|
||||
set handle [::chipscope::csejtag_session create 0]
|
||||
|
||||
# Open JTAG and lock
|
||||
set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
|
||||
set lock_result [::chipscope::csejtag_target lock $handle 1000]
|
||||
|
||||
set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
|
||||
|
||||
# Get Device ID
|
||||
set devtype "Virtex-4SX"
|
||||
set devid 2
|
||||
set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
|
||||
set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
|
||||
|
||||
set CSE_OP $CSEJTAG_SHIFT_READWRITE
|
||||
set CSE_ES $CSEJTAG_RUN_TEST_IDLE
|
||||
|
||||
# Write Program
|
||||
# JASM_ROM_INSERT_HERE
|
||||
|
||||
::chipscope::csejtag_target unlock $handle
|
||||
::chipscope::csejtag_target close $handle
|
||||
::chipscope::csejtag_session destroy $handle
|
||||
exit
|
||||
@@ -0,0 +1,472 @@
|
||||
; -------------------------------------------------
|
||||
; Register definitions
|
||||
; -------------------------------------------------
|
||||
include "../../../lib/jasm/cregs.inc.jsm"
|
||||
include "xregs.inc.jsm"
|
||||
|
||||
; -------------------------------------------------
|
||||
; Constants
|
||||
; -------------------------------------------------
|
||||
BURST_LEN: equ 8
|
||||
SD_CMD_WRITE: equ 0x06
|
||||
SD_CMD_READ: equ 0x05
|
||||
addr_msb_max: equ 0xFF
|
||||
|
||||
; External RAM/ROM
|
||||
xmem
|
||||
crlf: dc 13, 10, 0
|
||||
greet_txt: dc "SDRAM Test", 0
|
||||
msg_txt0: dc "Clearing SDRAM", 0
|
||||
msg_txt1: dc "Writing SDRAM", 0
|
||||
msg_txt2: dc "Reading SDRAM", 0
|
||||
verify_ok: dc "Verify OK", 0
|
||||
verify_nok: dc "Failed at ", 0
|
||||
dot: dc ".", 0
|
||||
|
||||
org 0x80
|
||||
sdram_data: db 8 ; SDRAM data window at X:0x80
|
||||
|
||||
; Internal RAM
|
||||
cmem 0
|
||||
round: db 1
|
||||
bmp_offset: db 4
|
||||
|
||||
; -------------------------------------------------
|
||||
; Program
|
||||
; -------------------------------------------------
|
||||
code
|
||||
reset: org 0x000
|
||||
jmp main
|
||||
|
||||
; -------------------------------------------------
|
||||
; ISR
|
||||
; -------------------------------------------------
|
||||
org 0x001
|
||||
push R0
|
||||
xin R0, (ctrl_reg)
|
||||
or R0, 0x10
|
||||
xout (ctrl_reg), R0
|
||||
pop R0
|
||||
reti
|
||||
|
||||
; -------------------------------------------------
|
||||
; Main
|
||||
; -------------------------------------------------
|
||||
main:
|
||||
call LCD_init
|
||||
mov R0, 0x00
|
||||
xout (led_port), R0
|
||||
|
||||
mov R0, CTRL_VGA_ENABLE
|
||||
xout (ctrl_reg), R0
|
||||
|
||||
|
||||
cin R0, (cpu_int_ctrl)
|
||||
or R0, 0x05
|
||||
cout (cpu_int_ctrl), R0
|
||||
|
||||
; Clear LCD
|
||||
mov R0, LCD_CMD_CLEAR
|
||||
call LCD_writecmd
|
||||
|
||||
mov R0, 0
|
||||
mov R1, 0xC0
|
||||
xout (reg_color_red), R1
|
||||
xout (reg_color_grn), R1
|
||||
xout (reg_color_blu), R1
|
||||
|
||||
call cg_wait_rdy
|
||||
call cg_clr_screen
|
||||
|
||||
; Print greeting message
|
||||
mov R1, greet_txt
|
||||
call LCD_putsx
|
||||
|
||||
mov R1, greet_txt
|
||||
call cg_puts
|
||||
mov R1, crlf
|
||||
call cg_puts_clr
|
||||
|
||||
xin R0, (ctrl_reg)
|
||||
or R0, 0x10
|
||||
xout (ctrl_reg), R0
|
||||
call delay100ms
|
||||
or R0, 0x20
|
||||
xout (ctrl_reg), R0
|
||||
call delay100ms
|
||||
and R0, 0xEF
|
||||
xout (ctrl_reg), R0
|
||||
call delay100ms
|
||||
and R0, 0xCF
|
||||
xout (ctrl_reg), R0
|
||||
|
||||
; ----------------------------------------------------------
|
||||
; SDRAM clear
|
||||
; ----------------------------------------------------------
|
||||
do_clear:
|
||||
; Clear LCD
|
||||
mov R0, LCD_CMD_CLEAR
|
||||
call LCD_writecmd
|
||||
|
||||
; Print Clear message
|
||||
mov R1, msg_txt0
|
||||
call LCD_putsx
|
||||
|
||||
mov R1, msg_txt0
|
||||
call cg_clr_puts
|
||||
mov R1, crlf
|
||||
call cg_puts_clr
|
||||
|
||||
; Set SDRAM address register to 0
|
||||
call AddrCnt_Init
|
||||
|
||||
; Fill SDR Buffer with zeros
|
||||
mov R0, sdram_data
|
||||
mov R15, 8
|
||||
buf_clr_loop: movx (R0), 0
|
||||
inc R0
|
||||
dec R15
|
||||
jnz buf_clr_loop
|
||||
|
||||
sdr_clear: xin R0, (sdram_addr+2)
|
||||
cmp R0, addr_msb_max
|
||||
jeq clear_finished
|
||||
|
||||
mov R2, BURST_LEN
|
||||
|
||||
poll_clear_full:
|
||||
xin R0, (sdram_reg)
|
||||
xout (led_port), R0
|
||||
and R0, FIFO_STAT_WRITE_DATA_FULL
|
||||
jnz poll_clear_full
|
||||
|
||||
; Fill FIFO
|
||||
mov R0, FIFO_CTRL_IS_WRITE
|
||||
xout (sdram_reg), R0
|
||||
|
||||
sub R2, 2
|
||||
jnz poll_clear_full
|
||||
|
||||
; Start SDR write
|
||||
call wait_cmd_rdy
|
||||
mov R0, SD_CMD_WRITE
|
||||
xout (sdram_reg), R0
|
||||
|
||||
; Advance address counter
|
||||
mov R0, BURST_LEN
|
||||
call AddrCnt_Adv
|
||||
|
||||
jmp sdr_clear
|
||||
|
||||
clear_finished:
|
||||
call AddrCnt_Disp
|
||||
call delay1s
|
||||
jmp do_write
|
||||
|
||||
; ----------------------------------------------------------
|
||||
; SDRAM Write
|
||||
; ----------------------------------------------------------
|
||||
do_write:
|
||||
; Clear LCD
|
||||
mov R0, LCD_CMD_CLEAR
|
||||
call LCD_writecmd
|
||||
|
||||
; Print Write message
|
||||
mov R1, msg_txt1
|
||||
call LCD_putsx
|
||||
|
||||
mov R1, msg_txt1
|
||||
call cg_clr_puts
|
||||
mov R1, crlf
|
||||
call cg_puts_clr
|
||||
|
||||
; Set SDRAM address register to 0
|
||||
call AddrCnt_Init
|
||||
mov R0, 0
|
||||
movc (round), R0
|
||||
|
||||
sdr_write: xin R0, (sdram_addr+2)
|
||||
cmp R0, addr_msb_max
|
||||
jeq write_finished
|
||||
|
||||
mov R2, BURST_LEN
|
||||
|
||||
; Fill SDR Buffer
|
||||
sdr_burst_wr: movc R1, (round)
|
||||
; xin R0, (sdram_addr+2)
|
||||
; cmp R0, 0x7F
|
||||
; jne force_no_err
|
||||
; inc R1
|
||||
force_no_err: mov R0, sdram_data
|
||||
mov R15, 8
|
||||
write_loop: movx (R0), R1
|
||||
inc R0
|
||||
inc R1
|
||||
dec R15
|
||||
jnz write_loop
|
||||
|
||||
poll_write_full:
|
||||
xin R0, (sdram_reg)
|
||||
xout (led_port), R0
|
||||
and R0, FIFO_STAT_WRITE_DATA_FULL
|
||||
jnz poll_write_full
|
||||
|
||||
; Fill FIFO
|
||||
mov R0, FIFO_CTRL_IS_WRITE
|
||||
xout (sdram_reg), R0
|
||||
|
||||
movc R0, (round)
|
||||
inc R0
|
||||
movc (round), R0
|
||||
|
||||
sub R2, 2
|
||||
jnz sdr_burst_wr
|
||||
|
||||
; Start SDR write
|
||||
call wait_cmd_rdy
|
||||
mov R0, SD_CMD_WRITE
|
||||
xout (sdram_reg), R0
|
||||
|
||||
; Advance address counter
|
||||
mov R0, BURST_LEN
|
||||
call AddrCnt_Adv
|
||||
|
||||
jmp sdr_write
|
||||
|
||||
write_finished: call AddrCnt_Disp
|
||||
call delay1s
|
||||
|
||||
; ----------------------------------------------------------
|
||||
; SDRAM Verify
|
||||
; ----------------------------------------------------------
|
||||
do_read:
|
||||
; Clear LCD
|
||||
mov R0, LCD_CMD_CLEAR
|
||||
call LCD_writecmd
|
||||
|
||||
; Print Read message
|
||||
mov R1, msg_txt2
|
||||
call LCD_putsx
|
||||
|
||||
mov R1, msg_txt2
|
||||
call cg_clr_puts
|
||||
mov R1, crlf
|
||||
call cg_puts_clr
|
||||
|
||||
; Set SDRAM address register to 0
|
||||
call AddrCnt_Init
|
||||
mov R0, 0
|
||||
movc (round), R0
|
||||
|
||||
sdr_read: xin R0, (sdram_addr+2)
|
||||
cmp R0, addr_msb_max
|
||||
jeq read_finished
|
||||
|
||||
; Start SDR read
|
||||
call wait_cmd_rdy
|
||||
mov R0, SD_CMD_READ
|
||||
xout (sdram_reg), R0
|
||||
|
||||
; mov R0, LCD_CMD_Z1
|
||||
; call LCD_writecmd
|
||||
; call print_addr
|
||||
; mov R0, LCD_CMD_Z2
|
||||
; call LCD_writecmd
|
||||
; call print_data
|
||||
|
||||
mov R3, BURST_LEN
|
||||
|
||||
; Wait last read
|
||||
poll_read_fin: xin R0, (sdram_reg)
|
||||
xout (led_port), R0
|
||||
and R0, FIFO_STAT_READ_DATA_EMPTY
|
||||
jnz poll_read_fin
|
||||
|
||||
; Verify SDR Buffer
|
||||
movc R1, (round)
|
||||
mov R0, sdram_data
|
||||
mov R15, 8
|
||||
read_loop: movx R2, (R0)
|
||||
cmp R2, R1
|
||||
jne verify_error
|
||||
inc R0
|
||||
inc R1
|
||||
dec R15
|
||||
jnz read_loop
|
||||
|
||||
; Advance Read-FIFO
|
||||
mov R0, FIFO_CTRL_IS_READ
|
||||
xout (sdram_reg), R0
|
||||
|
||||
movc R0, (round)
|
||||
inc R0
|
||||
movc (round), R0
|
||||
|
||||
sub R3, 2
|
||||
jnz poll_read_fin
|
||||
|
||||
; Advance address counter
|
||||
mov R0, BURST_LEN
|
||||
call AddrCnt_Adv
|
||||
jmp sdr_read
|
||||
|
||||
; ----------------------------------------------------------
|
||||
sd_request: push R0
|
||||
mov R0, SDRAM_CTRL_REQUEST
|
||||
xout (sdram_reg), R0
|
||||
wait4grant: xin R0, (sdram_reg)
|
||||
xout (led_port), R0
|
||||
and R0, SDRAM_STAT_ACCESS
|
||||
jz wait4grant
|
||||
pop R0
|
||||
ret
|
||||
|
||||
; ----------------------------------------------------------
|
||||
wait_cmd_rdy: call sd_request
|
||||
push R0
|
||||
wait4cmd: xin R0, (sdram_reg)
|
||||
xout (led_port), R0
|
||||
and R0, FIFO_STAT_CMD_FULL
|
||||
jnz wait4cmd
|
||||
pop R0
|
||||
ret
|
||||
|
||||
; ----------------------------------------------------------
|
||||
read_finished:
|
||||
no_error: mov R0, LCD_CMD_CLEAR
|
||||
call LCD_writecmd
|
||||
mov R1, verify_ok
|
||||
call LCD_putsx
|
||||
mov R0, LCD_CMD_Z2
|
||||
call LCD_writecmd
|
||||
call print_addr
|
||||
|
||||
mov R1, verify_ok
|
||||
call cg_clr_puts
|
||||
mov R1, crlf
|
||||
call cg_puts_clr
|
||||
|
||||
jmp ende
|
||||
|
||||
verify_error: mov R0, LCD_CMD_CLEAR
|
||||
call LCD_writecmd
|
||||
mov R1, verify_nok
|
||||
call LCD_putsx
|
||||
call print_addr
|
||||
call print_data
|
||||
mov R1, verify_nok
|
||||
call cg_clr_puts
|
||||
mov R1, crlf
|
||||
call cg_puts_clr
|
||||
|
||||
jmp ende
|
||||
|
||||
ende: call delay1s
|
||||
jmp do_clear
|
||||
|
||||
; -------------------------------------------------
|
||||
AddrCnt_Init: push R0
|
||||
mov R0, 0x00
|
||||
xout (sdram_addr+0), R0
|
||||
xout (sdram_addr+1), R0
|
||||
xout (sdram_addr+2), R0
|
||||
pop R0
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; Parameter
|
||||
; R0: increment value
|
||||
AddrCnt_Adv: push R1
|
||||
push R2
|
||||
push R3
|
||||
xin R1, (sdram_addr+0)
|
||||
xin R2, (sdram_addr+1)
|
||||
xin R3, (sdram_addr+2)
|
||||
add R1, R0
|
||||
addc R2, 0
|
||||
addc R3, 0
|
||||
xout (sdram_addr+0), R1
|
||||
xout (sdram_addr+1), R2
|
||||
xout (sdram_addr+2), R3
|
||||
pop R3
|
||||
pop R2
|
||||
pop R1
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; Display Address counter
|
||||
AddrCnt_Disp: mov R0, LCD_CMD_Z2
|
||||
call LCD_writecmd
|
||||
call print_addr
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; PutHexByte
|
||||
; R0 : Byte value
|
||||
PutHexByte: push R1
|
||||
call bin2hex
|
||||
call LCD_writechar
|
||||
mov R0, R1
|
||||
call LCD_writechar
|
||||
pop R1
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
print_addr: push R0
|
||||
xin R0, (sdram_addr+2)
|
||||
call PutHexByte
|
||||
xin R0, (sdram_addr+1)
|
||||
call PutHexByte
|
||||
xin R0, (sdram_addr+0)
|
||||
call PutHexByte
|
||||
pop R0
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; R1 : ptr to byte array
|
||||
print_dword: push R0
|
||||
add R1, 3
|
||||
movc R0, (R1)
|
||||
call PutHexByte
|
||||
dec R1
|
||||
movc R0, (R1)
|
||||
call PutHexByte
|
||||
dec R1
|
||||
movc R0, (R1)
|
||||
call PutHexByte
|
||||
dec R1
|
||||
movc R0, (R1)
|
||||
call PutHexByte
|
||||
pop R0
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
print_data: push R0
|
||||
mov R0, LCD_CMD_Z2
|
||||
call LCD_writecmd
|
||||
movx R0, (sdram_data+7)
|
||||
call PutHexByte
|
||||
movx R0, (sdram_data+6)
|
||||
call PutHexByte
|
||||
movx R0, (sdram_data+5)
|
||||
call PutHexByte
|
||||
movx R0, (sdram_data+4)
|
||||
call PutHexByte
|
||||
movx R0, (sdram_data+3)
|
||||
call PutHexByte
|
||||
movx R0, (sdram_data+2)
|
||||
call PutHexByte
|
||||
movx R0, (sdram_data+1)
|
||||
call PutHexByte
|
||||
movx R0, (sdram_data+0)
|
||||
call PutHexByte
|
||||
pop R0
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
include "../../../lib/jasm/utils.inc.jsm"
|
||||
include "../../../lib/jasm/lcd.inc.jsm"
|
||||
include "../../../lib/jasm/cg.inc.jsm"
|
||||
include "../../../lib/jasm/delays.inc.jsm"
|
||||
include "../../../lib/jasm/uart.inc.jsm"
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,308 @@
|
||||
; -------------------------------------------------
|
||||
; Register definitions
|
||||
; -------------------------------------------------
|
||||
include "../../../lib/jasm/cregs.inc.jsm"
|
||||
include "xregs.inc.jsm"
|
||||
|
||||
; -------------------------------------------------
|
||||
; Constants
|
||||
; -------------------------------------------------
|
||||
BURST_LEN: equ 8
|
||||
SD_CMD_WRITE: equ 0x06
|
||||
SD_CMD_READ: equ 0x05
|
||||
addr_msb_max: equ 0x40
|
||||
|
||||
; External RAM/ROM
|
||||
xmem
|
||||
crlf: dc 13, 10, 0
|
||||
greet_txt: dc "SDRAM Test", 0
|
||||
msg_txt0: dc "Clearing SDRAM", 0
|
||||
msg_txt1: dc "Writing SDRAM", 0
|
||||
msg_txt2: dc "Reading SDRAM", 0
|
||||
verify_ok: dc "Verify OK", 0
|
||||
verify_nok: dc "Failed at ", 0
|
||||
dot: dc ".", 0
|
||||
|
||||
org 0x80
|
||||
sdram_data: db 8 ; SDRAM data window at X:0x80
|
||||
|
||||
; Internal RAM
|
||||
cmem 0
|
||||
round: db 1
|
||||
|
||||
; -------------------------------------------------
|
||||
; Program
|
||||
; -------------------------------------------------
|
||||
code
|
||||
reset: org 0x000
|
||||
jmp main
|
||||
|
||||
; -------------------------------------------------
|
||||
; ISR
|
||||
; -------------------------------------------------
|
||||
org 0x001
|
||||
reti
|
||||
|
||||
; -------------------------------------------------
|
||||
; Main
|
||||
; -------------------------------------------------
|
||||
main:
|
||||
mov R0, 0x00
|
||||
xout (led_port), R0
|
||||
|
||||
; xin R0, (btn_port)
|
||||
; tst R0
|
||||
; jz no_vga
|
||||
mov R0, CTRL_VGA_ENABLE
|
||||
xout (ctrl_reg), R0
|
||||
|
||||
|
||||
no_vga: mov R0, 0
|
||||
mov R1, 0x80
|
||||
xout (reg_color_red), R0
|
||||
xout (reg_color_grn), R1
|
||||
xout (reg_color_blu), R0
|
||||
|
||||
jmp do_write
|
||||
|
||||
; ----------------------------------------------------------
|
||||
; SDRAM clear
|
||||
; ----------------------------------------------------------
|
||||
|
||||
; Set SDRAM address register to 0
|
||||
do_clear: call AddrCnt_Init
|
||||
|
||||
; Fill SDR Buffer with zeros
|
||||
mov R0, sdram_data
|
||||
mov R15, 8
|
||||
buf_clr_loop: movx (R0), 0
|
||||
inc R0
|
||||
dec R15
|
||||
jnz buf_clr_loop
|
||||
|
||||
sdr_clear: xin R0, (sdram_addr+0)
|
||||
cmp R0, addr_msb_max
|
||||
jeq clear_finished
|
||||
|
||||
mov R2, BURST_LEN
|
||||
|
||||
poll_clear_full:
|
||||
xin R0, (sdram_reg)
|
||||
xout (led_port), R0
|
||||
and R0, FIFO_STAT_WRITE_DATA_FULL
|
||||
jnz poll_clear_full
|
||||
|
||||
; Fill FIFO
|
||||
mov R0, FIFO_CTRL_IS_WRITE
|
||||
xout (sdram_reg), R0
|
||||
|
||||
sub R2, 2
|
||||
jnz poll_clear_full
|
||||
|
||||
; Start SDR write
|
||||
call wait_cmd_rdy
|
||||
mov R0, SD_CMD_WRITE
|
||||
xout (sdram_reg), R0
|
||||
|
||||
; Advance address counter
|
||||
mov R0, BURST_LEN
|
||||
call AddrCnt_Adv
|
||||
|
||||
jmp sdr_clear
|
||||
|
||||
clear_finished:
|
||||
call AddrCnt_Disp
|
||||
|
||||
; ----------------------------------------------------------
|
||||
; SDRAM Write
|
||||
; ----------------------------------------------------------
|
||||
do_write: ; Clear LCD
|
||||
|
||||
|
||||
; Set SDRAM address register to 0
|
||||
call AddrCnt_Init
|
||||
mov R0, 0
|
||||
movc (round), R0
|
||||
|
||||
sdr_write: xin R0, (sdram_addr+0)
|
||||
cmp R0, addr_msb_max
|
||||
jeq write_finished
|
||||
|
||||
mov R2, BURST_LEN
|
||||
|
||||
; Fill SDR Buffer
|
||||
sdr_burst_wr: movc R1, (round)
|
||||
; xin R0, (sdram_addr+2)
|
||||
; cmp R0, 0x7F
|
||||
; jne force_no_err
|
||||
; inc R1
|
||||
force_no_err: mov R0, sdram_data
|
||||
mov R15, 8
|
||||
write_loop: movx (R0), R1
|
||||
inc R0
|
||||
inc R1
|
||||
dec R15
|
||||
jnz write_loop
|
||||
|
||||
poll_write_full:
|
||||
xin R0, (sdram_reg)
|
||||
xout (led_port), R0
|
||||
and R0, FIFO_STAT_WRITE_DATA_FULL
|
||||
jnz poll_write_full
|
||||
|
||||
; Fill FIFO
|
||||
mov R0, FIFO_CTRL_IS_WRITE
|
||||
xout (sdram_reg), R0
|
||||
|
||||
movc R0, (round)
|
||||
inc R0
|
||||
movc (round), R0
|
||||
|
||||
sub R2, 2
|
||||
jnz sdr_burst_wr
|
||||
|
||||
; Start SDR write
|
||||
call wait_cmd_rdy
|
||||
mov R0, SD_CMD_WRITE
|
||||
xout (sdram_reg), R0
|
||||
|
||||
; Advance address counter
|
||||
mov R0, BURST_LEN
|
||||
call AddrCnt_Adv
|
||||
|
||||
jmp sdr_write
|
||||
|
||||
write_finished: call AddrCnt_Disp
|
||||
|
||||
; ----------------------------------------------------------
|
||||
; SDRAM Verify
|
||||
; ----------------------------------------------------------
|
||||
do_read: ; Clear LCD
|
||||
|
||||
; Set SDRAM address register to 0
|
||||
call AddrCnt_Init
|
||||
mov R0, 0
|
||||
movc (round), R0
|
||||
|
||||
sdr_read: xin R0, (sdram_addr+2)
|
||||
cmp R0, addr_msb_max
|
||||
jeq read_finished
|
||||
|
||||
; Start SDR read
|
||||
call wait_cmd_rdy
|
||||
mov R0, SD_CMD_READ
|
||||
xout (sdram_reg), R0
|
||||
|
||||
|
||||
mov R3, BURST_LEN
|
||||
|
||||
; Wait last read
|
||||
poll_read_fin: xin R0, (sdram_reg)
|
||||
xout (led_port), R0
|
||||
and R0, FIFO_STAT_READ_DATA_EMPTY
|
||||
jnz poll_read_fin
|
||||
|
||||
; Verify SDR Buffer
|
||||
movc R1, (round)
|
||||
mov R0, sdram_data
|
||||
mov R15, 8
|
||||
read_loop: movx R2, (R0)
|
||||
cmp R2, R1
|
||||
jne verify_error
|
||||
inc R0
|
||||
inc R1
|
||||
dec R15
|
||||
jnz read_loop
|
||||
|
||||
; Advance Read-FIFO
|
||||
mov R0, FIFO_CTRL_IS_READ
|
||||
xout (sdram_reg), R0
|
||||
|
||||
movc R0, (round)
|
||||
inc R0
|
||||
movc (round), R0
|
||||
|
||||
sub R3, 2
|
||||
jnz poll_read_fin
|
||||
|
||||
; Advance address counter
|
||||
mov R0, BURST_LEN
|
||||
call AddrCnt_Adv
|
||||
jmp sdr_read
|
||||
|
||||
; ----------------------------------------------------------
|
||||
sd_request: push R0
|
||||
mov R0, SDRAM_CTRL_REQUEST
|
||||
xout (sdram_reg), R0
|
||||
wait4grant: xin R0, (sdram_reg)
|
||||
xout (led_port), R0
|
||||
and R0, SDRAM_STAT_ACCESS
|
||||
jz wait4grant
|
||||
pop R0
|
||||
ret
|
||||
|
||||
; ----------------------------------------------------------
|
||||
wait_cmd_rdy: call sd_request
|
||||
push R0
|
||||
wait4cmd: xin R0, (sdram_reg)
|
||||
xout (led_port), R0
|
||||
and R0, FIFO_STAT_CMD_FULL
|
||||
jnz wait4cmd
|
||||
pop R0
|
||||
ret
|
||||
|
||||
; ----------------------------------------------------------
|
||||
read_finished:
|
||||
no_error: jmp ende
|
||||
|
||||
verify_error: jmp ende
|
||||
|
||||
ende: jmp do_clear
|
||||
|
||||
; -------------------------------------------------
|
||||
AddrCnt_Init: push R0
|
||||
mov R0, 0x00
|
||||
xout (sdram_addr+0), R0
|
||||
xout (sdram_addr+1), R0
|
||||
xout (sdram_addr+2), R0
|
||||
pop R0
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; Parameter
|
||||
; R0: increment value
|
||||
AddrCnt_Adv: push R1
|
||||
push R2
|
||||
push R3
|
||||
xin R1, (sdram_addr+0)
|
||||
xin R2, (sdram_addr+1)
|
||||
xin R3, (sdram_addr+2)
|
||||
add R1, R0
|
||||
addc R2, 0
|
||||
addc R3, 0
|
||||
xout (sdram_addr+0), R1
|
||||
xout (sdram_addr+1), R2
|
||||
xout (sdram_addr+2), R3
|
||||
pop R3
|
||||
pop R2
|
||||
pop R1
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; Display Address counter
|
||||
AddrCnt_Disp: ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; PutHexByte
|
||||
; R0 : Byte value
|
||||
PutHexByte: ret
|
||||
|
||||
; -------------------------------------------------
|
||||
print_addr: ret
|
||||
|
||||
; -------------------------------------------------
|
||||
print_data: ret
|
||||
|
||||
; -------------------------------------------------
|
||||
include "../../../lib/jasm/utils.inc.jsm"
|
||||
|
||||
@@ -0,0 +1,704 @@
|
||||
# ----------------------------------------------------------------------
|
||||
# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
# This file: The ROM file for upload to target over JTAG
|
||||
#
|
||||
# Copyright (C) 2007 J. Ahrensfeld
|
||||
#
|
||||
# This program is free software: you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation, either version 3 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# For questions and ideas, please contact the author at jens@jayfield.org
|
||||
#
|
||||
# ---------------------------------------------------------------------
|
||||
|
||||
# ---------------------------------------------------------------------
|
||||
# For Chipscope 9.1
|
||||
# ---------------------------------------------------------------------
|
||||
# Source JTAG/TCL frame work
|
||||
cd $env(CHIPSCOPE)\\bin\\nt
|
||||
source csejtag.tcl
|
||||
|
||||
namespace import ::chipscope::*
|
||||
|
||||
# Platform USB Cable
|
||||
set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
|
||||
# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
|
||||
|
||||
# Create session
|
||||
set handle [::chipscope::csejtag_session create 0]
|
||||
|
||||
# Open JTAG and lock
|
||||
set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
|
||||
set lock_result [::chipscope::csejtag_target lock $handle 1000]
|
||||
|
||||
set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
|
||||
|
||||
# Get Device ID
|
||||
set devtype "Virtex-4SX"
|
||||
set devid 2
|
||||
set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
|
||||
set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
|
||||
|
||||
set CSE_OP $CSEJTAG_SHIFT_READWRITE
|
||||
set CSE_ES $CSEJTAG_RUN_TEST_IDLE
|
||||
|
||||
# Write Program
|
||||
# JASM_ROM_INSERT_HERE
|
||||
# Assembled from sdram_test_short.jsm
|
||||
# ---------------------------------------------------------------
|
||||
# Shift the USER2 Instruction (b1111000010) into the Instruction Register of FPGA
|
||||
# User 1
|
||||
set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C2"]
|
||||
|
||||
# 0x000: JMP 0x002
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00030002"
|
||||
|
||||
# 0x001: RETI
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0013F000"
|
||||
|
||||
# 0x002: MOV R00, 0x00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00203000"
|
||||
|
||||
# 0x003: XOUT (0x01), R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00324010"
|
||||
|
||||
# 0x004: MOV R00, 0x04
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00403040"
|
||||
|
||||
# 0x005: XOUT (0x04), R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00524040"
|
||||
|
||||
# 0x006: MOV R00, 0x00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00603000"
|
||||
|
||||
# 0x007: MOV R01, 0x80
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00703801"
|
||||
|
||||
# 0x008: XOUT (0x10), R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00824100"
|
||||
|
||||
# 0x009: XOUT (0x11), R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00924111"
|
||||
|
||||
# 0x00A: XOUT (0x12), R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00A24120"
|
||||
|
||||
# 0x00B: JMP 0x026
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00B30026"
|
||||
|
||||
# 0x00C: CALL 0x07D
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00C3B07D"
|
||||
|
||||
# 0x00D: MOV R00, 0x80
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00D03800"
|
||||
|
||||
# 0x00E: MOV R15, 0x08
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00E0308F"
|
||||
|
||||
# 0x00F: MOVX (R00), 0x00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00F07000"
|
||||
|
||||
# 0x010: INC R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01011010"
|
||||
|
||||
# 0x011: DEC R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0111501F"
|
||||
|
||||
# 0x012: JNZ 0x00F
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0123200F"
|
||||
|
||||
# 0x013: XIN R00, (0x08)
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01328080"
|
||||
|
||||
# 0x014: CMP R00, 0x40
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0140F400"
|
||||
|
||||
# 0x015: JEQ 0x025
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01539025"
|
||||
|
||||
# 0x016: MOV R02, 0x08
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01603082"
|
||||
|
||||
# 0x017: XIN R00, (0x07)
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01728070"
|
||||
|
||||
# 0x018: XOUT (0x01), R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01824010"
|
||||
|
||||
# 0x019: AND R00, 0x04
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01919040"
|
||||
|
||||
# 0x01A: JNZ 0x017
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01A32017"
|
||||
|
||||
# 0x01B: MOV R00, 0x10
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01B03100"
|
||||
|
||||
# 0x01C: XOUT (0x07), R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01C24070"
|
||||
|
||||
# 0x01D: SUB R02, 0x02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01D15022"
|
||||
|
||||
# 0x01E: JNZ 0x017
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01E32017"
|
||||
|
||||
# 0x01F: CALL 0x072
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01F3B072"
|
||||
|
||||
# 0x020: MOV R00, 0x06
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02003060"
|
||||
|
||||
# 0x021: XOUT (0x07), R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02124070"
|
||||
|
||||
# 0x022: MOV R00, 0x08
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02203080"
|
||||
|
||||
# 0x023: CALL 0x084
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0233B084"
|
||||
|
||||
# 0x024: JMP 0x013
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02430013"
|
||||
|
||||
# 0x025: CALL 0x094
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0253B094"
|
||||
|
||||
# 0x026: CALL 0x07D
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0263B07D"
|
||||
|
||||
# 0x027: MOV R00, 0x00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02703000"
|
||||
|
||||
# 0x028: MOVC (0x00), R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0280D000"
|
||||
|
||||
# 0x029: XIN R00, (0x08)
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02928080"
|
||||
|
||||
# 0x02A: CMP R00, 0x40
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02A0F400"
|
||||
|
||||
# 0x02B: JEQ 0x046
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02B39046"
|
||||
|
||||
# 0x02C: MOV R02, 0x08
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02C03082"
|
||||
|
||||
# 0x02D: MOVC R01, (0x00)
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02D0A001"
|
||||
|
||||
# 0x02E: MOV R00, 0x80
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02E03800"
|
||||
|
||||
# 0x02F: MOV R15, 0x08
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02F0308F"
|
||||
|
||||
# 0x030: MOVX (R01), R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03006001"
|
||||
|
||||
# 0x031: INC R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03111010"
|
||||
|
||||
# 0x032: INC R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03211011"
|
||||
|
||||
# 0x033: DEC R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0331501F"
|
||||
|
||||
# 0x034: JNZ 0x030
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03432030"
|
||||
|
||||
# 0x035: XIN R00, (0x07)
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03528070"
|
||||
|
||||
# 0x036: XOUT (0x01), R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03624010"
|
||||
|
||||
# 0x037: AND R00, 0x04
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03719040"
|
||||
|
||||
# 0x038: JNZ 0x035
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03832035"
|
||||
|
||||
# 0x039: MOV R00, 0x10
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03903100"
|
||||
|
||||
# 0x03A: XOUT (0x07), R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03A24070"
|
||||
|
||||
# 0x03B: MOVC R00, (0x00)
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03B0A000"
|
||||
|
||||
# 0x03C: INC R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03C11010"
|
||||
|
||||
# 0x03D: MOVC (0x00), R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03D0D000"
|
||||
|
||||
# 0x03E: SUB R02, 0x02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03E15022"
|
||||
|
||||
# 0x03F: JNZ 0x02D
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03F3202D"
|
||||
|
||||
# 0x040: CALL 0x072
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0403B072"
|
||||
|
||||
# 0x041: MOV R00, 0x06
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04103060"
|
||||
|
||||
# 0x042: XOUT (0x07), R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04224070"
|
||||
|
||||
# 0x043: MOV R00, 0x08
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04303080"
|
||||
|
||||
# 0x044: CALL 0x084
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0443B084"
|
||||
|
||||
# 0x045: JMP 0x029
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04530029"
|
||||
|
||||
# 0x046: CALL 0x094
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0463B094"
|
||||
|
||||
# 0x047: CALL 0x07D
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0473B07D"
|
||||
|
||||
# 0x048: MOV R00, 0x00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04803000"
|
||||
|
||||
# 0x049: MOVC (0x00), R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0490D000"
|
||||
|
||||
# 0x04A: XIN R00, (0x0A)
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04A280A0"
|
||||
|
||||
# 0x04B: CMP R00, 0x40
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04B0F400"
|
||||
|
||||
# 0x04C: JEQ 0x07A
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04C3907A"
|
||||
|
||||
# 0x04D: CALL 0x072
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04D3B072"
|
||||
|
||||
# 0x04E: MOV R00, 0x05
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04E03050"
|
||||
|
||||
# 0x04F: XOUT (0x07), R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04F24070"
|
||||
|
||||
# 0x050: MOV R03, 0x08
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05003083"
|
||||
|
||||
# 0x051: XIN R00, (0x07)
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05128070"
|
||||
|
||||
# 0x052: XOUT (0x01), R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05224010"
|
||||
|
||||
# 0x053: AND R00, 0x20
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05319200"
|
||||
|
||||
# 0x054: JNZ 0x051
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05432051"
|
||||
|
||||
# 0x055: MOVC R01, (0x00)
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0550A001"
|
||||
|
||||
# 0x056: MOV R00, 0x80
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05603800"
|
||||
|
||||
# 0x057: MOV R15, 0x08
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0570308F"
|
||||
|
||||
# 0x058: MOVX R02, (R00)
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05804002"
|
||||
|
||||
# 0x059: CMP R02, R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0590E012"
|
||||
|
||||
# 0x05A: JNE 0x07B
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05A3A07B"
|
||||
|
||||
# 0x05B: INC R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05B11010"
|
||||
|
||||
# 0x05C: INC R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05C11011"
|
||||
|
||||
# 0x05D: DEC R15
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05D1501F"
|
||||
|
||||
# 0x05E: JNZ 0x058
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05E32058"
|
||||
|
||||
# 0x05F: MOV R00, 0x20
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05F03200"
|
||||
|
||||
# 0x060: XOUT (0x07), R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06024070"
|
||||
|
||||
# 0x061: MOVC R00, (0x00)
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0610A000"
|
||||
|
||||
# 0x062: INC R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06211010"
|
||||
|
||||
# 0x063: MOVC (0x00), R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0630D000"
|
||||
|
||||
# 0x064: SUB R03, 0x02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06415023"
|
||||
|
||||
# 0x065: JNZ 0x051
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06532051"
|
||||
|
||||
# 0x066: MOV R00, 0x08
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06603080"
|
||||
|
||||
# 0x067: CALL 0x084
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0673B084"
|
||||
|
||||
# 0x068: JMP 0x04A
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0683004A"
|
||||
|
||||
# 0x069: PUSH R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0693C000"
|
||||
|
||||
# 0x06A: MOV R00, 0x80
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06A03800"
|
||||
|
||||
# 0x06B: XOUT (0x07), R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06B24070"
|
||||
|
||||
# 0x06C: XIN R00, (0x07)
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06C28070"
|
||||
|
||||
# 0x06D: XOUT (0x01), R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06D24010"
|
||||
|
||||
# 0x06E: AND R00, 0x80
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06E19800"
|
||||
|
||||
# 0x06F: JZ 0x06C
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06F3106C"
|
||||
|
||||
# 0x070: POP R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0703D000"
|
||||
|
||||
# 0x071: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0713E000"
|
||||
|
||||
# 0x072: CALL 0x069
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0723B069"
|
||||
|
||||
# 0x073: PUSH R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0733C000"
|
||||
|
||||
# 0x074: XIN R00, (0x07)
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07428070"
|
||||
|
||||
# 0x075: XOUT (0x01), R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07524010"
|
||||
|
||||
# 0x076: AND R00, 0x01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07619010"
|
||||
|
||||
# 0x077: JNZ 0x074
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07732074"
|
||||
|
||||
# 0x078: POP R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0783D000"
|
||||
|
||||
# 0x079: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0793E000"
|
||||
|
||||
# 0x07A: JMP 0x07C
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07A3007C"
|
||||
|
||||
# 0x07B: JMP 0x07C
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07B3007C"
|
||||
|
||||
# 0x07C: JMP 0x00C
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07C3000C"
|
||||
|
||||
# 0x07D: PUSH R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07D3C000"
|
||||
|
||||
# 0x07E: MOV R00, 0x00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07E03000"
|
||||
|
||||
# 0x07F: XOUT (0x08), R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07F24080"
|
||||
|
||||
# 0x080: XOUT (0x09), R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "08024090"
|
||||
|
||||
# 0x081: XOUT (0x0A), R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "081240A0"
|
||||
|
||||
# 0x082: POP R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0823D000"
|
||||
|
||||
# 0x083: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0833E000"
|
||||
|
||||
# 0x084: PUSH R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0843C001"
|
||||
|
||||
# 0x085: PUSH R02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0853C002"
|
||||
|
||||
# 0x086: PUSH R03
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0863C003"
|
||||
|
||||
# 0x087: XIN R01, (0x08)
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "08728081"
|
||||
|
||||
# 0x088: XIN R02, (0x09)
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "08828092"
|
||||
|
||||
# 0x089: XIN R03, (0x0A)
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "089280A3"
|
||||
|
||||
# 0x08A: ADD R01, R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "08A10001"
|
||||
|
||||
# 0x08B: ADDC R02, 0x00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "08B13002"
|
||||
|
||||
# 0x08C: ADDC R03, 0x00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "08C13003"
|
||||
|
||||
# 0x08D: XOUT (0x08), R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "08D24081"
|
||||
|
||||
# 0x08E: XOUT (0x09), R02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "08E24092"
|
||||
|
||||
# 0x08F: XOUT (0x0A), R03
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "08F240A3"
|
||||
|
||||
# 0x090: POP R03
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0903D003"
|
||||
|
||||
# 0x091: POP R02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0913D002"
|
||||
|
||||
# 0x092: POP R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0923D001"
|
||||
|
||||
# 0x093: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0933E000"
|
||||
|
||||
# 0x094: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0943E000"
|
||||
|
||||
# 0x095: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0953E000"
|
||||
|
||||
# 0x096: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0963E000"
|
||||
|
||||
# 0x097: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0973E000"
|
||||
|
||||
# 0x098: AND R00, 0x0F
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "098190F0"
|
||||
|
||||
# 0x099: CMP R00, 0x0A
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0990F0A0"
|
||||
|
||||
# 0x09A: JLT 0x09C
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09A3509C"
|
||||
|
||||
# 0x09B: ADD R00, 0x07
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09B11070"
|
||||
|
||||
# 0x09C: ADD R00, 0x30
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09C11300"
|
||||
|
||||
# 0x09D: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09D3E000"
|
||||
|
||||
# 0x09E: PUSH R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09E3C000"
|
||||
|
||||
# 0x09F: CALL 0x098
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09F3B098"
|
||||
|
||||
# 0x0A0: MOV R01, R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A002001"
|
||||
|
||||
# 0x0A1: POP R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A13D000"
|
||||
|
||||
# 0x0A2: SWAP R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A22A000"
|
||||
|
||||
# 0x0A3: CALL 0x098
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A33B098"
|
||||
|
||||
# 0x0A4: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A43E000"
|
||||
|
||||
# Assembled from sdram_test_short.jsm
|
||||
# ---------------------------------------------------------------
|
||||
# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA
|
||||
# User 2
|
||||
set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C3"]
|
||||
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "000D"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "010A"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0200"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0353"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0444"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0552"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0641"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "074D"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0820"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0954"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0A65"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0B73"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0C74"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0D00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0E43"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0F6C"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1065"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1161"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1272"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1369"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "146E"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1567"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1620"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1753"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1844"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1952"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1A41"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1B4D"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1C00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1D57"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1E72"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1F69"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2074"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2169"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "226E"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2367"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2420"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2553"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2644"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2752"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2841"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "294D"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2A00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2B52"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2C65"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2D61"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2E64"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2F69"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "306E"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3167"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3220"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3353"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3444"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3552"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3641"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "374D"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3800"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3956"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3A65"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3B72"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3C69"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3D66"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3E79"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3F20"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "404F"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "414B"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4200"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4346"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4461"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4569"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "466C"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4765"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4864"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4920"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4A61"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4B74"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4C20"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4D00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4E2E"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4F00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5000"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5100"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5200"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5300"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5400"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5500"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5600"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5700"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5800"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5900"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5A00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5B00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5C00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5D00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5E00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5F00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6000"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6100"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6200"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6300"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6400"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6500"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6600"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6700"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6800"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6900"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6A00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6B00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6C00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6D00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6E00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6F00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7000"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7100"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7200"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7300"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7400"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7500"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7600"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7700"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7800"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7900"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7A00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7B00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7C00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7D00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7E00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7F00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8000"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8100"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8200"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8300"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8400"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8500"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8600"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8700"
|
||||
|
||||
::chipscope::csejtag_target unlock $handle
|
||||
::chipscope::csejtag_target close $handle
|
||||
::chipscope::csejtag_session destroy $handle
|
||||
exit
|
||||
@@ -0,0 +1,188 @@
|
||||
; PROJECT "test"
|
||||
|
||||
data 10
|
||||
constant: DROM 55, 33,3a,5b,01,4f
|
||||
rxbuf: DRAM 16
|
||||
txbuf: DRAM 16
|
||||
message: DROM 12, 99, 45, 2a, 5c, 0, 0d, 0a
|
||||
|
||||
reset: jmp start
|
||||
inc R14
|
||||
mov R8, R15
|
||||
mov R15, #00
|
||||
add R15, R14
|
||||
mov R15, R8
|
||||
reti
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
|
||||
const1: equ 01
|
||||
const2: equ 02
|
||||
const3: equ 03
|
||||
const4: equ EF
|
||||
const5: equ BE
|
||||
|
||||
org 10
|
||||
|
||||
f1:
|
||||
f2: inc R13
|
||||
ret
|
||||
|
||||
start: mov R11, message
|
||||
nop
|
||||
; This is a comment:
|
||||
mov R0, #00
|
||||
mov R1, const1
|
||||
mov R2, const2
|
||||
mov R3, const3
|
||||
mov R4, const4
|
||||
mov R5, const5
|
||||
mov R6, #06
|
||||
mov R7, #07
|
||||
mov R8, #08
|
||||
mov R9, #09
|
||||
mov R10, #10
|
||||
mov R11, #65
|
||||
mov R12, #12
|
||||
mov R13, #40
|
||||
mov R14, #00
|
||||
mov R15, #15
|
||||
movx (#21), R5
|
||||
movx (R14), #65
|
||||
tst R0
|
||||
tst R5
|
||||
shr R13
|
||||
shr R13
|
||||
shl R13
|
||||
shl R13
|
||||
ror R13
|
||||
ror R13
|
||||
ror R13
|
||||
ror R13
|
||||
ror R13
|
||||
ror R13
|
||||
ror R13
|
||||
ror R13
|
||||
ror R13
|
||||
ror R13
|
||||
ror R13
|
||||
ror R13
|
||||
rol R13
|
||||
rol R13
|
||||
rol R13
|
||||
rol R13
|
||||
rol R13
|
||||
rol R13
|
||||
rol R13
|
||||
rol R13
|
||||
rol R13
|
||||
rol R13
|
||||
rol R13
|
||||
rol R13
|
||||
rol R13
|
||||
ror R15
|
||||
ror R15
|
||||
ror R15
|
||||
ror R15
|
||||
halt
|
||||
nop
|
||||
mov R8, #80
|
||||
mov R15, #00
|
||||
shl R8
|
||||
rolc R15
|
||||
rol R15
|
||||
rol R15
|
||||
rol R15
|
||||
rol R15
|
||||
rol R15
|
||||
rol R15
|
||||
rol R15
|
||||
|
||||
xor R9, #08
|
||||
or R6, #50
|
||||
and R15, #51
|
||||
|
||||
cmp R0, #00
|
||||
jne error
|
||||
jlt error
|
||||
jgt error
|
||||
jne error
|
||||
jeq ok10
|
||||
jmp error
|
||||
ok10:
|
||||
jle ok11
|
||||
jmp error
|
||||
ok11:
|
||||
jge ok12
|
||||
jmp error
|
||||
ok12:
|
||||
|
||||
cmp R1, #00
|
||||
jeq error
|
||||
jlt error
|
||||
jgt ok20
|
||||
ok20:
|
||||
jne ok21
|
||||
ok21:
|
||||
jge ok22
|
||||
jmp error
|
||||
ok22:
|
||||
|
||||
cmp R11 #64
|
||||
jeq error
|
||||
cmp R11 #65
|
||||
jle ok30
|
||||
jmp error
|
||||
ok30:
|
||||
jge ok31
|
||||
jmp error
|
||||
ok31:
|
||||
jgt error
|
||||
jlt error
|
||||
|
||||
cmp R11 #66
|
||||
jle ok40
|
||||
jmp error
|
||||
ok40:
|
||||
jgt error
|
||||
jge error
|
||||
jlt label2
|
||||
jmp error
|
||||
|
||||
label2: movx (const4), R10
|
||||
linit: mov R2, #10
|
||||
mov R1, #01
|
||||
loop: sub R2, R1
|
||||
jnz loop
|
||||
jmp sub
|
||||
|
||||
sub: mov R15, #20
|
||||
push R15
|
||||
mov R8, #01
|
||||
call f1
|
||||
call f2
|
||||
call stub
|
||||
mov R7, const4
|
||||
pop R15
|
||||
mov R15, R7
|
||||
jmp linit
|
||||
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
|
||||
stub: mov R0, #00
|
||||
L2: movx (R0), R7;
|
||||
add R0, #02
|
||||
sub R15, #01; Subtract
|
||||
jnz L2 ; exit, if zero
|
||||
|
||||
movx R5, (#09)
|
||||
movx R7, (R0)
|
||||
ret
|
||||
|
||||
error:
|
||||
nop
|
||||
jmp error
|
||||
|
||||
@@ -0,0 +1,510 @@
|
||||
; -------------------------------------------------
|
||||
; Uart test
|
||||
; -------------------------------------------------
|
||||
reset: jmp init
|
||||
|
||||
org 0x001
|
||||
jmp isr
|
||||
|
||||
; -------------------------------------------------
|
||||
; Constants
|
||||
; -------------------------------------------------
|
||||
ram_start: equ 0x00 ; R/W
|
||||
txt_start: equ 0x80 ; RO
|
||||
txt_end: equ 0x8B ; RO
|
||||
btn_port: equ 0xC0 ; RO
|
||||
led_port: equ 0xC1 ; Write
|
||||
uart_data: equ 0xC2 ; Write
|
||||
lcd_port: equ 0xC3 ; R/W
|
||||
ctrl_reg: equ 0xC4 ; R/W
|
||||
dip_port: equ 0xC5 ; RO
|
||||
uart_status: equ 0xC6 ; Read
|
||||
|
||||
lcd_read: equ 0x20
|
||||
lcd_data: equ 0x40
|
||||
lcd_enable: equ 0x80
|
||||
|
||||
DIV10: equ 0x0A
|
||||
|
||||
CR: equ 0x0D
|
||||
LF: equ 0x0A
|
||||
|
||||
count0: equ 0x00
|
||||
count1: equ 0x01
|
||||
count2: equ 0x02
|
||||
count3: equ 0x03
|
||||
|
||||
cntDigit0: equ 0x04
|
||||
cntDigit1: equ 0x05
|
||||
cntDigit2: equ 0x06
|
||||
cntDigit3: equ 0x07
|
||||
cntDigit4: equ 0x08
|
||||
cntDigit5: equ 0x09
|
||||
cntDigit6: equ 0x0A
|
||||
cntDigit7: equ 0x0B
|
||||
|
||||
LCD_CMD_Z1: equ 0x80
|
||||
LCD_CMD_Z2: equ 0xC0
|
||||
|
||||
count_stat: equ 0x0C
|
||||
|
||||
; Chip register
|
||||
cpu_revision: equ 0x00 ; RO
|
||||
cpu_control: equ 0x01 ; R/W
|
||||
cpu_status: equ 0x02 ; RO
|
||||
cpu_int_ctrl: equ 0x03 ; R/W
|
||||
|
||||
; -------------------------------------------------
|
||||
; Main
|
||||
; -------------------------------------------------
|
||||
org 010
|
||||
|
||||
init: mov R1, 0x55
|
||||
movx (led_port), R1
|
||||
; jmp init
|
||||
call CounterInit
|
||||
call LCD_init
|
||||
mov R0, 0x00
|
||||
movc (count_stat), R0
|
||||
mov R1, 0x04
|
||||
movx R0, (btn_port)
|
||||
and R0, 0x01
|
||||
jz not_pressed
|
||||
mov R1, 0x00
|
||||
not_pressed: movx (led_port), R1
|
||||
|
||||
mov R0, ctrl_reg
|
||||
; Enable timer
|
||||
movx (R0), 0x02
|
||||
; Enable interrupt
|
||||
movx (R0), 0x03
|
||||
|
||||
; Enable CPU interrupt
|
||||
cin R0, (cpu_int_ctrl)
|
||||
or R0, 0x01
|
||||
cout (cpu_int_ctrl), R0
|
||||
|
||||
start: halt
|
||||
call Cnt32
|
||||
call UpdateDigits
|
||||
mov R15, cntDigit7
|
||||
|
||||
movc R0, (count_stat)
|
||||
tst R0
|
||||
jz start
|
||||
mov R0, 0x00
|
||||
movc (count_stat), R0
|
||||
|
||||
loop: call subprog
|
||||
movc R0, (R15)
|
||||
call sout
|
||||
cmp R15, cntDigit0
|
||||
jeq sendCRLF
|
||||
dec R15
|
||||
jmp loop
|
||||
|
||||
sendCRLF: mov R0, CR
|
||||
call sout
|
||||
mov R0, LF
|
||||
call sout
|
||||
|
||||
jmp start
|
||||
|
||||
; -------------------------------------------------
|
||||
CounterInit: mov R0, 0x00
|
||||
movc (count0), R0
|
||||
movc (count1), R0
|
||||
movc (count2), R0
|
||||
movc (count3), R0
|
||||
ret
|
||||
|
||||
Cnt32: mov R0, count0
|
||||
cloop: movc R1, (R0)
|
||||
inc R1
|
||||
movc (R0), R1
|
||||
; ----------------
|
||||
mov R7, R1
|
||||
mov R14, R7
|
||||
mov R7, 0x55
|
||||
mov R7, 0xAA
|
||||
xor R7, R7
|
||||
xor R14, 0x99
|
||||
; ----------------
|
||||
jnc CountRdy
|
||||
cmp R0, count3
|
||||
jeq CountRdy
|
||||
inc R0
|
||||
jmp cloop
|
||||
CountRdy: ret
|
||||
|
||||
UpdateDigits: mov R2, cntDigit0
|
||||
mov R0, count0
|
||||
dualLoop: movc R1, (R0)
|
||||
and R1, 0x0F
|
||||
cmp R1, 0x0A
|
||||
jlt isNum1
|
||||
add R1, 0x07
|
||||
isNum1: add R1, 0x30
|
||||
movc (R2), R1
|
||||
inc R2
|
||||
movc R1, (R0)
|
||||
shr R1
|
||||
shr R1
|
||||
shr R1
|
||||
shr R1
|
||||
and R1, 0x0F
|
||||
cmp R1, 0x0A
|
||||
jlt isNum2
|
||||
add R1, 0x07
|
||||
isNum2: add R1, 0x30
|
||||
movc (R2), R1
|
||||
cmp R0, count3
|
||||
jeq UpdRdy
|
||||
inc R0
|
||||
inc R2
|
||||
jmp dualLoop
|
||||
UpdRdy: ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; subprog
|
||||
; -------------------------------------------------
|
||||
subprog: push R0
|
||||
push R1
|
||||
push R2
|
||||
push R3
|
||||
push R4
|
||||
push R5
|
||||
push R6
|
||||
push R7
|
||||
push R8
|
||||
push R9
|
||||
push R10
|
||||
push R11
|
||||
push R12
|
||||
push R13
|
||||
push R14
|
||||
push R15
|
||||
pop R15
|
||||
pop R14
|
||||
pop R13
|
||||
pop R12
|
||||
pop R11
|
||||
pop R10
|
||||
pop R9
|
||||
pop R8
|
||||
pop R7
|
||||
pop R6
|
||||
pop R5
|
||||
pop R4
|
||||
pop R3
|
||||
pop R2
|
||||
pop R1
|
||||
pop R0
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; sout
|
||||
; -------------------------------------------------
|
||||
; R0 = input
|
||||
sout: push R1
|
||||
sout1: movx R1, (uart_status)
|
||||
and R1, 0x02
|
||||
jnz sout1
|
||||
movx (uart_data), R0
|
||||
pop R1
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; sin
|
||||
; -------------------------------------------------
|
||||
; R0 = output
|
||||
sin: push R1
|
||||
sin1: movx R1, (uart_status)
|
||||
and R1, 0x10
|
||||
jnz sin1
|
||||
movx R0, (uart_data)
|
||||
pop R1
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; Init LCD
|
||||
; -------------------------------------------------
|
||||
LCD_init: mov R1, lcd_port
|
||||
movx (R1), lcd_read
|
||||
|
||||
call delay10ms
|
||||
|
||||
; 0.
|
||||
mov R2, 0x00
|
||||
mov R0, 0x03
|
||||
call LCD_write_
|
||||
call delay10ms
|
||||
mov R2, 0x00
|
||||
mov R0, 0x03
|
||||
call LCD_write_
|
||||
call delay10ms
|
||||
|
||||
mov R2, 0x00
|
||||
mov R0, 0x02
|
||||
call LCD_write_
|
||||
call delay1ms
|
||||
|
||||
; 1.
|
||||
mov R0, 0x28
|
||||
call LCD_writecmd
|
||||
|
||||
; 2.
|
||||
mov R0, 0x0E
|
||||
call LCD_writecmd
|
||||
|
||||
; 3.
|
||||
mov R0, 0x06
|
||||
call LCD_writecmd
|
||||
|
||||
; 3.
|
||||
mov R0, 0x01
|
||||
call LCD_writecmd
|
||||
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; LCD_Clear
|
||||
; -------------------------------------------------
|
||||
LCD_clear: push R0
|
||||
mov R0, 0x01
|
||||
call LCD_writecmd
|
||||
pop R0
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; LCD_writecmd
|
||||
; -------------------------------------------------
|
||||
; R0 = cmd
|
||||
LCD_writecmd: call LCD_waitbsy
|
||||
push R2
|
||||
push R0
|
||||
push R0
|
||||
mov R2, 0x00
|
||||
shr R0
|
||||
shr R0
|
||||
shr R0
|
||||
shr R0
|
||||
call LCD_write_
|
||||
pop R0
|
||||
and R0, 0x0F
|
||||
call LCD_write_
|
||||
pop R0
|
||||
pop R2
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; LCD_writechar
|
||||
; -------------------------------------------------
|
||||
; R0 = char
|
||||
LCD_writechar: call LCD_waitbsy
|
||||
push R2
|
||||
push R0
|
||||
push R0
|
||||
mov R2, lcd_data
|
||||
shr R0
|
||||
shr R0
|
||||
shr R0
|
||||
shr R0
|
||||
call LCD_write_
|
||||
pop R0
|
||||
and R0, 0x0F
|
||||
call LCD_write_
|
||||
pop R0
|
||||
pop R2
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; LCD_write_
|
||||
; -------------------------------------------------
|
||||
; R0 = input
|
||||
LCD_write_: push R1
|
||||
|
||||
mov R1, R0
|
||||
or R1, R2
|
||||
movx (lcd_port), R1
|
||||
call delay1us
|
||||
|
||||
mov R1, R0
|
||||
or R1, R2
|
||||
or R1, lcd_enable
|
||||
movx (lcd_port), R1
|
||||
call delay1us
|
||||
|
||||
mov R1, R0
|
||||
or R1, R2
|
||||
movx (lcd_port), R1
|
||||
call delay1us
|
||||
|
||||
pop R1
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; LCD_read_
|
||||
; -------------------------------------------------
|
||||
; R0 = output
|
||||
LCD_read_: push R1
|
||||
|
||||
mov R1, lcd_read
|
||||
or R1, R2
|
||||
movx (lcd_port), R1
|
||||
call delay1us
|
||||
|
||||
mov R1, lcd_read
|
||||
or R1, R2
|
||||
or R1, lcd_enable
|
||||
movx (lcd_port), R1
|
||||
call delay1us
|
||||
movx R0, (lcd_port)
|
||||
|
||||
mov R1, lcd_read
|
||||
or R1, R2
|
||||
movx (lcd_port), R1
|
||||
call delay1us
|
||||
|
||||
pop R1
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; LCD_readstat
|
||||
; -------------------------------------------------
|
||||
; R0 = status
|
||||
LCD_readstat: push R2
|
||||
mov R2, 0x00
|
||||
call LCD_read_
|
||||
shl R0
|
||||
shl R0
|
||||
shl R0
|
||||
shl R0
|
||||
push R0
|
||||
call LCD_read_
|
||||
and R0, 0x0F
|
||||
pop R2
|
||||
or R0, R2
|
||||
pop R2
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; LCD_waitbsy
|
||||
; -------------------------------------------------
|
||||
LCD_waitbsy: push R0
|
||||
bsy_loop: call LCD_readstat
|
||||
and R0, 0x80
|
||||
jz ex_bsy
|
||||
call delay1us
|
||||
jmp bsy_loop
|
||||
ex_bsy: pop R0
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; ISR
|
||||
; -------------------------------------------------
|
||||
isr: push R0
|
||||
push R1
|
||||
movx R0, (led_port)
|
||||
xor R0, 0x02
|
||||
movx (led_port), R0
|
||||
|
||||
call LCD_clear
|
||||
|
||||
mov R0, LCD_CMD_Z1
|
||||
call LCD_writecmd
|
||||
|
||||
mov R1, txt_start
|
||||
read_rom: movx R0, (R1)
|
||||
call LCD_writechar
|
||||
inc R1
|
||||
cmp R1, txt_end
|
||||
jlt read_rom
|
||||
|
||||
mov R0, LCD_CMD_Z2
|
||||
call LCD_writecmd
|
||||
mov R1, cntDigit1
|
||||
movc R0, (R1)
|
||||
mov R1, cntDigit7
|
||||
cmp R0, 0x30
|
||||
jne print_num
|
||||
mov R0, 0x01
|
||||
movc (count_stat), R0
|
||||
|
||||
print_num: movc R0, (R1)
|
||||
call LCD_writechar
|
||||
cmp R1, cntDigit0
|
||||
jeq ex_isr
|
||||
dec R1
|
||||
jmp print_num
|
||||
|
||||
ex_isr: call delay1ms
|
||||
pop R1
|
||||
pop R0
|
||||
|
||||
reti
|
||||
|
||||
; -------------------------------------------------
|
||||
; Delays
|
||||
; -------------------------------------------------
|
||||
delay1s: push R15
|
||||
mov R15, DIV10
|
||||
loop1s: call delay100ms
|
||||
dec R15
|
||||
jnz loop1s
|
||||
pop R15
|
||||
ret
|
||||
|
||||
delay100ms: push R15
|
||||
mov R15, DIV10
|
||||
loop100ms: call delay10ms
|
||||
dec R15
|
||||
jnz loop100ms
|
||||
pop R15
|
||||
ret
|
||||
|
||||
delay10ms: push R15
|
||||
mov R15, DIV10
|
||||
loop10ms: call delay1ms
|
||||
dec R15
|
||||
jnz loop10ms
|
||||
pop R15
|
||||
ret
|
||||
|
||||
delay1ms: push R15
|
||||
mov R15, DIV10
|
||||
loop1ms: call delay100us
|
||||
dec R15
|
||||
jnz loop1ms
|
||||
pop R15
|
||||
ret
|
||||
|
||||
delay100us: push R15
|
||||
mov R15, DIV10
|
||||
loop100us: call delay10us
|
||||
dec R15
|
||||
jnz loop100us
|
||||
pop R15
|
||||
ret
|
||||
|
||||
delay10us: push R15
|
||||
mov R15, DIV10
|
||||
loop10us: call delay1us
|
||||
dec R15
|
||||
jnz loop10us
|
||||
pop R15
|
||||
ret
|
||||
|
||||
delay1us: push R15
|
||||
mov R15, DIV10
|
||||
loop1us: call delay100ns
|
||||
dec R15
|
||||
jnz loop1us
|
||||
pop R15
|
||||
ret
|
||||
|
||||
delay100ns: nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
ret
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,736 @@
|
||||
; -------------------------------------------------
|
||||
; Register definitions
|
||||
; -------------------------------------------------
|
||||
include "../../../lib/jasm/cregs.inc.jsm"
|
||||
include "xregs.inc.jsm"
|
||||
|
||||
; -------------------------------------------------
|
||||
; Constants
|
||||
; -------------------------------------------------
|
||||
BURST_LEN: equ 8
|
||||
SD_CMD_WRITE: equ 0x06
|
||||
SD_CMD_READ: equ 0x05
|
||||
START_ADDR0: equ 0x00
|
||||
START_ADDR1: equ 0x00
|
||||
START_ADDR2: equ 0x20
|
||||
END_ADDR0: equ 0xF8
|
||||
END_ADDR1: equ 0xFF
|
||||
END_ADDR2: equ 0xFF
|
||||
SIO_TIMEOUT0: equ 0xE8
|
||||
SIO_TIMEOUT1: equ 0x03
|
||||
SIO_BUFSIZE: equ 64
|
||||
|
||||
; External RAM/ROM
|
||||
xmem
|
||||
crlf: dc 13, 10, 0
|
||||
greet_txt: dc "SDRAM Test", 0
|
||||
msg_txt0: dc "Clearing SDRAM", 0
|
||||
msg_txt1: dc "Writing SDRAM", 0
|
||||
msg_txt2: dc "Reading SDRAM", 0
|
||||
msg_txt3: dc "Reading Bitmap", 0
|
||||
verify_ok: dc "Verify OK", 0
|
||||
verify_nok: dc "Failed at ", 0
|
||||
dot: dc ".", 0
|
||||
|
||||
org 0x80
|
||||
sdram_data: db 8 ; SDRAM data window at X:0x80
|
||||
|
||||
; Internal RAM
|
||||
cmem 0
|
||||
block_cnt: db 1
|
||||
round_cnt: db 1
|
||||
bmp_offset: db 4
|
||||
pixel_buf: db 24
|
||||
|
||||
sio_rx_buf: db 64
|
||||
sio_rx_ptr_r: db 1
|
||||
sio_rx_ptr_w: db 1
|
||||
sio_timeout: db 2
|
||||
|
||||
; -------------------------------------------------
|
||||
; Program
|
||||
; -------------------------------------------------
|
||||
code
|
||||
reset: org 0x000
|
||||
jmp main
|
||||
|
||||
; -------------------------------------------------
|
||||
; ISR
|
||||
; -------------------------------------------------
|
||||
org 0x001
|
||||
sio_isr: push R0
|
||||
push R1
|
||||
u_get_nxt: xin R1, (uart_status)
|
||||
and R1, 0x10
|
||||
jz ex_uart_isr
|
||||
xin R0, (uart_data)
|
||||
movc R1, (sio_rx_ptr_w)
|
||||
movc (R1), R0
|
||||
inc R1
|
||||
cmp R1, sio_rx_buf+64
|
||||
jne u_upd_nxt
|
||||
mov R1, sio_rx_buf
|
||||
u_upd_nxt: movc (sio_rx_ptr_w), R1
|
||||
movc R0, (sio_rx_ptr_r)
|
||||
cmp R0, R1
|
||||
jne u_get_nxt
|
||||
xin R0, (ctrl_reg)
|
||||
or R0, 0x20
|
||||
xout (ctrl_reg), R0
|
||||
jmp u_get_nxt
|
||||
ex_uart_isr: call Timer_isr
|
||||
pop R1
|
||||
pop R0
|
||||
reti
|
||||
|
||||
Timer_isr: xin R0, (btn_port)
|
||||
and R0, 0x01
|
||||
jz btn_chk2
|
||||
mov R0, vga_read_addr
|
||||
xout (R0), 0x00
|
||||
inc R0
|
||||
xout (R0), 0x00
|
||||
inc R0
|
||||
xout (R0), 0x00
|
||||
jmp ex_t_isr
|
||||
btn_chk2: xin R0, (btn_port)
|
||||
and R0, 0x02
|
||||
jz ex_t_isr
|
||||
mov R0, vga_read_addr
|
||||
xout (R0), 0x00
|
||||
inc R0
|
||||
xout (R0), 0x00
|
||||
inc R0
|
||||
xout (R0), 0x20
|
||||
ex_t_isr: ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; Main
|
||||
; -------------------------------------------------
|
||||
main: call sio_init
|
||||
call LCD_init
|
||||
mov R0, 0x00
|
||||
xout (led_port), R0
|
||||
|
||||
mov R0, CTRL_VGA_ENABLE
|
||||
xout (ctrl_reg), R0
|
||||
|
||||
xin R0, (ctrl_reg)
|
||||
or R0, CTRL_TIMER_ENABLE
|
||||
xout (ctrl_reg), R0
|
||||
|
||||
mov R0, 0x03
|
||||
cout (cpu_int_ctrl), R0
|
||||
|
||||
; Clear LCD
|
||||
mov R0, LCD_CMD_CLEAR
|
||||
call LCD_writecmd
|
||||
|
||||
mov R0, 0
|
||||
mov R1, 0xC0
|
||||
xout (reg_color_red), R1
|
||||
xout (reg_color_grn), R1
|
||||
xout (reg_color_blu), R1
|
||||
|
||||
call cg_wait_rdy
|
||||
call cg_clr_screen
|
||||
|
||||
; Print greeting message
|
||||
mov R1, greet_txt
|
||||
call LCD_putsx
|
||||
|
||||
mov R1, greet_txt
|
||||
call cg_puts
|
||||
mov R1, crlf
|
||||
call cg_puts_clr
|
||||
|
||||
xin R0, (ctrl_reg)
|
||||
and R0, 0xCF
|
||||
xout (ctrl_reg), R0
|
||||
|
||||
mov R0, 0
|
||||
movc (round_cnt), R0
|
||||
|
||||
|
||||
main_loop: call write_uart_data
|
||||
; call do_clear
|
||||
ML1: call do_write
|
||||
call do_read
|
||||
movc R0, (round_cnt)
|
||||
inc R0
|
||||
movc (round_cnt), R0
|
||||
jmp ML1
|
||||
|
||||
; ----------------------------------------------------------
|
||||
; SDRAM clear
|
||||
; ----------------------------------------------------------
|
||||
do_clear:
|
||||
; Clear LCD
|
||||
mov R0, LCD_CMD_CLEAR
|
||||
call LCD_writecmd
|
||||
|
||||
; Print Clear message
|
||||
mov R1, msg_txt0
|
||||
call LCD_putsx
|
||||
|
||||
mov R1, msg_txt0
|
||||
call cg_clr_puts
|
||||
mov R1, crlf
|
||||
call cg_puts_clr
|
||||
|
||||
; Set SDRAM address register to 0
|
||||
mov R0, 0
|
||||
mov R1, 0
|
||||
mov R2, 0
|
||||
call AddrCnt_Init
|
||||
|
||||
; Fill SDR Buffer with zeros
|
||||
mov R0, sdram_data
|
||||
mov R15, 8
|
||||
buf_clr_loop: movx (R0), 0
|
||||
inc R0
|
||||
dec R15
|
||||
jnz buf_clr_loop
|
||||
|
||||
sdr_clear: mov R2, BURST_LEN
|
||||
|
||||
poll_clear_full:
|
||||
xin R0, (sdram_reg)
|
||||
xout (led_port), R0
|
||||
and R0, FIFO_STAT_WRITE_DATA_FULL
|
||||
jnz poll_clear_full
|
||||
|
||||
; Fill FIFO
|
||||
mov R0, FIFO_CTRL_IS_WRITE
|
||||
xout (sdram_reg), R0
|
||||
|
||||
sub R2, 2
|
||||
jnz poll_clear_full
|
||||
|
||||
; Start SDR write
|
||||
call wait_cmd_rdy
|
||||
mov R0, SD_CMD_WRITE
|
||||
xout (sdram_reg), R0
|
||||
|
||||
xin R0, (sdram_addr+0)
|
||||
cmp R0, END_ADDR0
|
||||
jne next_addr_c
|
||||
xin R0, (sdram_addr+1)
|
||||
cmp R0, END_ADDR1
|
||||
jne next_addr_c
|
||||
xin R0, (sdram_addr+2)
|
||||
cmp R0, END_ADDR2
|
||||
jeq clear_finished
|
||||
|
||||
; Advance address counter
|
||||
next_addr_c: mov R0, BURST_LEN
|
||||
call AddrCnt_Inc
|
||||
|
||||
jmp sdr_clear
|
||||
|
||||
clear_finished:
|
||||
call AddrCnt_Disp
|
||||
call delay1s
|
||||
ret
|
||||
|
||||
; ----------------------------------------------------------
|
||||
; SDRAM Write
|
||||
; ----------------------------------------------------------
|
||||
write_uart_data:
|
||||
; Clear LCD
|
||||
mov R0, LCD_CMD_CLEAR
|
||||
call LCD_writecmd
|
||||
|
||||
; Print Clear message
|
||||
mov R1, msg_txt3
|
||||
call LCD_putsx
|
||||
|
||||
mov R1, msg_txt3
|
||||
call cg_clr_puts
|
||||
mov R1, crlf
|
||||
call cg_puts_clr
|
||||
|
||||
; Set SDRAM address register to 0
|
||||
; mov R0, 0xF8 ; 800x600
|
||||
; mov R1, 0x52 ; 800x600
|
||||
; mov R2, 0x07 ; 800x600
|
||||
mov R0, 0xF8 ; 1280x1024
|
||||
mov R1, 0xFF ; 1280x1024
|
||||
mov R2, 0x13 ; 1280x1024
|
||||
call AddrCnt_Init
|
||||
|
||||
read_bmp: mov R15, 0
|
||||
skip_hdr1: call sio_getchar
|
||||
jc write_uart_data
|
||||
inc R15
|
||||
cmp R15, 10
|
||||
jne skip_hdr1
|
||||
|
||||
call sio_getchar
|
||||
jc write_uart_data
|
||||
inc R15
|
||||
movc (bmp_offset+0), R0
|
||||
|
||||
call sio_getchar
|
||||
jc write_uart_data
|
||||
inc R15
|
||||
movc (bmp_offset+1), R0
|
||||
|
||||
call sio_getchar
|
||||
jc write_uart_data
|
||||
inc R15
|
||||
movc (bmp_offset+2), R0
|
||||
|
||||
call sio_getchar
|
||||
jc write_uart_data
|
||||
inc R15
|
||||
movc (bmp_offset+3), R0
|
||||
|
||||
movc R1, (bmp_offset+0)
|
||||
skip_hdr2: call sio_getchar
|
||||
jc write_uart_data
|
||||
inc R15
|
||||
cmp R15, R1
|
||||
jne skip_hdr2
|
||||
|
||||
get_pixel: mov R15, 8
|
||||
mov R1, pixel_buf+23
|
||||
next_pixel: mov R2, 3
|
||||
next_color: dec R2
|
||||
mov R3, R1
|
||||
call sio_getchar
|
||||
jc sdw_fin
|
||||
sub R3, R2
|
||||
movc (R3), R0
|
||||
tst R2
|
||||
jnz next_color
|
||||
sub R1, 3
|
||||
dec R15
|
||||
jnz next_pixel
|
||||
|
||||
mov R2, BURST_LEN
|
||||
|
||||
; Fill SDR Buffer
|
||||
mov R1, pixel_buf
|
||||
wls: mov R3, sdram_data
|
||||
wls0: movc R0, (R1)
|
||||
movx (R3), R0
|
||||
inc R1
|
||||
inc R3
|
||||
cmp R3, sdram_data+6
|
||||
jne wls0
|
||||
|
||||
pwf: xin R0, (sdram_reg)
|
||||
xout (led_port), R0
|
||||
and R0, FIFO_STAT_WRITE_DATA_FULL
|
||||
jnz pwf
|
||||
|
||||
; Fill FIFO
|
||||
mov R0, FIFO_CTRL_IS_WRITE
|
||||
xout (sdram_reg), R0
|
||||
|
||||
sub R2, 2
|
||||
jnz wls
|
||||
|
||||
; Start SDR write
|
||||
call wait_cmd_rdy
|
||||
mov R0, SD_CMD_WRITE
|
||||
xout (sdram_reg), R0
|
||||
|
||||
call AddrCnt_Disp
|
||||
xin R0, (sdram_addr+0)
|
||||
tst R0
|
||||
jnz next_addr
|
||||
xin R0, (sdram_addr+1)
|
||||
tst R0
|
||||
jnz next_addr
|
||||
xin R0, (sdram_addr+2)
|
||||
tst R0
|
||||
jz sdw_fin
|
||||
|
||||
; Advance address counter
|
||||
next_addr: mov R0, BURST_LEN
|
||||
call AddrCnt_Dec
|
||||
jmp get_pixel
|
||||
sdw_fin: call delay1s
|
||||
ret
|
||||
|
||||
; ----------------------------------------------------------
|
||||
; SDRAM Write
|
||||
; ----------------------------------------------------------
|
||||
do_write:
|
||||
; Clear LCD
|
||||
mov R0, LCD_CMD_CLEAR
|
||||
call LCD_writecmd
|
||||
|
||||
; Print Write message
|
||||
mov R1, msg_txt1
|
||||
call LCD_putsx
|
||||
|
||||
mov R1, msg_txt1
|
||||
call cg_clr_puts
|
||||
mov R1, crlf
|
||||
call cg_puts_clr
|
||||
|
||||
; Set SDRAM address register to 0
|
||||
mov R0, START_ADDR0
|
||||
mov R1, START_ADDR1
|
||||
mov R2, START_ADDR2
|
||||
call AddrCnt_Init
|
||||
movc R0, (round_cnt)
|
||||
movc (block_cnt), R0
|
||||
|
||||
sdr_write: mov R2, BURST_LEN
|
||||
|
||||
; Fill SDR Buffer
|
||||
sdr_burst_wr: movc R1, (block_cnt)
|
||||
mov R0, sdram_data
|
||||
mov R15, 8
|
||||
write_loop: movx (R0), R1
|
||||
inc R0
|
||||
inc R1
|
||||
dec R15
|
||||
jnz write_loop
|
||||
|
||||
poll_write_full:
|
||||
xin R0, (sdram_reg)
|
||||
xout (led_port), R0
|
||||
and R0, FIFO_STAT_WRITE_DATA_FULL
|
||||
jnz poll_write_full
|
||||
|
||||
; Fill FIFO
|
||||
mov R0, FIFO_CTRL_IS_WRITE
|
||||
xout (sdram_reg), R0
|
||||
|
||||
movc R0, (block_cnt)
|
||||
inc R0
|
||||
movc (block_cnt), R0
|
||||
|
||||
sub R2, 2
|
||||
jnz sdr_burst_wr
|
||||
|
||||
; Start SDR write
|
||||
call wait_cmd_rdy
|
||||
mov R0, SD_CMD_WRITE
|
||||
xout (sdram_reg), R0
|
||||
|
||||
xin R0, (sdram_addr+0)
|
||||
cmp R0, END_ADDR0
|
||||
jne next_addr_w
|
||||
xin R0, (sdram_addr+1)
|
||||
cmp R0, END_ADDR1
|
||||
jne next_addr_w
|
||||
xin R0, (sdram_addr+2)
|
||||
cmp R0, END_ADDR2
|
||||
jeq write_finished
|
||||
|
||||
; Advance address counter
|
||||
next_addr_w: mov R0, BURST_LEN
|
||||
call AddrCnt_Inc
|
||||
|
||||
jmp sdr_write
|
||||
|
||||
write_finished: call AddrCnt_Disp
|
||||
call delay1s
|
||||
ret
|
||||
|
||||
; ----------------------------------------------------------
|
||||
; SDRAM Verify
|
||||
; ----------------------------------------------------------
|
||||
do_read:
|
||||
; Clear LCD
|
||||
mov R0, LCD_CMD_CLEAR
|
||||
call LCD_writecmd
|
||||
|
||||
; Print Read message
|
||||
mov R1, msg_txt2
|
||||
call LCD_putsx
|
||||
|
||||
mov R1, msg_txt2
|
||||
call cg_clr_puts
|
||||
mov R1, crlf
|
||||
call cg_puts_clr
|
||||
|
||||
; Set SDRAM address register to 0
|
||||
mov R0, START_ADDR0
|
||||
mov R1, START_ADDR1
|
||||
mov R2, START_ADDR2
|
||||
call AddrCnt_Init
|
||||
movc R0, (round_cnt)
|
||||
movc (block_cnt), R0
|
||||
|
||||
; flush_data
|
||||
flush_data: xin R0, (sdram_reg)
|
||||
xout (led_port), R0
|
||||
and R0, FIFO_STAT_READ_DATA_EMPTY
|
||||
jnz sdr_read
|
||||
mov R0, FIFO_CTRL_IS_READ
|
||||
xout (sdram_reg), R0
|
||||
jmp flush_data
|
||||
|
||||
sdr_read: ; Start SDR read
|
||||
call wait_cmd_rdy
|
||||
mov R0, SD_CMD_READ
|
||||
xout (sdram_reg), R0
|
||||
|
||||
mov R3, BURST_LEN
|
||||
|
||||
; Wait last read
|
||||
poll_read_fin: xin R0, (sdram_reg)
|
||||
xout (led_port), R0
|
||||
and R0, FIFO_STAT_READ_DATA_EMPTY
|
||||
jnz poll_read_fin
|
||||
|
||||
; Verify SDR Buffer
|
||||
movc R1, (block_cnt)
|
||||
mov R0, sdram_data
|
||||
mov R15, 8
|
||||
read_loop: movx R2, (R0)
|
||||
cmp R2, R1
|
||||
jne verify_error
|
||||
inc R0
|
||||
inc R1
|
||||
dec R15
|
||||
jnz read_loop
|
||||
|
||||
; Advance Read-FIFO
|
||||
mov R0, FIFO_CTRL_IS_READ
|
||||
xout (sdram_reg), R0
|
||||
|
||||
movc R0, (block_cnt)
|
||||
inc R0
|
||||
movc (block_cnt), R0
|
||||
|
||||
sub R3, 2
|
||||
jnz poll_read_fin
|
||||
|
||||
xin R0, (sdram_addr+0)
|
||||
cmp R0, END_ADDR0
|
||||
jne next_addr_r
|
||||
xin R0, (sdram_addr+1)
|
||||
cmp R0, END_ADDR1
|
||||
jne next_addr_r
|
||||
xin R0, (sdram_addr+2)
|
||||
cmp R0, END_ADDR2
|
||||
jeq read_finished
|
||||
|
||||
; Advance address counter
|
||||
next_addr_r: mov R0, BURST_LEN
|
||||
call AddrCnt_Inc
|
||||
jmp sdr_read
|
||||
|
||||
; ----------------------------------------------------------
|
||||
wait_cmd_rdy: push R0
|
||||
wait4cmd: xin R0, (sdram_reg)
|
||||
xout (led_port), R0
|
||||
and R0, FIFO_STAT_CMD_FULL
|
||||
jnz wait4cmd
|
||||
pop R0
|
||||
ret
|
||||
|
||||
; ----------------------------------------------------------
|
||||
read_finished:
|
||||
no_error: mov R0, LCD_CMD_CLEAR
|
||||
call LCD_writecmd
|
||||
mov R1, verify_ok
|
||||
call LCD_putsx
|
||||
mov R0, LCD_CMD_Z2
|
||||
call LCD_writecmd
|
||||
call print_addr
|
||||
|
||||
mov R1, verify_ok
|
||||
call cg_clr_puts
|
||||
mov R1, crlf
|
||||
call cg_puts_clr
|
||||
|
||||
jmp ende
|
||||
|
||||
verify_error: mov R0, LCD_CMD_CLEAR
|
||||
call LCD_writecmd
|
||||
mov R1, verify_nok
|
||||
call LCD_putsx
|
||||
call print_addr
|
||||
call print_data
|
||||
mov R1, verify_nok
|
||||
call cg_clr_puts
|
||||
mov R1, crlf
|
||||
call cg_puts_clr
|
||||
xin R0, (ctrl_reg)
|
||||
or R0, 0x10
|
||||
xout (ctrl_reg), R0
|
||||
|
||||
jmp ende
|
||||
|
||||
ende: call delay1s
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
AddrCnt_Init: xout (sdram_addr+0), R0
|
||||
xout (sdram_addr+1), R1
|
||||
xout (sdram_addr+2), R2
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; Parameter
|
||||
; R0: increment value
|
||||
AddrCnt_Inc: push R1
|
||||
push R2
|
||||
push R3
|
||||
xin R1, (sdram_addr+0)
|
||||
xin R2, (sdram_addr+1)
|
||||
xin R3, (sdram_addr+2)
|
||||
add R1, R0
|
||||
addc R2, 0
|
||||
addc R3, 0
|
||||
xout (sdram_addr+0), R1
|
||||
xout (sdram_addr+1), R2
|
||||
xout (sdram_addr+2), R3
|
||||
pop R3
|
||||
pop R2
|
||||
pop R1
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; Parameter
|
||||
; R0: decrement value
|
||||
AddrCnt_Dec: push R1
|
||||
push R2
|
||||
push R3
|
||||
xin R1, (sdram_addr+0)
|
||||
xin R2, (sdram_addr+1)
|
||||
xin R3, (sdram_addr+2)
|
||||
sub R1, R0
|
||||
subc R2, 0
|
||||
subc R3, 0
|
||||
xout (sdram_addr+0), R1
|
||||
xout (sdram_addr+1), R2
|
||||
xout (sdram_addr+2), R3
|
||||
pop R3
|
||||
pop R2
|
||||
pop R1
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; Display Address counter
|
||||
AddrCnt_Disp: mov R0, LCD_CMD_Z2
|
||||
call LCD_writecmd
|
||||
call print_addr
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; PutHexByte
|
||||
; R0 : Byte value
|
||||
PutHexByte: push R1
|
||||
call bin2hex
|
||||
call LCD_writechar
|
||||
mov R0, R1
|
||||
call LCD_writechar
|
||||
pop R1
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
print_addr: push R0
|
||||
xin R0, (sdram_addr+2)
|
||||
call PutHexByte
|
||||
xin R0, (sdram_addr+1)
|
||||
call PutHexByte
|
||||
xin R0, (sdram_addr+0)
|
||||
call PutHexByte
|
||||
pop R0
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; R1 : ptr to byte array
|
||||
print_dword: push R0
|
||||
add R1, 3
|
||||
movc R0, (R1)
|
||||
call PutHexByte
|
||||
dec R1
|
||||
movc R0, (R1)
|
||||
call PutHexByte
|
||||
dec R1
|
||||
movc R0, (R1)
|
||||
call PutHexByte
|
||||
dec R1
|
||||
movc R0, (R1)
|
||||
call PutHexByte
|
||||
pop R0
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
print_data: push R0
|
||||
mov R0, LCD_CMD_Z2
|
||||
call LCD_writecmd
|
||||
movx R0, (sdram_data+7)
|
||||
call PutHexByte
|
||||
movx R0, (sdram_data+6)
|
||||
call PutHexByte
|
||||
movx R0, (sdram_data+5)
|
||||
call PutHexByte
|
||||
movx R0, (sdram_data+4)
|
||||
call PutHexByte
|
||||
movx R0, (sdram_data+3)
|
||||
call PutHexByte
|
||||
movx R0, (sdram_data+2)
|
||||
call PutHexByte
|
||||
movx R0, (sdram_data+1)
|
||||
call PutHexByte
|
||||
movx R0, (sdram_data+0)
|
||||
call PutHexByte
|
||||
pop R0
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
sio_init: push R0
|
||||
mov R0, 13
|
||||
xout (uart_baudrate), R0
|
||||
mov R0, sio_rx_buf
|
||||
movc (sio_rx_ptr_r), R0
|
||||
movc (sio_rx_ptr_w), R0
|
||||
mov R0, SIO_TIMEOUT0
|
||||
movc (sio_timeout+0), R0
|
||||
mov R0, SIO_TIMEOUT1
|
||||
movc (sio_timeout+1), R0
|
||||
pop R0
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; Params: none
|
||||
; Return:
|
||||
; R0 : received character
|
||||
sio_getchar: push R1
|
||||
push R2
|
||||
push R3
|
||||
movc R2, (sio_timeout+0)
|
||||
movc R3, (sio_timeout+1)
|
||||
movc R1, (sio_rx_ptr_r)
|
||||
sio_wait_rx: movc R0, (sio_rx_ptr_w)
|
||||
cmp R0, R1
|
||||
jeq wait_rx_stub
|
||||
movc R0, (R1)
|
||||
inc R1
|
||||
cmp R1, sio_rx_buf+64
|
||||
jne u_upd_r_ptr
|
||||
mov R1, sio_rx_buf
|
||||
u_upd_r_ptr: movc (sio_rx_ptr_r), R1
|
||||
clrc
|
||||
ex_sio_gc: pop R3
|
||||
pop R2
|
||||
pop R1
|
||||
ret
|
||||
wait_rx_stub: call delay1ms
|
||||
dec R2
|
||||
subc R3, 0
|
||||
jnz sio_wait_rx
|
||||
tst R2
|
||||
jnz sio_wait_rx
|
||||
sio_to: setc
|
||||
jmp ex_sio_gc
|
||||
|
||||
; -------------------------------------------------
|
||||
include "../../../lib/jasm/utils.inc.jsm"
|
||||
include "../../../lib/jasm/lcd.inc.jsm"
|
||||
include "../../../lib/jasm/cg.inc.jsm"
|
||||
include "../../../lib/jasm/delays.inc.jsm"
|
||||
include "../../../lib/jasm/uart.inc.jsm"
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,41 @@
|
||||
; External registers
|
||||
btn_port: equ 0x00 ; RO
|
||||
led_port: equ 0x01 ; R/W
|
||||
uart_data: equ 0x02 ; R/W
|
||||
lcd_port: equ 0x03 ; R/W
|
||||
ctrl_reg: equ 0x04 ; R/W
|
||||
CTRL_VGA_ENABLE: equ 0x04
|
||||
CTRL_TIMER_ENABLE: equ 0x02
|
||||
dip_port: equ 0x05 ; RO
|
||||
uart_status: equ 0x06 ; RO
|
||||
sdram_reg: equ 0x07 ; R/W
|
||||
FIFO_CTRL_IS_CMD: equ 0x04
|
||||
FIFO_CTRL_IS_WRITE: equ 0x10
|
||||
FIFO_CTRL_IS_READ: equ 0x20
|
||||
FIFO_STAT_CMD_FULL: equ 0x01
|
||||
FIFO_STAT_CMD_EMPTY: equ 0x02
|
||||
FIFO_STAT_WRITE_DATA_FULL: equ 0x04
|
||||
FIFO_STAT_WRITE_DATA_EMPTY: equ 0x08
|
||||
FIFO_STAT_READ_DATA_FULL: equ 0x10
|
||||
FIFO_STAT_READ_DATA_EMPTY: equ 0x20
|
||||
sdram_addr: equ 0x08 ; R/W
|
||||
sdram_addr0: equ 0x08 ; R/W
|
||||
sdram_addr1: equ 0x09 ; R/W
|
||||
sdram_addr2: equ 0x0A ; R/W
|
||||
reg_cg_char_addr: equ 0x0B ; RW
|
||||
reg_cg_line_addr: equ 0x0C ; RW
|
||||
reg_cg_data: equ 0x0D ; RW
|
||||
reg_cg_ctrl: equ 0x0E ; WO
|
||||
reg_hwstat: equ 0x0E ; RO
|
||||
reg_color_red: equ 0x10 ; RW
|
||||
reg_color_grn: equ 0x11 ; RW
|
||||
reg_color_blu: equ 0x12 ; RW
|
||||
uart_baudrate: equ 0x13 ; R/W
|
||||
vga_read_addr: equ 0x14 ; R/W
|
||||
vga_read_addr0: equ 0x14 ; R/W
|
||||
vga_read_addr1: equ 0x15 ; R/W
|
||||
vga_read_addr2: equ 0x16 ; R/W
|
||||
timer_reload: equ 0x17 ; R/W
|
||||
timer_reload0: equ 0x17 ; R/W
|
||||
timer_reload1: equ 0x18 ; R/W
|
||||
timer_reload2: equ 0x19 ; R/W
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -0,0 +1,51 @@
|
||||
## NOTE: Do not edit this file.
|
||||
## Autogenerated by ProjNav (creatfdo.tcl) on Sat Feb 24 12:58:28 Westeuropäische Normalzeit 2007
|
||||
##
|
||||
vlib work
|
||||
# CPU
|
||||
vcom -explicit -93 "../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
|
||||
vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_types.vhd"
|
||||
vcom -explicit -93 "../src/systest/sdram_config.vhd"
|
||||
vcom -explicit -93 "../../../lib/misc/utils_pkg.vhd"
|
||||
vcom -explicit -93 "../../../lib/FIFO/src/gray_counter.vhd"
|
||||
vcom -explicit -93 "../../../lib/CPUs/JCpu/src/core/cpu_pkg.vhd"
|
||||
vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_sync.vhd"
|
||||
vcom -explicit -93 "../../../lib/VGA_ctrl/src/dpram.vhd"
|
||||
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_3/src/sdram_types.vhd"
|
||||
vcom -explicit -93 "../../../lib/FIFO/src/async_fifo_ctrl.vhd"
|
||||
vcom -explicit -93 "../src/systest/sdram_test_short_irom_ld.vhdl"
|
||||
vcom -explicit -93 "../../../lib/uart/kcuart_tx.vhd"
|
||||
vcom -explicit -93 "../../../lib/uart/kcuart_rx.vhd"
|
||||
vcom -explicit -93 "../../../lib/uart/bbfifo_16x8.vhd"
|
||||
vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_timing.vhd"
|
||||
vcom -explicit -93 "../../../lib/VGA_ctrl/src/linefifo.vhd"
|
||||
vcom -explicit -93 "../../../lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd"
|
||||
vcom -explicit -93 "../../../lib/VGA_ctrl/src/clkgen_virtex4.vhd"
|
||||
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_3/src/sdram_ctrl.vhd"
|
||||
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_3/src/sdram_cmd.vhd"
|
||||
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_3/src/reset_virtex4.vhd"
|
||||
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_3/src/ddr_phy_virtex4.vhd"
|
||||
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_3/src/clockgen_virtex4.vhd"
|
||||
vcom -explicit -93 "../../../lib/FIFO/src/sync_fifo_ctrl.vhd"
|
||||
vcom -explicit -93 "../src/systest/sdram_test_short_xrom_ld.vhdl"
|
||||
vcom -explicit -93 "../src/systest/cpu_embedded.vhd"
|
||||
vcom -explicit -93 "../../../lib/uart/uart_tx.vhd"
|
||||
vcom -explicit -93 "../../../lib/uart/uart_rx.vhd"
|
||||
vcom -explicit -93 "../../../lib/misc/lcd_port.vhd"
|
||||
vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_backend.vhd"
|
||||
vcom -explicit -93 "../../../lib/VGA_ctrl/src/char_gen.vhd"
|
||||
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_3/src/sdram_ctrl_top.vhd"
|
||||
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_3/src/fifo_sync.vhd"
|
||||
|
||||
# Top and TB
|
||||
vcom -explicit -93 "../src/systest/systest.vhd"
|
||||
vcom -explicit -93 "../src/systest/tb_systest.vhd"
|
||||
|
||||
vsim -t 1ps -lib work tb_systest
|
||||
do {tb_systest.wdo}
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
run 200us
|
||||
|
||||
|
||||
@@ -0,0 +1,18 @@
|
||||
## NOTE: Do not edit this file.
|
||||
## Auto generated by Project Navigator for Post-Map Simulation
|
||||
##
|
||||
vlib work
|
||||
## Compile Post-Map Model
|
||||
vcom -explicit -93 "../../../lib/CPUs/JCpu/src/core/cpu_pkg.vhd"
|
||||
vcom -explicit -93 "../src/systest/ddr_sdr_conf_pkg.vhd"
|
||||
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_2/src/mt46v16m16.vhd"
|
||||
vcom -93 "../ise91/systest/netgen/map/systest_map.vhd"
|
||||
vcom -93 "../src/systest/tb_systest.vhd"
|
||||
vsim -t 1ps -sdfmax "/UUT=../ise91/systest/netgen/map/systest_map.sdf" -lib work tb_systest
|
||||
#do {tb_systest.wdo}
|
||||
view wave
|
||||
add wave *
|
||||
view structure
|
||||
view signals
|
||||
run 2us
|
||||
## End
|
||||
@@ -0,0 +1,18 @@
|
||||
## NOTE: Do not edit this file.
|
||||
## Auto generated by Project Navigator for Post-Translate Simulation
|
||||
##
|
||||
vlib work
|
||||
## Compile Post-Translate Model
|
||||
vcom -explicit -93 "../../../lib/CPUs/JCpu/src/core/cpu_pkg.vhd"
|
||||
vcom -explicit -93 "../src/systest/ddr_sdr_conf_pkg.vhd"
|
||||
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_2/src/mt46v16m16.vhd"
|
||||
vcom -93 "../ise91/systest/netgen/translate/systest_translate.vhd"
|
||||
vcom -93 "../src/systest/tb_systest.vhd"
|
||||
vsim -t 1ps -lib work tb_systest
|
||||
#do {tb_systest.wdo}
|
||||
view wave
|
||||
add wave *
|
||||
view structure
|
||||
view signals
|
||||
run 5us
|
||||
## End
|
||||
@@ -0,0 +1,18 @@
|
||||
## NOTE: Do not edit this file.
|
||||
## Auto generated by Project Navigator for Post-PAR Simulation
|
||||
##
|
||||
vlib work
|
||||
## Compile Post-PAR Model
|
||||
vcom -explicit -93 "../../../lib/CPUs/JCpu/src/core/cpu_pkg.vhd"
|
||||
vcom -explicit -93 "../src/systest/sdr_config_pkg.vhd"
|
||||
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_3/src/sdr_pkg.vhd"
|
||||
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_3/src/mt46v16m16.vhd"
|
||||
vcom -93 "../ise91/systest/netgen/par/systest_timesim.vhd"
|
||||
vcom -93 "../src/systest/tb_systest.vhd"
|
||||
vsim -t 1ps -sdfmax "/UUT=../ise91/systest/netgen/par/systest_timesim.sdf" -lib work tb_systest
|
||||
view wave
|
||||
do {tb_systest.wtdo}
|
||||
view structure
|
||||
view signals
|
||||
run 20us
|
||||
## End
|
||||
@@ -0,0 +1,96 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -divider {DDR-CPU I/F}
|
||||
add wave -noupdate -divider LCD
|
||||
add wave -noupdate -divider UART
|
||||
add wave -noupdate -divider {DDR Ctrl SDRAM}
|
||||
add wave -noupdate -divider {CPU chipram}
|
||||
add wave -noupdate -divider CPU
|
||||
add wave -noupdate -divider {DDR Ctrl Host}
|
||||
add wave -noupdate -divider DCMs
|
||||
add wave -noupdate -divider {DDR-CPU I/F}
|
||||
add wave -noupdate -divider DCMs
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_systest/uut/cmd_fifo_dout
|
||||
add wave -noupdate -format Logic /tb_systest/uut/cmd_fifo_re
|
||||
add wave -noupdate -format Logic /tb_systest/uut/cmd_fifo_empty
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_systest/uut/cmd_fifo_din
|
||||
add wave -noupdate -format Logic /tb_systest/uut/cmd_fifo_we
|
||||
add wave -noupdate -format Logic /tb_systest/uut/cmd_fifo_full
|
||||
add wave -noupdate -format Logic /tb_systest/uut/sd_cpu_request
|
||||
add wave -noupdate -format Logic /tb_systest/uut/sd_vga_request
|
||||
add wave -noupdate -format Logic /tb_systest/uut/sd_cpu_access
|
||||
add wave -noupdate -format Logic /tb_systest/uut/sd_vga_access
|
||||
add wave -noupdate -divider {DDR-CPU I/F}
|
||||
add wave -noupdate -format Logic /tb_systest/uut/clk
|
||||
add wave -noupdate -format Logic /tb_systest/uut/rst
|
||||
add wave -noupdate -format Logic /tb_systest/sys_tx
|
||||
add wave -noupdate -format Logic /tb_systest/sys_sdr_clk_fb
|
||||
add wave -noupdate -format Logic /tb_systest/sys_rst_n_in
|
||||
add wave -noupdate -format Logic /tb_systest/sys_clk_in
|
||||
add wave -noupdate -format Literal /tb_systest/sys_error
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_systest/btn
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_systest/led
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_systest/uut/cpu_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_systest/uut/cpu_dout
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_systest/uut/cpu_addr
|
||||
add wave -noupdate -format Logic /tb_systest/uut/cpu_we
|
||||
add wave -noupdate -format Literal /tb_systest/uut/uart_status_port
|
||||
add wave -noupdate -format Logic /tb_systest/uut/cpu_re
|
||||
add wave -noupdate -format Logic /tb_systest/uut/write_to_uart
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_systest/uut/sdr_data
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_systest/uut/sdr_buf_in
|
||||
add wave -noupdate -format Logic /tb_systest/uut/clk
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_systest/uut/sdr_udata_out_q
|
||||
add wave -noupdate -format Logic -radix hexadecimal /tb_systest/uut/sdr_udata_vld_q
|
||||
add wave -noupdate -divider LCD
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_systest/uut/sys_lcd_d
|
||||
add wave -noupdate -format Logic /tb_systest/uut/sys_lcd_e
|
||||
add wave -noupdate -format Logic /tb_systest/uut/sys_lcd_rs
|
||||
add wave -noupdate -format Logic /tb_systest/uut/sys_lcd_rw
|
||||
add wave -noupdate -divider UART
|
||||
add wave -noupdate -format Logic /tb_systest/sys_rx
|
||||
add wave -noupdate -format Logic /tb_systest/sys_tx
|
||||
add wave -noupdate -divider {DDR Ctrl SDRAM}
|
||||
add wave -noupdate -format Logic /tb_systest/refresh
|
||||
add wave -noupdate -format Logic /tb_systest/sys_sdr_clk_p
|
||||
add wave -noupdate -format Logic /tb_systest/sys_sdr_clk_n
|
||||
add wave -noupdate -format Logic /tb_systest/sys_sdr_cke_q
|
||||
add wave -noupdate -format Logic /tb_systest/sys_sdr_cs_qn
|
||||
add wave -noupdate -format Logic /tb_systest/sys_sdr_ras_qn
|
||||
add wave -noupdate -format Logic /tb_systest/sys_sdr_cas_qn
|
||||
add wave -noupdate -format Logic /tb_systest/sys_sdr_we_qn
|
||||
add wave -noupdate -format Literal /tb_systest/sys_sdr_dm_q
|
||||
add wave -noupdate -format Literal /tb_systest/sys_sdr_dqs_q
|
||||
add wave -noupdate -format Literal /tb_systest/sys_sdr_ba_q
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_systest/sys_sdr_a_q
|
||||
add wave -noupdate -format Logic /tb_systest/uut/clk
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_systest/sys_sdr_data
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_systest/uut/sdr_udata_out_q
|
||||
add wave -noupdate -divider {DDR Ctrl Host}
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_systest/uut/sdr_buf_in
|
||||
add wave -noupdate -format Literal /tb_systest/uut/sdr_ucmd
|
||||
add wave -noupdate -format Logic /tb_systest/uut/sdr_ucmd_vld
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_systest/uut/sdr_addr
|
||||
add wave -noupdate -format Logic /tb_systest/uut/sdr_busy_q
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_systest/uut/sdr_udata_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_systest/uut/sdr_udata_out_q
|
||||
add wave -noupdate -format Logic /tb_systest/uut/sdr_udata_vld_q
|
||||
add wave -noupdate -divider DCMs
|
||||
add wave -noupdate -format Logic /tb_systest/sys_sdr_clk_fb
|
||||
add wave -noupdate -divider {DDR-CPU I/F}
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {13733736 ps} 0}
|
||||
configure wave -namecolwidth 205
|
||||
configure wave -valuecolwidth 144
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
update
|
||||
WaveRestoreZoom {13683002 ps} {13792198 ps}
|
||||
@@ -0,0 +1,50 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -format Logic /tb_systest/sys_rst_n_in
|
||||
add wave -noupdate -format Logic /tb_systest/sys_clk_in
|
||||
add wave -noupdate -format Literal /tb_systest/sys_error
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_systest/uut/sdr_buf_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_systest/uut/sdr_buf_out
|
||||
add wave -noupdate -format Logic /tb_systest/uut/clk
|
||||
add wave -noupdate -format Literal /tb_systest/dip
|
||||
add wave -noupdate -format Literal /tb_systest/btn
|
||||
add wave -noupdate -format Literal /tb_systest/led
|
||||
add wave -noupdate -format Logic -label Data_vld /tb_systest/uut/inst_sdram_ctrl_inst_ddr_phy_sdr_data_vld_53
|
||||
add wave -noupdate -format Logic /tb_systest/sys_rx
|
||||
add wave -noupdate -format Logic /tb_systest/sys_tx
|
||||
add wave -noupdate -format Literal /tb_systest/sys_lcd_d
|
||||
add wave -noupdate -format Logic /tb_systest/sys_lcd_e
|
||||
add wave -noupdate -format Logic /tb_systest/sys_lcd_rs
|
||||
add wave -noupdate -format Logic /tb_systest/sys_lcd_rw
|
||||
add wave -noupdate -format Logic /tb_systest/refresh
|
||||
add wave -noupdate -format Logic -label Read_clk /tb_systest/uut/inst_sdram_ctrl_inst_clockgen_read_clk0
|
||||
add wave -noupdate -format Logic /tb_systest/sys_sdr_clk_fb
|
||||
add wave -noupdate -format Logic /tb_systest/sys_sdr_clk_p
|
||||
add wave -noupdate -format Logic /tb_systest/sys_sdr_clk_n
|
||||
add wave -noupdate -format Logic /tb_systest/sys_sdr_cke_q
|
||||
add wave -noupdate -format Logic /tb_systest/sys_sdr_cs_qn
|
||||
add wave -noupdate -format Logic /tb_systest/sys_sdr_ras_qn
|
||||
add wave -noupdate -format Logic /tb_systest/sys_sdr_cas_qn
|
||||
add wave -noupdate -format Logic /tb_systest/sys_sdr_we_qn
|
||||
add wave -noupdate -format Literal /tb_systest/sys_sdr_dm_q
|
||||
add wave -noupdate -format Literal /tb_systest/sys_sdr_dqs_q
|
||||
add wave -noupdate -format Literal /tb_systest/sys_sdr_ba_q
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_systest/sys_sdr_a_q
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_systest/sys_sdr_data
|
||||
add wave -noupdate -format Logic /tb_systest/uut/clk
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {10626080 ps} 0} {{Cursor 4} {15061456 ps} 0} {{Cursor 3} {15953324 ps} 0}
|
||||
configure wave -namecolwidth 164
|
||||
configure wave -valuecolwidth 134
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
update
|
||||
WaveRestoreZoom {15924926 ps} {15982360 ps}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,318 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
ENTITY xrom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in dmem_addr_t;
|
||||
dout : out dmem_data_t
|
||||
);
|
||||
END xrom;
|
||||
|
||||
ARCHITECTURE counter OF xrom IS
|
||||
|
||||
type xmem_rom_t is array (0 to 255) of dmem_data_t;
|
||||
|
||||
-- Assembled from counter.jsm
|
||||
constant xmem_rom : xmem_rom_t :=
|
||||
(
|
||||
X"4A", -- 0x00
|
||||
X"2D", -- 0x01
|
||||
X"43", -- 0x02
|
||||
X"50", -- 0x03
|
||||
X"55", -- 0x04
|
||||
X"20", -- 0x05
|
||||
X"56", -- 0x06
|
||||
X"31", -- 0x07
|
||||
X"2E", -- 0x08
|
||||
X"00", -- 0x09
|
||||
X"00", -- 0x0A
|
||||
X"00", -- 0x0B
|
||||
X"00", -- 0x0C
|
||||
X"00", -- 0x0D
|
||||
X"00", -- 0x0E
|
||||
X"00", -- 0x0F
|
||||
X"00", -- 0x10
|
||||
X"00", -- 0x11
|
||||
X"00", -- 0x12
|
||||
X"00", -- 0x13
|
||||
X"00", -- 0x14
|
||||
X"00", -- 0x15
|
||||
X"00", -- 0x16
|
||||
X"00", -- 0x17
|
||||
X"00", -- 0x18
|
||||
X"00", -- 0x19
|
||||
X"00", -- 0x1A
|
||||
X"00", -- 0x1B
|
||||
X"00", -- 0x1C
|
||||
X"00", -- 0x1D
|
||||
X"00", -- 0x1E
|
||||
X"00", -- 0x1F
|
||||
X"00", -- 0x20
|
||||
X"00", -- 0x21
|
||||
X"00", -- 0x22
|
||||
X"00", -- 0x23
|
||||
X"00", -- 0x24
|
||||
X"00", -- 0x25
|
||||
X"00", -- 0x26
|
||||
X"00", -- 0x27
|
||||
X"00", -- 0x28
|
||||
X"00", -- 0x29
|
||||
X"00", -- 0x2A
|
||||
X"00", -- 0x2B
|
||||
X"00", -- 0x2C
|
||||
X"00", -- 0x2D
|
||||
X"00", -- 0x2E
|
||||
X"00", -- 0x2F
|
||||
X"00", -- 0x30
|
||||
X"00", -- 0x31
|
||||
X"00", -- 0x32
|
||||
X"00", -- 0x33
|
||||
X"00", -- 0x34
|
||||
X"00", -- 0x35
|
||||
X"00", -- 0x36
|
||||
X"00", -- 0x37
|
||||
X"00", -- 0x38
|
||||
X"00", -- 0x39
|
||||
X"00", -- 0x3A
|
||||
X"00", -- 0x3B
|
||||
X"00", -- 0x3C
|
||||
X"00", -- 0x3D
|
||||
X"00", -- 0x3E
|
||||
X"00", -- 0x3F
|
||||
X"00", -- 0x40
|
||||
X"00", -- 0x41
|
||||
X"00", -- 0x42
|
||||
X"00", -- 0x43
|
||||
X"00", -- 0x44
|
||||
X"00", -- 0x45
|
||||
X"00", -- 0x46
|
||||
X"00", -- 0x47
|
||||
X"00", -- 0x48
|
||||
X"00", -- 0x49
|
||||
X"00", -- 0x4A
|
||||
X"00", -- 0x4B
|
||||
X"00", -- 0x4C
|
||||
X"00", -- 0x4D
|
||||
X"00", -- 0x4E
|
||||
X"00", -- 0x4F
|
||||
X"00", -- 0x50
|
||||
X"00", -- 0x51
|
||||
X"00", -- 0x52
|
||||
X"00", -- 0x53
|
||||
X"00", -- 0x54
|
||||
X"00", -- 0x55
|
||||
X"00", -- 0x56
|
||||
X"00", -- 0x57
|
||||
X"00", -- 0x58
|
||||
X"00", -- 0x59
|
||||
X"00", -- 0x5A
|
||||
X"00", -- 0x5B
|
||||
X"00", -- 0x5C
|
||||
X"00", -- 0x5D
|
||||
X"00", -- 0x5E
|
||||
X"00", -- 0x5F
|
||||
X"00", -- 0x60
|
||||
X"00", -- 0x61
|
||||
X"00", -- 0x62
|
||||
X"00", -- 0x63
|
||||
X"00", -- 0x64
|
||||
X"00", -- 0x65
|
||||
X"00", -- 0x66
|
||||
X"00", -- 0x67
|
||||
X"00", -- 0x68
|
||||
X"00", -- 0x69
|
||||
X"00", -- 0x6A
|
||||
X"00", -- 0x6B
|
||||
X"00", -- 0x6C
|
||||
X"00", -- 0x6D
|
||||
X"00", -- 0x6E
|
||||
X"00", -- 0x6F
|
||||
X"00", -- 0x70
|
||||
X"00", -- 0x71
|
||||
X"00", -- 0x72
|
||||
X"00", -- 0x73
|
||||
X"00", -- 0x74
|
||||
X"00", -- 0x75
|
||||
X"00", -- 0x76
|
||||
X"00", -- 0x77
|
||||
X"00", -- 0x78
|
||||
X"00", -- 0x79
|
||||
X"00", -- 0x7A
|
||||
X"00", -- 0x7B
|
||||
X"00", -- 0x7C
|
||||
X"00", -- 0x7D
|
||||
X"00", -- 0x7E
|
||||
X"00", -- 0x7F
|
||||
X"00", -- 0x80
|
||||
X"00", -- 0x81
|
||||
X"00", -- 0x82
|
||||
X"00", -- 0x83
|
||||
X"00", -- 0x84
|
||||
X"00", -- 0x85
|
||||
X"00", -- 0x86
|
||||
X"00", -- 0x87
|
||||
X"00", -- 0x88
|
||||
X"00", -- 0x89
|
||||
X"00", -- 0x8A
|
||||
X"00", -- 0x8B
|
||||
X"00", -- 0x8C
|
||||
X"00", -- 0x8D
|
||||
X"00", -- 0x8E
|
||||
X"00", -- 0x8F
|
||||
X"00", -- 0x90
|
||||
X"00", -- 0x91
|
||||
X"00", -- 0x92
|
||||
X"00", -- 0x93
|
||||
X"00", -- 0x94
|
||||
X"00", -- 0x95
|
||||
X"00", -- 0x96
|
||||
X"00", -- 0x97
|
||||
X"00", -- 0x98
|
||||
X"00", -- 0x99
|
||||
X"00", -- 0x9A
|
||||
X"00", -- 0x9B
|
||||
X"00", -- 0x9C
|
||||
X"00", -- 0x9D
|
||||
X"00", -- 0x9E
|
||||
X"00", -- 0x9F
|
||||
X"00", -- 0xA0
|
||||
X"00", -- 0xA1
|
||||
X"00", -- 0xA2
|
||||
X"00", -- 0xA3
|
||||
X"00", -- 0xA4
|
||||
X"00", -- 0xA5
|
||||
X"00", -- 0xA6
|
||||
X"00", -- 0xA7
|
||||
X"00", -- 0xA8
|
||||
X"00", -- 0xA9
|
||||
X"00", -- 0xAA
|
||||
X"00", -- 0xAB
|
||||
X"00", -- 0xAC
|
||||
X"00", -- 0xAD
|
||||
X"00", -- 0xAE
|
||||
X"00", -- 0xAF
|
||||
X"00", -- 0xB0
|
||||
X"00", -- 0xB1
|
||||
X"00", -- 0xB2
|
||||
X"00", -- 0xB3
|
||||
X"00", -- 0xB4
|
||||
X"00", -- 0xB5
|
||||
X"00", -- 0xB6
|
||||
X"00", -- 0xB7
|
||||
X"00", -- 0xB8
|
||||
X"00", -- 0xB9
|
||||
X"00", -- 0xBA
|
||||
X"00", -- 0xBB
|
||||
X"00", -- 0xBC
|
||||
X"00", -- 0xBD
|
||||
X"00", -- 0xBE
|
||||
X"00", -- 0xBF
|
||||
X"00", -- 0xC0
|
||||
X"00", -- 0xC1
|
||||
X"00", -- 0xC2
|
||||
X"00", -- 0xC3
|
||||
X"00", -- 0xC4
|
||||
X"00", -- 0xC5
|
||||
X"00", -- 0xC6
|
||||
X"00", -- 0xC7
|
||||
X"00", -- 0xC8
|
||||
X"00", -- 0xC9
|
||||
X"00", -- 0xCA
|
||||
X"00", -- 0xCB
|
||||
X"00", -- 0xCC
|
||||
X"00", -- 0xCD
|
||||
X"00", -- 0xCE
|
||||
X"00", -- 0xCF
|
||||
X"00", -- 0xD0
|
||||
X"00", -- 0xD1
|
||||
X"00", -- 0xD2
|
||||
X"00", -- 0xD3
|
||||
X"00", -- 0xD4
|
||||
X"00", -- 0xD5
|
||||
X"00", -- 0xD6
|
||||
X"00", -- 0xD7
|
||||
X"00", -- 0xD8
|
||||
X"00", -- 0xD9
|
||||
X"00", -- 0xDA
|
||||
X"00", -- 0xDB
|
||||
X"00", -- 0xDC
|
||||
X"00", -- 0xDD
|
||||
X"00", -- 0xDE
|
||||
X"00", -- 0xDF
|
||||
X"00", -- 0xE0
|
||||
X"00", -- 0xE1
|
||||
X"00", -- 0xE2
|
||||
X"00", -- 0xE3
|
||||
X"00", -- 0xE4
|
||||
X"00", -- 0xE5
|
||||
X"00", -- 0xE6
|
||||
X"00", -- 0xE7
|
||||
X"00", -- 0xE8
|
||||
X"00", -- 0xE9
|
||||
X"00", -- 0xEA
|
||||
X"00", -- 0xEB
|
||||
X"00", -- 0xEC
|
||||
X"00", -- 0xED
|
||||
X"00", -- 0xEE
|
||||
X"00", -- 0xEF
|
||||
X"00", -- 0xF0
|
||||
X"00", -- 0xF1
|
||||
X"00", -- 0xF2
|
||||
X"00", -- 0xF3
|
||||
X"00", -- 0xF4
|
||||
X"00", -- 0xF5
|
||||
X"00", -- 0xF6
|
||||
X"00", -- 0xF7
|
||||
X"00", -- 0xF8
|
||||
X"00", -- 0xF9
|
||||
X"00", -- 0xFA
|
||||
X"00", -- 0xFB
|
||||
X"00", -- 0xFC
|
||||
X"00", -- 0xFD
|
||||
X"00", -- 0xFE
|
||||
X"00" -- 0xFF
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= xmem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end counter;
|
||||
|
||||
@@ -0,0 +1,414 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: loadable ROM
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library UNISIM;
|
||||
use UNISIM.VComponents.all;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
ENTITY xrom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in dmem_addr_t;
|
||||
dout : out dmem_data_t
|
||||
);
|
||||
|
||||
END xrom;
|
||||
|
||||
ARCHITECTURE loadable OF xrom IS
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
|
||||
-- Assembled from counter.jsm
|
||||
type xmem_rom_t is array (0 to 255) of dmem_data_t;
|
||||
signal xmem_rom : xmem_rom_t :=
|
||||
(
|
||||
X"4A", -- 0x00
|
||||
X"2D", -- 0x01
|
||||
X"43", -- 0x02
|
||||
X"50", -- 0x03
|
||||
X"55", -- 0x04
|
||||
X"20", -- 0x05
|
||||
X"56", -- 0x06
|
||||
X"31", -- 0x07
|
||||
X"2E", -- 0x08
|
||||
X"00", -- 0x09
|
||||
X"00", -- 0x0A
|
||||
X"00", -- 0x0B
|
||||
X"00", -- 0x0C
|
||||
X"00", -- 0x0D
|
||||
X"00", -- 0x0E
|
||||
X"00", -- 0x0F
|
||||
X"00", -- 0x10
|
||||
X"00", -- 0x11
|
||||
X"00", -- 0x12
|
||||
X"00", -- 0x13
|
||||
X"00", -- 0x14
|
||||
X"00", -- 0x15
|
||||
X"00", -- 0x16
|
||||
X"00", -- 0x17
|
||||
X"00", -- 0x18
|
||||
X"00", -- 0x19
|
||||
X"00", -- 0x1A
|
||||
X"00", -- 0x1B
|
||||
X"00", -- 0x1C
|
||||
X"00", -- 0x1D
|
||||
X"00", -- 0x1E
|
||||
X"00", -- 0x1F
|
||||
X"00", -- 0x20
|
||||
X"00", -- 0x21
|
||||
X"00", -- 0x22
|
||||
X"00", -- 0x23
|
||||
X"00", -- 0x24
|
||||
X"00", -- 0x25
|
||||
X"00", -- 0x26
|
||||
X"00", -- 0x27
|
||||
X"00", -- 0x28
|
||||
X"00", -- 0x29
|
||||
X"00", -- 0x2A
|
||||
X"00", -- 0x2B
|
||||
X"00", -- 0x2C
|
||||
X"00", -- 0x2D
|
||||
X"00", -- 0x2E
|
||||
X"00", -- 0x2F
|
||||
X"00", -- 0x30
|
||||
X"00", -- 0x31
|
||||
X"00", -- 0x32
|
||||
X"00", -- 0x33
|
||||
X"00", -- 0x34
|
||||
X"00", -- 0x35
|
||||
X"00", -- 0x36
|
||||
X"00", -- 0x37
|
||||
X"00", -- 0x38
|
||||
X"00", -- 0x39
|
||||
X"00", -- 0x3A
|
||||
X"00", -- 0x3B
|
||||
X"00", -- 0x3C
|
||||
X"00", -- 0x3D
|
||||
X"00", -- 0x3E
|
||||
X"00", -- 0x3F
|
||||
X"00", -- 0x40
|
||||
X"00", -- 0x41
|
||||
X"00", -- 0x42
|
||||
X"00", -- 0x43
|
||||
X"00", -- 0x44
|
||||
X"00", -- 0x45
|
||||
X"00", -- 0x46
|
||||
X"00", -- 0x47
|
||||
X"00", -- 0x48
|
||||
X"00", -- 0x49
|
||||
X"00", -- 0x4A
|
||||
X"00", -- 0x4B
|
||||
X"00", -- 0x4C
|
||||
X"00", -- 0x4D
|
||||
X"00", -- 0x4E
|
||||
X"00", -- 0x4F
|
||||
X"00", -- 0x50
|
||||
X"00", -- 0x51
|
||||
X"00", -- 0x52
|
||||
X"00", -- 0x53
|
||||
X"00", -- 0x54
|
||||
X"00", -- 0x55
|
||||
X"00", -- 0x56
|
||||
X"00", -- 0x57
|
||||
X"00", -- 0x58
|
||||
X"00", -- 0x59
|
||||
X"00", -- 0x5A
|
||||
X"00", -- 0x5B
|
||||
X"00", -- 0x5C
|
||||
X"00", -- 0x5D
|
||||
X"00", -- 0x5E
|
||||
X"00", -- 0x5F
|
||||
X"00", -- 0x60
|
||||
X"00", -- 0x61
|
||||
X"00", -- 0x62
|
||||
X"00", -- 0x63
|
||||
X"00", -- 0x64
|
||||
X"00", -- 0x65
|
||||
X"00", -- 0x66
|
||||
X"00", -- 0x67
|
||||
X"00", -- 0x68
|
||||
X"00", -- 0x69
|
||||
X"00", -- 0x6A
|
||||
X"00", -- 0x6B
|
||||
X"00", -- 0x6C
|
||||
X"00", -- 0x6D
|
||||
X"00", -- 0x6E
|
||||
X"00", -- 0x6F
|
||||
X"00", -- 0x70
|
||||
X"00", -- 0x71
|
||||
X"00", -- 0x72
|
||||
X"00", -- 0x73
|
||||
X"00", -- 0x74
|
||||
X"00", -- 0x75
|
||||
X"00", -- 0x76
|
||||
X"00", -- 0x77
|
||||
X"00", -- 0x78
|
||||
X"00", -- 0x79
|
||||
X"00", -- 0x7A
|
||||
X"00", -- 0x7B
|
||||
X"00", -- 0x7C
|
||||
X"00", -- 0x7D
|
||||
X"00", -- 0x7E
|
||||
X"00", -- 0x7F
|
||||
X"00", -- 0x80
|
||||
X"00", -- 0x81
|
||||
X"00", -- 0x82
|
||||
X"00", -- 0x83
|
||||
X"00", -- 0x84
|
||||
X"00", -- 0x85
|
||||
X"00", -- 0x86
|
||||
X"00", -- 0x87
|
||||
X"00", -- 0x88
|
||||
X"00", -- 0x89
|
||||
X"00", -- 0x8A
|
||||
X"00", -- 0x8B
|
||||
X"00", -- 0x8C
|
||||
X"00", -- 0x8D
|
||||
X"00", -- 0x8E
|
||||
X"00", -- 0x8F
|
||||
X"00", -- 0x90
|
||||
X"00", -- 0x91
|
||||
X"00", -- 0x92
|
||||
X"00", -- 0x93
|
||||
X"00", -- 0x94
|
||||
X"00", -- 0x95
|
||||
X"00", -- 0x96
|
||||
X"00", -- 0x97
|
||||
X"00", -- 0x98
|
||||
X"00", -- 0x99
|
||||
X"00", -- 0x9A
|
||||
X"00", -- 0x9B
|
||||
X"00", -- 0x9C
|
||||
X"00", -- 0x9D
|
||||
X"00", -- 0x9E
|
||||
X"00", -- 0x9F
|
||||
X"00", -- 0xA0
|
||||
X"00", -- 0xA1
|
||||
X"00", -- 0xA2
|
||||
X"00", -- 0xA3
|
||||
X"00", -- 0xA4
|
||||
X"00", -- 0xA5
|
||||
X"00", -- 0xA6
|
||||
X"00", -- 0xA7
|
||||
X"00", -- 0xA8
|
||||
X"00", -- 0xA9
|
||||
X"00", -- 0xAA
|
||||
X"00", -- 0xAB
|
||||
X"00", -- 0xAC
|
||||
X"00", -- 0xAD
|
||||
X"00", -- 0xAE
|
||||
X"00", -- 0xAF
|
||||
X"00", -- 0xB0
|
||||
X"00", -- 0xB1
|
||||
X"00", -- 0xB2
|
||||
X"00", -- 0xB3
|
||||
X"00", -- 0xB4
|
||||
X"00", -- 0xB5
|
||||
X"00", -- 0xB6
|
||||
X"00", -- 0xB7
|
||||
X"00", -- 0xB8
|
||||
X"00", -- 0xB9
|
||||
X"00", -- 0xBA
|
||||
X"00", -- 0xBB
|
||||
X"00", -- 0xBC
|
||||
X"00", -- 0xBD
|
||||
X"00", -- 0xBE
|
||||
X"00", -- 0xBF
|
||||
X"00", -- 0xC0
|
||||
X"00", -- 0xC1
|
||||
X"00", -- 0xC2
|
||||
X"00", -- 0xC3
|
||||
X"00", -- 0xC4
|
||||
X"00", -- 0xC5
|
||||
X"00", -- 0xC6
|
||||
X"00", -- 0xC7
|
||||
X"00", -- 0xC8
|
||||
X"00", -- 0xC9
|
||||
X"00", -- 0xCA
|
||||
X"00", -- 0xCB
|
||||
X"00", -- 0xCC
|
||||
X"00", -- 0xCD
|
||||
X"00", -- 0xCE
|
||||
X"00", -- 0xCF
|
||||
X"00", -- 0xD0
|
||||
X"00", -- 0xD1
|
||||
X"00", -- 0xD2
|
||||
X"00", -- 0xD3
|
||||
X"00", -- 0xD4
|
||||
X"00", -- 0xD5
|
||||
X"00", -- 0xD6
|
||||
X"00", -- 0xD7
|
||||
X"00", -- 0xD8
|
||||
X"00", -- 0xD9
|
||||
X"00", -- 0xDA
|
||||
X"00", -- 0xDB
|
||||
X"00", -- 0xDC
|
||||
X"00", -- 0xDD
|
||||
X"00", -- 0xDE
|
||||
X"00", -- 0xDF
|
||||
X"00", -- 0xE0
|
||||
X"00", -- 0xE1
|
||||
X"00", -- 0xE2
|
||||
X"00", -- 0xE3
|
||||
X"00", -- 0xE4
|
||||
X"00", -- 0xE5
|
||||
X"00", -- 0xE6
|
||||
X"00", -- 0xE7
|
||||
X"00", -- 0xE8
|
||||
X"00", -- 0xE9
|
||||
X"00", -- 0xEA
|
||||
X"00", -- 0xEB
|
||||
X"00", -- 0xEC
|
||||
X"00", -- 0xED
|
||||
X"00", -- 0xEE
|
||||
X"00", -- 0xEF
|
||||
X"00", -- 0xF0
|
||||
X"00", -- 0xF1
|
||||
X"00", -- 0xF2
|
||||
X"00", -- 0xF3
|
||||
X"00", -- 0xF4
|
||||
X"00", -- 0xF5
|
||||
X"00", -- 0xF6
|
||||
X"00", -- 0xF7
|
||||
X"00", -- 0xF8
|
||||
X"00", -- 0xF9
|
||||
X"00", -- 0xFA
|
||||
X"00", -- 0xFB
|
||||
X"00", -- 0xFC
|
||||
X"00", -- 0xFD
|
||||
X"00", -- 0xFE
|
||||
X"00" -- 0xFF
|
||||
);
|
||||
|
||||
signal jtag_ld_clk : STD_LOGIC;
|
||||
signal jtag_ld_we : STD_LOGIC;
|
||||
signal jtag_ld_addr : dmem_addr_t;
|
||||
signal jtag_ld_dout : dmem_data_t;
|
||||
signal jtag_ld_din : dmem_data_t;
|
||||
signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
|
||||
signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
|
||||
signal user_regi, user_rego : unsigned (15 downto 0);
|
||||
constant id : unsigned (15 downto 0) := X"BEEF";
|
||||
|
||||
begin
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- Virtex-4: JTAG Loader
|
||||
--------------------------------------------------------------------------
|
||||
i00_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_clk1,
|
||||
I => bs_clk0
|
||||
);
|
||||
|
||||
i01_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_update1,
|
||||
I => bs_update0
|
||||
);
|
||||
|
||||
BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4
|
||||
generic map
|
||||
(
|
||||
JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
|
||||
)
|
||||
port map
|
||||
(
|
||||
CAPTURE => bs_capture, -- CAPTURE output from TAP controller
|
||||
DRCK => bs_clk0, -- Data register output for USER functions
|
||||
RESET => bs_rst, -- Reset output from TAP controller
|
||||
SEL => bs_sel, -- USER active output
|
||||
SHIFT => bs_shift, -- SHIFT output from TAP controller
|
||||
TDI => bs_tdi, -- TDI output from TAP controller
|
||||
UPDATE => bs_update0, -- UPDATE output from TAP controller
|
||||
TDO => bs_tdo -- Data input for USER function
|
||||
);
|
||||
|
||||
jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1);
|
||||
jtag_ld_din <= user_regi(dmem_data_t'left downto 0);
|
||||
jtag_ld_clk <= bs_update1;
|
||||
jtag_ld_we <= bs_sel;
|
||||
|
||||
sipo:
|
||||
process (bs_rst, bs_clk1, bs_tdi, bs_shift)
|
||||
begin
|
||||
if bs_rst = '1' then
|
||||
user_regi <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
piso:
|
||||
process (bs_rst, bs_clk1, bs_shift, user_rego)
|
||||
begin
|
||||
bs_tdo <= user_rego(0);
|
||||
if bs_rst = '1' then
|
||||
user_rego <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
|
||||
else
|
||||
user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout;
|
||||
-- user_rego <= id;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- ROM Read/Write
|
||||
--------------------------------------------------------------------------
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= xmem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
PROM_WRITE:
|
||||
process(jtag_ld_clk, jtag_ld_we)
|
||||
begin
|
||||
if rising_edge(jtag_ld_clk) then
|
||||
if jtag_ld_we = '1' then
|
||||
xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
|
||||
else
|
||||
jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
end loadable;
|
||||
@@ -0,0 +1,107 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: cpu_embedded using cpu_core and rom
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
entity cpu_embedded is
|
||||
Port (
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
int_in : in STD_LOGIC;
|
||||
int_ack : out STD_LOGIC;
|
||||
xmem_we : out STD_LOGIC;
|
||||
xmem_re : out STD_LOGIC;
|
||||
xmem_din : in unsigned (DMEM_DATA_WIDTH-1 downto 0);
|
||||
xmem_dout : out unsigned (DMEM_DATA_WIDTH-1 downto 0);
|
||||
xmem_addr : out unsigned (DMEM_ADDR_WIDTH-1 downto 0);
|
||||
io_sel : out STD_LOGIC
|
||||
);
|
||||
end cpu_embedded;
|
||||
|
||||
architecture rtl of cpu_embedded is
|
||||
|
||||
signal rom_data : unsigned (IMEM_DATA_WIDTH-1 downto 0);
|
||||
signal rom_addr : unsigned (IMEM_ADDR_WIDTH-1 downto 0);
|
||||
|
||||
COMPONENT cpu
|
||||
Port (
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
int_in : in STD_LOGIC;
|
||||
int_ack : out STD_LOGIC;
|
||||
xmem_we : out STD_LOGIC;
|
||||
xmem_re : out STD_LOGIC;
|
||||
instr_din : in unsigned (IMEM_DATA_WIDTH-1 downto 0);
|
||||
instr_addr : out unsigned (IMEM_ADDR_WIDTH-1 downto 0);
|
||||
xmem_din : in unsigned (DMEM_DATA_WIDTH-1 downto 0);
|
||||
xmem_dout : out unsigned (DMEM_DATA_WIDTH-1 downto 0);
|
||||
xmem_addr : out unsigned (DMEM_DATA_WIDTH-1 downto 0);
|
||||
io_sel : out STD_LOGIC
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
|
||||
COMPONENT irom
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in inst_addr_t;
|
||||
dout : out inst_t
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
begin
|
||||
|
||||
inst_cpu: cpu
|
||||
PORT MAP(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
ce => ce,
|
||||
int_in => int_in,
|
||||
int_ack => int_ack,
|
||||
xmem_we => xmem_we,
|
||||
xmem_re => xmem_re,
|
||||
instr_din => rom_data,
|
||||
instr_addr => rom_addr,
|
||||
xmem_din => xmem_din,
|
||||
xmem_dout => xmem_dout,
|
||||
xmem_addr => xmem_addr,
|
||||
io_sel => io_sel
|
||||
);
|
||||
|
||||
inst_irom: irom
|
||||
PORT MAP(
|
||||
clk => clk,
|
||||
ce => ce,
|
||||
addr => rom_addr,
|
||||
dout => rom_data
|
||||
);
|
||||
|
||||
end rtl;
|
||||
@@ -0,0 +1,405 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
ENTITY irom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in inst_addr_t;
|
||||
dout : out inst_t
|
||||
);
|
||||
END irom;
|
||||
|
||||
ARCHITECTURE sdr_test OF irom IS
|
||||
|
||||
type imem_rom_t is array (0 to 342) of inst_t;
|
||||
|
||||
-- Assembled from sdr_test.jsm
|
||||
constant imem_rom : imem_rom_t :=
|
||||
(
|
||||
"110000" & X"002", -- 0x000: JMP 0x002
|
||||
"111111" & X"000", -- 0x001: RETI
|
||||
"111011" & X"0B1", -- 0x002: CALL 0x0B1
|
||||
"000011" & X"000", -- 0x003: MOV R00, 0x00
|
||||
"100100" & X"010", -- 0x004: XOUT (0x01), R00
|
||||
"000011" & X"010", -- 0x005: MOV R00, 0x01
|
||||
"111011" & X"0CE", -- 0x006: CALL 0x0CE
|
||||
"101000" & X"070", -- 0x007: XIN R00, (0x07)
|
||||
"100100" & X"010", -- 0x008: XOUT (0x01), R00
|
||||
"011001" & X"800", -- 0x009: AND R00, 0x80
|
||||
"110010" & X"007", -- 0x00A: JNZ 0x007
|
||||
"000011" & X"001", -- 0x00B: MOV R01, 0x00
|
||||
"111011" & X"0D3", -- 0x00C: CALL 0x0D3
|
||||
"101000" & X"040", -- 0x00D: XIN R00, (0x04)
|
||||
"011011" & X"100", -- 0x00E: OR R00, 0x10
|
||||
"100100" & X"040", -- 0x00F: XOUT (0x04), R00
|
||||
"111011" & X"129", -- 0x010: CALL 0x129
|
||||
"011011" & X"200", -- 0x011: OR R00, 0x20
|
||||
"100100" & X"040", -- 0x012: XOUT (0x04), R00
|
||||
"111011" & X"129", -- 0x013: CALL 0x129
|
||||
"011001" & X"EF0", -- 0x014: AND R00, 0xEF
|
||||
"100100" & X"040", -- 0x015: XOUT (0x04), R00
|
||||
"111011" & X"129", -- 0x016: CALL 0x129
|
||||
"011001" & X"CF0", -- 0x017: AND R00, 0xCF
|
||||
"100100" & X"040", -- 0x018: XOUT (0x04), R00
|
||||
"110000" & X"01A", -- 0x019: JMP 0x01A
|
||||
"000011" & X"010", -- 0x01A: MOV R00, 0x01
|
||||
"111011" & X"0CE", -- 0x01B: CALL 0x0CE
|
||||
"000011" & X"0B1", -- 0x01C: MOV R01, 0x0B
|
||||
"111011" & X"0D3", -- 0x01D: CALL 0x0D3
|
||||
"111011" & X"07F", -- 0x01E: CALL 0x07F
|
||||
"000011" & X"800", -- 0x01F: MOV R00, 0x80
|
||||
"000011" & X"08F", -- 0x020: MOV R15, 0x08
|
||||
"000111" & X"000", -- 0x021: MOVX (R00), 0x00
|
||||
"010001" & X"010", -- 0x022: INC R00
|
||||
"010101" & X"01F", -- 0x023: DEC R15
|
||||
"110010" & X"021", -- 0x024: JNZ 0x021
|
||||
"101000" & X"0A0", -- 0x025: XIN R00, (0x0A)
|
||||
"001111" & X"FF0", -- 0x026: CMP R00, 0xFF
|
||||
"111001" & X"031", -- 0x027: JEQ 0x031
|
||||
"101000" & X"070", -- 0x028: XIN R00, (0x07)
|
||||
"100100" & X"010", -- 0x029: XOUT (0x01), R00
|
||||
"011001" & X"020", -- 0x02A: AND R00, 0x02
|
||||
"110010" & X"028", -- 0x02B: JNZ 0x028
|
||||
"000011" & X"070", -- 0x02C: MOV R00, 0x07
|
||||
"100101" & X"020", -- 0x02D: XOUT (R00), 0x02
|
||||
"000011" & X"020", -- 0x02E: MOV R00, 0x02
|
||||
"111011" & X"086", -- 0x02F: CALL 0x086
|
||||
"110000" & X"025", -- 0x030: JMP 0x025
|
||||
"111011" & X"096", -- 0x031: CALL 0x096
|
||||
"111011" & X"122", -- 0x032: CALL 0x122
|
||||
"000011" & X"010", -- 0x033: MOV R00, 0x01
|
||||
"111011" & X"0CE", -- 0x034: CALL 0x0CE
|
||||
"000011" & X"1A1", -- 0x035: MOV R01, 0x1A
|
||||
"111011" & X"0D3", -- 0x036: CALL 0x0D3
|
||||
"111011" & X"07F", -- 0x037: CALL 0x07F
|
||||
"000011" & X"000", -- 0x038: MOV R00, 0x00
|
||||
"001101" & X"000", -- 0x039: MOVC (0x00), R00
|
||||
"101000" & X"0A0", -- 0x03A: XIN R00, (0x0A)
|
||||
"001111" & X"FF0", -- 0x03B: CMP R00, 0xFF
|
||||
"111001" & X"051", -- 0x03C: JEQ 0x051
|
||||
"001010" & X"001", -- 0x03D: MOVC R01, (0x00)
|
||||
"000011" & X"800", -- 0x03E: MOV R00, 0x80
|
||||
"000011" & X"08F", -- 0x03F: MOV R15, 0x08
|
||||
"000110" & X"001", -- 0x040: MOVX (R01), R00
|
||||
"010001" & X"010", -- 0x041: INC R00
|
||||
"010001" & X"011", -- 0x042: INC R01
|
||||
"010101" & X"01F", -- 0x043: DEC R15
|
||||
"110010" & X"040", -- 0x044: JNZ 0x040
|
||||
"101000" & X"070", -- 0x045: XIN R00, (0x07)
|
||||
"100100" & X"010", -- 0x046: XOUT (0x01), R00
|
||||
"011001" & X"020", -- 0x047: AND R00, 0x02
|
||||
"110010" & X"045", -- 0x048: JNZ 0x045
|
||||
"000011" & X"070", -- 0x049: MOV R00, 0x07
|
||||
"100101" & X"020", -- 0x04A: XOUT (R00), 0x02
|
||||
"000011" & X"020", -- 0x04B: MOV R00, 0x02
|
||||
"111011" & X"086", -- 0x04C: CALL 0x086
|
||||
"001010" & X"000", -- 0x04D: MOVC R00, (0x00)
|
||||
"010001" & X"010", -- 0x04E: INC R00
|
||||
"001101" & X"000", -- 0x04F: MOVC (0x00), R00
|
||||
"110000" & X"03A", -- 0x050: JMP 0x03A
|
||||
"111011" & X"096", -- 0x051: CALL 0x096
|
||||
"111011" & X"122", -- 0x052: CALL 0x122
|
||||
"000011" & X"010", -- 0x053: MOV R00, 0x01
|
||||
"111011" & X"0CE", -- 0x054: CALL 0x0CE
|
||||
"000011" & X"281", -- 0x055: MOV R01, 0x28
|
||||
"111011" & X"0D3", -- 0x056: CALL 0x0D3
|
||||
"111011" & X"07F", -- 0x057: CALL 0x07F
|
||||
"000011" & X"000", -- 0x058: MOV R00, 0x00
|
||||
"001101" & X"000", -- 0x059: MOVC (0x00), R00
|
||||
"101000" & X"0A0", -- 0x05A: XIN R00, (0x0A)
|
||||
"001111" & X"FF0", -- 0x05B: CMP R00, 0xFF
|
||||
"111001" & X"073", -- 0x05C: JEQ 0x073
|
||||
"000011" & X"070", -- 0x05D: MOV R00, 0x07
|
||||
"100101" & X"010", -- 0x05E: XOUT (R00), 0x01
|
||||
"101000" & X"070", -- 0x05F: XIN R00, (0x07)
|
||||
"100100" & X"010", -- 0x060: XOUT (0x01), R00
|
||||
"011001" & X"010", -- 0x061: AND R00, 0x01
|
||||
"110010" & X"05F", -- 0x062: JNZ 0x05F
|
||||
"001010" & X"001", -- 0x063: MOVC R01, (0x00)
|
||||
"000011" & X"800", -- 0x064: MOV R00, 0x80
|
||||
"000011" & X"08F", -- 0x065: MOV R15, 0x08
|
||||
"000100" & X"002", -- 0x066: MOVX R02, (R00)
|
||||
"001110" & X"012", -- 0x067: CMP R02, R01
|
||||
"111010" & X"078", -- 0x068: JNE 0x078
|
||||
"010001" & X"010", -- 0x069: INC R00
|
||||
"010001" & X"011", -- 0x06A: INC R01
|
||||
"010101" & X"01F", -- 0x06B: DEC R15
|
||||
"110010" & X"066", -- 0x06C: JNZ 0x066
|
||||
"000011" & X"020", -- 0x06D: MOV R00, 0x02
|
||||
"111011" & X"086", -- 0x06E: CALL 0x086
|
||||
"001010" & X"000", -- 0x06F: MOVC R00, (0x00)
|
||||
"010001" & X"010", -- 0x070: INC R00
|
||||
"001101" & X"000", -- 0x071: MOVC (0x00), R00
|
||||
"110000" & X"05A", -- 0x072: JMP 0x05A
|
||||
"000011" & X"C00", -- 0x073: MOV R00, 0xC0
|
||||
"111011" & X"0CE", -- 0x074: CALL 0x0CE
|
||||
"000011" & X"361", -- 0x075: MOV R01, 0x36
|
||||
"111011" & X"0D3", -- 0x076: CALL 0x0D3
|
||||
"110000" & X"07D", -- 0x077: JMP 0x07D
|
||||
"000011" & X"C00", -- 0x078: MOV R00, 0xC0
|
||||
"111011" & X"0CE", -- 0x079: CALL 0x0CE
|
||||
"000011" & X"401", -- 0x07A: MOV R01, 0x40
|
||||
"111011" & X"0D3", -- 0x07B: CALL 0x0D3
|
||||
"110000" & X"07D", -- 0x07C: JMP 0x07D
|
||||
"111011" & X"122", -- 0x07D: CALL 0x122
|
||||
"110000" & X"01A", -- 0x07E: JMP 0x01A
|
||||
"111100" & X"000", -- 0x07F: PUSH R00
|
||||
"000011" & X"000", -- 0x080: MOV R00, 0x00
|
||||
"100100" & X"080", -- 0x081: XOUT (0x08), R00
|
||||
"100100" & X"090", -- 0x082: XOUT (0x09), R00
|
||||
"100100" & X"0A0", -- 0x083: XOUT (0x0A), R00
|
||||
"111101" & X"000", -- 0x084: POP R00
|
||||
"111110" & X"000", -- 0x085: RET
|
||||
"111100" & X"001", -- 0x086: PUSH R01
|
||||
"111100" & X"002", -- 0x087: PUSH R02
|
||||
"111100" & X"003", -- 0x088: PUSH R03
|
||||
"101000" & X"081", -- 0x089: XIN R01, (0x08)
|
||||
"101000" & X"092", -- 0x08A: XIN R02, (0x09)
|
||||
"101000" & X"0A3", -- 0x08B: XIN R03, (0x0A)
|
||||
"010000" & X"001", -- 0x08C: ADD R01, R00
|
||||
"010011" & X"002", -- 0x08D: ADDC R02, 0x00
|
||||
"010011" & X"003", -- 0x08E: ADDC R03, 0x00
|
||||
"100100" & X"081", -- 0x08F: XOUT (0x08), R01
|
||||
"100100" & X"092", -- 0x090: XOUT (0x09), R02
|
||||
"100100" & X"0A3", -- 0x091: XOUT (0x0A), R03
|
||||
"111101" & X"003", -- 0x092: POP R03
|
||||
"111101" & X"002", -- 0x093: POP R02
|
||||
"111101" & X"001", -- 0x094: POP R01
|
||||
"111110" & X"000", -- 0x095: RET
|
||||
"000011" & X"C00", -- 0x096: MOV R00, 0xC0
|
||||
"111011" & X"0CE", -- 0x097: CALL 0x0CE
|
||||
"101000" & X"0A0", -- 0x098: XIN R00, (0x0A)
|
||||
"111011" & X"09F", -- 0x099: CALL 0x09F
|
||||
"101000" & X"090", -- 0x09A: XIN R00, (0x09)
|
||||
"111011" & X"09F", -- 0x09B: CALL 0x09F
|
||||
"101000" & X"080", -- 0x09C: XIN R00, (0x08)
|
||||
"111011" & X"09F", -- 0x09D: CALL 0x09F
|
||||
"111110" & X"000", -- 0x09E: RET
|
||||
"111011" & X"0AA", -- 0x09F: CALL 0x0AA
|
||||
"111011" & X"0E5", -- 0x0A0: CALL 0x0E5
|
||||
"000010" & X"010", -- 0x0A1: MOV R00, R01
|
||||
"111011" & X"0E5", -- 0x0A2: CALL 0x0E5
|
||||
"111110" & X"000", -- 0x0A3: RET
|
||||
"011001" & X"0F0", -- 0x0A4: AND R00, 0x0F
|
||||
"001111" & X"0A0", -- 0x0A5: CMP R00, 0x0A
|
||||
"110101" & X"0A8", -- 0x0A6: JLT 0x0A8
|
||||
"010001" & X"070", -- 0x0A7: ADD R00, 0x07
|
||||
"010001" & X"300", -- 0x0A8: ADD R00, 0x30
|
||||
"111110" & X"000", -- 0x0A9: RET
|
||||
"111100" & X"000", -- 0x0AA: PUSH R00
|
||||
"111011" & X"0A4", -- 0x0AB: CALL 0x0A4
|
||||
"000010" & X"001", -- 0x0AC: MOV R01, R00
|
||||
"111101" & X"000", -- 0x0AD: POP R00
|
||||
"101010" & X"000", -- 0x0AE: SWAP R00
|
||||
"111011" & X"0A4", -- 0x0AF: CALL 0x0A4
|
||||
"111110" & X"000", -- 0x0B0: RET
|
||||
"000011" & X"002", -- 0x0B1: MOV R02, 0x00
|
||||
"000011" & X"030", -- 0x0B2: MOV R00, 0x03
|
||||
"111011" & X"0FD", -- 0x0B3: CALL 0x0FD
|
||||
"111011" & X"130", -- 0x0B4: CALL 0x130
|
||||
"000011" & X"002", -- 0x0B5: MOV R02, 0x00
|
||||
"000011" & X"030", -- 0x0B6: MOV R00, 0x03
|
||||
"111011" & X"0FD", -- 0x0B7: CALL 0x0FD
|
||||
"111011" & X"130", -- 0x0B8: CALL 0x130
|
||||
"000011" & X"002", -- 0x0B9: MOV R02, 0x00
|
||||
"000011" & X"020", -- 0x0BA: MOV R00, 0x02
|
||||
"111011" & X"0FD", -- 0x0BB: CALL 0x0FD
|
||||
"111011" & X"137", -- 0x0BC: CALL 0x137
|
||||
"000011" & X"280", -- 0x0BD: MOV R00, 0x28
|
||||
"111011" & X"0CE", -- 0x0BE: CALL 0x0CE
|
||||
"000011" & X"0C0", -- 0x0BF: MOV R00, 0x0C
|
||||
"111011" & X"0CE", -- 0x0C0: CALL 0x0CE
|
||||
"000011" & X"060", -- 0x0C1: MOV R00, 0x06
|
||||
"111011" & X"0CE", -- 0x0C2: CALL 0x0CE
|
||||
"000011" & X"010", -- 0x0C3: MOV R00, 0x01
|
||||
"111011" & X"0CE", -- 0x0C4: CALL 0x0CE
|
||||
"111110" & X"000", -- 0x0C5: RET
|
||||
"111100" & X"000", -- 0x0C6: PUSH R00
|
||||
"111011" & X"0F1", -- 0x0C7: CALL 0x0F1
|
||||
"011001" & X"800", -- 0x0C8: AND R00, 0x80
|
||||
"110001" & X"0CC", -- 0x0C9: JZ 0x0CC
|
||||
"111011" & X"14E", -- 0x0CA: CALL 0x14E
|
||||
"110000" & X"0C7", -- 0x0CB: JMP 0x0C7
|
||||
"111101" & X"000", -- 0x0CC: POP R00
|
||||
"111110" & X"000", -- 0x0CD: RET
|
||||
"111100" & X"002", -- 0x0CE: PUSH R02
|
||||
"000011" & X"002", -- 0x0CF: MOV R02, 0x00
|
||||
"111011" & X"0EA", -- 0x0D0: CALL 0x0EA
|
||||
"111101" & X"002", -- 0x0D1: POP R02
|
||||
"111110" & X"000", -- 0x0D2: RET
|
||||
"111100" & X"000", -- 0x0D3: PUSH R00
|
||||
"000100" & X"010", -- 0x0D4: MOVX R00, (R01)
|
||||
"010001" & X"011", -- 0x0D5: INC R01
|
||||
"001111" & X"000", -- 0x0D6: TST R00
|
||||
"110001" & X"0DA", -- 0x0D7: JZ 0x0DA
|
||||
"111011" & X"0E5", -- 0x0D8: CALL 0x0E5
|
||||
"110000" & X"0D4", -- 0x0D9: JMP 0x0D4
|
||||
"111101" & X"000", -- 0x0DA: POP R00
|
||||
"111110" & X"000", -- 0x0DB: RET
|
||||
"111100" & X"000", -- 0x0DC: PUSH R00
|
||||
"001001" & X"010", -- 0x0DD: MOVC R00, (R01)
|
||||
"010001" & X"011", -- 0x0DE: INC R01
|
||||
"001111" & X"000", -- 0x0DF: TST R00
|
||||
"110001" & X"0E3", -- 0x0E0: JZ 0x0E3
|
||||
"111011" & X"0E5", -- 0x0E1: CALL 0x0E5
|
||||
"110000" & X"0DD", -- 0x0E2: JMP 0x0DD
|
||||
"111101" & X"000", -- 0x0E3: POP R00
|
||||
"111110" & X"000", -- 0x0E4: RET
|
||||
"111100" & X"002", -- 0x0E5: PUSH R02
|
||||
"000011" & X"402", -- 0x0E6: MOV R02, 0x40
|
||||
"111011" & X"0EA", -- 0x0E7: CALL 0x0EA
|
||||
"111101" & X"002", -- 0x0E8: POP R02
|
||||
"111110" & X"000", -- 0x0E9: RET
|
||||
"111011" & X"0C6", -- 0x0EA: CALL 0x0C6
|
||||
"111100" & X"000", -- 0x0EB: PUSH R00
|
||||
"101010" & X"000", -- 0x0EC: SWAP R00
|
||||
"111011" & X"0FD", -- 0x0ED: CALL 0x0FD
|
||||
"111101" & X"000", -- 0x0EE: POP R00
|
||||
"111011" & X"0FD", -- 0x0EF: CALL 0x0FD
|
||||
"111110" & X"000", -- 0x0F0: RET
|
||||
"111100" & X"002", -- 0x0F1: PUSH R02
|
||||
"000011" & X"002", -- 0x0F2: MOV R02, 0x00
|
||||
"111011" & X"0F6", -- 0x0F3: CALL 0x0F6
|
||||
"111101" & X"002", -- 0x0F4: POP R02
|
||||
"111110" & X"000", -- 0x0F5: RET
|
||||
"111011" & X"110", -- 0x0F6: CALL 0x110
|
||||
"101010" & X"000", -- 0x0F7: SWAP R00
|
||||
"111100" & X"000", -- 0x0F8: PUSH R00
|
||||
"111011" & X"110", -- 0x0F9: CALL 0x110
|
||||
"111101" & X"002", -- 0x0FA: POP R02
|
||||
"011010" & X"020", -- 0x0FB: OR R00, R02
|
||||
"111110" & X"000", -- 0x0FC: RET
|
||||
"111100" & X"001", -- 0x0FD: PUSH R01
|
||||
"011001" & X"0F0", -- 0x0FE: AND R00, 0x0F
|
||||
"000010" & X"001", -- 0x0FF: MOV R01, R00
|
||||
"011010" & X"021", -- 0x100: OR R01, R02
|
||||
"100100" & X"031", -- 0x101: XOUT (0x03), R01
|
||||
"111011" & X"14E", -- 0x102: CALL 0x14E
|
||||
"000010" & X"001", -- 0x103: MOV R01, R00
|
||||
"011010" & X"021", -- 0x104: OR R01, R02
|
||||
"011011" & X"801", -- 0x105: OR R01, 0x80
|
||||
"100100" & X"031", -- 0x106: XOUT (0x03), R01
|
||||
"111011" & X"14E", -- 0x107: CALL 0x14E
|
||||
"000010" & X"001", -- 0x108: MOV R01, R00
|
||||
"011010" & X"021", -- 0x109: OR R01, R02
|
||||
"100100" & X"031", -- 0x10A: XOUT (0x03), R01
|
||||
"111011" & X"14E", -- 0x10B: CALL 0x14E
|
||||
"011011" & X"201", -- 0x10C: OR R01, 0x20
|
||||
"100100" & X"031", -- 0x10D: XOUT (0x03), R01
|
||||
"111101" & X"001", -- 0x10E: POP R01
|
||||
"111110" & X"000", -- 0x10F: RET
|
||||
"111100" & X"001", -- 0x110: PUSH R01
|
||||
"000011" & X"201", -- 0x111: MOV R01, 0x20
|
||||
"011010" & X"021", -- 0x112: OR R01, R02
|
||||
"100100" & X"031", -- 0x113: XOUT (0x03), R01
|
||||
"111011" & X"14E", -- 0x114: CALL 0x14E
|
||||
"000011" & X"201", -- 0x115: MOV R01, 0x20
|
||||
"011010" & X"021", -- 0x116: OR R01, R02
|
||||
"011011" & X"801", -- 0x117: OR R01, 0x80
|
||||
"100100" & X"031", -- 0x118: XOUT (0x03), R01
|
||||
"111011" & X"14E", -- 0x119: CALL 0x14E
|
||||
"101000" & X"030", -- 0x11A: XIN R00, (0x03)
|
||||
"011001" & X"0F0", -- 0x11B: AND R00, 0x0F
|
||||
"000011" & X"201", -- 0x11C: MOV R01, 0x20
|
||||
"011010" & X"021", -- 0x11D: OR R01, R02
|
||||
"100100" & X"031", -- 0x11E: XOUT (0x03), R01
|
||||
"111011" & X"14E", -- 0x11F: CALL 0x14E
|
||||
"111101" & X"001", -- 0x120: POP R01
|
||||
"111110" & X"000", -- 0x121: RET
|
||||
"111100" & X"00F", -- 0x122: PUSH R15
|
||||
"000011" & X"0AF", -- 0x123: MOV R15, 0x0A
|
||||
"111011" & X"129", -- 0x124: CALL 0x129
|
||||
"010101" & X"01F", -- 0x125: DEC R15
|
||||
"110010" & X"124", -- 0x126: JNZ 0x124
|
||||
"111101" & X"00F", -- 0x127: POP R15
|
||||
"111110" & X"000", -- 0x128: RET
|
||||
"111100" & X"00F", -- 0x129: PUSH R15
|
||||
"000011" & X"0AF", -- 0x12A: MOV R15, 0x0A
|
||||
"111011" & X"130", -- 0x12B: CALL 0x130
|
||||
"010101" & X"01F", -- 0x12C: DEC R15
|
||||
"110010" & X"12B", -- 0x12D: JNZ 0x12B
|
||||
"111101" & X"00F", -- 0x12E: POP R15
|
||||
"111110" & X"000", -- 0x12F: RET
|
||||
"111100" & X"00F", -- 0x130: PUSH R15
|
||||
"000011" & X"0AF", -- 0x131: MOV R15, 0x0A
|
||||
"111011" & X"137", -- 0x132: CALL 0x137
|
||||
"010101" & X"01F", -- 0x133: DEC R15
|
||||
"110010" & X"132", -- 0x134: JNZ 0x132
|
||||
"111101" & X"00F", -- 0x135: POP R15
|
||||
"111110" & X"000", -- 0x136: RET
|
||||
"111100" & X"00F", -- 0x137: PUSH R15
|
||||
"000011" & X"0AF", -- 0x138: MOV R15, 0x0A
|
||||
"111011" & X"13E", -- 0x139: CALL 0x13E
|
||||
"010101" & X"01F", -- 0x13A: DEC R15
|
||||
"110010" & X"139", -- 0x13B: JNZ 0x139
|
||||
"111101" & X"00F", -- 0x13C: POP R15
|
||||
"111110" & X"000", -- 0x13D: RET
|
||||
"111100" & X"00F", -- 0x13E: PUSH R15
|
||||
"000011" & X"0AF", -- 0x13F: MOV R15, 0x0A
|
||||
"111011" & X"145", -- 0x140: CALL 0x145
|
||||
"010101" & X"01F", -- 0x141: DEC R15
|
||||
"110010" & X"140", -- 0x142: JNZ 0x140
|
||||
"111101" & X"00F", -- 0x143: POP R15
|
||||
"111110" & X"000", -- 0x144: RET
|
||||
"111100" & X"00F", -- 0x145: PUSH R15
|
||||
"000011" & X"63F", -- 0x146: MOV R15, 0x63
|
||||
"000000" & X"000", -- 0x147: NOP
|
||||
"000000" & X"000", -- 0x148: NOP
|
||||
"000000" & X"000", -- 0x149: NOP
|
||||
"010101" & X"01F", -- 0x14A: DEC R15
|
||||
"110010" & X"147", -- 0x14B: JNZ 0x147
|
||||
"111101" & X"00F", -- 0x14C: POP R15
|
||||
"111110" & X"000", -- 0x14D: RET
|
||||
"111100" & X"00F", -- 0x14E: PUSH R15
|
||||
"000011" & X"09F", -- 0x14F: MOV R15, 0x09
|
||||
"000000" & X"000", -- 0x150: NOP
|
||||
"000000" & X"000", -- 0x151: NOP
|
||||
"000000" & X"000", -- 0x152: NOP
|
||||
"010101" & X"01F", -- 0x153: DEC R15
|
||||
"110010" & X"150", -- 0x154: JNZ 0x150
|
||||
"111101" & X"00F", -- 0x155: POP R15
|
||||
"111110" & X"000" -- 0x156: RET
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= imem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end sdr_test;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,172 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
ENTITY irom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in inst_addr_t;
|
||||
dout : out inst_t
|
||||
);
|
||||
END irom;
|
||||
|
||||
ARCHITECTURE sdr_test_short OF irom IS
|
||||
|
||||
type imem_rom_t is array (0 to 110) of inst_t;
|
||||
|
||||
-- Assembled from sdr_test_short.jsm
|
||||
constant imem_rom : imem_rom_t :=
|
||||
(
|
||||
"110000" & X"002", -- 0x000: JMP 0x002
|
||||
"111111" & X"000", -- 0x001: RETI
|
||||
"000011" & X"000", -- 0x002: MOV R00, 0x00
|
||||
"100100" & X"010", -- 0x003: XOUT (0x01), R00
|
||||
"101000" & X"040", -- 0x004: XIN R00, (0x04)
|
||||
"011001" & X"CF0", -- 0x005: AND R00, 0xCF
|
||||
"100100" & X"040", -- 0x006: XOUT (0x04), R00
|
||||
"101000" & X"070", -- 0x007: XIN R00, (0x07)
|
||||
"011001" & X"800", -- 0x008: AND R00, 0x80
|
||||
"110010" & X"007", -- 0x009: JNZ 0x007
|
||||
"110000" & X"00B", -- 0x00A: JMP 0x00B
|
||||
"111011" & X"058", -- 0x00B: CALL 0x058
|
||||
"000011" & X"800", -- 0x00C: MOV R00, 0x80
|
||||
"000011" & X"08F", -- 0x00D: MOV R15, 0x08
|
||||
"000111" & X"000", -- 0x00E: MOVX (R00), 0x00
|
||||
"010001" & X"010", -- 0x00F: INC R00
|
||||
"010101" & X"01F", -- 0x010: DEC R15
|
||||
"110010" & X"00E", -- 0x011: JNZ 0x00E
|
||||
"101000" & X"080", -- 0x012: XIN R00, (0x08)
|
||||
"001111" & X"080", -- 0x013: CMP R00, 0x08
|
||||
"111001" & X"01D", -- 0x014: JEQ 0x01D
|
||||
"101000" & X"070", -- 0x015: XIN R00, (0x07)
|
||||
"011001" & X"020", -- 0x016: AND R00, 0x02
|
||||
"110010" & X"015", -- 0x017: JNZ 0x015
|
||||
"000011" & X"070", -- 0x018: MOV R00, 0x07
|
||||
"100101" & X"020", -- 0x019: XOUT (R00), 0x02
|
||||
"000011" & X"020", -- 0x01A: MOV R00, 0x02
|
||||
"111011" & X"05F", -- 0x01B: CALL 0x05F
|
||||
"110000" & X"012", -- 0x01C: JMP 0x012
|
||||
"111011" & X"058", -- 0x01D: CALL 0x058
|
||||
"000011" & X"000", -- 0x01E: MOV R00, 0x00
|
||||
"001101" & X"000", -- 0x01F: MOVC (0x00), R00
|
||||
"101000" & X"080", -- 0x020: XIN R00, (0x08)
|
||||
"001111" & X"080", -- 0x021: CMP R00, 0x08
|
||||
"111001" & X"037", -- 0x022: JEQ 0x037
|
||||
"001010" & X"001", -- 0x023: MOVC R01, (0x00)
|
||||
"000011" & X"800", -- 0x024: MOV R00, 0x80
|
||||
"000011" & X"08F", -- 0x025: MOV R15, 0x08
|
||||
"000110" & X"001", -- 0x026: MOVX (R01), R00
|
||||
"010001" & X"010", -- 0x027: INC R00
|
||||
"010001" & X"011", -- 0x028: INC R01
|
||||
"010101" & X"01F", -- 0x029: DEC R15
|
||||
"110010" & X"026", -- 0x02A: JNZ 0x026
|
||||
"101000" & X"070", -- 0x02B: XIN R00, (0x07)
|
||||
"011001" & X"020", -- 0x02C: AND R00, 0x02
|
||||
"110010" & X"02B", -- 0x02D: JNZ 0x02B
|
||||
"000000" & X"000", -- 0x02E: NOP
|
||||
"000011" & X"070", -- 0x02F: MOV R00, 0x07
|
||||
"100101" & X"020", -- 0x030: XOUT (R00), 0x02
|
||||
"000011" & X"020", -- 0x031: MOV R00, 0x02
|
||||
"111011" & X"05F", -- 0x032: CALL 0x05F
|
||||
"001010" & X"000", -- 0x033: MOVC R00, (0x00)
|
||||
"010001" & X"010", -- 0x034: INC R00
|
||||
"001101" & X"000", -- 0x035: MOVC (0x00), R00
|
||||
"110000" & X"020", -- 0x036: JMP 0x020
|
||||
"111011" & X"058", -- 0x037: CALL 0x058
|
||||
"000011" & X"000", -- 0x038: MOV R00, 0x00
|
||||
"001101" & X"000", -- 0x039: MOVC (0x00), R00
|
||||
"101000" & X"080", -- 0x03A: XIN R00, (0x08)
|
||||
"001111" & X"080", -- 0x03B: CMP R00, 0x08
|
||||
"111001" & X"052", -- 0x03C: JEQ 0x052
|
||||
"000011" & X"070", -- 0x03D: MOV R00, 0x07
|
||||
"100101" & X"010", -- 0x03E: XOUT (R00), 0x01
|
||||
"101000" & X"070", -- 0x03F: XIN R00, (0x07)
|
||||
"011001" & X"010", -- 0x040: AND R00, 0x01
|
||||
"110010" & X"03F", -- 0x041: JNZ 0x03F
|
||||
"001010" & X"001", -- 0x042: MOVC R01, (0x00)
|
||||
"000011" & X"800", -- 0x043: MOV R00, 0x80
|
||||
"000011" & X"08F", -- 0x044: MOV R15, 0x08
|
||||
"000100" & X"002", -- 0x045: MOVX R02, (R00)
|
||||
"001110" & X"012", -- 0x046: CMP R02, R01
|
||||
"111010" & X"053", -- 0x047: JNE 0x053
|
||||
"010001" & X"010", -- 0x048: INC R00
|
||||
"010001" & X"011", -- 0x049: INC R01
|
||||
"010101" & X"01F", -- 0x04A: DEC R15
|
||||
"110010" & X"045", -- 0x04B: JNZ 0x045
|
||||
"000011" & X"020", -- 0x04C: MOV R00, 0x02
|
||||
"111011" & X"05F", -- 0x04D: CALL 0x05F
|
||||
"001010" & X"000", -- 0x04E: MOVC R00, (0x00)
|
||||
"010001" & X"010", -- 0x04F: INC R00
|
||||
"001101" & X"000", -- 0x050: MOVC (0x00), R00
|
||||
"110000" & X"03A", -- 0x051: JMP 0x03A
|
||||
"110000" & X"057", -- 0x052: JMP 0x057
|
||||
"101000" & X"040", -- 0x053: XIN R00, (0x04)
|
||||
"011011" & X"100", -- 0x054: OR R00, 0x10
|
||||
"100100" & X"040", -- 0x055: XOUT (0x04), R00
|
||||
"110000" & X"057", -- 0x056: JMP 0x057
|
||||
"110000" & X"057", -- 0x057: JMP 0x057
|
||||
"111100" & X"000", -- 0x058: PUSH R00
|
||||
"000011" & X"000", -- 0x059: MOV R00, 0x00
|
||||
"100100" & X"080", -- 0x05A: XOUT (0x08), R00
|
||||
"100100" & X"090", -- 0x05B: XOUT (0x09), R00
|
||||
"100100" & X"0A0", -- 0x05C: XOUT (0x0A), R00
|
||||
"111101" & X"000", -- 0x05D: POP R00
|
||||
"111110" & X"000", -- 0x05E: RET
|
||||
"111100" & X"001", -- 0x05F: PUSH R01
|
||||
"111100" & X"002", -- 0x060: PUSH R02
|
||||
"111100" & X"003", -- 0x061: PUSH R03
|
||||
"101000" & X"081", -- 0x062: XIN R01, (0x08)
|
||||
"101000" & X"092", -- 0x063: XIN R02, (0x09)
|
||||
"101000" & X"0A3", -- 0x064: XIN R03, (0x0A)
|
||||
"010000" & X"001", -- 0x065: ADD R01, R00
|
||||
"010011" & X"002", -- 0x066: ADDC R02, 0x00
|
||||
"010011" & X"003", -- 0x067: ADDC R03, 0x00
|
||||
"100100" & X"081", -- 0x068: XOUT (0x08), R01
|
||||
"100100" & X"092", -- 0x069: XOUT (0x09), R02
|
||||
"100100" & X"0A3", -- 0x06A: XOUT (0x0A), R03
|
||||
"111101" & X"003", -- 0x06B: POP R03
|
||||
"111101" & X"002", -- 0x06C: POP R02
|
||||
"111101" & X"001", -- 0x06D: POP R01
|
||||
"111110" & X"000" -- 0x06E: RET
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= imem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end sdr_test_short;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,317 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
ENTITY xrom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in dmem_addr_t;
|
||||
dout : out dmem_data_t
|
||||
);
|
||||
END xrom;
|
||||
|
||||
ARCHITECTURE sdr_test_short OF xrom IS
|
||||
|
||||
type xmem_rom_t is array (0 to 255) of dmem_data_t;
|
||||
|
||||
-- Assembled from sdr_test_short.jsm
|
||||
constant xmem_rom : xmem_rom_t :=
|
||||
(
|
||||
X"00", -- 0x00
|
||||
X"00", -- 0x01
|
||||
X"00", -- 0x02
|
||||
X"00", -- 0x03
|
||||
X"00", -- 0x04
|
||||
X"00", -- 0x05
|
||||
X"00", -- 0x06
|
||||
X"00", -- 0x07
|
||||
X"00", -- 0x08
|
||||
X"00", -- 0x09
|
||||
X"00", -- 0x0A
|
||||
X"00", -- 0x0B
|
||||
X"00", -- 0x0C
|
||||
X"00", -- 0x0D
|
||||
X"00", -- 0x0E
|
||||
X"00", -- 0x0F
|
||||
X"00", -- 0x10
|
||||
X"00", -- 0x11
|
||||
X"00", -- 0x12
|
||||
X"00", -- 0x13
|
||||
X"00", -- 0x14
|
||||
X"00", -- 0x15
|
||||
X"00", -- 0x16
|
||||
X"00", -- 0x17
|
||||
X"00", -- 0x18
|
||||
X"00", -- 0x19
|
||||
X"00", -- 0x1A
|
||||
X"00", -- 0x1B
|
||||
X"00", -- 0x1C
|
||||
X"00", -- 0x1D
|
||||
X"00", -- 0x1E
|
||||
X"00", -- 0x1F
|
||||
X"00", -- 0x20
|
||||
X"00", -- 0x21
|
||||
X"00", -- 0x22
|
||||
X"00", -- 0x23
|
||||
X"00", -- 0x24
|
||||
X"00", -- 0x25
|
||||
X"00", -- 0x26
|
||||
X"00", -- 0x27
|
||||
X"00", -- 0x28
|
||||
X"00", -- 0x29
|
||||
X"00", -- 0x2A
|
||||
X"00", -- 0x2B
|
||||
X"00", -- 0x2C
|
||||
X"00", -- 0x2D
|
||||
X"00", -- 0x2E
|
||||
X"00", -- 0x2F
|
||||
X"00", -- 0x30
|
||||
X"00", -- 0x31
|
||||
X"00", -- 0x32
|
||||
X"00", -- 0x33
|
||||
X"00", -- 0x34
|
||||
X"00", -- 0x35
|
||||
X"00", -- 0x36
|
||||
X"00", -- 0x37
|
||||
X"00", -- 0x38
|
||||
X"00", -- 0x39
|
||||
X"00", -- 0x3A
|
||||
X"00", -- 0x3B
|
||||
X"00", -- 0x3C
|
||||
X"00", -- 0x3D
|
||||
X"00", -- 0x3E
|
||||
X"00", -- 0x3F
|
||||
X"00", -- 0x40
|
||||
X"00", -- 0x41
|
||||
X"00", -- 0x42
|
||||
X"00", -- 0x43
|
||||
X"00", -- 0x44
|
||||
X"00", -- 0x45
|
||||
X"00", -- 0x46
|
||||
X"00", -- 0x47
|
||||
X"00", -- 0x48
|
||||
X"00", -- 0x49
|
||||
X"00", -- 0x4A
|
||||
X"00", -- 0x4B
|
||||
X"00", -- 0x4C
|
||||
X"00", -- 0x4D
|
||||
X"00", -- 0x4E
|
||||
X"00", -- 0x4F
|
||||
X"00", -- 0x50
|
||||
X"00", -- 0x51
|
||||
X"00", -- 0x52
|
||||
X"00", -- 0x53
|
||||
X"00", -- 0x54
|
||||
X"00", -- 0x55
|
||||
X"00", -- 0x56
|
||||
X"00", -- 0x57
|
||||
X"00", -- 0x58
|
||||
X"00", -- 0x59
|
||||
X"00", -- 0x5A
|
||||
X"00", -- 0x5B
|
||||
X"00", -- 0x5C
|
||||
X"00", -- 0x5D
|
||||
X"00", -- 0x5E
|
||||
X"00", -- 0x5F
|
||||
X"00", -- 0x60
|
||||
X"00", -- 0x61
|
||||
X"00", -- 0x62
|
||||
X"00", -- 0x63
|
||||
X"00", -- 0x64
|
||||
X"00", -- 0x65
|
||||
X"00", -- 0x66
|
||||
X"00", -- 0x67
|
||||
X"00", -- 0x68
|
||||
X"00", -- 0x69
|
||||
X"00", -- 0x6A
|
||||
X"00", -- 0x6B
|
||||
X"00", -- 0x6C
|
||||
X"00", -- 0x6D
|
||||
X"00", -- 0x6E
|
||||
X"00", -- 0x6F
|
||||
X"00", -- 0x70
|
||||
X"00", -- 0x71
|
||||
X"00", -- 0x72
|
||||
X"00", -- 0x73
|
||||
X"00", -- 0x74
|
||||
X"00", -- 0x75
|
||||
X"00", -- 0x76
|
||||
X"00", -- 0x77
|
||||
X"00", -- 0x78
|
||||
X"00", -- 0x79
|
||||
X"00", -- 0x7A
|
||||
X"00", -- 0x7B
|
||||
X"00", -- 0x7C
|
||||
X"00", -- 0x7D
|
||||
X"00", -- 0x7E
|
||||
X"00", -- 0x7F
|
||||
X"00", -- 0x80
|
||||
X"00", -- 0x81
|
||||
X"00", -- 0x82
|
||||
X"00", -- 0x83
|
||||
X"00", -- 0x84
|
||||
X"00", -- 0x85
|
||||
X"00", -- 0x86
|
||||
X"00", -- 0x87
|
||||
X"00", -- 0x88
|
||||
X"00", -- 0x89
|
||||
X"00", -- 0x8A
|
||||
X"00", -- 0x8B
|
||||
X"00", -- 0x8C
|
||||
X"00", -- 0x8D
|
||||
X"00", -- 0x8E
|
||||
X"00", -- 0x8F
|
||||
X"00", -- 0x90
|
||||
X"00", -- 0x91
|
||||
X"00", -- 0x92
|
||||
X"00", -- 0x93
|
||||
X"00", -- 0x94
|
||||
X"00", -- 0x95
|
||||
X"00", -- 0x96
|
||||
X"00", -- 0x97
|
||||
X"00", -- 0x98
|
||||
X"00", -- 0x99
|
||||
X"00", -- 0x9A
|
||||
X"00", -- 0x9B
|
||||
X"00", -- 0x9C
|
||||
X"00", -- 0x9D
|
||||
X"00", -- 0x9E
|
||||
X"00", -- 0x9F
|
||||
X"00", -- 0xA0
|
||||
X"00", -- 0xA1
|
||||
X"00", -- 0xA2
|
||||
X"00", -- 0xA3
|
||||
X"00", -- 0xA4
|
||||
X"00", -- 0xA5
|
||||
X"00", -- 0xA6
|
||||
X"00", -- 0xA7
|
||||
X"00", -- 0xA8
|
||||
X"00", -- 0xA9
|
||||
X"00", -- 0xAA
|
||||
X"00", -- 0xAB
|
||||
X"00", -- 0xAC
|
||||
X"00", -- 0xAD
|
||||
X"00", -- 0xAE
|
||||
X"00", -- 0xAF
|
||||
X"00", -- 0xB0
|
||||
X"00", -- 0xB1
|
||||
X"00", -- 0xB2
|
||||
X"00", -- 0xB3
|
||||
X"00", -- 0xB4
|
||||
X"00", -- 0xB5
|
||||
X"00", -- 0xB6
|
||||
X"00", -- 0xB7
|
||||
X"00", -- 0xB8
|
||||
X"00", -- 0xB9
|
||||
X"00", -- 0xBA
|
||||
X"00", -- 0xBB
|
||||
X"00", -- 0xBC
|
||||
X"00", -- 0xBD
|
||||
X"00", -- 0xBE
|
||||
X"00", -- 0xBF
|
||||
X"00", -- 0xC0
|
||||
X"00", -- 0xC1
|
||||
X"00", -- 0xC2
|
||||
X"00", -- 0xC3
|
||||
X"00", -- 0xC4
|
||||
X"00", -- 0xC5
|
||||
X"00", -- 0xC6
|
||||
X"00", -- 0xC7
|
||||
X"00", -- 0xC8
|
||||
X"00", -- 0xC9
|
||||
X"00", -- 0xCA
|
||||
X"00", -- 0xCB
|
||||
X"00", -- 0xCC
|
||||
X"00", -- 0xCD
|
||||
X"00", -- 0xCE
|
||||
X"00", -- 0xCF
|
||||
X"00", -- 0xD0
|
||||
X"00", -- 0xD1
|
||||
X"00", -- 0xD2
|
||||
X"00", -- 0xD3
|
||||
X"00", -- 0xD4
|
||||
X"00", -- 0xD5
|
||||
X"00", -- 0xD6
|
||||
X"00", -- 0xD7
|
||||
X"00", -- 0xD8
|
||||
X"00", -- 0xD9
|
||||
X"00", -- 0xDA
|
||||
X"00", -- 0xDB
|
||||
X"00", -- 0xDC
|
||||
X"00", -- 0xDD
|
||||
X"00", -- 0xDE
|
||||
X"00", -- 0xDF
|
||||
X"00", -- 0xE0
|
||||
X"00", -- 0xE1
|
||||
X"00", -- 0xE2
|
||||
X"00", -- 0xE3
|
||||
X"00", -- 0xE4
|
||||
X"00", -- 0xE5
|
||||
X"00", -- 0xE6
|
||||
X"00", -- 0xE7
|
||||
X"00", -- 0xE8
|
||||
X"00", -- 0xE9
|
||||
X"00", -- 0xEA
|
||||
X"00", -- 0xEB
|
||||
X"00", -- 0xEC
|
||||
X"00", -- 0xED
|
||||
X"00", -- 0xEE
|
||||
X"00", -- 0xEF
|
||||
X"00", -- 0xF0
|
||||
X"00", -- 0xF1
|
||||
X"00", -- 0xF2
|
||||
X"00", -- 0xF3
|
||||
X"00", -- 0xF4
|
||||
X"00", -- 0xF5
|
||||
X"00", -- 0xF6
|
||||
X"00", -- 0xF7
|
||||
X"00", -- 0xF8
|
||||
X"00", -- 0xF9
|
||||
X"00", -- 0xFA
|
||||
X"00", -- 0xFB
|
||||
X"00", -- 0xFC
|
||||
X"00", -- 0xFD
|
||||
X"00", -- 0xFE
|
||||
X"00" -- 0xFF
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= xmem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end sdr_test_short;
|
||||
|
||||
@@ -0,0 +1,413 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: loadable ROM
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library UNISIM;
|
||||
use UNISIM.VComponents.all;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
ENTITY xrom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in dmem_addr_t;
|
||||
dout : out dmem_data_t
|
||||
);
|
||||
|
||||
END xrom;
|
||||
|
||||
ARCHITECTURE loadable OF xrom IS
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
|
||||
-- Assembled from sdr_test_short.jsm
|
||||
type xmem_rom_t is array (0 to 255) of dmem_data_t;
|
||||
signal xmem_rom : xmem_rom_t :=
|
||||
(
|
||||
X"00", -- 0x00
|
||||
X"00", -- 0x01
|
||||
X"00", -- 0x02
|
||||
X"00", -- 0x03
|
||||
X"00", -- 0x04
|
||||
X"00", -- 0x05
|
||||
X"00", -- 0x06
|
||||
X"00", -- 0x07
|
||||
X"00", -- 0x08
|
||||
X"00", -- 0x09
|
||||
X"00", -- 0x0A
|
||||
X"00", -- 0x0B
|
||||
X"00", -- 0x0C
|
||||
X"00", -- 0x0D
|
||||
X"00", -- 0x0E
|
||||
X"00", -- 0x0F
|
||||
X"00", -- 0x10
|
||||
X"00", -- 0x11
|
||||
X"00", -- 0x12
|
||||
X"00", -- 0x13
|
||||
X"00", -- 0x14
|
||||
X"00", -- 0x15
|
||||
X"00", -- 0x16
|
||||
X"00", -- 0x17
|
||||
X"00", -- 0x18
|
||||
X"00", -- 0x19
|
||||
X"00", -- 0x1A
|
||||
X"00", -- 0x1B
|
||||
X"00", -- 0x1C
|
||||
X"00", -- 0x1D
|
||||
X"00", -- 0x1E
|
||||
X"00", -- 0x1F
|
||||
X"00", -- 0x20
|
||||
X"00", -- 0x21
|
||||
X"00", -- 0x22
|
||||
X"00", -- 0x23
|
||||
X"00", -- 0x24
|
||||
X"00", -- 0x25
|
||||
X"00", -- 0x26
|
||||
X"00", -- 0x27
|
||||
X"00", -- 0x28
|
||||
X"00", -- 0x29
|
||||
X"00", -- 0x2A
|
||||
X"00", -- 0x2B
|
||||
X"00", -- 0x2C
|
||||
X"00", -- 0x2D
|
||||
X"00", -- 0x2E
|
||||
X"00", -- 0x2F
|
||||
X"00", -- 0x30
|
||||
X"00", -- 0x31
|
||||
X"00", -- 0x32
|
||||
X"00", -- 0x33
|
||||
X"00", -- 0x34
|
||||
X"00", -- 0x35
|
||||
X"00", -- 0x36
|
||||
X"00", -- 0x37
|
||||
X"00", -- 0x38
|
||||
X"00", -- 0x39
|
||||
X"00", -- 0x3A
|
||||
X"00", -- 0x3B
|
||||
X"00", -- 0x3C
|
||||
X"00", -- 0x3D
|
||||
X"00", -- 0x3E
|
||||
X"00", -- 0x3F
|
||||
X"00", -- 0x40
|
||||
X"00", -- 0x41
|
||||
X"00", -- 0x42
|
||||
X"00", -- 0x43
|
||||
X"00", -- 0x44
|
||||
X"00", -- 0x45
|
||||
X"00", -- 0x46
|
||||
X"00", -- 0x47
|
||||
X"00", -- 0x48
|
||||
X"00", -- 0x49
|
||||
X"00", -- 0x4A
|
||||
X"00", -- 0x4B
|
||||
X"00", -- 0x4C
|
||||
X"00", -- 0x4D
|
||||
X"00", -- 0x4E
|
||||
X"00", -- 0x4F
|
||||
X"00", -- 0x50
|
||||
X"00", -- 0x51
|
||||
X"00", -- 0x52
|
||||
X"00", -- 0x53
|
||||
X"00", -- 0x54
|
||||
X"00", -- 0x55
|
||||
X"00", -- 0x56
|
||||
X"00", -- 0x57
|
||||
X"00", -- 0x58
|
||||
X"00", -- 0x59
|
||||
X"00", -- 0x5A
|
||||
X"00", -- 0x5B
|
||||
X"00", -- 0x5C
|
||||
X"00", -- 0x5D
|
||||
X"00", -- 0x5E
|
||||
X"00", -- 0x5F
|
||||
X"00", -- 0x60
|
||||
X"00", -- 0x61
|
||||
X"00", -- 0x62
|
||||
X"00", -- 0x63
|
||||
X"00", -- 0x64
|
||||
X"00", -- 0x65
|
||||
X"00", -- 0x66
|
||||
X"00", -- 0x67
|
||||
X"00", -- 0x68
|
||||
X"00", -- 0x69
|
||||
X"00", -- 0x6A
|
||||
X"00", -- 0x6B
|
||||
X"00", -- 0x6C
|
||||
X"00", -- 0x6D
|
||||
X"00", -- 0x6E
|
||||
X"00", -- 0x6F
|
||||
X"00", -- 0x70
|
||||
X"00", -- 0x71
|
||||
X"00", -- 0x72
|
||||
X"00", -- 0x73
|
||||
X"00", -- 0x74
|
||||
X"00", -- 0x75
|
||||
X"00", -- 0x76
|
||||
X"00", -- 0x77
|
||||
X"00", -- 0x78
|
||||
X"00", -- 0x79
|
||||
X"00", -- 0x7A
|
||||
X"00", -- 0x7B
|
||||
X"00", -- 0x7C
|
||||
X"00", -- 0x7D
|
||||
X"00", -- 0x7E
|
||||
X"00", -- 0x7F
|
||||
X"00", -- 0x80
|
||||
X"00", -- 0x81
|
||||
X"00", -- 0x82
|
||||
X"00", -- 0x83
|
||||
X"00", -- 0x84
|
||||
X"00", -- 0x85
|
||||
X"00", -- 0x86
|
||||
X"00", -- 0x87
|
||||
X"00", -- 0x88
|
||||
X"00", -- 0x89
|
||||
X"00", -- 0x8A
|
||||
X"00", -- 0x8B
|
||||
X"00", -- 0x8C
|
||||
X"00", -- 0x8D
|
||||
X"00", -- 0x8E
|
||||
X"00", -- 0x8F
|
||||
X"00", -- 0x90
|
||||
X"00", -- 0x91
|
||||
X"00", -- 0x92
|
||||
X"00", -- 0x93
|
||||
X"00", -- 0x94
|
||||
X"00", -- 0x95
|
||||
X"00", -- 0x96
|
||||
X"00", -- 0x97
|
||||
X"00", -- 0x98
|
||||
X"00", -- 0x99
|
||||
X"00", -- 0x9A
|
||||
X"00", -- 0x9B
|
||||
X"00", -- 0x9C
|
||||
X"00", -- 0x9D
|
||||
X"00", -- 0x9E
|
||||
X"00", -- 0x9F
|
||||
X"00", -- 0xA0
|
||||
X"00", -- 0xA1
|
||||
X"00", -- 0xA2
|
||||
X"00", -- 0xA3
|
||||
X"00", -- 0xA4
|
||||
X"00", -- 0xA5
|
||||
X"00", -- 0xA6
|
||||
X"00", -- 0xA7
|
||||
X"00", -- 0xA8
|
||||
X"00", -- 0xA9
|
||||
X"00", -- 0xAA
|
||||
X"00", -- 0xAB
|
||||
X"00", -- 0xAC
|
||||
X"00", -- 0xAD
|
||||
X"00", -- 0xAE
|
||||
X"00", -- 0xAF
|
||||
X"00", -- 0xB0
|
||||
X"00", -- 0xB1
|
||||
X"00", -- 0xB2
|
||||
X"00", -- 0xB3
|
||||
X"00", -- 0xB4
|
||||
X"00", -- 0xB5
|
||||
X"00", -- 0xB6
|
||||
X"00", -- 0xB7
|
||||
X"00", -- 0xB8
|
||||
X"00", -- 0xB9
|
||||
X"00", -- 0xBA
|
||||
X"00", -- 0xBB
|
||||
X"00", -- 0xBC
|
||||
X"00", -- 0xBD
|
||||
X"00", -- 0xBE
|
||||
X"00", -- 0xBF
|
||||
X"00", -- 0xC0
|
||||
X"00", -- 0xC1
|
||||
X"00", -- 0xC2
|
||||
X"00", -- 0xC3
|
||||
X"00", -- 0xC4
|
||||
X"00", -- 0xC5
|
||||
X"00", -- 0xC6
|
||||
X"00", -- 0xC7
|
||||
X"00", -- 0xC8
|
||||
X"00", -- 0xC9
|
||||
X"00", -- 0xCA
|
||||
X"00", -- 0xCB
|
||||
X"00", -- 0xCC
|
||||
X"00", -- 0xCD
|
||||
X"00", -- 0xCE
|
||||
X"00", -- 0xCF
|
||||
X"00", -- 0xD0
|
||||
X"00", -- 0xD1
|
||||
X"00", -- 0xD2
|
||||
X"00", -- 0xD3
|
||||
X"00", -- 0xD4
|
||||
X"00", -- 0xD5
|
||||
X"00", -- 0xD6
|
||||
X"00", -- 0xD7
|
||||
X"00", -- 0xD8
|
||||
X"00", -- 0xD9
|
||||
X"00", -- 0xDA
|
||||
X"00", -- 0xDB
|
||||
X"00", -- 0xDC
|
||||
X"00", -- 0xDD
|
||||
X"00", -- 0xDE
|
||||
X"00", -- 0xDF
|
||||
X"00", -- 0xE0
|
||||
X"00", -- 0xE1
|
||||
X"00", -- 0xE2
|
||||
X"00", -- 0xE3
|
||||
X"00", -- 0xE4
|
||||
X"00", -- 0xE5
|
||||
X"00", -- 0xE6
|
||||
X"00", -- 0xE7
|
||||
X"00", -- 0xE8
|
||||
X"00", -- 0xE9
|
||||
X"00", -- 0xEA
|
||||
X"00", -- 0xEB
|
||||
X"00", -- 0xEC
|
||||
X"00", -- 0xED
|
||||
X"00", -- 0xEE
|
||||
X"00", -- 0xEF
|
||||
X"00", -- 0xF0
|
||||
X"00", -- 0xF1
|
||||
X"00", -- 0xF2
|
||||
X"00", -- 0xF3
|
||||
X"00", -- 0xF4
|
||||
X"00", -- 0xF5
|
||||
X"00", -- 0xF6
|
||||
X"00", -- 0xF7
|
||||
X"00", -- 0xF8
|
||||
X"00", -- 0xF9
|
||||
X"00", -- 0xFA
|
||||
X"00", -- 0xFB
|
||||
X"00", -- 0xFC
|
||||
X"00", -- 0xFD
|
||||
X"00", -- 0xFE
|
||||
X"00" -- 0xFF
|
||||
);
|
||||
|
||||
signal jtag_ld_clk : STD_LOGIC;
|
||||
signal jtag_ld_we : STD_LOGIC;
|
||||
signal jtag_ld_addr : dmem_addr_t;
|
||||
signal jtag_ld_dout : dmem_data_t;
|
||||
signal jtag_ld_din : dmem_data_t;
|
||||
signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
|
||||
signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
|
||||
signal user_regi, user_rego : unsigned (15 downto 0);
|
||||
constant id : unsigned (15 downto 0) := X"BEEF";
|
||||
|
||||
begin
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- Virtex-4: JTAG Loader
|
||||
--------------------------------------------------------------------------
|
||||
i00_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_clk1,
|
||||
I => bs_clk0
|
||||
);
|
||||
|
||||
i01_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_update1,
|
||||
I => bs_update0
|
||||
);
|
||||
|
||||
BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4
|
||||
generic map
|
||||
(
|
||||
JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
|
||||
)
|
||||
port map
|
||||
(
|
||||
CAPTURE => bs_capture, -- CAPTURE output from TAP controller
|
||||
DRCK => bs_clk0, -- Data register output for USER functions
|
||||
RESET => bs_rst, -- Reset output from TAP controller
|
||||
SEL => bs_sel, -- USER active output
|
||||
SHIFT => bs_shift, -- SHIFT output from TAP controller
|
||||
TDI => bs_tdi, -- TDI output from TAP controller
|
||||
UPDATE => bs_update0, -- UPDATE output from TAP controller
|
||||
TDO => bs_tdo -- Data input for USER function
|
||||
);
|
||||
|
||||
jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1);
|
||||
jtag_ld_din <= user_regi(dmem_data_t'left downto 0);
|
||||
jtag_ld_clk <= bs_update1;
|
||||
jtag_ld_we <= bs_sel;
|
||||
|
||||
sipo:
|
||||
process (bs_rst, bs_clk1, bs_tdi, bs_shift)
|
||||
begin
|
||||
if bs_rst = '1' then
|
||||
user_regi <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
piso:
|
||||
process (bs_rst, bs_clk1, bs_shift, user_rego)
|
||||
begin
|
||||
bs_tdo <= user_rego(0);
|
||||
if bs_rst = '1' then
|
||||
user_rego <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
|
||||
else
|
||||
user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout;
|
||||
-- user_rego <= id;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- ROM Read/Write
|
||||
--------------------------------------------------------------------------
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= xmem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
PROM_WRITE:
|
||||
process(jtag_ld_clk, jtag_ld_we)
|
||||
begin
|
||||
if rising_edge(jtag_ld_clk) then
|
||||
if jtag_ld_we = '1' then
|
||||
xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
|
||||
else
|
||||
jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
end loadable;
|
||||
@@ -0,0 +1,318 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
ENTITY xrom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in dmem_addr_t;
|
||||
dout : out dmem_data_t
|
||||
);
|
||||
END xrom;
|
||||
|
||||
ARCHITECTURE sdr_test OF xrom IS
|
||||
|
||||
type xmem_rom_t is array (0 to 255) of dmem_data_t;
|
||||
|
||||
-- Assembled from sdr_test.jsm
|
||||
constant xmem_rom : xmem_rom_t :=
|
||||
(
|
||||
X"53", -- 0x00
|
||||
X"44", -- 0x01
|
||||
X"52", -- 0x02
|
||||
X"41", -- 0x03
|
||||
X"4D", -- 0x04
|
||||
X"20", -- 0x05
|
||||
X"54", -- 0x06
|
||||
X"65", -- 0x07
|
||||
X"73", -- 0x08
|
||||
X"74", -- 0x09
|
||||
X"00", -- 0x0A
|
||||
X"43", -- 0x0B
|
||||
X"6C", -- 0x0C
|
||||
X"65", -- 0x0D
|
||||
X"61", -- 0x0E
|
||||
X"72", -- 0x0F
|
||||
X"69", -- 0x10
|
||||
X"6E", -- 0x11
|
||||
X"67", -- 0x12
|
||||
X"20", -- 0x13
|
||||
X"53", -- 0x14
|
||||
X"44", -- 0x15
|
||||
X"52", -- 0x16
|
||||
X"41", -- 0x17
|
||||
X"4D", -- 0x18
|
||||
X"00", -- 0x19
|
||||
X"57", -- 0x1A
|
||||
X"72", -- 0x1B
|
||||
X"69", -- 0x1C
|
||||
X"74", -- 0x1D
|
||||
X"69", -- 0x1E
|
||||
X"6E", -- 0x1F
|
||||
X"67", -- 0x20
|
||||
X"20", -- 0x21
|
||||
X"53", -- 0x22
|
||||
X"44", -- 0x23
|
||||
X"52", -- 0x24
|
||||
X"41", -- 0x25
|
||||
X"4D", -- 0x26
|
||||
X"00", -- 0x27
|
||||
X"52", -- 0x28
|
||||
X"65", -- 0x29
|
||||
X"61", -- 0x2A
|
||||
X"64", -- 0x2B
|
||||
X"69", -- 0x2C
|
||||
X"6E", -- 0x2D
|
||||
X"67", -- 0x2E
|
||||
X"20", -- 0x2F
|
||||
X"53", -- 0x30
|
||||
X"44", -- 0x31
|
||||
X"52", -- 0x32
|
||||
X"41", -- 0x33
|
||||
X"4D", -- 0x34
|
||||
X"00", -- 0x35
|
||||
X"56", -- 0x36
|
||||
X"65", -- 0x37
|
||||
X"72", -- 0x38
|
||||
X"69", -- 0x39
|
||||
X"66", -- 0x3A
|
||||
X"79", -- 0x3B
|
||||
X"20", -- 0x3C
|
||||
X"4F", -- 0x3D
|
||||
X"4B", -- 0x3E
|
||||
X"00", -- 0x3F
|
||||
X"56", -- 0x40
|
||||
X"65", -- 0x41
|
||||
X"72", -- 0x42
|
||||
X"69", -- 0x43
|
||||
X"66", -- 0x44
|
||||
X"79", -- 0x45
|
||||
X"20", -- 0x46
|
||||
X"46", -- 0x47
|
||||
X"61", -- 0x48
|
||||
X"69", -- 0x49
|
||||
X"6C", -- 0x4A
|
||||
X"65", -- 0x4B
|
||||
X"64", -- 0x4C
|
||||
X"00", -- 0x4D
|
||||
X"2E", -- 0x4E
|
||||
X"00", -- 0x4F
|
||||
X"00", -- 0x50
|
||||
X"00", -- 0x51
|
||||
X"00", -- 0x52
|
||||
X"00", -- 0x53
|
||||
X"00", -- 0x54
|
||||
X"00", -- 0x55
|
||||
X"00", -- 0x56
|
||||
X"00", -- 0x57
|
||||
X"00", -- 0x58
|
||||
X"00", -- 0x59
|
||||
X"00", -- 0x5A
|
||||
X"00", -- 0x5B
|
||||
X"00", -- 0x5C
|
||||
X"00", -- 0x5D
|
||||
X"00", -- 0x5E
|
||||
X"00", -- 0x5F
|
||||
X"00", -- 0x60
|
||||
X"00", -- 0x61
|
||||
X"00", -- 0x62
|
||||
X"00", -- 0x63
|
||||
X"00", -- 0x64
|
||||
X"00", -- 0x65
|
||||
X"00", -- 0x66
|
||||
X"00", -- 0x67
|
||||
X"00", -- 0x68
|
||||
X"00", -- 0x69
|
||||
X"00", -- 0x6A
|
||||
X"00", -- 0x6B
|
||||
X"00", -- 0x6C
|
||||
X"00", -- 0x6D
|
||||
X"00", -- 0x6E
|
||||
X"00", -- 0x6F
|
||||
X"00", -- 0x70
|
||||
X"00", -- 0x71
|
||||
X"00", -- 0x72
|
||||
X"00", -- 0x73
|
||||
X"00", -- 0x74
|
||||
X"00", -- 0x75
|
||||
X"00", -- 0x76
|
||||
X"00", -- 0x77
|
||||
X"00", -- 0x78
|
||||
X"00", -- 0x79
|
||||
X"00", -- 0x7A
|
||||
X"00", -- 0x7B
|
||||
X"00", -- 0x7C
|
||||
X"00", -- 0x7D
|
||||
X"00", -- 0x7E
|
||||
X"00", -- 0x7F
|
||||
X"00", -- 0x80
|
||||
X"00", -- 0x81
|
||||
X"00", -- 0x82
|
||||
X"00", -- 0x83
|
||||
X"00", -- 0x84
|
||||
X"00", -- 0x85
|
||||
X"00", -- 0x86
|
||||
X"00", -- 0x87
|
||||
X"00", -- 0x88
|
||||
X"00", -- 0x89
|
||||
X"00", -- 0x8A
|
||||
X"00", -- 0x8B
|
||||
X"00", -- 0x8C
|
||||
X"00", -- 0x8D
|
||||
X"00", -- 0x8E
|
||||
X"00", -- 0x8F
|
||||
X"00", -- 0x90
|
||||
X"00", -- 0x91
|
||||
X"00", -- 0x92
|
||||
X"00", -- 0x93
|
||||
X"00", -- 0x94
|
||||
X"00", -- 0x95
|
||||
X"00", -- 0x96
|
||||
X"00", -- 0x97
|
||||
X"00", -- 0x98
|
||||
X"00", -- 0x99
|
||||
X"00", -- 0x9A
|
||||
X"00", -- 0x9B
|
||||
X"00", -- 0x9C
|
||||
X"00", -- 0x9D
|
||||
X"00", -- 0x9E
|
||||
X"00", -- 0x9F
|
||||
X"00", -- 0xA0
|
||||
X"00", -- 0xA1
|
||||
X"00", -- 0xA2
|
||||
X"00", -- 0xA3
|
||||
X"00", -- 0xA4
|
||||
X"00", -- 0xA5
|
||||
X"00", -- 0xA6
|
||||
X"00", -- 0xA7
|
||||
X"00", -- 0xA8
|
||||
X"00", -- 0xA9
|
||||
X"00", -- 0xAA
|
||||
X"00", -- 0xAB
|
||||
X"00", -- 0xAC
|
||||
X"00", -- 0xAD
|
||||
X"00", -- 0xAE
|
||||
X"00", -- 0xAF
|
||||
X"00", -- 0xB0
|
||||
X"00", -- 0xB1
|
||||
X"00", -- 0xB2
|
||||
X"00", -- 0xB3
|
||||
X"00", -- 0xB4
|
||||
X"00", -- 0xB5
|
||||
X"00", -- 0xB6
|
||||
X"00", -- 0xB7
|
||||
X"00", -- 0xB8
|
||||
X"00", -- 0xB9
|
||||
X"00", -- 0xBA
|
||||
X"00", -- 0xBB
|
||||
X"00", -- 0xBC
|
||||
X"00", -- 0xBD
|
||||
X"00", -- 0xBE
|
||||
X"00", -- 0xBF
|
||||
X"00", -- 0xC0
|
||||
X"00", -- 0xC1
|
||||
X"00", -- 0xC2
|
||||
X"00", -- 0xC3
|
||||
X"00", -- 0xC4
|
||||
X"00", -- 0xC5
|
||||
X"00", -- 0xC6
|
||||
X"00", -- 0xC7
|
||||
X"00", -- 0xC8
|
||||
X"00", -- 0xC9
|
||||
X"00", -- 0xCA
|
||||
X"00", -- 0xCB
|
||||
X"00", -- 0xCC
|
||||
X"00", -- 0xCD
|
||||
X"00", -- 0xCE
|
||||
X"00", -- 0xCF
|
||||
X"00", -- 0xD0
|
||||
X"00", -- 0xD1
|
||||
X"00", -- 0xD2
|
||||
X"00", -- 0xD3
|
||||
X"00", -- 0xD4
|
||||
X"00", -- 0xD5
|
||||
X"00", -- 0xD6
|
||||
X"00", -- 0xD7
|
||||
X"00", -- 0xD8
|
||||
X"00", -- 0xD9
|
||||
X"00", -- 0xDA
|
||||
X"00", -- 0xDB
|
||||
X"00", -- 0xDC
|
||||
X"00", -- 0xDD
|
||||
X"00", -- 0xDE
|
||||
X"00", -- 0xDF
|
||||
X"00", -- 0xE0
|
||||
X"00", -- 0xE1
|
||||
X"00", -- 0xE2
|
||||
X"00", -- 0xE3
|
||||
X"00", -- 0xE4
|
||||
X"00", -- 0xE5
|
||||
X"00", -- 0xE6
|
||||
X"00", -- 0xE7
|
||||
X"00", -- 0xE8
|
||||
X"00", -- 0xE9
|
||||
X"00", -- 0xEA
|
||||
X"00", -- 0xEB
|
||||
X"00", -- 0xEC
|
||||
X"00", -- 0xED
|
||||
X"00", -- 0xEE
|
||||
X"00", -- 0xEF
|
||||
X"00", -- 0xF0
|
||||
X"00", -- 0xF1
|
||||
X"00", -- 0xF2
|
||||
X"00", -- 0xF3
|
||||
X"00", -- 0xF4
|
||||
X"00", -- 0xF5
|
||||
X"00", -- 0xF6
|
||||
X"00", -- 0xF7
|
||||
X"00", -- 0xF8
|
||||
X"00", -- 0xF9
|
||||
X"00", -- 0xFA
|
||||
X"00", -- 0xFB
|
||||
X"00", -- 0xFC
|
||||
X"00", -- 0xFD
|
||||
X"00", -- 0xFE
|
||||
X"00" -- 0xFF
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= xmem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end sdr_test;
|
||||
|
||||
@@ -0,0 +1,414 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: loadable ROM
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library UNISIM;
|
||||
use UNISIM.VComponents.all;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
ENTITY xrom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in dmem_addr_t;
|
||||
dout : out dmem_data_t
|
||||
);
|
||||
|
||||
END xrom;
|
||||
|
||||
ARCHITECTURE loadable OF xrom IS
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
|
||||
-- Assembled from sdr_test.jsm
|
||||
type xmem_rom_t is array (0 to 255) of dmem_data_t;
|
||||
signal xmem_rom : xmem_rom_t :=
|
||||
(
|
||||
X"53", -- 0x00
|
||||
X"44", -- 0x01
|
||||
X"52", -- 0x02
|
||||
X"41", -- 0x03
|
||||
X"4D", -- 0x04
|
||||
X"20", -- 0x05
|
||||
X"54", -- 0x06
|
||||
X"65", -- 0x07
|
||||
X"73", -- 0x08
|
||||
X"74", -- 0x09
|
||||
X"00", -- 0x0A
|
||||
X"43", -- 0x0B
|
||||
X"6C", -- 0x0C
|
||||
X"65", -- 0x0D
|
||||
X"61", -- 0x0E
|
||||
X"72", -- 0x0F
|
||||
X"69", -- 0x10
|
||||
X"6E", -- 0x11
|
||||
X"67", -- 0x12
|
||||
X"20", -- 0x13
|
||||
X"53", -- 0x14
|
||||
X"44", -- 0x15
|
||||
X"52", -- 0x16
|
||||
X"41", -- 0x17
|
||||
X"4D", -- 0x18
|
||||
X"00", -- 0x19
|
||||
X"57", -- 0x1A
|
||||
X"72", -- 0x1B
|
||||
X"69", -- 0x1C
|
||||
X"74", -- 0x1D
|
||||
X"69", -- 0x1E
|
||||
X"6E", -- 0x1F
|
||||
X"67", -- 0x20
|
||||
X"20", -- 0x21
|
||||
X"53", -- 0x22
|
||||
X"44", -- 0x23
|
||||
X"52", -- 0x24
|
||||
X"41", -- 0x25
|
||||
X"4D", -- 0x26
|
||||
X"00", -- 0x27
|
||||
X"52", -- 0x28
|
||||
X"65", -- 0x29
|
||||
X"61", -- 0x2A
|
||||
X"64", -- 0x2B
|
||||
X"69", -- 0x2C
|
||||
X"6E", -- 0x2D
|
||||
X"67", -- 0x2E
|
||||
X"20", -- 0x2F
|
||||
X"53", -- 0x30
|
||||
X"44", -- 0x31
|
||||
X"52", -- 0x32
|
||||
X"41", -- 0x33
|
||||
X"4D", -- 0x34
|
||||
X"00", -- 0x35
|
||||
X"56", -- 0x36
|
||||
X"65", -- 0x37
|
||||
X"72", -- 0x38
|
||||
X"69", -- 0x39
|
||||
X"66", -- 0x3A
|
||||
X"79", -- 0x3B
|
||||
X"20", -- 0x3C
|
||||
X"4F", -- 0x3D
|
||||
X"4B", -- 0x3E
|
||||
X"00", -- 0x3F
|
||||
X"56", -- 0x40
|
||||
X"65", -- 0x41
|
||||
X"72", -- 0x42
|
||||
X"69", -- 0x43
|
||||
X"66", -- 0x44
|
||||
X"79", -- 0x45
|
||||
X"20", -- 0x46
|
||||
X"46", -- 0x47
|
||||
X"61", -- 0x48
|
||||
X"69", -- 0x49
|
||||
X"6C", -- 0x4A
|
||||
X"65", -- 0x4B
|
||||
X"64", -- 0x4C
|
||||
X"00", -- 0x4D
|
||||
X"2E", -- 0x4E
|
||||
X"00", -- 0x4F
|
||||
X"00", -- 0x50
|
||||
X"00", -- 0x51
|
||||
X"00", -- 0x52
|
||||
X"00", -- 0x53
|
||||
X"00", -- 0x54
|
||||
X"00", -- 0x55
|
||||
X"00", -- 0x56
|
||||
X"00", -- 0x57
|
||||
X"00", -- 0x58
|
||||
X"00", -- 0x59
|
||||
X"00", -- 0x5A
|
||||
X"00", -- 0x5B
|
||||
X"00", -- 0x5C
|
||||
X"00", -- 0x5D
|
||||
X"00", -- 0x5E
|
||||
X"00", -- 0x5F
|
||||
X"00", -- 0x60
|
||||
X"00", -- 0x61
|
||||
X"00", -- 0x62
|
||||
X"00", -- 0x63
|
||||
X"00", -- 0x64
|
||||
X"00", -- 0x65
|
||||
X"00", -- 0x66
|
||||
X"00", -- 0x67
|
||||
X"00", -- 0x68
|
||||
X"00", -- 0x69
|
||||
X"00", -- 0x6A
|
||||
X"00", -- 0x6B
|
||||
X"00", -- 0x6C
|
||||
X"00", -- 0x6D
|
||||
X"00", -- 0x6E
|
||||
X"00", -- 0x6F
|
||||
X"00", -- 0x70
|
||||
X"00", -- 0x71
|
||||
X"00", -- 0x72
|
||||
X"00", -- 0x73
|
||||
X"00", -- 0x74
|
||||
X"00", -- 0x75
|
||||
X"00", -- 0x76
|
||||
X"00", -- 0x77
|
||||
X"00", -- 0x78
|
||||
X"00", -- 0x79
|
||||
X"00", -- 0x7A
|
||||
X"00", -- 0x7B
|
||||
X"00", -- 0x7C
|
||||
X"00", -- 0x7D
|
||||
X"00", -- 0x7E
|
||||
X"00", -- 0x7F
|
||||
X"00", -- 0x80
|
||||
X"00", -- 0x81
|
||||
X"00", -- 0x82
|
||||
X"00", -- 0x83
|
||||
X"00", -- 0x84
|
||||
X"00", -- 0x85
|
||||
X"00", -- 0x86
|
||||
X"00", -- 0x87
|
||||
X"00", -- 0x88
|
||||
X"00", -- 0x89
|
||||
X"00", -- 0x8A
|
||||
X"00", -- 0x8B
|
||||
X"00", -- 0x8C
|
||||
X"00", -- 0x8D
|
||||
X"00", -- 0x8E
|
||||
X"00", -- 0x8F
|
||||
X"00", -- 0x90
|
||||
X"00", -- 0x91
|
||||
X"00", -- 0x92
|
||||
X"00", -- 0x93
|
||||
X"00", -- 0x94
|
||||
X"00", -- 0x95
|
||||
X"00", -- 0x96
|
||||
X"00", -- 0x97
|
||||
X"00", -- 0x98
|
||||
X"00", -- 0x99
|
||||
X"00", -- 0x9A
|
||||
X"00", -- 0x9B
|
||||
X"00", -- 0x9C
|
||||
X"00", -- 0x9D
|
||||
X"00", -- 0x9E
|
||||
X"00", -- 0x9F
|
||||
X"00", -- 0xA0
|
||||
X"00", -- 0xA1
|
||||
X"00", -- 0xA2
|
||||
X"00", -- 0xA3
|
||||
X"00", -- 0xA4
|
||||
X"00", -- 0xA5
|
||||
X"00", -- 0xA6
|
||||
X"00", -- 0xA7
|
||||
X"00", -- 0xA8
|
||||
X"00", -- 0xA9
|
||||
X"00", -- 0xAA
|
||||
X"00", -- 0xAB
|
||||
X"00", -- 0xAC
|
||||
X"00", -- 0xAD
|
||||
X"00", -- 0xAE
|
||||
X"00", -- 0xAF
|
||||
X"00", -- 0xB0
|
||||
X"00", -- 0xB1
|
||||
X"00", -- 0xB2
|
||||
X"00", -- 0xB3
|
||||
X"00", -- 0xB4
|
||||
X"00", -- 0xB5
|
||||
X"00", -- 0xB6
|
||||
X"00", -- 0xB7
|
||||
X"00", -- 0xB8
|
||||
X"00", -- 0xB9
|
||||
X"00", -- 0xBA
|
||||
X"00", -- 0xBB
|
||||
X"00", -- 0xBC
|
||||
X"00", -- 0xBD
|
||||
X"00", -- 0xBE
|
||||
X"00", -- 0xBF
|
||||
X"00", -- 0xC0
|
||||
X"00", -- 0xC1
|
||||
X"00", -- 0xC2
|
||||
X"00", -- 0xC3
|
||||
X"00", -- 0xC4
|
||||
X"00", -- 0xC5
|
||||
X"00", -- 0xC6
|
||||
X"00", -- 0xC7
|
||||
X"00", -- 0xC8
|
||||
X"00", -- 0xC9
|
||||
X"00", -- 0xCA
|
||||
X"00", -- 0xCB
|
||||
X"00", -- 0xCC
|
||||
X"00", -- 0xCD
|
||||
X"00", -- 0xCE
|
||||
X"00", -- 0xCF
|
||||
X"00", -- 0xD0
|
||||
X"00", -- 0xD1
|
||||
X"00", -- 0xD2
|
||||
X"00", -- 0xD3
|
||||
X"00", -- 0xD4
|
||||
X"00", -- 0xD5
|
||||
X"00", -- 0xD6
|
||||
X"00", -- 0xD7
|
||||
X"00", -- 0xD8
|
||||
X"00", -- 0xD9
|
||||
X"00", -- 0xDA
|
||||
X"00", -- 0xDB
|
||||
X"00", -- 0xDC
|
||||
X"00", -- 0xDD
|
||||
X"00", -- 0xDE
|
||||
X"00", -- 0xDF
|
||||
X"00", -- 0xE0
|
||||
X"00", -- 0xE1
|
||||
X"00", -- 0xE2
|
||||
X"00", -- 0xE3
|
||||
X"00", -- 0xE4
|
||||
X"00", -- 0xE5
|
||||
X"00", -- 0xE6
|
||||
X"00", -- 0xE7
|
||||
X"00", -- 0xE8
|
||||
X"00", -- 0xE9
|
||||
X"00", -- 0xEA
|
||||
X"00", -- 0xEB
|
||||
X"00", -- 0xEC
|
||||
X"00", -- 0xED
|
||||
X"00", -- 0xEE
|
||||
X"00", -- 0xEF
|
||||
X"00", -- 0xF0
|
||||
X"00", -- 0xF1
|
||||
X"00", -- 0xF2
|
||||
X"00", -- 0xF3
|
||||
X"00", -- 0xF4
|
||||
X"00", -- 0xF5
|
||||
X"00", -- 0xF6
|
||||
X"00", -- 0xF7
|
||||
X"00", -- 0xF8
|
||||
X"00", -- 0xF9
|
||||
X"00", -- 0xFA
|
||||
X"00", -- 0xFB
|
||||
X"00", -- 0xFC
|
||||
X"00", -- 0xFD
|
||||
X"00", -- 0xFE
|
||||
X"00" -- 0xFF
|
||||
);
|
||||
|
||||
signal jtag_ld_clk : STD_LOGIC;
|
||||
signal jtag_ld_we : STD_LOGIC;
|
||||
signal jtag_ld_addr : dmem_addr_t;
|
||||
signal jtag_ld_dout : dmem_data_t;
|
||||
signal jtag_ld_din : dmem_data_t;
|
||||
signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
|
||||
signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
|
||||
signal user_regi, user_rego : unsigned (15 downto 0);
|
||||
constant id : unsigned (15 downto 0) := X"BEEF";
|
||||
|
||||
begin
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- Virtex-4: JTAG Loader
|
||||
--------------------------------------------------------------------------
|
||||
i00_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_clk1,
|
||||
I => bs_clk0
|
||||
);
|
||||
|
||||
i01_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_update1,
|
||||
I => bs_update0
|
||||
);
|
||||
|
||||
BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4
|
||||
generic map
|
||||
(
|
||||
JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
|
||||
)
|
||||
port map
|
||||
(
|
||||
CAPTURE => bs_capture, -- CAPTURE output from TAP controller
|
||||
DRCK => bs_clk0, -- Data register output for USER functions
|
||||
RESET => bs_rst, -- Reset output from TAP controller
|
||||
SEL => bs_sel, -- USER active output
|
||||
SHIFT => bs_shift, -- SHIFT output from TAP controller
|
||||
TDI => bs_tdi, -- TDI output from TAP controller
|
||||
UPDATE => bs_update0, -- UPDATE output from TAP controller
|
||||
TDO => bs_tdo -- Data input for USER function
|
||||
);
|
||||
|
||||
jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1);
|
||||
jtag_ld_din <= user_regi(dmem_data_t'left downto 0);
|
||||
jtag_ld_clk <= bs_update1;
|
||||
jtag_ld_we <= bs_sel;
|
||||
|
||||
sipo:
|
||||
process (bs_rst, bs_clk1, bs_tdi, bs_shift)
|
||||
begin
|
||||
if bs_rst = '1' then
|
||||
user_regi <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
piso:
|
||||
process (bs_rst, bs_clk1, bs_shift, user_rego)
|
||||
begin
|
||||
bs_tdo <= user_rego(0);
|
||||
if bs_rst = '1' then
|
||||
user_rego <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
|
||||
else
|
||||
user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout;
|
||||
-- user_rego <= id;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- ROM Read/Write
|
||||
--------------------------------------------------------------------------
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= xmem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
PROM_WRITE:
|
||||
process(jtag_ld_clk, jtag_ld_we)
|
||||
begin
|
||||
if rising_edge(jtag_ld_clk) then
|
||||
if jtag_ld_we = '1' then
|
||||
xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
|
||||
else
|
||||
jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
end loadable;
|
||||
@@ -0,0 +1,74 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: SDRAM controller
|
||||
-- This file: User SDRAM component adjustments
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
package sdram_config is
|
||||
|
||||
constant DDR_DATA_WIDTH : positive := 32; -- External DDR-SDRAM Module data bus width
|
||||
constant DDR_ADDR_WIDTH : positive := 13; -- number of address lines to DDR-SDRAM Device/Module
|
||||
constant DDR_BANK_WIDTH : positive := 2; -- Number of BANK address lines of external DDR-SDRAM
|
||||
constant DDR_ROW_ADDR_WIDTH : positive := 13; --
|
||||
constant DDR_COL_ADDR_WIDTH : positive := 9; --
|
||||
|
||||
constant LMR_REG_BASE : natural := 0;
|
||||
constant LMR_REG_EXTENDED : natural := 1;
|
||||
constant LMR_OP_NORMAL : natural := 0;
|
||||
constant LMR_OP_RES_DLL : natural := 2;
|
||||
constant LMR_BT_SEQ : natural := 0;
|
||||
constant LMR_BT_ILVD : natural := 1;
|
||||
constant LMR_BL2 : natural := 1;
|
||||
constant LMR_BL4 : natural := 2;
|
||||
constant LMR_BL8 : natural := 3;
|
||||
constant LMR_CL2 : natural := 2;
|
||||
constant LMR_CL3 : natural := 3;
|
||||
constant LMR_CL2_5 : natural := 6;
|
||||
|
||||
-- DDR SDRAM Hardware defined constants
|
||||
constant BIT_AUTO_PRE : positive := 10; -- bit-position in column address for auto precharge (see Data Sheet)
|
||||
constant BIT_PRE_ALL : positive := 10; -- bit-position in column address for precharge all (see Data Sheet)
|
||||
constant ENABLE_PRE_ALL : std_logic := '1';
|
||||
constant ENABLE_AUTO_PRE : std_logic := '0';
|
||||
|
||||
-- DDR-SDR TIMING constants ------------------------------------------------------------------
|
||||
-- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh
|
||||
constant REFRESH_INTERVAL : real := 7.8125; -- us
|
||||
|
||||
-- These values are for your SDRAM part (see datasheet)
|
||||
constant TCAS : positive := 2; -- CAS latency [clocks]
|
||||
constant TRP : positive := 2; -- precharge command period
|
||||
constant TRAS : positive := 5; -- active to precharge delay
|
||||
constant TRFC : positive := 8; -- auto refresh command period
|
||||
constant TMRD : positive := 2; -- load mode register command cylce time
|
||||
constant TRCD : positive := 2; -- active to read or write delay !
|
||||
constant TWR : positive := 2; -- write recovery time
|
||||
|
||||
constant PWR_UP_WAIT : natural := 220; -- µs
|
||||
|
||||
subtype user_tag_t is unsigned(3 downto 0);
|
||||
|
||||
----------------------------------------------------------------------------------------------
|
||||
|
||||
end sdram_config;
|
||||
@@ -0,0 +1,575 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
ENTITY irom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in inst_addr_t;
|
||||
dout : out inst_t
|
||||
);
|
||||
END irom;
|
||||
|
||||
ARCHITECTURE sdram_test OF irom IS
|
||||
|
||||
type imem_rom_t is array (0 to 513) of inst_t;
|
||||
|
||||
-- Assembled from sdram_test.jsm
|
||||
constant imem_rom : imem_rom_t :=
|
||||
(
|
||||
"110000" & X"007", -- 0x000: JMP 0x007
|
||||
"111100" & X"000", -- 0x001: PUSH R00
|
||||
"101000" & X"040", -- 0x002: XIN R00, (0x04)
|
||||
"011011" & X"100", -- 0x003: OR R00, 0x10
|
||||
"100100" & X"040", -- 0x004: XOUT (0x04), R00
|
||||
"111101" & X"000", -- 0x005: POP R00
|
||||
"111111" & X"000", -- 0x006: RETI
|
||||
"111011" & X"128", -- 0x007: CALL 0x128
|
||||
"000011" & X"000", -- 0x008: MOV R00, 0x00
|
||||
"100100" & X"010", -- 0x009: XOUT (0x01), R00
|
||||
"000011" & X"040", -- 0x00A: MOV R00, 0x04
|
||||
"100100" & X"040", -- 0x00B: XOUT (0x04), R00
|
||||
"101001" & X"030", -- 0x00C: CIN R00, (0x03)
|
||||
"011011" & X"050", -- 0x00D: OR R00, 0x05
|
||||
"100110" & X"030", -- 0x00E: COUT (0x03), R00
|
||||
"000011" & X"010", -- 0x00F: MOV R00, 0x01
|
||||
"111011" & X"145", -- 0x010: CALL 0x145
|
||||
"000011" & X"000", -- 0x011: MOV R00, 0x00
|
||||
"000011" & X"C01", -- 0x012: MOV R01, 0xC0
|
||||
"100100" & X"101", -- 0x013: XOUT (0x10), R01
|
||||
"100100" & X"111", -- 0x014: XOUT (0x11), R01
|
||||
"100100" & X"121", -- 0x015: XOUT (0x12), R01
|
||||
"111011" & X"1B9", -- 0x016: CALL 0x1B9
|
||||
"111011" & X"19E", -- 0x017: CALL 0x19E
|
||||
"000011" & X"031", -- 0x018: MOV R01, 0x03
|
||||
"111011" & X"14A", -- 0x019: CALL 0x14A
|
||||
"000011" & X"031", -- 0x01A: MOV R01, 0x03
|
||||
"111011" & X"1AA", -- 0x01B: CALL 0x1AA
|
||||
"000011" & X"001", -- 0x01C: MOV R01, 0x00
|
||||
"111011" & X"1B6", -- 0x01D: CALL 0x1B6
|
||||
"101000" & X"040", -- 0x01E: XIN R00, (0x04)
|
||||
"011011" & X"100", -- 0x01F: OR R00, 0x10
|
||||
"100100" & X"040", -- 0x020: XOUT (0x04), R00
|
||||
"111011" & X"1C6", -- 0x021: CALL 0x1C6
|
||||
"011011" & X"200", -- 0x022: OR R00, 0x20
|
||||
"100100" & X"040", -- 0x023: XOUT (0x04), R00
|
||||
"111011" & X"1C6", -- 0x024: CALL 0x1C6
|
||||
"011001" & X"EF0", -- 0x025: AND R00, 0xEF
|
||||
"100100" & X"040", -- 0x026: XOUT (0x04), R00
|
||||
"111011" & X"1C6", -- 0x027: CALL 0x1C6
|
||||
"011001" & X"CF0", -- 0x028: AND R00, 0xCF
|
||||
"100100" & X"040", -- 0x029: XOUT (0x04), R00
|
||||
"000011" & X"010", -- 0x02A: MOV R00, 0x01
|
||||
"111011" & X"145", -- 0x02B: CALL 0x145
|
||||
"000011" & X"0E1", -- 0x02C: MOV R01, 0x0E
|
||||
"111011" & X"14A", -- 0x02D: CALL 0x14A
|
||||
"000011" & X"0E1", -- 0x02E: MOV R01, 0x0E
|
||||
"111011" & X"1B3", -- 0x02F: CALL 0x1B3
|
||||
"000011" & X"001", -- 0x030: MOV R01, 0x00
|
||||
"111011" & X"1B6", -- 0x031: CALL 0x1B6
|
||||
"111011" & X"0CC", -- 0x032: CALL 0x0CC
|
||||
"000011" & X"800", -- 0x033: MOV R00, 0x80
|
||||
"000011" & X"08F", -- 0x034: MOV R15, 0x08
|
||||
"000111" & X"000", -- 0x035: MOVX (R00), 0x00
|
||||
"010001" & X"010", -- 0x036: INC R00
|
||||
"010101" & X"01F", -- 0x037: DEC R15
|
||||
"110010" & X"035", -- 0x038: JNZ 0x035
|
||||
"101000" & X"0A0", -- 0x039: XIN R00, (0x0A)
|
||||
"001111" & X"FF0", -- 0x03A: CMP R00, 0xFF
|
||||
"111001" & X"04B", -- 0x03B: JEQ 0x04B
|
||||
"000011" & X"082", -- 0x03C: MOV R02, 0x08
|
||||
"101000" & X"070", -- 0x03D: XIN R00, (0x07)
|
||||
"100100" & X"010", -- 0x03E: XOUT (0x01), R00
|
||||
"011001" & X"040", -- 0x03F: AND R00, 0x04
|
||||
"110010" & X"03D", -- 0x040: JNZ 0x03D
|
||||
"000011" & X"100", -- 0x041: MOV R00, 0x10
|
||||
"100100" & X"070", -- 0x042: XOUT (0x07), R00
|
||||
"010101" & X"022", -- 0x043: SUB R02, 0x02
|
||||
"110010" & X"03D", -- 0x044: JNZ 0x03D
|
||||
"111011" & X"0AB", -- 0x045: CALL 0x0AB
|
||||
"000011" & X"060", -- 0x046: MOV R00, 0x06
|
||||
"100100" & X"070", -- 0x047: XOUT (0x07), R00
|
||||
"000011" & X"080", -- 0x048: MOV R00, 0x08
|
||||
"111011" & X"0D3", -- 0x049: CALL 0x0D3
|
||||
"110000" & X"039", -- 0x04A: JMP 0x039
|
||||
"111011" & X"0E3", -- 0x04B: CALL 0x0E3
|
||||
"111011" & X"1BF", -- 0x04C: CALL 0x1BF
|
||||
"110000" & X"04E", -- 0x04D: JMP 0x04E
|
||||
"000011" & X"010", -- 0x04E: MOV R00, 0x01
|
||||
"111011" & X"145", -- 0x04F: CALL 0x145
|
||||
"000011" & X"1D1", -- 0x050: MOV R01, 0x1D
|
||||
"111011" & X"14A", -- 0x051: CALL 0x14A
|
||||
"000011" & X"1D1", -- 0x052: MOV R01, 0x1D
|
||||
"111011" & X"1B3", -- 0x053: CALL 0x1B3
|
||||
"000011" & X"001", -- 0x054: MOV R01, 0x00
|
||||
"111011" & X"1B6", -- 0x055: CALL 0x1B6
|
||||
"111011" & X"0CC", -- 0x056: CALL 0x0CC
|
||||
"000011" & X"000", -- 0x057: MOV R00, 0x00
|
||||
"001101" & X"000", -- 0x058: MOVC (0x00), R00
|
||||
"101000" & X"0A0", -- 0x059: XIN R00, (0x0A)
|
||||
"001111" & X"FF0", -- 0x05A: CMP R00, 0xFF
|
||||
"111001" & X"076", -- 0x05B: JEQ 0x076
|
||||
"000011" & X"082", -- 0x05C: MOV R02, 0x08
|
||||
"001010" & X"001", -- 0x05D: MOVC R01, (0x00)
|
||||
"000011" & X"800", -- 0x05E: MOV R00, 0x80
|
||||
"000011" & X"08F", -- 0x05F: MOV R15, 0x08
|
||||
"000110" & X"001", -- 0x060: MOVX (R01), R00
|
||||
"010001" & X"010", -- 0x061: INC R00
|
||||
"010001" & X"011", -- 0x062: INC R01
|
||||
"010101" & X"01F", -- 0x063: DEC R15
|
||||
"110010" & X"060", -- 0x064: JNZ 0x060
|
||||
"101000" & X"070", -- 0x065: XIN R00, (0x07)
|
||||
"100100" & X"010", -- 0x066: XOUT (0x01), R00
|
||||
"011001" & X"040", -- 0x067: AND R00, 0x04
|
||||
"110010" & X"065", -- 0x068: JNZ 0x065
|
||||
"000011" & X"100", -- 0x069: MOV R00, 0x10
|
||||
"100100" & X"070", -- 0x06A: XOUT (0x07), R00
|
||||
"001010" & X"000", -- 0x06B: MOVC R00, (0x00)
|
||||
"010001" & X"010", -- 0x06C: INC R00
|
||||
"001101" & X"000", -- 0x06D: MOVC (0x00), R00
|
||||
"010101" & X"022", -- 0x06E: SUB R02, 0x02
|
||||
"110010" & X"05D", -- 0x06F: JNZ 0x05D
|
||||
"111011" & X"0AB", -- 0x070: CALL 0x0AB
|
||||
"000011" & X"060", -- 0x071: MOV R00, 0x06
|
||||
"100100" & X"070", -- 0x072: XOUT (0x07), R00
|
||||
"000011" & X"080", -- 0x073: MOV R00, 0x08
|
||||
"111011" & X"0D3", -- 0x074: CALL 0x0D3
|
||||
"110000" & X"059", -- 0x075: JMP 0x059
|
||||
"111011" & X"0E3", -- 0x076: CALL 0x0E3
|
||||
"111011" & X"1BF", -- 0x077: CALL 0x1BF
|
||||
"000011" & X"010", -- 0x078: MOV R00, 0x01
|
||||
"111011" & X"145", -- 0x079: CALL 0x145
|
||||
"000011" & X"2B1", -- 0x07A: MOV R01, 0x2B
|
||||
"111011" & X"14A", -- 0x07B: CALL 0x14A
|
||||
"000011" & X"2B1", -- 0x07C: MOV R01, 0x2B
|
||||
"111011" & X"1B3", -- 0x07D: CALL 0x1B3
|
||||
"000011" & X"001", -- 0x07E: MOV R01, 0x00
|
||||
"111011" & X"1B6", -- 0x07F: CALL 0x1B6
|
||||
"111011" & X"0CC", -- 0x080: CALL 0x0CC
|
||||
"000011" & X"000", -- 0x081: MOV R00, 0x00
|
||||
"001101" & X"000", -- 0x082: MOVC (0x00), R00
|
||||
"101000" & X"0A0", -- 0x083: XIN R00, (0x0A)
|
||||
"001111" & X"FF0", -- 0x084: CMP R00, 0xFF
|
||||
"111001" & X"0B3", -- 0x085: JEQ 0x0B3
|
||||
"111011" & X"0AB", -- 0x086: CALL 0x0AB
|
||||
"000011" & X"050", -- 0x087: MOV R00, 0x05
|
||||
"100100" & X"070", -- 0x088: XOUT (0x07), R00
|
||||
"000011" & X"083", -- 0x089: MOV R03, 0x08
|
||||
"101000" & X"070", -- 0x08A: XIN R00, (0x07)
|
||||
"100100" & X"010", -- 0x08B: XOUT (0x01), R00
|
||||
"011001" & X"200", -- 0x08C: AND R00, 0x20
|
||||
"110010" & X"08A", -- 0x08D: JNZ 0x08A
|
||||
"001010" & X"001", -- 0x08E: MOVC R01, (0x00)
|
||||
"000011" & X"800", -- 0x08F: MOV R00, 0x80
|
||||
"000011" & X"08F", -- 0x090: MOV R15, 0x08
|
||||
"000100" & X"002", -- 0x091: MOVX R02, (R00)
|
||||
"001110" & X"012", -- 0x092: CMP R02, R01
|
||||
"111010" & X"0BF", -- 0x093: JNE 0x0BF
|
||||
"010001" & X"010", -- 0x094: INC R00
|
||||
"010001" & X"011", -- 0x095: INC R01
|
||||
"010101" & X"01F", -- 0x096: DEC R15
|
||||
"110010" & X"091", -- 0x097: JNZ 0x091
|
||||
"000011" & X"200", -- 0x098: MOV R00, 0x20
|
||||
"100100" & X"070", -- 0x099: XOUT (0x07), R00
|
||||
"001010" & X"000", -- 0x09A: MOVC R00, (0x00)
|
||||
"010001" & X"010", -- 0x09B: INC R00
|
||||
"001101" & X"000", -- 0x09C: MOVC (0x00), R00
|
||||
"010101" & X"023", -- 0x09D: SUB R03, 0x02
|
||||
"110010" & X"08A", -- 0x09E: JNZ 0x08A
|
||||
"000011" & X"080", -- 0x09F: MOV R00, 0x08
|
||||
"111011" & X"0D3", -- 0x0A0: CALL 0x0D3
|
||||
"110000" & X"083", -- 0x0A1: JMP 0x083
|
||||
"111100" & X"000", -- 0x0A2: PUSH R00
|
||||
"000011" & X"800", -- 0x0A3: MOV R00, 0x80
|
||||
"100100" & X"070", -- 0x0A4: XOUT (0x07), R00
|
||||
"101000" & X"070", -- 0x0A5: XIN R00, (0x07)
|
||||
"100100" & X"010", -- 0x0A6: XOUT (0x01), R00
|
||||
"011001" & X"800", -- 0x0A7: AND R00, 0x80
|
||||
"110001" & X"0A5", -- 0x0A8: JZ 0x0A5
|
||||
"111101" & X"000", -- 0x0A9: POP R00
|
||||
"111110" & X"000", -- 0x0AA: RET
|
||||
"111011" & X"0A2", -- 0x0AB: CALL 0x0A2
|
||||
"111100" & X"000", -- 0x0AC: PUSH R00
|
||||
"101000" & X"070", -- 0x0AD: XIN R00, (0x07)
|
||||
"100100" & X"010", -- 0x0AE: XOUT (0x01), R00
|
||||
"011001" & X"010", -- 0x0AF: AND R00, 0x01
|
||||
"110010" & X"0AD", -- 0x0B0: JNZ 0x0AD
|
||||
"111101" & X"000", -- 0x0B1: POP R00
|
||||
"111110" & X"000", -- 0x0B2: RET
|
||||
"000011" & X"010", -- 0x0B3: MOV R00, 0x01
|
||||
"111011" & X"145", -- 0x0B4: CALL 0x145
|
||||
"000011" & X"391", -- 0x0B5: MOV R01, 0x39
|
||||
"111011" & X"14A", -- 0x0B6: CALL 0x14A
|
||||
"000011" & X"C00", -- 0x0B7: MOV R00, 0xC0
|
||||
"111011" & X"145", -- 0x0B8: CALL 0x145
|
||||
"111011" & X"0EE", -- 0x0B9: CALL 0x0EE
|
||||
"000011" & X"391", -- 0x0BA: MOV R01, 0x39
|
||||
"111011" & X"1B3", -- 0x0BB: CALL 0x1B3
|
||||
"000011" & X"001", -- 0x0BC: MOV R01, 0x00
|
||||
"111011" & X"1B6", -- 0x0BD: CALL 0x1B6
|
||||
"110000" & X"0CA", -- 0x0BE: JMP 0x0CA
|
||||
"000011" & X"010", -- 0x0BF: MOV R00, 0x01
|
||||
"111011" & X"145", -- 0x0C0: CALL 0x145
|
||||
"000011" & X"431", -- 0x0C1: MOV R01, 0x43
|
||||
"111011" & X"14A", -- 0x0C2: CALL 0x14A
|
||||
"111011" & X"0EE", -- 0x0C3: CALL 0x0EE
|
||||
"111011" & X"106", -- 0x0C4: CALL 0x106
|
||||
"000011" & X"431", -- 0x0C5: MOV R01, 0x43
|
||||
"111011" & X"1B3", -- 0x0C6: CALL 0x1B3
|
||||
"000011" & X"001", -- 0x0C7: MOV R01, 0x00
|
||||
"111011" & X"1B6", -- 0x0C8: CALL 0x1B6
|
||||
"110000" & X"0CA", -- 0x0C9: JMP 0x0CA
|
||||
"111011" & X"1BF", -- 0x0CA: CALL 0x1BF
|
||||
"110000" & X"02A", -- 0x0CB: JMP 0x02A
|
||||
"111100" & X"000", -- 0x0CC: PUSH R00
|
||||
"000011" & X"000", -- 0x0CD: MOV R00, 0x00
|
||||
"100100" & X"080", -- 0x0CE: XOUT (0x08), R00
|
||||
"100100" & X"090", -- 0x0CF: XOUT (0x09), R00
|
||||
"100100" & X"0A0", -- 0x0D0: XOUT (0x0A), R00
|
||||
"111101" & X"000", -- 0x0D1: POP R00
|
||||
"111110" & X"000", -- 0x0D2: RET
|
||||
"111100" & X"001", -- 0x0D3: PUSH R01
|
||||
"111100" & X"002", -- 0x0D4: PUSH R02
|
||||
"111100" & X"003", -- 0x0D5: PUSH R03
|
||||
"101000" & X"081", -- 0x0D6: XIN R01, (0x08)
|
||||
"101000" & X"092", -- 0x0D7: XIN R02, (0x09)
|
||||
"101000" & X"0A3", -- 0x0D8: XIN R03, (0x0A)
|
||||
"010000" & X"001", -- 0x0D9: ADD R01, R00
|
||||
"010011" & X"002", -- 0x0DA: ADDC R02, 0x00
|
||||
"010011" & X"003", -- 0x0DB: ADDC R03, 0x00
|
||||
"100100" & X"081", -- 0x0DC: XOUT (0x08), R01
|
||||
"100100" & X"092", -- 0x0DD: XOUT (0x09), R02
|
||||
"100100" & X"0A3", -- 0x0DE: XOUT (0x0A), R03
|
||||
"111101" & X"003", -- 0x0DF: POP R03
|
||||
"111101" & X"002", -- 0x0E0: POP R02
|
||||
"111101" & X"001", -- 0x0E1: POP R01
|
||||
"111110" & X"000", -- 0x0E2: RET
|
||||
"000011" & X"C00", -- 0x0E3: MOV R00, 0xC0
|
||||
"111011" & X"145", -- 0x0E4: CALL 0x145
|
||||
"111011" & X"0EE", -- 0x0E5: CALL 0x0EE
|
||||
"111110" & X"000", -- 0x0E6: RET
|
||||
"111100" & X"001", -- 0x0E7: PUSH R01
|
||||
"111011" & X"121", -- 0x0E8: CALL 0x121
|
||||
"111011" & X"15C", -- 0x0E9: CALL 0x15C
|
||||
"000010" & X"010", -- 0x0EA: MOV R00, R01
|
||||
"111011" & X"15C", -- 0x0EB: CALL 0x15C
|
||||
"111101" & X"001", -- 0x0EC: POP R01
|
||||
"111110" & X"000", -- 0x0ED: RET
|
||||
"111100" & X"000", -- 0x0EE: PUSH R00
|
||||
"101000" & X"0A0", -- 0x0EF: XIN R00, (0x0A)
|
||||
"111011" & X"0E7", -- 0x0F0: CALL 0x0E7
|
||||
"101000" & X"090", -- 0x0F1: XIN R00, (0x09)
|
||||
"111011" & X"0E7", -- 0x0F2: CALL 0x0E7
|
||||
"101000" & X"080", -- 0x0F3: XIN R00, (0x08)
|
||||
"111011" & X"0E7", -- 0x0F4: CALL 0x0E7
|
||||
"111101" & X"000", -- 0x0F5: POP R00
|
||||
"111110" & X"000", -- 0x0F6: RET
|
||||
"111100" & X"000", -- 0x0F7: PUSH R00
|
||||
"010001" & X"031", -- 0x0F8: ADD R01, 0x03
|
||||
"001001" & X"010", -- 0x0F9: MOVC R00, (R01)
|
||||
"111011" & X"0E7", -- 0x0FA: CALL 0x0E7
|
||||
"010101" & X"011", -- 0x0FB: DEC R01
|
||||
"001001" & X"010", -- 0x0FC: MOVC R00, (R01)
|
||||
"111011" & X"0E7", -- 0x0FD: CALL 0x0E7
|
||||
"010101" & X"011", -- 0x0FE: DEC R01
|
||||
"001001" & X"010", -- 0x0FF: MOVC R00, (R01)
|
||||
"111011" & X"0E7", -- 0x100: CALL 0x0E7
|
||||
"010101" & X"011", -- 0x101: DEC R01
|
||||
"001001" & X"010", -- 0x102: MOVC R00, (R01)
|
||||
"111011" & X"0E7", -- 0x103: CALL 0x0E7
|
||||
"111101" & X"000", -- 0x104: POP R00
|
||||
"111110" & X"000", -- 0x105: RET
|
||||
"111100" & X"000", -- 0x106: PUSH R00
|
||||
"000011" & X"C00", -- 0x107: MOV R00, 0xC0
|
||||
"111011" & X"145", -- 0x108: CALL 0x145
|
||||
"000101" & X"870", -- 0x109: MOVX R00, (0x87)
|
||||
"111011" & X"0E7", -- 0x10A: CALL 0x0E7
|
||||
"000101" & X"860", -- 0x10B: MOVX R00, (0x86)
|
||||
"111011" & X"0E7", -- 0x10C: CALL 0x0E7
|
||||
"000101" & X"850", -- 0x10D: MOVX R00, (0x85)
|
||||
"111011" & X"0E7", -- 0x10E: CALL 0x0E7
|
||||
"000101" & X"840", -- 0x10F: MOVX R00, (0x84)
|
||||
"111011" & X"0E7", -- 0x110: CALL 0x0E7
|
||||
"000101" & X"830", -- 0x111: MOVX R00, (0x83)
|
||||
"111011" & X"0E7", -- 0x112: CALL 0x0E7
|
||||
"000101" & X"820", -- 0x113: MOVX R00, (0x82)
|
||||
"111011" & X"0E7", -- 0x114: CALL 0x0E7
|
||||
"000101" & X"810", -- 0x115: MOVX R00, (0x81)
|
||||
"111011" & X"0E7", -- 0x116: CALL 0x0E7
|
||||
"000101" & X"800", -- 0x117: MOVX R00, (0x80)
|
||||
"111011" & X"0E7", -- 0x118: CALL 0x0E7
|
||||
"111101" & X"000", -- 0x119: POP R00
|
||||
"111110" & X"000", -- 0x11A: RET
|
||||
"011001" & X"0F0", -- 0x11B: AND R00, 0x0F
|
||||
"001111" & X"0A0", -- 0x11C: CMP R00, 0x0A
|
||||
"110101" & X"11F", -- 0x11D: JLT 0x11F
|
||||
"010001" & X"070", -- 0x11E: ADD R00, 0x07
|
||||
"010001" & X"300", -- 0x11F: ADD R00, 0x30
|
||||
"111110" & X"000", -- 0x120: RET
|
||||
"111100" & X"000", -- 0x121: PUSH R00
|
||||
"111011" & X"11B", -- 0x122: CALL 0x11B
|
||||
"000010" & X"001", -- 0x123: MOV R01, R00
|
||||
"111101" & X"000", -- 0x124: POP R00
|
||||
"101010" & X"000", -- 0x125: SWAP R00
|
||||
"111011" & X"11B", -- 0x126: CALL 0x11B
|
||||
"111110" & X"000", -- 0x127: RET
|
||||
"000011" & X"002", -- 0x128: MOV R02, 0x00
|
||||
"000011" & X"030", -- 0x129: MOV R00, 0x03
|
||||
"111011" & X"174", -- 0x12A: CALL 0x174
|
||||
"111011" & X"1CD", -- 0x12B: CALL 0x1CD
|
||||
"000011" & X"002", -- 0x12C: MOV R02, 0x00
|
||||
"000011" & X"030", -- 0x12D: MOV R00, 0x03
|
||||
"111011" & X"174", -- 0x12E: CALL 0x174
|
||||
"111011" & X"1CD", -- 0x12F: CALL 0x1CD
|
||||
"000011" & X"002", -- 0x130: MOV R02, 0x00
|
||||
"000011" & X"020", -- 0x131: MOV R00, 0x02
|
||||
"111011" & X"174", -- 0x132: CALL 0x174
|
||||
"111011" & X"1D4", -- 0x133: CALL 0x1D4
|
||||
"000011" & X"280", -- 0x134: MOV R00, 0x28
|
||||
"111011" & X"145", -- 0x135: CALL 0x145
|
||||
"000011" & X"0C0", -- 0x136: MOV R00, 0x0C
|
||||
"111011" & X"145", -- 0x137: CALL 0x145
|
||||
"000011" & X"060", -- 0x138: MOV R00, 0x06
|
||||
"111011" & X"145", -- 0x139: CALL 0x145
|
||||
"000011" & X"010", -- 0x13A: MOV R00, 0x01
|
||||
"111011" & X"145", -- 0x13B: CALL 0x145
|
||||
"111110" & X"000", -- 0x13C: RET
|
||||
"111100" & X"000", -- 0x13D: PUSH R00
|
||||
"111011" & X"168", -- 0x13E: CALL 0x168
|
||||
"011001" & X"800", -- 0x13F: AND R00, 0x80
|
||||
"110001" & X"143", -- 0x140: JZ 0x143
|
||||
"111011" & X"1EB", -- 0x141: CALL 0x1EB
|
||||
"110000" & X"13E", -- 0x142: JMP 0x13E
|
||||
"111101" & X"000", -- 0x143: POP R00
|
||||
"111110" & X"000", -- 0x144: RET
|
||||
"111100" & X"002", -- 0x145: PUSH R02
|
||||
"000011" & X"002", -- 0x146: MOV R02, 0x00
|
||||
"111011" & X"161", -- 0x147: CALL 0x161
|
||||
"111101" & X"002", -- 0x148: POP R02
|
||||
"111110" & X"000", -- 0x149: RET
|
||||
"111100" & X"000", -- 0x14A: PUSH R00
|
||||
"000100" & X"010", -- 0x14B: MOVX R00, (R01)
|
||||
"010001" & X"011", -- 0x14C: INC R01
|
||||
"001111" & X"000", -- 0x14D: TST R00
|
||||
"110001" & X"151", -- 0x14E: JZ 0x151
|
||||
"111011" & X"15C", -- 0x14F: CALL 0x15C
|
||||
"110000" & X"14B", -- 0x150: JMP 0x14B
|
||||
"111101" & X"000", -- 0x151: POP R00
|
||||
"111110" & X"000", -- 0x152: RET
|
||||
"111100" & X"000", -- 0x153: PUSH R00
|
||||
"001001" & X"010", -- 0x154: MOVC R00, (R01)
|
||||
"010001" & X"011", -- 0x155: INC R01
|
||||
"001111" & X"000", -- 0x156: TST R00
|
||||
"110001" & X"15A", -- 0x157: JZ 0x15A
|
||||
"111011" & X"15C", -- 0x158: CALL 0x15C
|
||||
"110000" & X"154", -- 0x159: JMP 0x154
|
||||
"111101" & X"000", -- 0x15A: POP R00
|
||||
"111110" & X"000", -- 0x15B: RET
|
||||
"111100" & X"002", -- 0x15C: PUSH R02
|
||||
"000011" & X"402", -- 0x15D: MOV R02, 0x40
|
||||
"111011" & X"161", -- 0x15E: CALL 0x161
|
||||
"111101" & X"002", -- 0x15F: POP R02
|
||||
"111110" & X"000", -- 0x160: RET
|
||||
"111011" & X"13D", -- 0x161: CALL 0x13D
|
||||
"111100" & X"000", -- 0x162: PUSH R00
|
||||
"101010" & X"000", -- 0x163: SWAP R00
|
||||
"111011" & X"174", -- 0x164: CALL 0x174
|
||||
"111101" & X"000", -- 0x165: POP R00
|
||||
"111011" & X"174", -- 0x166: CALL 0x174
|
||||
"111110" & X"000", -- 0x167: RET
|
||||
"111100" & X"002", -- 0x168: PUSH R02
|
||||
"000011" & X"002", -- 0x169: MOV R02, 0x00
|
||||
"111011" & X"16D", -- 0x16A: CALL 0x16D
|
||||
"111101" & X"002", -- 0x16B: POP R02
|
||||
"111110" & X"000", -- 0x16C: RET
|
||||
"111011" & X"187", -- 0x16D: CALL 0x187
|
||||
"101010" & X"000", -- 0x16E: SWAP R00
|
||||
"111100" & X"000", -- 0x16F: PUSH R00
|
||||
"111011" & X"187", -- 0x170: CALL 0x187
|
||||
"111101" & X"002", -- 0x171: POP R02
|
||||
"011010" & X"020", -- 0x172: OR R00, R02
|
||||
"111110" & X"000", -- 0x173: RET
|
||||
"111100" & X"001", -- 0x174: PUSH R01
|
||||
"011001" & X"0F0", -- 0x175: AND R00, 0x0F
|
||||
"000010" & X"001", -- 0x176: MOV R01, R00
|
||||
"011010" & X"021", -- 0x177: OR R01, R02
|
||||
"100100" & X"031", -- 0x178: XOUT (0x03), R01
|
||||
"111011" & X"1EB", -- 0x179: CALL 0x1EB
|
||||
"000010" & X"001", -- 0x17A: MOV R01, R00
|
||||
"011010" & X"021", -- 0x17B: OR R01, R02
|
||||
"011011" & X"801", -- 0x17C: OR R01, 0x80
|
||||
"100100" & X"031", -- 0x17D: XOUT (0x03), R01
|
||||
"111011" & X"1EB", -- 0x17E: CALL 0x1EB
|
||||
"000010" & X"001", -- 0x17F: MOV R01, R00
|
||||
"011010" & X"021", -- 0x180: OR R01, R02
|
||||
"100100" & X"031", -- 0x181: XOUT (0x03), R01
|
||||
"111011" & X"1EB", -- 0x182: CALL 0x1EB
|
||||
"011011" & X"201", -- 0x183: OR R01, 0x20
|
||||
"100100" & X"031", -- 0x184: XOUT (0x03), R01
|
||||
"111101" & X"001", -- 0x185: POP R01
|
||||
"111110" & X"000", -- 0x186: RET
|
||||
"111100" & X"001", -- 0x187: PUSH R01
|
||||
"000011" & X"201", -- 0x188: MOV R01, 0x20
|
||||
"011010" & X"021", -- 0x189: OR R01, R02
|
||||
"100100" & X"031", -- 0x18A: XOUT (0x03), R01
|
||||
"111011" & X"1EB", -- 0x18B: CALL 0x1EB
|
||||
"000011" & X"201", -- 0x18C: MOV R01, 0x20
|
||||
"011010" & X"021", -- 0x18D: OR R01, R02
|
||||
"011011" & X"801", -- 0x18E: OR R01, 0x80
|
||||
"100100" & X"031", -- 0x18F: XOUT (0x03), R01
|
||||
"111011" & X"1EB", -- 0x190: CALL 0x1EB
|
||||
"101000" & X"030", -- 0x191: XIN R00, (0x03)
|
||||
"011001" & X"0F0", -- 0x192: AND R00, 0x0F
|
||||
"000011" & X"201", -- 0x193: MOV R01, 0x20
|
||||
"011010" & X"021", -- 0x194: OR R01, R02
|
||||
"100100" & X"031", -- 0x195: XOUT (0x03), R01
|
||||
"111011" & X"1EB", -- 0x196: CALL 0x1EB
|
||||
"111101" & X"001", -- 0x197: POP R01
|
||||
"111110" & X"000", -- 0x198: RET
|
||||
"111100" & X"000", -- 0x199: PUSH R00
|
||||
"000011" & X"020", -- 0x19A: MOV R00, 0x02
|
||||
"100100" & X"0E0", -- 0x19B: XOUT (0x0E), R00
|
||||
"111101" & X"000", -- 0x19C: POP R00
|
||||
"111110" & X"000", -- 0x19D: RET
|
||||
"111100" & X"000", -- 0x19E: PUSH R00
|
||||
"000011" & X"010", -- 0x19F: MOV R00, 0x01
|
||||
"100100" & X"0E0", -- 0x1A0: XOUT (0x0E), R00
|
||||
"111101" & X"000", -- 0x1A1: POP R00
|
||||
"111110" & X"000", -- 0x1A2: RET
|
||||
"111011" & X"1B9", -- 0x1A3: CALL 0x1B9
|
||||
"100100" & X"0C1", -- 0x1A4: XOUT (0x0C), R01
|
||||
"100100" & X"0B0", -- 0x1A5: XOUT (0x0B), R00
|
||||
"111110" & X"000", -- 0x1A6: RET
|
||||
"111011" & X"1B9", -- 0x1A7: CALL 0x1B9
|
||||
"100100" & X"0D0", -- 0x1A8: XOUT (0x0D), R00
|
||||
"111110" & X"000", -- 0x1A9: RET
|
||||
"111100" & X"000", -- 0x1AA: PUSH R00
|
||||
"000100" & X"010", -- 0x1AB: MOVX R00, (R01)
|
||||
"010001" & X"011", -- 0x1AC: INC R01
|
||||
"001111" & X"000", -- 0x1AD: TST R00
|
||||
"110001" & X"1B1", -- 0x1AE: JZ 0x1B1
|
||||
"111011" & X"1A7", -- 0x1AF: CALL 0x1A7
|
||||
"110000" & X"1AB", -- 0x1B0: JMP 0x1AB
|
||||
"111101" & X"000", -- 0x1B1: POP R00
|
||||
"111110" & X"000", -- 0x1B2: RET
|
||||
"111011" & X"199", -- 0x1B3: CALL 0x199
|
||||
"111011" & X"1AA", -- 0x1B4: CALL 0x1AA
|
||||
"111110" & X"000", -- 0x1B5: RET
|
||||
"111011" & X"1AA", -- 0x1B6: CALL 0x1AA
|
||||
"111011" & X"199", -- 0x1B7: CALL 0x199
|
||||
"111110" & X"000", -- 0x1B8: RET
|
||||
"111100" & X"000", -- 0x1B9: PUSH R00
|
||||
"101000" & X"0E0", -- 0x1BA: XIN R00, (0x0E)
|
||||
"011001" & X"020", -- 0x1BB: AND R00, 0x02
|
||||
"110001" & X"1BA", -- 0x1BC: JZ 0x1BA
|
||||
"111101" & X"000", -- 0x1BD: POP R00
|
||||
"111110" & X"000", -- 0x1BE: RET
|
||||
"111100" & X"00F", -- 0x1BF: PUSH R15
|
||||
"000011" & X"0AF", -- 0x1C0: MOV R15, 0x0A
|
||||
"111011" & X"1C6", -- 0x1C1: CALL 0x1C6
|
||||
"010101" & X"01F", -- 0x1C2: DEC R15
|
||||
"110010" & X"1C1", -- 0x1C3: JNZ 0x1C1
|
||||
"111101" & X"00F", -- 0x1C4: POP R15
|
||||
"111110" & X"000", -- 0x1C5: RET
|
||||
"111100" & X"00F", -- 0x1C6: PUSH R15
|
||||
"000011" & X"0AF", -- 0x1C7: MOV R15, 0x0A
|
||||
"111011" & X"1CD", -- 0x1C8: CALL 0x1CD
|
||||
"010101" & X"01F", -- 0x1C9: DEC R15
|
||||
"110010" & X"1C8", -- 0x1CA: JNZ 0x1C8
|
||||
"111101" & X"00F", -- 0x1CB: POP R15
|
||||
"111110" & X"000", -- 0x1CC: RET
|
||||
"111100" & X"00F", -- 0x1CD: PUSH R15
|
||||
"000011" & X"0AF", -- 0x1CE: MOV R15, 0x0A
|
||||
"111011" & X"1D4", -- 0x1CF: CALL 0x1D4
|
||||
"010101" & X"01F", -- 0x1D0: DEC R15
|
||||
"110010" & X"1CF", -- 0x1D1: JNZ 0x1CF
|
||||
"111101" & X"00F", -- 0x1D2: POP R15
|
||||
"111110" & X"000", -- 0x1D3: RET
|
||||
"111100" & X"00F", -- 0x1D4: PUSH R15
|
||||
"000011" & X"0AF", -- 0x1D5: MOV R15, 0x0A
|
||||
"111011" & X"1DB", -- 0x1D6: CALL 0x1DB
|
||||
"010101" & X"01F", -- 0x1D7: DEC R15
|
||||
"110010" & X"1D6", -- 0x1D8: JNZ 0x1D6
|
||||
"111101" & X"00F", -- 0x1D9: POP R15
|
||||
"111110" & X"000", -- 0x1DA: RET
|
||||
"111100" & X"00F", -- 0x1DB: PUSH R15
|
||||
"000011" & X"0AF", -- 0x1DC: MOV R15, 0x0A
|
||||
"111011" & X"1E2", -- 0x1DD: CALL 0x1E2
|
||||
"010101" & X"01F", -- 0x1DE: DEC R15
|
||||
"110010" & X"1DD", -- 0x1DF: JNZ 0x1DD
|
||||
"111101" & X"00F", -- 0x1E0: POP R15
|
||||
"111110" & X"000", -- 0x1E1: RET
|
||||
"111100" & X"00F", -- 0x1E2: PUSH R15
|
||||
"000011" & X"63F", -- 0x1E3: MOV R15, 0x63
|
||||
"000000" & X"000", -- 0x1E4: NOP
|
||||
"000000" & X"000", -- 0x1E5: NOP
|
||||
"000000" & X"000", -- 0x1E6: NOP
|
||||
"010101" & X"01F", -- 0x1E7: DEC R15
|
||||
"110010" & X"1E4", -- 0x1E8: JNZ 0x1E4
|
||||
"111101" & X"00F", -- 0x1E9: POP R15
|
||||
"111110" & X"000", -- 0x1EA: RET
|
||||
"111100" & X"00F", -- 0x1EB: PUSH R15
|
||||
"000011" & X"09F", -- 0x1EC: MOV R15, 0x09
|
||||
"000000" & X"000", -- 0x1ED: NOP
|
||||
"000000" & X"000", -- 0x1EE: NOP
|
||||
"000000" & X"000", -- 0x1EF: NOP
|
||||
"010101" & X"01F", -- 0x1F0: DEC R15
|
||||
"110010" & X"1ED", -- 0x1F1: JNZ 0x1ED
|
||||
"111101" & X"00F", -- 0x1F2: POP R15
|
||||
"111110" & X"000", -- 0x1F3: RET
|
||||
"111100" & X"001", -- 0x1F4: PUSH R01
|
||||
"101000" & X"061", -- 0x1F5: XIN R01, (0x06)
|
||||
"011001" & X"021", -- 0x1F6: AND R01, 0x02
|
||||
"110010" & X"1F5", -- 0x1F7: JNZ 0x1F5
|
||||
"100100" & X"020", -- 0x1F8: XOUT (0x02), R00
|
||||
"111101" & X"001", -- 0x1F9: POP R01
|
||||
"111110" & X"000", -- 0x1FA: RET
|
||||
"111100" & X"001", -- 0x1FB: PUSH R01
|
||||
"101000" & X"061", -- 0x1FC: XIN R01, (0x06)
|
||||
"011001" & X"101", -- 0x1FD: AND R01, 0x10
|
||||
"110001" & X"1FC", -- 0x1FE: JZ 0x1FC
|
||||
"101000" & X"020", -- 0x1FF: XIN R00, (0x02)
|
||||
"111101" & X"001", -- 0x200: POP R01
|
||||
"111110" & X"000" -- 0x201: RET
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= imem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end sdram_test;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,226 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
ENTITY irom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in inst_addr_t;
|
||||
dout : out inst_t
|
||||
);
|
||||
END irom;
|
||||
|
||||
ARCHITECTURE sdram_test_short OF irom IS
|
||||
|
||||
type imem_rom_t is array (0 to 164) of inst_t;
|
||||
|
||||
-- Assembled from sdram_test_short.jsm
|
||||
constant imem_rom : imem_rom_t :=
|
||||
(
|
||||
"110000" & X"002", -- 0x000: JMP 0x002
|
||||
"111111" & X"000", -- 0x001: RETI
|
||||
"000011" & X"000", -- 0x002: MOV R00, 0x00
|
||||
"100100" & X"010", -- 0x003: XOUT (0x01), R00
|
||||
"000011" & X"040", -- 0x004: MOV R00, 0x04
|
||||
"100100" & X"040", -- 0x005: XOUT (0x04), R00
|
||||
"000011" & X"000", -- 0x006: MOV R00, 0x00
|
||||
"000011" & X"801", -- 0x007: MOV R01, 0x80
|
||||
"100100" & X"100", -- 0x008: XOUT (0x10), R00
|
||||
"100100" & X"111", -- 0x009: XOUT (0x11), R01
|
||||
"100100" & X"120", -- 0x00A: XOUT (0x12), R00
|
||||
"110000" & X"026", -- 0x00B: JMP 0x026
|
||||
"111011" & X"07D", -- 0x00C: CALL 0x07D
|
||||
"000011" & X"800", -- 0x00D: MOV R00, 0x80
|
||||
"000011" & X"08F", -- 0x00E: MOV R15, 0x08
|
||||
"000111" & X"000", -- 0x00F: MOVX (R00), 0x00
|
||||
"010001" & X"010", -- 0x010: INC R00
|
||||
"010101" & X"01F", -- 0x011: DEC R15
|
||||
"110010" & X"00F", -- 0x012: JNZ 0x00F
|
||||
"101000" & X"080", -- 0x013: XIN R00, (0x08)
|
||||
"001111" & X"400", -- 0x014: CMP R00, 0x40
|
||||
"111001" & X"025", -- 0x015: JEQ 0x025
|
||||
"000011" & X"082", -- 0x016: MOV R02, 0x08
|
||||
"101000" & X"070", -- 0x017: XIN R00, (0x07)
|
||||
"100100" & X"010", -- 0x018: XOUT (0x01), R00
|
||||
"011001" & X"040", -- 0x019: AND R00, 0x04
|
||||
"110010" & X"017", -- 0x01A: JNZ 0x017
|
||||
"000011" & X"100", -- 0x01B: MOV R00, 0x10
|
||||
"100100" & X"070", -- 0x01C: XOUT (0x07), R00
|
||||
"010101" & X"022", -- 0x01D: SUB R02, 0x02
|
||||
"110010" & X"017", -- 0x01E: JNZ 0x017
|
||||
"111011" & X"072", -- 0x01F: CALL 0x072
|
||||
"000011" & X"060", -- 0x020: MOV R00, 0x06
|
||||
"100100" & X"070", -- 0x021: XOUT (0x07), R00
|
||||
"000011" & X"080", -- 0x022: MOV R00, 0x08
|
||||
"111011" & X"084", -- 0x023: CALL 0x084
|
||||
"110000" & X"013", -- 0x024: JMP 0x013
|
||||
"111011" & X"094", -- 0x025: CALL 0x094
|
||||
"111011" & X"07D", -- 0x026: CALL 0x07D
|
||||
"000011" & X"000", -- 0x027: MOV R00, 0x00
|
||||
"001101" & X"000", -- 0x028: MOVC (0x00), R00
|
||||
"101000" & X"080", -- 0x029: XIN R00, (0x08)
|
||||
"001111" & X"400", -- 0x02A: CMP R00, 0x40
|
||||
"111001" & X"046", -- 0x02B: JEQ 0x046
|
||||
"000011" & X"082", -- 0x02C: MOV R02, 0x08
|
||||
"001010" & X"001", -- 0x02D: MOVC R01, (0x00)
|
||||
"000011" & X"800", -- 0x02E: MOV R00, 0x80
|
||||
"000011" & X"08F", -- 0x02F: MOV R15, 0x08
|
||||
"000110" & X"001", -- 0x030: MOVX (R01), R00
|
||||
"010001" & X"010", -- 0x031: INC R00
|
||||
"010001" & X"011", -- 0x032: INC R01
|
||||
"010101" & X"01F", -- 0x033: DEC R15
|
||||
"110010" & X"030", -- 0x034: JNZ 0x030
|
||||
"101000" & X"070", -- 0x035: XIN R00, (0x07)
|
||||
"100100" & X"010", -- 0x036: XOUT (0x01), R00
|
||||
"011001" & X"040", -- 0x037: AND R00, 0x04
|
||||
"110010" & X"035", -- 0x038: JNZ 0x035
|
||||
"000011" & X"100", -- 0x039: MOV R00, 0x10
|
||||
"100100" & X"070", -- 0x03A: XOUT (0x07), R00
|
||||
"001010" & X"000", -- 0x03B: MOVC R00, (0x00)
|
||||
"010001" & X"010", -- 0x03C: INC R00
|
||||
"001101" & X"000", -- 0x03D: MOVC (0x00), R00
|
||||
"010101" & X"022", -- 0x03E: SUB R02, 0x02
|
||||
"110010" & X"02D", -- 0x03F: JNZ 0x02D
|
||||
"111011" & X"072", -- 0x040: CALL 0x072
|
||||
"000011" & X"060", -- 0x041: MOV R00, 0x06
|
||||
"100100" & X"070", -- 0x042: XOUT (0x07), R00
|
||||
"000011" & X"080", -- 0x043: MOV R00, 0x08
|
||||
"111011" & X"084", -- 0x044: CALL 0x084
|
||||
"110000" & X"029", -- 0x045: JMP 0x029
|
||||
"111011" & X"094", -- 0x046: CALL 0x094
|
||||
"111011" & X"07D", -- 0x047: CALL 0x07D
|
||||
"000011" & X"000", -- 0x048: MOV R00, 0x00
|
||||
"001101" & X"000", -- 0x049: MOVC (0x00), R00
|
||||
"101000" & X"0A0", -- 0x04A: XIN R00, (0x0A)
|
||||
"001111" & X"400", -- 0x04B: CMP R00, 0x40
|
||||
"111001" & X"07A", -- 0x04C: JEQ 0x07A
|
||||
"111011" & X"072", -- 0x04D: CALL 0x072
|
||||
"000011" & X"050", -- 0x04E: MOV R00, 0x05
|
||||
"100100" & X"070", -- 0x04F: XOUT (0x07), R00
|
||||
"000011" & X"083", -- 0x050: MOV R03, 0x08
|
||||
"101000" & X"070", -- 0x051: XIN R00, (0x07)
|
||||
"100100" & X"010", -- 0x052: XOUT (0x01), R00
|
||||
"011001" & X"200", -- 0x053: AND R00, 0x20
|
||||
"110010" & X"051", -- 0x054: JNZ 0x051
|
||||
"001010" & X"001", -- 0x055: MOVC R01, (0x00)
|
||||
"000011" & X"800", -- 0x056: MOV R00, 0x80
|
||||
"000011" & X"08F", -- 0x057: MOV R15, 0x08
|
||||
"000100" & X"002", -- 0x058: MOVX R02, (R00)
|
||||
"001110" & X"012", -- 0x059: CMP R02, R01
|
||||
"111010" & X"07B", -- 0x05A: JNE 0x07B
|
||||
"010001" & X"010", -- 0x05B: INC R00
|
||||
"010001" & X"011", -- 0x05C: INC R01
|
||||
"010101" & X"01F", -- 0x05D: DEC R15
|
||||
"110010" & X"058", -- 0x05E: JNZ 0x058
|
||||
"000011" & X"200", -- 0x05F: MOV R00, 0x20
|
||||
"100100" & X"070", -- 0x060: XOUT (0x07), R00
|
||||
"001010" & X"000", -- 0x061: MOVC R00, (0x00)
|
||||
"010001" & X"010", -- 0x062: INC R00
|
||||
"001101" & X"000", -- 0x063: MOVC (0x00), R00
|
||||
"010101" & X"023", -- 0x064: SUB R03, 0x02
|
||||
"110010" & X"051", -- 0x065: JNZ 0x051
|
||||
"000011" & X"080", -- 0x066: MOV R00, 0x08
|
||||
"111011" & X"084", -- 0x067: CALL 0x084
|
||||
"110000" & X"04A", -- 0x068: JMP 0x04A
|
||||
"111100" & X"000", -- 0x069: PUSH R00
|
||||
"000011" & X"800", -- 0x06A: MOV R00, 0x80
|
||||
"100100" & X"070", -- 0x06B: XOUT (0x07), R00
|
||||
"101000" & X"070", -- 0x06C: XIN R00, (0x07)
|
||||
"100100" & X"010", -- 0x06D: XOUT (0x01), R00
|
||||
"011001" & X"800", -- 0x06E: AND R00, 0x80
|
||||
"110001" & X"06C", -- 0x06F: JZ 0x06C
|
||||
"111101" & X"000", -- 0x070: POP R00
|
||||
"111110" & X"000", -- 0x071: RET
|
||||
"111011" & X"069", -- 0x072: CALL 0x069
|
||||
"111100" & X"000", -- 0x073: PUSH R00
|
||||
"101000" & X"070", -- 0x074: XIN R00, (0x07)
|
||||
"100100" & X"010", -- 0x075: XOUT (0x01), R00
|
||||
"011001" & X"010", -- 0x076: AND R00, 0x01
|
||||
"110010" & X"074", -- 0x077: JNZ 0x074
|
||||
"111101" & X"000", -- 0x078: POP R00
|
||||
"111110" & X"000", -- 0x079: RET
|
||||
"110000" & X"07C", -- 0x07A: JMP 0x07C
|
||||
"110000" & X"07C", -- 0x07B: JMP 0x07C
|
||||
"110000" & X"00C", -- 0x07C: JMP 0x00C
|
||||
"111100" & X"000", -- 0x07D: PUSH R00
|
||||
"000011" & X"000", -- 0x07E: MOV R00, 0x00
|
||||
"100100" & X"080", -- 0x07F: XOUT (0x08), R00
|
||||
"100100" & X"090", -- 0x080: XOUT (0x09), R00
|
||||
"100100" & X"0A0", -- 0x081: XOUT (0x0A), R00
|
||||
"111101" & X"000", -- 0x082: POP R00
|
||||
"111110" & X"000", -- 0x083: RET
|
||||
"111100" & X"001", -- 0x084: PUSH R01
|
||||
"111100" & X"002", -- 0x085: PUSH R02
|
||||
"111100" & X"003", -- 0x086: PUSH R03
|
||||
"101000" & X"081", -- 0x087: XIN R01, (0x08)
|
||||
"101000" & X"092", -- 0x088: XIN R02, (0x09)
|
||||
"101000" & X"0A3", -- 0x089: XIN R03, (0x0A)
|
||||
"010000" & X"001", -- 0x08A: ADD R01, R00
|
||||
"010011" & X"002", -- 0x08B: ADDC R02, 0x00
|
||||
"010011" & X"003", -- 0x08C: ADDC R03, 0x00
|
||||
"100100" & X"081", -- 0x08D: XOUT (0x08), R01
|
||||
"100100" & X"092", -- 0x08E: XOUT (0x09), R02
|
||||
"100100" & X"0A3", -- 0x08F: XOUT (0x0A), R03
|
||||
"111101" & X"003", -- 0x090: POP R03
|
||||
"111101" & X"002", -- 0x091: POP R02
|
||||
"111101" & X"001", -- 0x092: POP R01
|
||||
"111110" & X"000", -- 0x093: RET
|
||||
"111110" & X"000", -- 0x094: RET
|
||||
"111110" & X"000", -- 0x095: RET
|
||||
"111110" & X"000", -- 0x096: RET
|
||||
"111110" & X"000", -- 0x097: RET
|
||||
"011001" & X"0F0", -- 0x098: AND R00, 0x0F
|
||||
"001111" & X"0A0", -- 0x099: CMP R00, 0x0A
|
||||
"110101" & X"09C", -- 0x09A: JLT 0x09C
|
||||
"010001" & X"070", -- 0x09B: ADD R00, 0x07
|
||||
"010001" & X"300", -- 0x09C: ADD R00, 0x30
|
||||
"111110" & X"000", -- 0x09D: RET
|
||||
"111100" & X"000", -- 0x09E: PUSH R00
|
||||
"111011" & X"098", -- 0x09F: CALL 0x098
|
||||
"000010" & X"001", -- 0x0A0: MOV R01, R00
|
||||
"111101" & X"000", -- 0x0A1: POP R00
|
||||
"101010" & X"000", -- 0x0A2: SWAP R00
|
||||
"111011" & X"098", -- 0x0A3: CALL 0x098
|
||||
"111110" & X"000" -- 0x0A4: RET
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= imem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end sdram_test_short;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,317 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
ENTITY xrom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in dmem_addr_t;
|
||||
dout : out dmem_data_t
|
||||
);
|
||||
END xrom;
|
||||
|
||||
ARCHITECTURE sdram_test_short OF xrom IS
|
||||
|
||||
type xmem_rom_t is array (0 to 255) of dmem_data_t;
|
||||
|
||||
-- Assembled from sdram_test_short.jsm
|
||||
constant xmem_rom : xmem_rom_t :=
|
||||
(
|
||||
X"0D", -- 0x00
|
||||
X"0A", -- 0x01
|
||||
X"00", -- 0x02
|
||||
X"53", -- 0x03
|
||||
X"44", -- 0x04
|
||||
X"52", -- 0x05
|
||||
X"41", -- 0x06
|
||||
X"4D", -- 0x07
|
||||
X"20", -- 0x08
|
||||
X"54", -- 0x09
|
||||
X"65", -- 0x0A
|
||||
X"73", -- 0x0B
|
||||
X"74", -- 0x0C
|
||||
X"00", -- 0x0D
|
||||
X"43", -- 0x0E
|
||||
X"6C", -- 0x0F
|
||||
X"65", -- 0x10
|
||||
X"61", -- 0x11
|
||||
X"72", -- 0x12
|
||||
X"69", -- 0x13
|
||||
X"6E", -- 0x14
|
||||
X"67", -- 0x15
|
||||
X"20", -- 0x16
|
||||
X"53", -- 0x17
|
||||
X"44", -- 0x18
|
||||
X"52", -- 0x19
|
||||
X"41", -- 0x1A
|
||||
X"4D", -- 0x1B
|
||||
X"00", -- 0x1C
|
||||
X"57", -- 0x1D
|
||||
X"72", -- 0x1E
|
||||
X"69", -- 0x1F
|
||||
X"74", -- 0x20
|
||||
X"69", -- 0x21
|
||||
X"6E", -- 0x22
|
||||
X"67", -- 0x23
|
||||
X"20", -- 0x24
|
||||
X"53", -- 0x25
|
||||
X"44", -- 0x26
|
||||
X"52", -- 0x27
|
||||
X"41", -- 0x28
|
||||
X"4D", -- 0x29
|
||||
X"00", -- 0x2A
|
||||
X"52", -- 0x2B
|
||||
X"65", -- 0x2C
|
||||
X"61", -- 0x2D
|
||||
X"64", -- 0x2E
|
||||
X"69", -- 0x2F
|
||||
X"6E", -- 0x30
|
||||
X"67", -- 0x31
|
||||
X"20", -- 0x32
|
||||
X"53", -- 0x33
|
||||
X"44", -- 0x34
|
||||
X"52", -- 0x35
|
||||
X"41", -- 0x36
|
||||
X"4D", -- 0x37
|
||||
X"00", -- 0x38
|
||||
X"56", -- 0x39
|
||||
X"65", -- 0x3A
|
||||
X"72", -- 0x3B
|
||||
X"69", -- 0x3C
|
||||
X"66", -- 0x3D
|
||||
X"79", -- 0x3E
|
||||
X"20", -- 0x3F
|
||||
X"4F", -- 0x40
|
||||
X"4B", -- 0x41
|
||||
X"00", -- 0x42
|
||||
X"46", -- 0x43
|
||||
X"61", -- 0x44
|
||||
X"69", -- 0x45
|
||||
X"6C", -- 0x46
|
||||
X"65", -- 0x47
|
||||
X"64", -- 0x48
|
||||
X"20", -- 0x49
|
||||
X"61", -- 0x4A
|
||||
X"74", -- 0x4B
|
||||
X"20", -- 0x4C
|
||||
X"00", -- 0x4D
|
||||
X"2E", -- 0x4E
|
||||
X"00", -- 0x4F
|
||||
X"00", -- 0x50
|
||||
X"00", -- 0x51
|
||||
X"00", -- 0x52
|
||||
X"00", -- 0x53
|
||||
X"00", -- 0x54
|
||||
X"00", -- 0x55
|
||||
X"00", -- 0x56
|
||||
X"00", -- 0x57
|
||||
X"00", -- 0x58
|
||||
X"00", -- 0x59
|
||||
X"00", -- 0x5A
|
||||
X"00", -- 0x5B
|
||||
X"00", -- 0x5C
|
||||
X"00", -- 0x5D
|
||||
X"00", -- 0x5E
|
||||
X"00", -- 0x5F
|
||||
X"00", -- 0x60
|
||||
X"00", -- 0x61
|
||||
X"00", -- 0x62
|
||||
X"00", -- 0x63
|
||||
X"00", -- 0x64
|
||||
X"00", -- 0x65
|
||||
X"00", -- 0x66
|
||||
X"00", -- 0x67
|
||||
X"00", -- 0x68
|
||||
X"00", -- 0x69
|
||||
X"00", -- 0x6A
|
||||
X"00", -- 0x6B
|
||||
X"00", -- 0x6C
|
||||
X"00", -- 0x6D
|
||||
X"00", -- 0x6E
|
||||
X"00", -- 0x6F
|
||||
X"00", -- 0x70
|
||||
X"00", -- 0x71
|
||||
X"00", -- 0x72
|
||||
X"00", -- 0x73
|
||||
X"00", -- 0x74
|
||||
X"00", -- 0x75
|
||||
X"00", -- 0x76
|
||||
X"00", -- 0x77
|
||||
X"00", -- 0x78
|
||||
X"00", -- 0x79
|
||||
X"00", -- 0x7A
|
||||
X"00", -- 0x7B
|
||||
X"00", -- 0x7C
|
||||
X"00", -- 0x7D
|
||||
X"00", -- 0x7E
|
||||
X"00", -- 0x7F
|
||||
X"00", -- 0x80
|
||||
X"00", -- 0x81
|
||||
X"00", -- 0x82
|
||||
X"00", -- 0x83
|
||||
X"00", -- 0x84
|
||||
X"00", -- 0x85
|
||||
X"00", -- 0x86
|
||||
X"00", -- 0x87
|
||||
X"00", -- 0x88
|
||||
X"00", -- 0x89
|
||||
X"00", -- 0x8A
|
||||
X"00", -- 0x8B
|
||||
X"00", -- 0x8C
|
||||
X"00", -- 0x8D
|
||||
X"00", -- 0x8E
|
||||
X"00", -- 0x8F
|
||||
X"00", -- 0x90
|
||||
X"00", -- 0x91
|
||||
X"00", -- 0x92
|
||||
X"00", -- 0x93
|
||||
X"00", -- 0x94
|
||||
X"00", -- 0x95
|
||||
X"00", -- 0x96
|
||||
X"00", -- 0x97
|
||||
X"00", -- 0x98
|
||||
X"00", -- 0x99
|
||||
X"00", -- 0x9A
|
||||
X"00", -- 0x9B
|
||||
X"00", -- 0x9C
|
||||
X"00", -- 0x9D
|
||||
X"00", -- 0x9E
|
||||
X"00", -- 0x9F
|
||||
X"00", -- 0xA0
|
||||
X"00", -- 0xA1
|
||||
X"00", -- 0xA2
|
||||
X"00", -- 0xA3
|
||||
X"00", -- 0xA4
|
||||
X"00", -- 0xA5
|
||||
X"00", -- 0xA6
|
||||
X"00", -- 0xA7
|
||||
X"00", -- 0xA8
|
||||
X"00", -- 0xA9
|
||||
X"00", -- 0xAA
|
||||
X"00", -- 0xAB
|
||||
X"00", -- 0xAC
|
||||
X"00", -- 0xAD
|
||||
X"00", -- 0xAE
|
||||
X"00", -- 0xAF
|
||||
X"00", -- 0xB0
|
||||
X"00", -- 0xB1
|
||||
X"00", -- 0xB2
|
||||
X"00", -- 0xB3
|
||||
X"00", -- 0xB4
|
||||
X"00", -- 0xB5
|
||||
X"00", -- 0xB6
|
||||
X"00", -- 0xB7
|
||||
X"00", -- 0xB8
|
||||
X"00", -- 0xB9
|
||||
X"00", -- 0xBA
|
||||
X"00", -- 0xBB
|
||||
X"00", -- 0xBC
|
||||
X"00", -- 0xBD
|
||||
X"00", -- 0xBE
|
||||
X"00", -- 0xBF
|
||||
X"00", -- 0xC0
|
||||
X"00", -- 0xC1
|
||||
X"00", -- 0xC2
|
||||
X"00", -- 0xC3
|
||||
X"00", -- 0xC4
|
||||
X"00", -- 0xC5
|
||||
X"00", -- 0xC6
|
||||
X"00", -- 0xC7
|
||||
X"00", -- 0xC8
|
||||
X"00", -- 0xC9
|
||||
X"00", -- 0xCA
|
||||
X"00", -- 0xCB
|
||||
X"00", -- 0xCC
|
||||
X"00", -- 0xCD
|
||||
X"00", -- 0xCE
|
||||
X"00", -- 0xCF
|
||||
X"00", -- 0xD0
|
||||
X"00", -- 0xD1
|
||||
X"00", -- 0xD2
|
||||
X"00", -- 0xD3
|
||||
X"00", -- 0xD4
|
||||
X"00", -- 0xD5
|
||||
X"00", -- 0xD6
|
||||
X"00", -- 0xD7
|
||||
X"00", -- 0xD8
|
||||
X"00", -- 0xD9
|
||||
X"00", -- 0xDA
|
||||
X"00", -- 0xDB
|
||||
X"00", -- 0xDC
|
||||
X"00", -- 0xDD
|
||||
X"00", -- 0xDE
|
||||
X"00", -- 0xDF
|
||||
X"00", -- 0xE0
|
||||
X"00", -- 0xE1
|
||||
X"00", -- 0xE2
|
||||
X"00", -- 0xE3
|
||||
X"00", -- 0xE4
|
||||
X"00", -- 0xE5
|
||||
X"00", -- 0xE6
|
||||
X"00", -- 0xE7
|
||||
X"00", -- 0xE8
|
||||
X"00", -- 0xE9
|
||||
X"00", -- 0xEA
|
||||
X"00", -- 0xEB
|
||||
X"00", -- 0xEC
|
||||
X"00", -- 0xED
|
||||
X"00", -- 0xEE
|
||||
X"00", -- 0xEF
|
||||
X"00", -- 0xF0
|
||||
X"00", -- 0xF1
|
||||
X"00", -- 0xF2
|
||||
X"00", -- 0xF3
|
||||
X"00", -- 0xF4
|
||||
X"00", -- 0xF5
|
||||
X"00", -- 0xF6
|
||||
X"00", -- 0xF7
|
||||
X"00", -- 0xF8
|
||||
X"00", -- 0xF9
|
||||
X"00", -- 0xFA
|
||||
X"00", -- 0xFB
|
||||
X"00", -- 0xFC
|
||||
X"00", -- 0xFD
|
||||
X"00", -- 0xFE
|
||||
X"00" -- 0xFF
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= xmem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end sdram_test_short;
|
||||
|
||||
@@ -0,0 +1,413 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: loadable ROM
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library UNISIM;
|
||||
use UNISIM.VComponents.all;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
ENTITY xrom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in dmem_addr_t;
|
||||
dout : out dmem_data_t
|
||||
);
|
||||
|
||||
END xrom;
|
||||
|
||||
ARCHITECTURE loadable OF xrom IS
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
|
||||
-- Assembled from sdram_test_short.jsm
|
||||
type xmem_rom_t is array (0 to 255) of dmem_data_t;
|
||||
signal xmem_rom : xmem_rom_t :=
|
||||
(
|
||||
X"0D", -- 0x00
|
||||
X"0A", -- 0x01
|
||||
X"00", -- 0x02
|
||||
X"53", -- 0x03
|
||||
X"44", -- 0x04
|
||||
X"52", -- 0x05
|
||||
X"41", -- 0x06
|
||||
X"4D", -- 0x07
|
||||
X"20", -- 0x08
|
||||
X"54", -- 0x09
|
||||
X"65", -- 0x0A
|
||||
X"73", -- 0x0B
|
||||
X"74", -- 0x0C
|
||||
X"00", -- 0x0D
|
||||
X"43", -- 0x0E
|
||||
X"6C", -- 0x0F
|
||||
X"65", -- 0x10
|
||||
X"61", -- 0x11
|
||||
X"72", -- 0x12
|
||||
X"69", -- 0x13
|
||||
X"6E", -- 0x14
|
||||
X"67", -- 0x15
|
||||
X"20", -- 0x16
|
||||
X"53", -- 0x17
|
||||
X"44", -- 0x18
|
||||
X"52", -- 0x19
|
||||
X"41", -- 0x1A
|
||||
X"4D", -- 0x1B
|
||||
X"00", -- 0x1C
|
||||
X"57", -- 0x1D
|
||||
X"72", -- 0x1E
|
||||
X"69", -- 0x1F
|
||||
X"74", -- 0x20
|
||||
X"69", -- 0x21
|
||||
X"6E", -- 0x22
|
||||
X"67", -- 0x23
|
||||
X"20", -- 0x24
|
||||
X"53", -- 0x25
|
||||
X"44", -- 0x26
|
||||
X"52", -- 0x27
|
||||
X"41", -- 0x28
|
||||
X"4D", -- 0x29
|
||||
X"00", -- 0x2A
|
||||
X"52", -- 0x2B
|
||||
X"65", -- 0x2C
|
||||
X"61", -- 0x2D
|
||||
X"64", -- 0x2E
|
||||
X"69", -- 0x2F
|
||||
X"6E", -- 0x30
|
||||
X"67", -- 0x31
|
||||
X"20", -- 0x32
|
||||
X"53", -- 0x33
|
||||
X"44", -- 0x34
|
||||
X"52", -- 0x35
|
||||
X"41", -- 0x36
|
||||
X"4D", -- 0x37
|
||||
X"00", -- 0x38
|
||||
X"56", -- 0x39
|
||||
X"65", -- 0x3A
|
||||
X"72", -- 0x3B
|
||||
X"69", -- 0x3C
|
||||
X"66", -- 0x3D
|
||||
X"79", -- 0x3E
|
||||
X"20", -- 0x3F
|
||||
X"4F", -- 0x40
|
||||
X"4B", -- 0x41
|
||||
X"00", -- 0x42
|
||||
X"46", -- 0x43
|
||||
X"61", -- 0x44
|
||||
X"69", -- 0x45
|
||||
X"6C", -- 0x46
|
||||
X"65", -- 0x47
|
||||
X"64", -- 0x48
|
||||
X"20", -- 0x49
|
||||
X"61", -- 0x4A
|
||||
X"74", -- 0x4B
|
||||
X"20", -- 0x4C
|
||||
X"00", -- 0x4D
|
||||
X"2E", -- 0x4E
|
||||
X"00", -- 0x4F
|
||||
X"00", -- 0x50
|
||||
X"00", -- 0x51
|
||||
X"00", -- 0x52
|
||||
X"00", -- 0x53
|
||||
X"00", -- 0x54
|
||||
X"00", -- 0x55
|
||||
X"00", -- 0x56
|
||||
X"00", -- 0x57
|
||||
X"00", -- 0x58
|
||||
X"00", -- 0x59
|
||||
X"00", -- 0x5A
|
||||
X"00", -- 0x5B
|
||||
X"00", -- 0x5C
|
||||
X"00", -- 0x5D
|
||||
X"00", -- 0x5E
|
||||
X"00", -- 0x5F
|
||||
X"00", -- 0x60
|
||||
X"00", -- 0x61
|
||||
X"00", -- 0x62
|
||||
X"00", -- 0x63
|
||||
X"00", -- 0x64
|
||||
X"00", -- 0x65
|
||||
X"00", -- 0x66
|
||||
X"00", -- 0x67
|
||||
X"00", -- 0x68
|
||||
X"00", -- 0x69
|
||||
X"00", -- 0x6A
|
||||
X"00", -- 0x6B
|
||||
X"00", -- 0x6C
|
||||
X"00", -- 0x6D
|
||||
X"00", -- 0x6E
|
||||
X"00", -- 0x6F
|
||||
X"00", -- 0x70
|
||||
X"00", -- 0x71
|
||||
X"00", -- 0x72
|
||||
X"00", -- 0x73
|
||||
X"00", -- 0x74
|
||||
X"00", -- 0x75
|
||||
X"00", -- 0x76
|
||||
X"00", -- 0x77
|
||||
X"00", -- 0x78
|
||||
X"00", -- 0x79
|
||||
X"00", -- 0x7A
|
||||
X"00", -- 0x7B
|
||||
X"00", -- 0x7C
|
||||
X"00", -- 0x7D
|
||||
X"00", -- 0x7E
|
||||
X"00", -- 0x7F
|
||||
X"00", -- 0x80
|
||||
X"00", -- 0x81
|
||||
X"00", -- 0x82
|
||||
X"00", -- 0x83
|
||||
X"00", -- 0x84
|
||||
X"00", -- 0x85
|
||||
X"00", -- 0x86
|
||||
X"00", -- 0x87
|
||||
X"00", -- 0x88
|
||||
X"00", -- 0x89
|
||||
X"00", -- 0x8A
|
||||
X"00", -- 0x8B
|
||||
X"00", -- 0x8C
|
||||
X"00", -- 0x8D
|
||||
X"00", -- 0x8E
|
||||
X"00", -- 0x8F
|
||||
X"00", -- 0x90
|
||||
X"00", -- 0x91
|
||||
X"00", -- 0x92
|
||||
X"00", -- 0x93
|
||||
X"00", -- 0x94
|
||||
X"00", -- 0x95
|
||||
X"00", -- 0x96
|
||||
X"00", -- 0x97
|
||||
X"00", -- 0x98
|
||||
X"00", -- 0x99
|
||||
X"00", -- 0x9A
|
||||
X"00", -- 0x9B
|
||||
X"00", -- 0x9C
|
||||
X"00", -- 0x9D
|
||||
X"00", -- 0x9E
|
||||
X"00", -- 0x9F
|
||||
X"00", -- 0xA0
|
||||
X"00", -- 0xA1
|
||||
X"00", -- 0xA2
|
||||
X"00", -- 0xA3
|
||||
X"00", -- 0xA4
|
||||
X"00", -- 0xA5
|
||||
X"00", -- 0xA6
|
||||
X"00", -- 0xA7
|
||||
X"00", -- 0xA8
|
||||
X"00", -- 0xA9
|
||||
X"00", -- 0xAA
|
||||
X"00", -- 0xAB
|
||||
X"00", -- 0xAC
|
||||
X"00", -- 0xAD
|
||||
X"00", -- 0xAE
|
||||
X"00", -- 0xAF
|
||||
X"00", -- 0xB0
|
||||
X"00", -- 0xB1
|
||||
X"00", -- 0xB2
|
||||
X"00", -- 0xB3
|
||||
X"00", -- 0xB4
|
||||
X"00", -- 0xB5
|
||||
X"00", -- 0xB6
|
||||
X"00", -- 0xB7
|
||||
X"00", -- 0xB8
|
||||
X"00", -- 0xB9
|
||||
X"00", -- 0xBA
|
||||
X"00", -- 0xBB
|
||||
X"00", -- 0xBC
|
||||
X"00", -- 0xBD
|
||||
X"00", -- 0xBE
|
||||
X"00", -- 0xBF
|
||||
X"00", -- 0xC0
|
||||
X"00", -- 0xC1
|
||||
X"00", -- 0xC2
|
||||
X"00", -- 0xC3
|
||||
X"00", -- 0xC4
|
||||
X"00", -- 0xC5
|
||||
X"00", -- 0xC6
|
||||
X"00", -- 0xC7
|
||||
X"00", -- 0xC8
|
||||
X"00", -- 0xC9
|
||||
X"00", -- 0xCA
|
||||
X"00", -- 0xCB
|
||||
X"00", -- 0xCC
|
||||
X"00", -- 0xCD
|
||||
X"00", -- 0xCE
|
||||
X"00", -- 0xCF
|
||||
X"00", -- 0xD0
|
||||
X"00", -- 0xD1
|
||||
X"00", -- 0xD2
|
||||
X"00", -- 0xD3
|
||||
X"00", -- 0xD4
|
||||
X"00", -- 0xD5
|
||||
X"00", -- 0xD6
|
||||
X"00", -- 0xD7
|
||||
X"00", -- 0xD8
|
||||
X"00", -- 0xD9
|
||||
X"00", -- 0xDA
|
||||
X"00", -- 0xDB
|
||||
X"00", -- 0xDC
|
||||
X"00", -- 0xDD
|
||||
X"00", -- 0xDE
|
||||
X"00", -- 0xDF
|
||||
X"00", -- 0xE0
|
||||
X"00", -- 0xE1
|
||||
X"00", -- 0xE2
|
||||
X"00", -- 0xE3
|
||||
X"00", -- 0xE4
|
||||
X"00", -- 0xE5
|
||||
X"00", -- 0xE6
|
||||
X"00", -- 0xE7
|
||||
X"00", -- 0xE8
|
||||
X"00", -- 0xE9
|
||||
X"00", -- 0xEA
|
||||
X"00", -- 0xEB
|
||||
X"00", -- 0xEC
|
||||
X"00", -- 0xED
|
||||
X"00", -- 0xEE
|
||||
X"00", -- 0xEF
|
||||
X"00", -- 0xF0
|
||||
X"00", -- 0xF1
|
||||
X"00", -- 0xF2
|
||||
X"00", -- 0xF3
|
||||
X"00", -- 0xF4
|
||||
X"00", -- 0xF5
|
||||
X"00", -- 0xF6
|
||||
X"00", -- 0xF7
|
||||
X"00", -- 0xF8
|
||||
X"00", -- 0xF9
|
||||
X"00", -- 0xFA
|
||||
X"00", -- 0xFB
|
||||
X"00", -- 0xFC
|
||||
X"00", -- 0xFD
|
||||
X"00", -- 0xFE
|
||||
X"00" -- 0xFF
|
||||
);
|
||||
|
||||
signal jtag_ld_clk : STD_LOGIC;
|
||||
signal jtag_ld_we : STD_LOGIC;
|
||||
signal jtag_ld_addr : dmem_addr_t;
|
||||
signal jtag_ld_dout : dmem_data_t;
|
||||
signal jtag_ld_din : dmem_data_t;
|
||||
signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
|
||||
signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
|
||||
signal user_regi, user_rego : unsigned (15 downto 0);
|
||||
constant id : unsigned (15 downto 0) := X"BEEF";
|
||||
|
||||
begin
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- Virtex-4: JTAG Loader
|
||||
--------------------------------------------------------------------------
|
||||
i00_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_clk1,
|
||||
I => bs_clk0
|
||||
);
|
||||
|
||||
i01_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_update1,
|
||||
I => bs_update0
|
||||
);
|
||||
|
||||
BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4
|
||||
generic map
|
||||
(
|
||||
JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
|
||||
)
|
||||
port map
|
||||
(
|
||||
CAPTURE => bs_capture, -- CAPTURE output from TAP controller
|
||||
DRCK => bs_clk0, -- Data register output for USER functions
|
||||
RESET => bs_rst, -- Reset output from TAP controller
|
||||
SEL => bs_sel, -- USER active output
|
||||
SHIFT => bs_shift, -- SHIFT output from TAP controller
|
||||
TDI => bs_tdi, -- TDI output from TAP controller
|
||||
UPDATE => bs_update0, -- UPDATE output from TAP controller
|
||||
TDO => bs_tdo -- Data input for USER function
|
||||
);
|
||||
|
||||
jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1);
|
||||
jtag_ld_din <= user_regi(dmem_data_t'left downto 0);
|
||||
jtag_ld_clk <= bs_update1;
|
||||
jtag_ld_we <= bs_sel;
|
||||
|
||||
sipo:
|
||||
process (bs_rst, bs_clk1, bs_tdi, bs_shift)
|
||||
begin
|
||||
if bs_rst = '1' then
|
||||
user_regi <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
piso:
|
||||
process (bs_rst, bs_clk1, bs_shift, user_rego)
|
||||
begin
|
||||
bs_tdo <= user_rego(0);
|
||||
if bs_rst = '1' then
|
||||
user_rego <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
|
||||
else
|
||||
user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout;
|
||||
-- user_rego <= id;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- ROM Read/Write
|
||||
--------------------------------------------------------------------------
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= xmem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
PROM_WRITE:
|
||||
process(jtag_ld_clk, jtag_ld_we)
|
||||
begin
|
||||
if rising_edge(jtag_ld_clk) then
|
||||
if jtag_ld_we = '1' then
|
||||
xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
|
||||
else
|
||||
jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
end loadable;
|
||||
@@ -0,0 +1,317 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
ENTITY xrom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in dmem_addr_t;
|
||||
dout : out dmem_data_t
|
||||
);
|
||||
END xrom;
|
||||
|
||||
ARCHITECTURE sdram_test OF xrom IS
|
||||
|
||||
type xmem_rom_t is array (0 to 255) of dmem_data_t;
|
||||
|
||||
-- Assembled from sdram_test.jsm
|
||||
constant xmem_rom : xmem_rom_t :=
|
||||
(
|
||||
X"0D", -- 0x00
|
||||
X"0A", -- 0x01
|
||||
X"00", -- 0x02
|
||||
X"53", -- 0x03
|
||||
X"44", -- 0x04
|
||||
X"52", -- 0x05
|
||||
X"41", -- 0x06
|
||||
X"4D", -- 0x07
|
||||
X"20", -- 0x08
|
||||
X"54", -- 0x09
|
||||
X"65", -- 0x0A
|
||||
X"73", -- 0x0B
|
||||
X"74", -- 0x0C
|
||||
X"00", -- 0x0D
|
||||
X"43", -- 0x0E
|
||||
X"6C", -- 0x0F
|
||||
X"65", -- 0x10
|
||||
X"61", -- 0x11
|
||||
X"72", -- 0x12
|
||||
X"69", -- 0x13
|
||||
X"6E", -- 0x14
|
||||
X"67", -- 0x15
|
||||
X"20", -- 0x16
|
||||
X"53", -- 0x17
|
||||
X"44", -- 0x18
|
||||
X"52", -- 0x19
|
||||
X"41", -- 0x1A
|
||||
X"4D", -- 0x1B
|
||||
X"00", -- 0x1C
|
||||
X"57", -- 0x1D
|
||||
X"72", -- 0x1E
|
||||
X"69", -- 0x1F
|
||||
X"74", -- 0x20
|
||||
X"69", -- 0x21
|
||||
X"6E", -- 0x22
|
||||
X"67", -- 0x23
|
||||
X"20", -- 0x24
|
||||
X"53", -- 0x25
|
||||
X"44", -- 0x26
|
||||
X"52", -- 0x27
|
||||
X"41", -- 0x28
|
||||
X"4D", -- 0x29
|
||||
X"00", -- 0x2A
|
||||
X"52", -- 0x2B
|
||||
X"65", -- 0x2C
|
||||
X"61", -- 0x2D
|
||||
X"64", -- 0x2E
|
||||
X"69", -- 0x2F
|
||||
X"6E", -- 0x30
|
||||
X"67", -- 0x31
|
||||
X"20", -- 0x32
|
||||
X"53", -- 0x33
|
||||
X"44", -- 0x34
|
||||
X"52", -- 0x35
|
||||
X"41", -- 0x36
|
||||
X"4D", -- 0x37
|
||||
X"00", -- 0x38
|
||||
X"56", -- 0x39
|
||||
X"65", -- 0x3A
|
||||
X"72", -- 0x3B
|
||||
X"69", -- 0x3C
|
||||
X"66", -- 0x3D
|
||||
X"79", -- 0x3E
|
||||
X"20", -- 0x3F
|
||||
X"4F", -- 0x40
|
||||
X"4B", -- 0x41
|
||||
X"00", -- 0x42
|
||||
X"46", -- 0x43
|
||||
X"61", -- 0x44
|
||||
X"69", -- 0x45
|
||||
X"6C", -- 0x46
|
||||
X"65", -- 0x47
|
||||
X"64", -- 0x48
|
||||
X"20", -- 0x49
|
||||
X"61", -- 0x4A
|
||||
X"74", -- 0x4B
|
||||
X"20", -- 0x4C
|
||||
X"00", -- 0x4D
|
||||
X"2E", -- 0x4E
|
||||
X"00", -- 0x4F
|
||||
X"00", -- 0x50
|
||||
X"00", -- 0x51
|
||||
X"00", -- 0x52
|
||||
X"00", -- 0x53
|
||||
X"00", -- 0x54
|
||||
X"00", -- 0x55
|
||||
X"00", -- 0x56
|
||||
X"00", -- 0x57
|
||||
X"00", -- 0x58
|
||||
X"00", -- 0x59
|
||||
X"00", -- 0x5A
|
||||
X"00", -- 0x5B
|
||||
X"00", -- 0x5C
|
||||
X"00", -- 0x5D
|
||||
X"00", -- 0x5E
|
||||
X"00", -- 0x5F
|
||||
X"00", -- 0x60
|
||||
X"00", -- 0x61
|
||||
X"00", -- 0x62
|
||||
X"00", -- 0x63
|
||||
X"00", -- 0x64
|
||||
X"00", -- 0x65
|
||||
X"00", -- 0x66
|
||||
X"00", -- 0x67
|
||||
X"00", -- 0x68
|
||||
X"00", -- 0x69
|
||||
X"00", -- 0x6A
|
||||
X"00", -- 0x6B
|
||||
X"00", -- 0x6C
|
||||
X"00", -- 0x6D
|
||||
X"00", -- 0x6E
|
||||
X"00", -- 0x6F
|
||||
X"00", -- 0x70
|
||||
X"00", -- 0x71
|
||||
X"00", -- 0x72
|
||||
X"00", -- 0x73
|
||||
X"00", -- 0x74
|
||||
X"00", -- 0x75
|
||||
X"00", -- 0x76
|
||||
X"00", -- 0x77
|
||||
X"00", -- 0x78
|
||||
X"00", -- 0x79
|
||||
X"00", -- 0x7A
|
||||
X"00", -- 0x7B
|
||||
X"00", -- 0x7C
|
||||
X"00", -- 0x7D
|
||||
X"00", -- 0x7E
|
||||
X"00", -- 0x7F
|
||||
X"00", -- 0x80
|
||||
X"00", -- 0x81
|
||||
X"00", -- 0x82
|
||||
X"00", -- 0x83
|
||||
X"00", -- 0x84
|
||||
X"00", -- 0x85
|
||||
X"00", -- 0x86
|
||||
X"00", -- 0x87
|
||||
X"00", -- 0x88
|
||||
X"00", -- 0x89
|
||||
X"00", -- 0x8A
|
||||
X"00", -- 0x8B
|
||||
X"00", -- 0x8C
|
||||
X"00", -- 0x8D
|
||||
X"00", -- 0x8E
|
||||
X"00", -- 0x8F
|
||||
X"00", -- 0x90
|
||||
X"00", -- 0x91
|
||||
X"00", -- 0x92
|
||||
X"00", -- 0x93
|
||||
X"00", -- 0x94
|
||||
X"00", -- 0x95
|
||||
X"00", -- 0x96
|
||||
X"00", -- 0x97
|
||||
X"00", -- 0x98
|
||||
X"00", -- 0x99
|
||||
X"00", -- 0x9A
|
||||
X"00", -- 0x9B
|
||||
X"00", -- 0x9C
|
||||
X"00", -- 0x9D
|
||||
X"00", -- 0x9E
|
||||
X"00", -- 0x9F
|
||||
X"00", -- 0xA0
|
||||
X"00", -- 0xA1
|
||||
X"00", -- 0xA2
|
||||
X"00", -- 0xA3
|
||||
X"00", -- 0xA4
|
||||
X"00", -- 0xA5
|
||||
X"00", -- 0xA6
|
||||
X"00", -- 0xA7
|
||||
X"00", -- 0xA8
|
||||
X"00", -- 0xA9
|
||||
X"00", -- 0xAA
|
||||
X"00", -- 0xAB
|
||||
X"00", -- 0xAC
|
||||
X"00", -- 0xAD
|
||||
X"00", -- 0xAE
|
||||
X"00", -- 0xAF
|
||||
X"00", -- 0xB0
|
||||
X"00", -- 0xB1
|
||||
X"00", -- 0xB2
|
||||
X"00", -- 0xB3
|
||||
X"00", -- 0xB4
|
||||
X"00", -- 0xB5
|
||||
X"00", -- 0xB6
|
||||
X"00", -- 0xB7
|
||||
X"00", -- 0xB8
|
||||
X"00", -- 0xB9
|
||||
X"00", -- 0xBA
|
||||
X"00", -- 0xBB
|
||||
X"00", -- 0xBC
|
||||
X"00", -- 0xBD
|
||||
X"00", -- 0xBE
|
||||
X"00", -- 0xBF
|
||||
X"00", -- 0xC0
|
||||
X"00", -- 0xC1
|
||||
X"00", -- 0xC2
|
||||
X"00", -- 0xC3
|
||||
X"00", -- 0xC4
|
||||
X"00", -- 0xC5
|
||||
X"00", -- 0xC6
|
||||
X"00", -- 0xC7
|
||||
X"00", -- 0xC8
|
||||
X"00", -- 0xC9
|
||||
X"00", -- 0xCA
|
||||
X"00", -- 0xCB
|
||||
X"00", -- 0xCC
|
||||
X"00", -- 0xCD
|
||||
X"00", -- 0xCE
|
||||
X"00", -- 0xCF
|
||||
X"00", -- 0xD0
|
||||
X"00", -- 0xD1
|
||||
X"00", -- 0xD2
|
||||
X"00", -- 0xD3
|
||||
X"00", -- 0xD4
|
||||
X"00", -- 0xD5
|
||||
X"00", -- 0xD6
|
||||
X"00", -- 0xD7
|
||||
X"00", -- 0xD8
|
||||
X"00", -- 0xD9
|
||||
X"00", -- 0xDA
|
||||
X"00", -- 0xDB
|
||||
X"00", -- 0xDC
|
||||
X"00", -- 0xDD
|
||||
X"00", -- 0xDE
|
||||
X"00", -- 0xDF
|
||||
X"00", -- 0xE0
|
||||
X"00", -- 0xE1
|
||||
X"00", -- 0xE2
|
||||
X"00", -- 0xE3
|
||||
X"00", -- 0xE4
|
||||
X"00", -- 0xE5
|
||||
X"00", -- 0xE6
|
||||
X"00", -- 0xE7
|
||||
X"00", -- 0xE8
|
||||
X"00", -- 0xE9
|
||||
X"00", -- 0xEA
|
||||
X"00", -- 0xEB
|
||||
X"00", -- 0xEC
|
||||
X"00", -- 0xED
|
||||
X"00", -- 0xEE
|
||||
X"00", -- 0xEF
|
||||
X"00", -- 0xF0
|
||||
X"00", -- 0xF1
|
||||
X"00", -- 0xF2
|
||||
X"00", -- 0xF3
|
||||
X"00", -- 0xF4
|
||||
X"00", -- 0xF5
|
||||
X"00", -- 0xF6
|
||||
X"00", -- 0xF7
|
||||
X"00", -- 0xF8
|
||||
X"00", -- 0xF9
|
||||
X"00", -- 0xFA
|
||||
X"00", -- 0xFB
|
||||
X"00", -- 0xFC
|
||||
X"00", -- 0xFD
|
||||
X"00", -- 0xFE
|
||||
X"00" -- 0xFF
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= xmem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end sdram_test;
|
||||
|
||||
@@ -0,0 +1,413 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: loadable ROM
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library UNISIM;
|
||||
use UNISIM.VComponents.all;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
ENTITY xrom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in dmem_addr_t;
|
||||
dout : out dmem_data_t
|
||||
);
|
||||
|
||||
END xrom;
|
||||
|
||||
ARCHITECTURE loadable OF xrom IS
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
|
||||
-- Assembled from sdram_test.jsm
|
||||
type xmem_rom_t is array (0 to 255) of dmem_data_t;
|
||||
signal xmem_rom : xmem_rom_t :=
|
||||
(
|
||||
X"0D", -- 0x00
|
||||
X"0A", -- 0x01
|
||||
X"00", -- 0x02
|
||||
X"53", -- 0x03
|
||||
X"44", -- 0x04
|
||||
X"52", -- 0x05
|
||||
X"41", -- 0x06
|
||||
X"4D", -- 0x07
|
||||
X"20", -- 0x08
|
||||
X"54", -- 0x09
|
||||
X"65", -- 0x0A
|
||||
X"73", -- 0x0B
|
||||
X"74", -- 0x0C
|
||||
X"00", -- 0x0D
|
||||
X"43", -- 0x0E
|
||||
X"6C", -- 0x0F
|
||||
X"65", -- 0x10
|
||||
X"61", -- 0x11
|
||||
X"72", -- 0x12
|
||||
X"69", -- 0x13
|
||||
X"6E", -- 0x14
|
||||
X"67", -- 0x15
|
||||
X"20", -- 0x16
|
||||
X"53", -- 0x17
|
||||
X"44", -- 0x18
|
||||
X"52", -- 0x19
|
||||
X"41", -- 0x1A
|
||||
X"4D", -- 0x1B
|
||||
X"00", -- 0x1C
|
||||
X"57", -- 0x1D
|
||||
X"72", -- 0x1E
|
||||
X"69", -- 0x1F
|
||||
X"74", -- 0x20
|
||||
X"69", -- 0x21
|
||||
X"6E", -- 0x22
|
||||
X"67", -- 0x23
|
||||
X"20", -- 0x24
|
||||
X"53", -- 0x25
|
||||
X"44", -- 0x26
|
||||
X"52", -- 0x27
|
||||
X"41", -- 0x28
|
||||
X"4D", -- 0x29
|
||||
X"00", -- 0x2A
|
||||
X"52", -- 0x2B
|
||||
X"65", -- 0x2C
|
||||
X"61", -- 0x2D
|
||||
X"64", -- 0x2E
|
||||
X"69", -- 0x2F
|
||||
X"6E", -- 0x30
|
||||
X"67", -- 0x31
|
||||
X"20", -- 0x32
|
||||
X"53", -- 0x33
|
||||
X"44", -- 0x34
|
||||
X"52", -- 0x35
|
||||
X"41", -- 0x36
|
||||
X"4D", -- 0x37
|
||||
X"00", -- 0x38
|
||||
X"56", -- 0x39
|
||||
X"65", -- 0x3A
|
||||
X"72", -- 0x3B
|
||||
X"69", -- 0x3C
|
||||
X"66", -- 0x3D
|
||||
X"79", -- 0x3E
|
||||
X"20", -- 0x3F
|
||||
X"4F", -- 0x40
|
||||
X"4B", -- 0x41
|
||||
X"00", -- 0x42
|
||||
X"46", -- 0x43
|
||||
X"61", -- 0x44
|
||||
X"69", -- 0x45
|
||||
X"6C", -- 0x46
|
||||
X"65", -- 0x47
|
||||
X"64", -- 0x48
|
||||
X"20", -- 0x49
|
||||
X"61", -- 0x4A
|
||||
X"74", -- 0x4B
|
||||
X"20", -- 0x4C
|
||||
X"00", -- 0x4D
|
||||
X"2E", -- 0x4E
|
||||
X"00", -- 0x4F
|
||||
X"00", -- 0x50
|
||||
X"00", -- 0x51
|
||||
X"00", -- 0x52
|
||||
X"00", -- 0x53
|
||||
X"00", -- 0x54
|
||||
X"00", -- 0x55
|
||||
X"00", -- 0x56
|
||||
X"00", -- 0x57
|
||||
X"00", -- 0x58
|
||||
X"00", -- 0x59
|
||||
X"00", -- 0x5A
|
||||
X"00", -- 0x5B
|
||||
X"00", -- 0x5C
|
||||
X"00", -- 0x5D
|
||||
X"00", -- 0x5E
|
||||
X"00", -- 0x5F
|
||||
X"00", -- 0x60
|
||||
X"00", -- 0x61
|
||||
X"00", -- 0x62
|
||||
X"00", -- 0x63
|
||||
X"00", -- 0x64
|
||||
X"00", -- 0x65
|
||||
X"00", -- 0x66
|
||||
X"00", -- 0x67
|
||||
X"00", -- 0x68
|
||||
X"00", -- 0x69
|
||||
X"00", -- 0x6A
|
||||
X"00", -- 0x6B
|
||||
X"00", -- 0x6C
|
||||
X"00", -- 0x6D
|
||||
X"00", -- 0x6E
|
||||
X"00", -- 0x6F
|
||||
X"00", -- 0x70
|
||||
X"00", -- 0x71
|
||||
X"00", -- 0x72
|
||||
X"00", -- 0x73
|
||||
X"00", -- 0x74
|
||||
X"00", -- 0x75
|
||||
X"00", -- 0x76
|
||||
X"00", -- 0x77
|
||||
X"00", -- 0x78
|
||||
X"00", -- 0x79
|
||||
X"00", -- 0x7A
|
||||
X"00", -- 0x7B
|
||||
X"00", -- 0x7C
|
||||
X"00", -- 0x7D
|
||||
X"00", -- 0x7E
|
||||
X"00", -- 0x7F
|
||||
X"00", -- 0x80
|
||||
X"00", -- 0x81
|
||||
X"00", -- 0x82
|
||||
X"00", -- 0x83
|
||||
X"00", -- 0x84
|
||||
X"00", -- 0x85
|
||||
X"00", -- 0x86
|
||||
X"00", -- 0x87
|
||||
X"00", -- 0x88
|
||||
X"00", -- 0x89
|
||||
X"00", -- 0x8A
|
||||
X"00", -- 0x8B
|
||||
X"00", -- 0x8C
|
||||
X"00", -- 0x8D
|
||||
X"00", -- 0x8E
|
||||
X"00", -- 0x8F
|
||||
X"00", -- 0x90
|
||||
X"00", -- 0x91
|
||||
X"00", -- 0x92
|
||||
X"00", -- 0x93
|
||||
X"00", -- 0x94
|
||||
X"00", -- 0x95
|
||||
X"00", -- 0x96
|
||||
X"00", -- 0x97
|
||||
X"00", -- 0x98
|
||||
X"00", -- 0x99
|
||||
X"00", -- 0x9A
|
||||
X"00", -- 0x9B
|
||||
X"00", -- 0x9C
|
||||
X"00", -- 0x9D
|
||||
X"00", -- 0x9E
|
||||
X"00", -- 0x9F
|
||||
X"00", -- 0xA0
|
||||
X"00", -- 0xA1
|
||||
X"00", -- 0xA2
|
||||
X"00", -- 0xA3
|
||||
X"00", -- 0xA4
|
||||
X"00", -- 0xA5
|
||||
X"00", -- 0xA6
|
||||
X"00", -- 0xA7
|
||||
X"00", -- 0xA8
|
||||
X"00", -- 0xA9
|
||||
X"00", -- 0xAA
|
||||
X"00", -- 0xAB
|
||||
X"00", -- 0xAC
|
||||
X"00", -- 0xAD
|
||||
X"00", -- 0xAE
|
||||
X"00", -- 0xAF
|
||||
X"00", -- 0xB0
|
||||
X"00", -- 0xB1
|
||||
X"00", -- 0xB2
|
||||
X"00", -- 0xB3
|
||||
X"00", -- 0xB4
|
||||
X"00", -- 0xB5
|
||||
X"00", -- 0xB6
|
||||
X"00", -- 0xB7
|
||||
X"00", -- 0xB8
|
||||
X"00", -- 0xB9
|
||||
X"00", -- 0xBA
|
||||
X"00", -- 0xBB
|
||||
X"00", -- 0xBC
|
||||
X"00", -- 0xBD
|
||||
X"00", -- 0xBE
|
||||
X"00", -- 0xBF
|
||||
X"00", -- 0xC0
|
||||
X"00", -- 0xC1
|
||||
X"00", -- 0xC2
|
||||
X"00", -- 0xC3
|
||||
X"00", -- 0xC4
|
||||
X"00", -- 0xC5
|
||||
X"00", -- 0xC6
|
||||
X"00", -- 0xC7
|
||||
X"00", -- 0xC8
|
||||
X"00", -- 0xC9
|
||||
X"00", -- 0xCA
|
||||
X"00", -- 0xCB
|
||||
X"00", -- 0xCC
|
||||
X"00", -- 0xCD
|
||||
X"00", -- 0xCE
|
||||
X"00", -- 0xCF
|
||||
X"00", -- 0xD0
|
||||
X"00", -- 0xD1
|
||||
X"00", -- 0xD2
|
||||
X"00", -- 0xD3
|
||||
X"00", -- 0xD4
|
||||
X"00", -- 0xD5
|
||||
X"00", -- 0xD6
|
||||
X"00", -- 0xD7
|
||||
X"00", -- 0xD8
|
||||
X"00", -- 0xD9
|
||||
X"00", -- 0xDA
|
||||
X"00", -- 0xDB
|
||||
X"00", -- 0xDC
|
||||
X"00", -- 0xDD
|
||||
X"00", -- 0xDE
|
||||
X"00", -- 0xDF
|
||||
X"00", -- 0xE0
|
||||
X"00", -- 0xE1
|
||||
X"00", -- 0xE2
|
||||
X"00", -- 0xE3
|
||||
X"00", -- 0xE4
|
||||
X"00", -- 0xE5
|
||||
X"00", -- 0xE6
|
||||
X"00", -- 0xE7
|
||||
X"00", -- 0xE8
|
||||
X"00", -- 0xE9
|
||||
X"00", -- 0xEA
|
||||
X"00", -- 0xEB
|
||||
X"00", -- 0xEC
|
||||
X"00", -- 0xED
|
||||
X"00", -- 0xEE
|
||||
X"00", -- 0xEF
|
||||
X"00", -- 0xF0
|
||||
X"00", -- 0xF1
|
||||
X"00", -- 0xF2
|
||||
X"00", -- 0xF3
|
||||
X"00", -- 0xF4
|
||||
X"00", -- 0xF5
|
||||
X"00", -- 0xF6
|
||||
X"00", -- 0xF7
|
||||
X"00", -- 0xF8
|
||||
X"00", -- 0xF9
|
||||
X"00", -- 0xFA
|
||||
X"00", -- 0xFB
|
||||
X"00", -- 0xFC
|
||||
X"00", -- 0xFD
|
||||
X"00", -- 0xFE
|
||||
X"00" -- 0xFF
|
||||
);
|
||||
|
||||
signal jtag_ld_clk : STD_LOGIC;
|
||||
signal jtag_ld_we : STD_LOGIC;
|
||||
signal jtag_ld_addr : dmem_addr_t;
|
||||
signal jtag_ld_dout : dmem_data_t;
|
||||
signal jtag_ld_din : dmem_data_t;
|
||||
signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
|
||||
signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
|
||||
signal user_regi, user_rego : unsigned (15 downto 0);
|
||||
constant id : unsigned (15 downto 0) := X"BEEF";
|
||||
|
||||
begin
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- Virtex-4: JTAG Loader
|
||||
--------------------------------------------------------------------------
|
||||
i00_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_clk1,
|
||||
I => bs_clk0
|
||||
);
|
||||
|
||||
i01_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_update1,
|
||||
I => bs_update0
|
||||
);
|
||||
|
||||
BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4
|
||||
generic map
|
||||
(
|
||||
JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
|
||||
)
|
||||
port map
|
||||
(
|
||||
CAPTURE => bs_capture, -- CAPTURE output from TAP controller
|
||||
DRCK => bs_clk0, -- Data register output for USER functions
|
||||
RESET => bs_rst, -- Reset output from TAP controller
|
||||
SEL => bs_sel, -- USER active output
|
||||
SHIFT => bs_shift, -- SHIFT output from TAP controller
|
||||
TDI => bs_tdi, -- TDI output from TAP controller
|
||||
UPDATE => bs_update0, -- UPDATE output from TAP controller
|
||||
TDO => bs_tdo -- Data input for USER function
|
||||
);
|
||||
|
||||
jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1);
|
||||
jtag_ld_din <= user_regi(dmem_data_t'left downto 0);
|
||||
jtag_ld_clk <= bs_update1;
|
||||
jtag_ld_we <= bs_sel;
|
||||
|
||||
sipo:
|
||||
process (bs_rst, bs_clk1, bs_tdi, bs_shift)
|
||||
begin
|
||||
if bs_rst = '1' then
|
||||
user_regi <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
piso:
|
||||
process (bs_rst, bs_clk1, bs_shift, user_rego)
|
||||
begin
|
||||
bs_tdo <= user_rego(0);
|
||||
if bs_rst = '1' then
|
||||
user_rego <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
|
||||
else
|
||||
user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout;
|
||||
-- user_rego <= id;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- ROM Read/Write
|
||||
--------------------------------------------------------------------------
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= xmem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
PROM_WRITE:
|
||||
process(jtag_ld_clk, jtag_ld_we)
|
||||
begin
|
||||
if rising_edge(jtag_ld_clk) then
|
||||
if jtag_ld_we = '1' then
|
||||
xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
|
||||
else
|
||||
jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
end loadable;
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,408 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: system test using Xilinx ML-402
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
use std.textio.all; -- Imports the standard textio package.
|
||||
|
||||
Library UNISIM;
|
||||
use UNISIM.vcomponents.all;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
ENTITY systest IS
|
||||
PORT
|
||||
(
|
||||
sys_rst_n_in : in std_logic;
|
||||
sys_clk_in : in std_logic;
|
||||
sys_btn : in std_logic_vector(4 downto 0);
|
||||
sys_dip : in std_logic_vector(7 downto 0);
|
||||
sys_led : out std_logic_vector(8 downto 0);
|
||||
sys_rx : in std_logic;
|
||||
sys_tx : out std_logic;
|
||||
sys_lcd_d : inout std_logic_vector(3 downto 0);
|
||||
sys_lcd_e : out std_logic;
|
||||
sys_lcd_rs : out std_logic;
|
||||
sys_lcd_rw : out std_logic
|
||||
);
|
||||
END systest;
|
||||
|
||||
|
||||
ARCHITECTURE behavior OF systest IS
|
||||
|
||||
COMPONENT embedded_cpu
|
||||
Port (
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
int_in : in STD_LOGIC;
|
||||
int_ack : out STD_LOGIC;
|
||||
xmem_we : out STD_LOGIC;
|
||||
xmem_re : out STD_LOGIC;
|
||||
xmem_din : in unsigned (DMEM_WIDTH-1 downto 0);
|
||||
xmem_dout : out unsigned (DMEM_WIDTH-1 downto 0);
|
||||
xmem_addr : out unsigned (DMEM_WIDTH-1 downto 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--
|
||||
-- declaration of UART transmitter with integral 16 byte FIFO buffer
|
||||
--
|
||||
component uart_tx
|
||||
Port ( data_in : in std_logic_vector(7 downto 0);
|
||||
write_buffer : in std_logic;
|
||||
reset_buffer : in std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
serial_out : out std_logic;
|
||||
buffer_full : out std_logic;
|
||||
buffer_half_full : out std_logic;
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
--
|
||||
-- declaration of UART Receiver with integral 16 byte FIFO buffer
|
||||
--
|
||||
component uart_rx
|
||||
Port ( serial_in : in std_logic;
|
||||
data_out : out std_logic_vector(7 downto 0);
|
||||
read_buffer : in std_logic;
|
||||
reset_buffer : in std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
buffer_data_present : out std_logic;
|
||||
buffer_full : out std_logic;
|
||||
buffer_half_full : out std_logic;
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
|
||||
signal rst : std_logic;
|
||||
signal clk, clk0 : std_logic;
|
||||
signal ce : std_logic;
|
||||
signal int_req, int_in, int_ack, int_en : std_logic;
|
||||
|
||||
signal cpu_din : data_t;
|
||||
signal cpu_dout : data_t;
|
||||
signal cpu_addr : unsigned (DMEM_WIDTH-1 downto 0);
|
||||
signal cpu_we, reg_sel : std_logic;
|
||||
signal cpu_re : std_logic;
|
||||
signal led_reg_we, lcd_reg_we, ctrl_reg_we : std_logic;
|
||||
signal rom_dout, reg_dout, ctrl_reg : data_t;
|
||||
signal led_reg : data_t;
|
||||
signal lcd_reg_out, lcd_reg_in: data_t;
|
||||
--
|
||||
-- Signals for connection of peripherals
|
||||
--
|
||||
signal uart_status_port : data_t;
|
||||
--
|
||||
-- Signals to form an timer generating an interrupt every microsecond
|
||||
--
|
||||
constant timer_reload : integer := 99999;
|
||||
signal timer_count : integer range 0 to 99999 :=0;
|
||||
signal timer_pulse, timer_en : std_logic;
|
||||
--
|
||||
-- Signals for UART connections
|
||||
--
|
||||
signal baud_count : integer range 0 to 255 :=0;
|
||||
signal en_16_x_baud : std_logic;
|
||||
signal write_to_uart : std_logic;
|
||||
signal tx_full : std_logic;
|
||||
signal tx_half_full : std_logic;
|
||||
signal read_from_uart : std_logic;
|
||||
signal rx_data : std_logic_vector(7 downto 0);
|
||||
signal rx_data_present : std_logic;
|
||||
signal rx_full : std_logic;
|
||||
signal rx_half_full : std_logic;
|
||||
|
||||
signal rom_addr : unsigned(5 downto 0);
|
||||
signal reg_addr : unsigned(5 downto 0);
|
||||
|
||||
constant rom_data : string(1 to 64) :=
|
||||
(
|
||||
"J-CPU V1.0 " &
|
||||
' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' &
|
||||
' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' &
|
||||
' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' &
|
||||
' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' '
|
||||
|
||||
);
|
||||
constant lcd_e : integer := 7;
|
||||
constant lcd_rs : integer := 6;
|
||||
constant lcd_rw : integer := 5;
|
||||
|
||||
BEGIN
|
||||
|
||||
int_in <= sys_btn(4) or sys_dip(7) or timer_pulse or ctrl_reg(7) or rx_data_present;
|
||||
clk0 <= sys_clk_in;
|
||||
ce <= not rst;
|
||||
int_en <= ctrl_reg(0);
|
||||
timer_en <= ctrl_reg(1);
|
||||
sys_led(8) <= int_in;
|
||||
sys_led (7 downto 0) <= std_logic_vector(led_reg(7 downto 0));
|
||||
uart_status_port <= "000" & rx_data_present & rx_full & rx_half_full & tx_full & tx_half_full ;
|
||||
sys_lcd_d <= std_logic_vector(lcd_reg_out(3 downto 0)) when lcd_reg_out(lcd_rw) = '0' else (others => 'Z');
|
||||
sys_lcd_e <= lcd_reg_out(lcd_e);
|
||||
sys_lcd_rw <= lcd_reg_out(lcd_rw);
|
||||
sys_lcd_rs <= lcd_reg_out(lcd_rs);
|
||||
rom_addr <= cpu_addr(5 downto 0);
|
||||
reg_addr <= cpu_addr(5 downto 0);
|
||||
|
||||
BUFG_inst : BUFG
|
||||
port map (
|
||||
O => clk, -- Clock buffer output
|
||||
I => clk0 -- Clock buffer input
|
||||
);
|
||||
|
||||
clock_halbe:
|
||||
process(sys_rst_n_in, sys_clk_in)
|
||||
variable reset_latency : integer range 0 to 999 := 999;
|
||||
begin
|
||||
if sys_rst_n_in = '0' then
|
||||
-- clk0 <= '0';
|
||||
rst <= '1';
|
||||
reset_latency := 999;
|
||||
elsif rising_edge(sys_clk_in) then
|
||||
rst <= '1';
|
||||
-- clk0 <= not clk0;
|
||||
if reset_latency /= 0 then
|
||||
reset_latency := reset_latency - 1;
|
||||
else
|
||||
rst <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
timer:
|
||||
process(rst, clk, timer_count, timer_en)
|
||||
begin
|
||||
if rst = '1' then
|
||||
timer_count <= timer_reload;
|
||||
timer_pulse <= '0';
|
||||
elsif rising_edge(clk) then
|
||||
timer_pulse <= '0';
|
||||
if timer_count /= 0 then
|
||||
if timer_en = '1' then
|
||||
timer_count <= timer_count - 1;
|
||||
end if;
|
||||
else
|
||||
timer_pulse <= '1';
|
||||
timer_count <= timer_reload;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
reg_mux:
|
||||
process(clk, reg_addr, reg_sel, cpu_we, cpu_re, sys_btn, sys_dip, lcd_reg_in, led_reg, uart_status_port)
|
||||
variable data : data_t;
|
||||
begin
|
||||
led_reg_we <= '0';
|
||||
lcd_reg_we <= '0';
|
||||
ctrl_reg_we <= '0';
|
||||
write_to_uart <= '0';
|
||||
read_from_uart <= '0';
|
||||
data := (others => '-');
|
||||
|
||||
if reg_sel = '1' then
|
||||
case reg_addr(2 downto 0) is
|
||||
|
||||
when "000" => -- C0
|
||||
data := "0000" & unsigned(sys_btn(3 downto 0));
|
||||
when "001" => -- C1
|
||||
data := led_reg;
|
||||
led_reg_we <= cpu_we;
|
||||
when "010" => -- C2
|
||||
data := unsigned(rx_data);
|
||||
write_to_uart <= cpu_we;
|
||||
read_from_uart <= cpu_re;
|
||||
when "011" => -- C3
|
||||
data := lcd_reg_in;
|
||||
lcd_reg_we <= cpu_we;
|
||||
when "100" => -- C4
|
||||
data := ctrl_reg;
|
||||
ctrl_reg_we <= cpu_we;
|
||||
when "101" => -- C5
|
||||
data := unsigned(sys_dip);
|
||||
when "110" => -- C6
|
||||
data := uart_status_port;
|
||||
when others => null;
|
||||
end case;
|
||||
|
||||
end if;
|
||||
|
||||
if rising_edge(clk) then
|
||||
reg_dout <= data;
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
din_mux:
|
||||
process(clk, cpu_addr, cpu_we, rom_dout, reg_dout)
|
||||
variable data : data_t;
|
||||
begin
|
||||
reg_sel <= '0';
|
||||
|
||||
case cpu_addr(7 downto 6) is
|
||||
when "00" | "01" => -- 00 .. 7F
|
||||
data := X"AA";
|
||||
when "10" => -- 80 .. BF
|
||||
data := rom_dout;
|
||||
when "11" => -- C0 .. FF
|
||||
data := reg_dout;
|
||||
reg_sel <= '1';
|
||||
|
||||
when others =>
|
||||
data := (others => '-');
|
||||
end case;
|
||||
|
||||
cpu_din <= data;
|
||||
|
||||
end process;
|
||||
|
||||
ctrl_reg_write:
|
||||
process(rst, clk, ctrl_reg_we, cpu_dout)
|
||||
begin
|
||||
if (rst = '1') then
|
||||
ctrl_reg <= (others => '0');
|
||||
elsif rising_edge(clk) then
|
||||
if ctrl_reg_we = '1' then
|
||||
ctrl_reg <= cpu_dout;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
led_reg_write:
|
||||
process(rst, clk, led_reg_we, cpu_dout)
|
||||
begin
|
||||
if (rst = '1') then
|
||||
led_reg <= (others => '0');
|
||||
elsif rising_edge(clk) then
|
||||
if led_reg_we = '1' then
|
||||
led_reg <= cpu_dout;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_lcd_reg_write:
|
||||
process(rst, clk, lcd_reg_we, cpu_dout)
|
||||
begin
|
||||
if (rst = '1') then
|
||||
lcd_reg_out <= (others => '0');
|
||||
elsif rising_edge(clk) then
|
||||
if lcd_reg_we = '1' then
|
||||
lcd_reg_out <= cpu_dout;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_lcd_reg_sample:
|
||||
process(rst, clk, sys_lcd_d, lcd_reg_out)
|
||||
begin
|
||||
if (rst = '1') then
|
||||
lcd_reg_in <= (others => '0');
|
||||
elsif rising_edge(clk) then
|
||||
if lcd_reg_out(lcd_rw) = '1' then
|
||||
lcd_reg_in <= unsigned("0000" & sys_lcd_d);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
int_register:
|
||||
process(rst, clk, int_in, int_ack)
|
||||
begin
|
||||
if (rst = '1') then
|
||||
int_req <= '0';
|
||||
elsif rising_edge(clk) then
|
||||
if int_ack = '1' then
|
||||
int_req <= '0';
|
||||
elsif int_en = '1' and int_in = '1' then
|
||||
int_req <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
the_embedded_cpu: embedded_cpu
|
||||
PORT MAP(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
ce => ce,
|
||||
int_in => int_req,
|
||||
int_ack => int_ack,
|
||||
xmem_we => cpu_we,
|
||||
xmem_re => cpu_re,
|
||||
xmem_din => cpu_din,
|
||||
xmem_dout => cpu_dout,
|
||||
xmem_addr => cpu_addr
|
||||
);
|
||||
|
||||
transmit: uart_tx
|
||||
port map ( data_in => std_logic_vector(cpu_dout),
|
||||
write_buffer => write_to_uart,
|
||||
reset_buffer => rst,
|
||||
en_16_x_baud => en_16_x_baud,
|
||||
serial_out => sys_tx,
|
||||
buffer_full => tx_full,
|
||||
buffer_half_full => tx_half_full,
|
||||
clk => clk );
|
||||
|
||||
receive: uart_rx
|
||||
port map ( serial_in => sys_rx,
|
||||
data_out => rx_data,
|
||||
read_buffer => read_from_uart,
|
||||
reset_buffer => rst,
|
||||
en_16_x_baud => en_16_x_baud,
|
||||
buffer_data_present => rx_data_present,
|
||||
buffer_full => rx_full,
|
||||
buffer_half_full => rx_half_full,
|
||||
clk => clk );
|
||||
--
|
||||
-- Set baud rate to 38400 for the UART communications
|
||||
-- Requires en_16_x_baud to be 614400Hz which is a single cycle pulse every 163 cycles at 100MHz
|
||||
--
|
||||
-- NOTE : If the highest value for baud_count exceeds 127 you will need to adjust
|
||||
-- the range of integers in the signal declaration for baud_count.
|
||||
--
|
||||
|
||||
baud_timer: process(clk)
|
||||
begin
|
||||
if clk'event and clk='1' then
|
||||
if baud_count=162 then
|
||||
baud_count <= 0;
|
||||
en_16_x_baud <= '1';
|
||||
else
|
||||
baud_count <= baud_count + 1;
|
||||
en_16_x_baud <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process baud_timer;
|
||||
|
||||
ROM_RD:
|
||||
process(rst, clk, rom_addr)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
rom_dout <= to_unsigned(character'pos(rom_data(to_integer(rom_addr)+1)), data_t'length);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
END;
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,19 @@
|
||||
library IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
configuration cpu_irom of cpu_embedded is
|
||||
for rtl
|
||||
for inst_irom : irom
|
||||
use entity work.irom(loadable);
|
||||
end for;
|
||||
end for;
|
||||
end configuration cpu_irom;
|
||||
|
||||
configuration system_xrom of systest is
|
||||
for behavior
|
||||
for inst_xrom : xrom
|
||||
use entity work.xrom(loadable);
|
||||
end for;
|
||||
end for;
|
||||
end configuration system_xrom;
|
||||
@@ -0,0 +1,166 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: testbench for system test using Xilinx ML-402
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
use std.textio.all; -- Imports the standard textio package.
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
use work.ddr_sdr_conf_pkg.all;
|
||||
use work.systest_cfg.all;
|
||||
|
||||
ENTITY tb_systest IS
|
||||
END tb_systest;
|
||||
|
||||
ARCHITECTURE behavior OF tb_systest IS
|
||||
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
signal sys_rst_n_in : std_logic := '0';
|
||||
signal sys_clk_in : std_logic := '1';
|
||||
signal dip : unsigned(7 downto 0) := (others => '0');
|
||||
signal btn : unsigned(4 downto 0) := (others => '0');
|
||||
signal led : unsigned(8 downto 0);
|
||||
signal sys_rx : std_logic := '0';
|
||||
signal sys_tx : std_logic;
|
||||
|
||||
signal sys_lcd_d : unsigned(3 downto 0);
|
||||
signal sys_lcd_e : std_logic;
|
||||
signal sys_lcd_rs : std_logic;
|
||||
signal sys_lcd_rw : std_logic;
|
||||
|
||||
signal refresh : boolean:= true;
|
||||
|
||||
signal sys_sdr_clk_p : std_logic; -- ddr_sdram_clock
|
||||
signal sys_sdr_clk_n : std_logic; -- /ddr_sdram_clock
|
||||
signal sys_sdr_cke_q : std_logic; -- clock enable
|
||||
signal sys_sdr_cs_qn : std_logic; -- /chip select
|
||||
signal sys_sdr_ras_qn : std_logic; -- /ras
|
||||
signal sys_sdr_cas_qn : std_logic; -- /cas
|
||||
signal sys_sdr_we_qn : std_logic; -- /write enable
|
||||
signal sys_sdr_dm_q : unsigned(DDR_DM_WIDTH-1 downto 0); -- data mask bits, set to "00"
|
||||
signal sys_sdr_dqs_q : unsigned(DDR_DQS_WIDTH-1 downto 0); -- data strobe, only for write
|
||||
signal sys_sdr_ba_q : unsigned(DDR_BANK_WIDTH-1 downto 0); -- bank select
|
||||
signal sys_sdr_a_q : unsigned(DDR_ADDR_WIDTH-1 downto 0); -- address bus
|
||||
signal sys_sdr_data : unsigned(DDR_DATA_WIDTH-1 downto 0); -- bidir data bus
|
||||
|
||||
signal sys_error : unsigned(1 downto 0); -- indicates DCM Errors
|
||||
signal sys_sdr_clk_fb : std_logic;
|
||||
|
||||
BEGIN
|
||||
|
||||
uut: entity work.systest
|
||||
-- GENERIC MAP
|
||||
-- (
|
||||
-- ddr_phaseshift => 90,
|
||||
-- ddr_frequency_hz => 100E6
|
||||
-- )
|
||||
PORT MAP
|
||||
(
|
||||
sys_rst_n_in => sys_rst_n_in,
|
||||
sys_clk_in => sys_clk_in,
|
||||
sys_btn => btn,
|
||||
sys_dip => dip,
|
||||
sys_led => led,
|
||||
sys_rx => sys_rx,
|
||||
sys_tx => sys_tx,
|
||||
sys_lcd_d => sys_lcd_d,
|
||||
sys_lcd_e => sys_lcd_e,
|
||||
sys_lcd_rs => sys_lcd_rs,
|
||||
sys_lcd_rw => sys_lcd_rw,
|
||||
|
||||
sys_sdr_clk_p => sys_sdr_clk_p,
|
||||
sys_sdr_clk_n => sys_sdr_clk_n,
|
||||
sys_sdr_cke_q => sys_sdr_cke_q,
|
||||
sys_sdr_clk_fb => sys_sdr_clk_fb,
|
||||
sys_sdr_cs_qn => sys_sdr_cs_qn,
|
||||
sys_sdr_ras_qn => sys_sdr_ras_qn,
|
||||
sys_sdr_cas_qn => sys_sdr_cas_qn,
|
||||
sys_sdr_we_qn => sys_sdr_we_qn,
|
||||
sys_sdr_dm_q => sys_sdr_dm_q,
|
||||
sys_sdr_dqs_q => sys_sdr_dqs_q,
|
||||
sys_sdr_ba_q => sys_sdr_ba_q,
|
||||
sys_sdr_a_q => sys_sdr_a_q,
|
||||
sys_sdr_data => sys_sdr_data,
|
||||
sys_error => sys_error
|
||||
);
|
||||
|
||||
-- MICRON DDR SDRAM Simulation Model
|
||||
i_mt46v16m16_0 : entity work.mt46v16m16
|
||||
port map (
|
||||
dq => std_logic_vector(sys_sdr_data(15 downto 0)),
|
||||
dqs => std_logic_vector(sys_sdr_dqs_q(1 downto 0)),
|
||||
addr => std_logic_vector(sys_sdr_a_q),
|
||||
ba => std_logic_vector(sys_sdr_ba_q),
|
||||
clk => sys_sdr_clk_p,
|
||||
clk_n => sys_sdr_clk_n,
|
||||
cke => sys_sdr_cke_q,
|
||||
cs_n => sys_sdr_cs_qn,
|
||||
ras_n => sys_sdr_ras_qn,
|
||||
cas_n => sys_sdr_cas_qn,
|
||||
we_n => sys_sdr_we_qn,
|
||||
dm => std_logic_vector(sys_sdr_dm_q(1 downto 0))
|
||||
);
|
||||
|
||||
-- MICRON DDR SDRAM Simulation Model
|
||||
i_mt46v16m16_1 : entity work.mt46v16m16
|
||||
port map (
|
||||
dq => std_logic_vector(sys_sdr_data(31 downto 16)),
|
||||
dqs => std_logic_vector(sys_sdr_dqs_q(3 downto 2)),
|
||||
addr => std_logic_vector(sys_sdr_a_q),
|
||||
ba => std_logic_vector(sys_sdr_ba_q),
|
||||
clk => sys_sdr_clk_p,
|
||||
clk_n => sys_sdr_clk_n,
|
||||
cke => sys_sdr_cke_q,
|
||||
cs_n => sys_sdr_cs_qn,
|
||||
ras_n => sys_sdr_ras_qn,
|
||||
cas_n => sys_sdr_cas_qn,
|
||||
we_n => sys_sdr_we_qn,
|
||||
dm => std_logic_vector(sys_sdr_dm_q(3 downto 2))
|
||||
);
|
||||
|
||||
sys_sdr_clk_fb <= sys_sdr_clk_p after 2300 ps;
|
||||
refresh <= true when falling_edge(sys_sdr_ras_qn) and falling_edge(sys_sdr_cas_qn) and sys_sdr_we_qn='1' else false;
|
||||
|
||||
CLK_GEN: process
|
||||
begin
|
||||
wait for CLK_PERIOD/2;
|
||||
sys_clk_in <= not sys_clk_in;
|
||||
end process;
|
||||
|
||||
STIMULUS: process
|
||||
|
||||
begin
|
||||
|
||||
wait for 3*CLK_PERIOD;
|
||||
sys_rst_n_in <= '1';
|
||||
wait for 2*CLK_PERIOD;
|
||||
|
||||
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
END;
|
||||
@@ -0,0 +1,786 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
ENTITY irom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in inst_addr_t;
|
||||
dout : out inst_t
|
||||
);
|
||||
END irom;
|
||||
|
||||
ARCHITECTURE vga_test OF irom IS
|
||||
|
||||
type imem_rom_t is array (0 to 724) of inst_t;
|
||||
|
||||
-- Assembled from vga_test.jsm
|
||||
constant imem_rom : imem_rom_t :=
|
||||
(
|
||||
"110000" & X"02D", -- 0x000: JMP 0x02D
|
||||
"111100" & X"000", -- 0x001: PUSH R00
|
||||
"111100" & X"001", -- 0x002: PUSH R01
|
||||
"101000" & X"061", -- 0x003: XIN R01, (0x06)
|
||||
"011001" & X"101", -- 0x004: AND R01, 0x10
|
||||
"110001" & X"015", -- 0x005: JZ 0x015
|
||||
"101000" & X"020", -- 0x006: XIN R00, (0x02)
|
||||
"001010" & X"5F1", -- 0x007: MOVC R01, (0x5F)
|
||||
"001011" & X"010", -- 0x008: MOVC (R00), R01
|
||||
"010001" & X"011", -- 0x009: INC R01
|
||||
"001111" & X"5E1", -- 0x00A: CMP R01, 0x5E
|
||||
"111010" & X"00D", -- 0x00B: JNE 0x00D
|
||||
"000011" & X"1E1", -- 0x00C: MOV R01, 0x1E
|
||||
"001101" & X"5F1", -- 0x00D: MOVC (0x5F), R01
|
||||
"001010" & X"5E0", -- 0x00E: MOVC R00, (0x5E)
|
||||
"001110" & X"010", -- 0x00F: CMP R00, R01
|
||||
"111010" & X"003", -- 0x010: JNE 0x003
|
||||
"101000" & X"040", -- 0x011: XIN R00, (0x04)
|
||||
"011011" & X"200", -- 0x012: OR R00, 0x20
|
||||
"100100" & X"040", -- 0x013: XOUT (0x04), R00
|
||||
"110000" & X"003", -- 0x014: JMP 0x003
|
||||
"111011" & X"019", -- 0x015: CALL 0x019
|
||||
"111101" & X"001", -- 0x016: POP R01
|
||||
"111101" & X"000", -- 0x017: POP R00
|
||||
"111111" & X"000", -- 0x018: RETI
|
||||
"101000" & X"000", -- 0x019: XIN R00, (0x00)
|
||||
"011001" & X"010", -- 0x01A: AND R00, 0x01
|
||||
"110001" & X"023", -- 0x01B: JZ 0x023
|
||||
"000011" & X"140", -- 0x01C: MOV R00, 0x14
|
||||
"100101" & X"000", -- 0x01D: XOUT (R00), 0x00
|
||||
"010001" & X"010", -- 0x01E: INC R00
|
||||
"100101" & X"000", -- 0x01F: XOUT (R00), 0x00
|
||||
"010001" & X"010", -- 0x020: INC R00
|
||||
"100101" & X"000", -- 0x021: XOUT (R00), 0x00
|
||||
"110000" & X"02C", -- 0x022: JMP 0x02C
|
||||
"101000" & X"000", -- 0x023: XIN R00, (0x00)
|
||||
"011001" & X"020", -- 0x024: AND R00, 0x02
|
||||
"110001" & X"02C", -- 0x025: JZ 0x02C
|
||||
"000011" & X"140", -- 0x026: MOV R00, 0x14
|
||||
"100101" & X"000", -- 0x027: XOUT (R00), 0x00
|
||||
"010001" & X"010", -- 0x028: INC R00
|
||||
"100101" & X"000", -- 0x029: XOUT (R00), 0x00
|
||||
"010001" & X"010", -- 0x02A: INC R00
|
||||
"100101" & X"200", -- 0x02B: XOUT (R00), 0x20
|
||||
"111110" & X"000", -- 0x02C: RET
|
||||
"111011" & X"1C6", -- 0x02D: CALL 0x1C6
|
||||
"111011" & X"1FB", -- 0x02E: CALL 0x1FB
|
||||
"000011" & X"000", -- 0x02F: MOV R00, 0x00
|
||||
"100100" & X"010", -- 0x030: XOUT (0x01), R00
|
||||
"000011" & X"040", -- 0x031: MOV R00, 0x04
|
||||
"100100" & X"040", -- 0x032: XOUT (0x04), R00
|
||||
"101000" & X"040", -- 0x033: XIN R00, (0x04)
|
||||
"011011" & X"020", -- 0x034: OR R00, 0x02
|
||||
"100100" & X"040", -- 0x035: XOUT (0x04), R00
|
||||
"000011" & X"030", -- 0x036: MOV R00, 0x03
|
||||
"100110" & X"030", -- 0x037: COUT (0x03), R00
|
||||
"000011" & X"010", -- 0x038: MOV R00, 0x01
|
||||
"111011" & X"218", -- 0x039: CALL 0x218
|
||||
"000011" & X"000", -- 0x03A: MOV R00, 0x00
|
||||
"000011" & X"C01", -- 0x03B: MOV R01, 0xC0
|
||||
"100100" & X"101", -- 0x03C: XOUT (0x10), R01
|
||||
"100100" & X"111", -- 0x03D: XOUT (0x11), R01
|
||||
"100100" & X"121", -- 0x03E: XOUT (0x12), R01
|
||||
"111011" & X"28C", -- 0x03F: CALL 0x28C
|
||||
"111011" & X"271", -- 0x040: CALL 0x271
|
||||
"000011" & X"031", -- 0x041: MOV R01, 0x03
|
||||
"111011" & X"21D", -- 0x042: CALL 0x21D
|
||||
"000011" & X"031", -- 0x043: MOV R01, 0x03
|
||||
"111011" & X"27D", -- 0x044: CALL 0x27D
|
||||
"000011" & X"001", -- 0x045: MOV R01, 0x00
|
||||
"111011" & X"289", -- 0x046: CALL 0x289
|
||||
"101000" & X"040", -- 0x047: XIN R00, (0x04)
|
||||
"011001" & X"CF0", -- 0x048: AND R00, 0xCF
|
||||
"100100" & X"040", -- 0x049: XOUT (0x04), R00
|
||||
"000011" & X"000", -- 0x04A: MOV R00, 0x00
|
||||
"001101" & X"010", -- 0x04B: MOVC (0x01), R00
|
||||
"111011" & X"080", -- 0x04C: CALL 0x080
|
||||
"111011" & X"0D9", -- 0x04D: CALL 0x0D9
|
||||
"111011" & X"10D", -- 0x04E: CALL 0x10D
|
||||
"001010" & X"010", -- 0x04F: MOVC R00, (0x01)
|
||||
"010001" & X"010", -- 0x050: INC R00
|
||||
"001101" & X"010", -- 0x051: MOVC (0x01), R00
|
||||
"110000" & X"04D", -- 0x052: JMP 0x04D
|
||||
"000011" & X"010", -- 0x053: MOV R00, 0x01
|
||||
"111011" & X"218", -- 0x054: CALL 0x218
|
||||
"000011" & X"0E1", -- 0x055: MOV R01, 0x0E
|
||||
"111011" & X"21D", -- 0x056: CALL 0x21D
|
||||
"000011" & X"0E1", -- 0x057: MOV R01, 0x0E
|
||||
"111011" & X"286", -- 0x058: CALL 0x286
|
||||
"000011" & X"001", -- 0x059: MOV R01, 0x00
|
||||
"111011" & X"289", -- 0x05A: CALL 0x289
|
||||
"000011" & X"000", -- 0x05B: MOV R00, 0x00
|
||||
"000011" & X"001", -- 0x05C: MOV R01, 0x00
|
||||
"000011" & X"002", -- 0x05D: MOV R02, 0x00
|
||||
"111011" & X"16A", -- 0x05E: CALL 0x16A
|
||||
"000011" & X"800", -- 0x05F: MOV R00, 0x80
|
||||
"000011" & X"08F", -- 0x060: MOV R15, 0x08
|
||||
"000111" & X"000", -- 0x061: MOVX (R00), 0x00
|
||||
"010001" & X"010", -- 0x062: INC R00
|
||||
"010101" & X"01F", -- 0x063: DEC R15
|
||||
"110010" & X"061", -- 0x064: JNZ 0x061
|
||||
"000011" & X"082", -- 0x065: MOV R02, 0x08
|
||||
"101000" & X"070", -- 0x066: XIN R00, (0x07)
|
||||
"100100" & X"010", -- 0x067: XOUT (0x01), R00
|
||||
"011001" & X"040", -- 0x068: AND R00, 0x04
|
||||
"110010" & X"066", -- 0x069: JNZ 0x066
|
||||
"000011" & X"100", -- 0x06A: MOV R00, 0x10
|
||||
"100100" & X"070", -- 0x06B: XOUT (0x07), R00
|
||||
"010101" & X"022", -- 0x06C: SUB R02, 0x02
|
||||
"110010" & X"066", -- 0x06D: JNZ 0x066
|
||||
"111011" & X"147", -- 0x06E: CALL 0x147
|
||||
"000011" & X"060", -- 0x06F: MOV R00, 0x06
|
||||
"100100" & X"070", -- 0x070: XOUT (0x07), R00
|
||||
"101000" & X"080", -- 0x071: XIN R00, (0x08)
|
||||
"001111" & X"F80", -- 0x072: CMP R00, 0xF8
|
||||
"111010" & X"07A", -- 0x073: JNE 0x07A
|
||||
"101000" & X"090", -- 0x074: XIN R00, (0x09)
|
||||
"001111" & X"FF0", -- 0x075: CMP R00, 0xFF
|
||||
"111010" & X"07A", -- 0x076: JNE 0x07A
|
||||
"101000" & X"0A0", -- 0x077: XIN R00, (0x0A)
|
||||
"001111" & X"FF0", -- 0x078: CMP R00, 0xFF
|
||||
"111001" & X"07D", -- 0x079: JEQ 0x07D
|
||||
"000011" & X"080", -- 0x07A: MOV R00, 0x08
|
||||
"111011" & X"16E", -- 0x07B: CALL 0x16E
|
||||
"110000" & X"065", -- 0x07C: JMP 0x065
|
||||
"111011" & X"18E", -- 0x07D: CALL 0x18E
|
||||
"111011" & X"292", -- 0x07E: CALL 0x292
|
||||
"111110" & X"000", -- 0x07F: RET
|
||||
"000011" & X"010", -- 0x080: MOV R00, 0x01
|
||||
"111011" & X"218", -- 0x081: CALL 0x218
|
||||
"000011" & X"391", -- 0x082: MOV R01, 0x39
|
||||
"111011" & X"21D", -- 0x083: CALL 0x21D
|
||||
"000011" & X"391", -- 0x084: MOV R01, 0x39
|
||||
"111011" & X"286", -- 0x085: CALL 0x286
|
||||
"000011" & X"001", -- 0x086: MOV R01, 0x00
|
||||
"111011" & X"289", -- 0x087: CALL 0x289
|
||||
"000011" & X"F80", -- 0x088: MOV R00, 0xF8
|
||||
"000011" & X"FF1", -- 0x089: MOV R01, 0xFF
|
||||
"000011" & X"132", -- 0x08A: MOV R02, 0x13
|
||||
"111011" & X"16A", -- 0x08B: CALL 0x16A
|
||||
"000011" & X"00F", -- 0x08C: MOV R15, 0x00
|
||||
"111011" & X"1D2", -- 0x08D: CALL 0x1D2
|
||||
"110011" & X"080", -- 0x08E: JC 0x080
|
||||
"010001" & X"01F", -- 0x08F: INC R15
|
||||
"001111" & X"0AF", -- 0x090: CMP R15, 0x0A
|
||||
"111010" & X"08D", -- 0x091: JNE 0x08D
|
||||
"111011" & X"1D2", -- 0x092: CALL 0x1D2
|
||||
"110011" & X"080", -- 0x093: JC 0x080
|
||||
"010001" & X"01F", -- 0x094: INC R15
|
||||
"001101" & X"020", -- 0x095: MOVC (0x02), R00
|
||||
"111011" & X"1D2", -- 0x096: CALL 0x1D2
|
||||
"110011" & X"080", -- 0x097: JC 0x080
|
||||
"010001" & X"01F", -- 0x098: INC R15
|
||||
"001101" & X"030", -- 0x099: MOVC (0x03), R00
|
||||
"111011" & X"1D2", -- 0x09A: CALL 0x1D2
|
||||
"110011" & X"080", -- 0x09B: JC 0x080
|
||||
"010001" & X"01F", -- 0x09C: INC R15
|
||||
"001101" & X"040", -- 0x09D: MOVC (0x04), R00
|
||||
"111011" & X"1D2", -- 0x09E: CALL 0x1D2
|
||||
"110011" & X"080", -- 0x09F: JC 0x080
|
||||
"010001" & X"01F", -- 0x0A0: INC R15
|
||||
"001101" & X"050", -- 0x0A1: MOVC (0x05), R00
|
||||
"001010" & X"021", -- 0x0A2: MOVC R01, (0x02)
|
||||
"111011" & X"1D2", -- 0x0A3: CALL 0x1D2
|
||||
"110011" & X"080", -- 0x0A4: JC 0x080
|
||||
"010001" & X"01F", -- 0x0A5: INC R15
|
||||
"001110" & X"01F", -- 0x0A6: CMP R15, R01
|
||||
"111010" & X"0A3", -- 0x0A7: JNE 0x0A3
|
||||
"000011" & X"08F", -- 0x0A8: MOV R15, 0x08
|
||||
"000011" & X"1D1", -- 0x0A9: MOV R01, 0x1D
|
||||
"000011" & X"032", -- 0x0AA: MOV R02, 0x03
|
||||
"010101" & X"012", -- 0x0AB: DEC R02
|
||||
"000010" & X"013", -- 0x0AC: MOV R03, R01
|
||||
"111011" & X"1D2", -- 0x0AD: CALL 0x1D2
|
||||
"110011" & X"0D7", -- 0x0AE: JC 0x0D7
|
||||
"010100" & X"023", -- 0x0AF: SUB R03, R02
|
||||
"001011" & X"030", -- 0x0B0: MOVC (R00), R03
|
||||
"001111" & X"002", -- 0x0B1: TST R02
|
||||
"110010" & X"0AB", -- 0x0B2: JNZ 0x0AB
|
||||
"010101" & X"031", -- 0x0B3: SUB R01, 0x03
|
||||
"010101" & X"01F", -- 0x0B4: DEC R15
|
||||
"110010" & X"0AA", -- 0x0B5: JNZ 0x0AA
|
||||
"000011" & X"082", -- 0x0B6: MOV R02, 0x08
|
||||
"000011" & X"061", -- 0x0B7: MOV R01, 0x06
|
||||
"000011" & X"803", -- 0x0B8: MOV R03, 0x80
|
||||
"001001" & X"010", -- 0x0B9: MOVC R00, (R01)
|
||||
"000110" & X"030", -- 0x0BA: MOVX (R00), R03
|
||||
"010001" & X"011", -- 0x0BB: INC R01
|
||||
"010001" & X"013", -- 0x0BC: INC R03
|
||||
"001111" & X"863", -- 0x0BD: CMP R03, 0x86
|
||||
"111010" & X"0B9", -- 0x0BE: JNE 0x0B9
|
||||
"101000" & X"070", -- 0x0BF: XIN R00, (0x07)
|
||||
"100100" & X"010", -- 0x0C0: XOUT (0x01), R00
|
||||
"011001" & X"040", -- 0x0C1: AND R00, 0x04
|
||||
"110010" & X"0BF", -- 0x0C2: JNZ 0x0BF
|
||||
"000011" & X"100", -- 0x0C3: MOV R00, 0x10
|
||||
"100100" & X"070", -- 0x0C4: XOUT (0x07), R00
|
||||
"010101" & X"022", -- 0x0C5: SUB R02, 0x02
|
||||
"110010" & X"0B8", -- 0x0C6: JNZ 0x0B8
|
||||
"111011" & X"147", -- 0x0C7: CALL 0x147
|
||||
"000011" & X"060", -- 0x0C8: MOV R00, 0x06
|
||||
"100100" & X"070", -- 0x0C9: XOUT (0x07), R00
|
||||
"111011" & X"18E", -- 0x0CA: CALL 0x18E
|
||||
"101000" & X"080", -- 0x0CB: XIN R00, (0x08)
|
||||
"001111" & X"000", -- 0x0CC: TST R00
|
||||
"110010" & X"0D4", -- 0x0CD: JNZ 0x0D4
|
||||
"101000" & X"090", -- 0x0CE: XIN R00, (0x09)
|
||||
"001111" & X"000", -- 0x0CF: TST R00
|
||||
"110010" & X"0D4", -- 0x0D0: JNZ 0x0D4
|
||||
"101000" & X"0A0", -- 0x0D1: XIN R00, (0x0A)
|
||||
"001111" & X"000", -- 0x0D2: TST R00
|
||||
"110001" & X"0D7", -- 0x0D3: JZ 0x0D7
|
||||
"000011" & X"080", -- 0x0D4: MOV R00, 0x08
|
||||
"111011" & X"17E", -- 0x0D5: CALL 0x17E
|
||||
"110000" & X"0A8", -- 0x0D6: JMP 0x0A8
|
||||
"111011" & X"292", -- 0x0D7: CALL 0x292
|
||||
"111110" & X"000", -- 0x0D8: RET
|
||||
"000011" & X"010", -- 0x0D9: MOV R00, 0x01
|
||||
"111011" & X"218", -- 0x0DA: CALL 0x218
|
||||
"000011" & X"1D1", -- 0x0DB: MOV R01, 0x1D
|
||||
"111011" & X"21D", -- 0x0DC: CALL 0x21D
|
||||
"000011" & X"1D1", -- 0x0DD: MOV R01, 0x1D
|
||||
"111011" & X"286", -- 0x0DE: CALL 0x286
|
||||
"000011" & X"001", -- 0x0DF: MOV R01, 0x00
|
||||
"111011" & X"289", -- 0x0E0: CALL 0x289
|
||||
"000011" & X"000", -- 0x0E1: MOV R00, 0x00
|
||||
"000011" & X"001", -- 0x0E2: MOV R01, 0x00
|
||||
"000011" & X"202", -- 0x0E3: MOV R02, 0x20
|
||||
"111011" & X"16A", -- 0x0E4: CALL 0x16A
|
||||
"001010" & X"010", -- 0x0E5: MOVC R00, (0x01)
|
||||
"001101" & X"000", -- 0x0E6: MOVC (0x00), R00
|
||||
"000011" & X"082", -- 0x0E7: MOV R02, 0x08
|
||||
"001010" & X"001", -- 0x0E8: MOVC R01, (0x00)
|
||||
"000011" & X"800", -- 0x0E9: MOV R00, 0x80
|
||||
"000011" & X"08F", -- 0x0EA: MOV R15, 0x08
|
||||
"000110" & X"001", -- 0x0EB: MOVX (R01), R00
|
||||
"010001" & X"010", -- 0x0EC: INC R00
|
||||
"010001" & X"011", -- 0x0ED: INC R01
|
||||
"010101" & X"01F", -- 0x0EE: DEC R15
|
||||
"110010" & X"0EB", -- 0x0EF: JNZ 0x0EB
|
||||
"101000" & X"070", -- 0x0F0: XIN R00, (0x07)
|
||||
"100100" & X"010", -- 0x0F1: XOUT (0x01), R00
|
||||
"011001" & X"040", -- 0x0F2: AND R00, 0x04
|
||||
"110010" & X"0F0", -- 0x0F3: JNZ 0x0F0
|
||||
"000011" & X"100", -- 0x0F4: MOV R00, 0x10
|
||||
"100100" & X"070", -- 0x0F5: XOUT (0x07), R00
|
||||
"001010" & X"000", -- 0x0F6: MOVC R00, (0x00)
|
||||
"010001" & X"010", -- 0x0F7: INC R00
|
||||
"001101" & X"000", -- 0x0F8: MOVC (0x00), R00
|
||||
"010101" & X"022", -- 0x0F9: SUB R02, 0x02
|
||||
"110010" & X"0E8", -- 0x0FA: JNZ 0x0E8
|
||||
"111011" & X"147", -- 0x0FB: CALL 0x147
|
||||
"000011" & X"060", -- 0x0FC: MOV R00, 0x06
|
||||
"100100" & X"070", -- 0x0FD: XOUT (0x07), R00
|
||||
"101000" & X"080", -- 0x0FE: XIN R00, (0x08)
|
||||
"001111" & X"F80", -- 0x0FF: CMP R00, 0xF8
|
||||
"111010" & X"107", -- 0x100: JNE 0x107
|
||||
"101000" & X"090", -- 0x101: XIN R00, (0x09)
|
||||
"001111" & X"FF0", -- 0x102: CMP R00, 0xFF
|
||||
"111010" & X"107", -- 0x103: JNE 0x107
|
||||
"101000" & X"0A0", -- 0x104: XIN R00, (0x0A)
|
||||
"001111" & X"FF0", -- 0x105: CMP R00, 0xFF
|
||||
"111001" & X"10A", -- 0x106: JEQ 0x10A
|
||||
"000011" & X"080", -- 0x107: MOV R00, 0x08
|
||||
"111011" & X"16E", -- 0x108: CALL 0x16E
|
||||
"110000" & X"0E7", -- 0x109: JMP 0x0E7
|
||||
"111011" & X"18E", -- 0x10A: CALL 0x18E
|
||||
"111011" & X"292", -- 0x10B: CALL 0x292
|
||||
"111110" & X"000", -- 0x10C: RET
|
||||
"000011" & X"010", -- 0x10D: MOV R00, 0x01
|
||||
"111011" & X"218", -- 0x10E: CALL 0x218
|
||||
"000011" & X"2B1", -- 0x10F: MOV R01, 0x2B
|
||||
"111011" & X"21D", -- 0x110: CALL 0x21D
|
||||
"000011" & X"2B1", -- 0x111: MOV R01, 0x2B
|
||||
"111011" & X"286", -- 0x112: CALL 0x286
|
||||
"000011" & X"001", -- 0x113: MOV R01, 0x00
|
||||
"111011" & X"289", -- 0x114: CALL 0x289
|
||||
"000011" & X"000", -- 0x115: MOV R00, 0x00
|
||||
"000011" & X"001", -- 0x116: MOV R01, 0x00
|
||||
"000011" & X"202", -- 0x117: MOV R02, 0x20
|
||||
"111011" & X"16A", -- 0x118: CALL 0x16A
|
||||
"001010" & X"010", -- 0x119: MOVC R00, (0x01)
|
||||
"001101" & X"000", -- 0x11A: MOVC (0x00), R00
|
||||
"101000" & X"070", -- 0x11B: XIN R00, (0x07)
|
||||
"100100" & X"010", -- 0x11C: XOUT (0x01), R00
|
||||
"011001" & X"200", -- 0x11D: AND R00, 0x20
|
||||
"110010" & X"122", -- 0x11E: JNZ 0x122
|
||||
"000011" & X"200", -- 0x11F: MOV R00, 0x20
|
||||
"100100" & X"070", -- 0x120: XOUT (0x07), R00
|
||||
"110000" & X"11B", -- 0x121: JMP 0x11B
|
||||
"111011" & X"147", -- 0x122: CALL 0x147
|
||||
"000011" & X"050", -- 0x123: MOV R00, 0x05
|
||||
"100100" & X"070", -- 0x124: XOUT (0x07), R00
|
||||
"000011" & X"083", -- 0x125: MOV R03, 0x08
|
||||
"101000" & X"070", -- 0x126: XIN R00, (0x07)
|
||||
"100100" & X"010", -- 0x127: XOUT (0x01), R00
|
||||
"011001" & X"200", -- 0x128: AND R00, 0x20
|
||||
"110010" & X"126", -- 0x129: JNZ 0x126
|
||||
"001010" & X"001", -- 0x12A: MOVC R01, (0x00)
|
||||
"000011" & X"800", -- 0x12B: MOV R00, 0x80
|
||||
"000011" & X"08F", -- 0x12C: MOV R15, 0x08
|
||||
"000100" & X"002", -- 0x12D: MOVX R02, (R00)
|
||||
"001110" & X"012", -- 0x12E: CMP R02, R01
|
||||
"111010" & X"15A", -- 0x12F: JNE 0x15A
|
||||
"010001" & X"010", -- 0x130: INC R00
|
||||
"010001" & X"011", -- 0x131: INC R01
|
||||
"010101" & X"01F", -- 0x132: DEC R15
|
||||
"110010" & X"12D", -- 0x133: JNZ 0x12D
|
||||
"000011" & X"200", -- 0x134: MOV R00, 0x20
|
||||
"100100" & X"070", -- 0x135: XOUT (0x07), R00
|
||||
"001010" & X"000", -- 0x136: MOVC R00, (0x00)
|
||||
"010001" & X"010", -- 0x137: INC R00
|
||||
"001101" & X"000", -- 0x138: MOVC (0x00), R00
|
||||
"010101" & X"023", -- 0x139: SUB R03, 0x02
|
||||
"110010" & X"126", -- 0x13A: JNZ 0x126
|
||||
"101000" & X"080", -- 0x13B: XIN R00, (0x08)
|
||||
"001111" & X"F80", -- 0x13C: CMP R00, 0xF8
|
||||
"111010" & X"144", -- 0x13D: JNE 0x144
|
||||
"101000" & X"090", -- 0x13E: XIN R00, (0x09)
|
||||
"001111" & X"FF0", -- 0x13F: CMP R00, 0xFF
|
||||
"111010" & X"144", -- 0x140: JNE 0x144
|
||||
"101000" & X"0A0", -- 0x141: XIN R00, (0x0A)
|
||||
"001111" & X"FF0", -- 0x142: CMP R00, 0xFF
|
||||
"111001" & X"14E", -- 0x143: JEQ 0x14E
|
||||
"000011" & X"080", -- 0x144: MOV R00, 0x08
|
||||
"111011" & X"16E", -- 0x145: CALL 0x16E
|
||||
"110000" & X"122", -- 0x146: JMP 0x122
|
||||
"111100" & X"000", -- 0x147: PUSH R00
|
||||
"101000" & X"070", -- 0x148: XIN R00, (0x07)
|
||||
"100100" & X"010", -- 0x149: XOUT (0x01), R00
|
||||
"011001" & X"010", -- 0x14A: AND R00, 0x01
|
||||
"110010" & X"148", -- 0x14B: JNZ 0x148
|
||||
"111101" & X"000", -- 0x14C: POP R00
|
||||
"111110" & X"000", -- 0x14D: RET
|
||||
"000011" & X"010", -- 0x14E: MOV R00, 0x01
|
||||
"111011" & X"218", -- 0x14F: CALL 0x218
|
||||
"000011" & X"481", -- 0x150: MOV R01, 0x48
|
||||
"111011" & X"21D", -- 0x151: CALL 0x21D
|
||||
"000011" & X"C00", -- 0x152: MOV R00, 0xC0
|
||||
"111011" & X"218", -- 0x153: CALL 0x218
|
||||
"111011" & X"199", -- 0x154: CALL 0x199
|
||||
"000011" & X"481", -- 0x155: MOV R01, 0x48
|
||||
"111011" & X"286", -- 0x156: CALL 0x286
|
||||
"000011" & X"001", -- 0x157: MOV R01, 0x00
|
||||
"111011" & X"289", -- 0x158: CALL 0x289
|
||||
"110000" & X"168", -- 0x159: JMP 0x168
|
||||
"000011" & X"010", -- 0x15A: MOV R00, 0x01
|
||||
"111011" & X"218", -- 0x15B: CALL 0x218
|
||||
"000011" & X"521", -- 0x15C: MOV R01, 0x52
|
||||
"111011" & X"21D", -- 0x15D: CALL 0x21D
|
||||
"111011" & X"199", -- 0x15E: CALL 0x199
|
||||
"111011" & X"1B1", -- 0x15F: CALL 0x1B1
|
||||
"000011" & X"521", -- 0x160: MOV R01, 0x52
|
||||
"111011" & X"286", -- 0x161: CALL 0x286
|
||||
"000011" & X"001", -- 0x162: MOV R01, 0x00
|
||||
"111011" & X"289", -- 0x163: CALL 0x289
|
||||
"101000" & X"040", -- 0x164: XIN R00, (0x04)
|
||||
"011011" & X"100", -- 0x165: OR R00, 0x10
|
||||
"100100" & X"040", -- 0x166: XOUT (0x04), R00
|
||||
"110000" & X"168", -- 0x167: JMP 0x168
|
||||
"111011" & X"292", -- 0x168: CALL 0x292
|
||||
"111110" & X"000", -- 0x169: RET
|
||||
"100100" & X"080", -- 0x16A: XOUT (0x08), R00
|
||||
"100100" & X"091", -- 0x16B: XOUT (0x09), R01
|
||||
"100100" & X"0A2", -- 0x16C: XOUT (0x0A), R02
|
||||
"111110" & X"000", -- 0x16D: RET
|
||||
"111100" & X"001", -- 0x16E: PUSH R01
|
||||
"111100" & X"002", -- 0x16F: PUSH R02
|
||||
"111100" & X"003", -- 0x170: PUSH R03
|
||||
"101000" & X"081", -- 0x171: XIN R01, (0x08)
|
||||
"101000" & X"092", -- 0x172: XIN R02, (0x09)
|
||||
"101000" & X"0A3", -- 0x173: XIN R03, (0x0A)
|
||||
"010000" & X"001", -- 0x174: ADD R01, R00
|
||||
"010011" & X"002", -- 0x175: ADDC R02, 0x00
|
||||
"010011" & X"003", -- 0x176: ADDC R03, 0x00
|
||||
"100100" & X"081", -- 0x177: XOUT (0x08), R01
|
||||
"100100" & X"092", -- 0x178: XOUT (0x09), R02
|
||||
"100100" & X"0A3", -- 0x179: XOUT (0x0A), R03
|
||||
"111101" & X"003", -- 0x17A: POP R03
|
||||
"111101" & X"002", -- 0x17B: POP R02
|
||||
"111101" & X"001", -- 0x17C: POP R01
|
||||
"111110" & X"000", -- 0x17D: RET
|
||||
"111100" & X"001", -- 0x17E: PUSH R01
|
||||
"111100" & X"002", -- 0x17F: PUSH R02
|
||||
"111100" & X"003", -- 0x180: PUSH R03
|
||||
"101000" & X"081", -- 0x181: XIN R01, (0x08)
|
||||
"101000" & X"092", -- 0x182: XIN R02, (0x09)
|
||||
"101000" & X"0A3", -- 0x183: XIN R03, (0x0A)
|
||||
"010100" & X"001", -- 0x184: SUB R01, R00
|
||||
"010111" & X"002", -- 0x185: SUBC R02, 0x00
|
||||
"010111" & X"003", -- 0x186: SUBC R03, 0x00
|
||||
"100100" & X"081", -- 0x187: XOUT (0x08), R01
|
||||
"100100" & X"092", -- 0x188: XOUT (0x09), R02
|
||||
"100100" & X"0A3", -- 0x189: XOUT (0x0A), R03
|
||||
"111101" & X"003", -- 0x18A: POP R03
|
||||
"111101" & X"002", -- 0x18B: POP R02
|
||||
"111101" & X"001", -- 0x18C: POP R01
|
||||
"111110" & X"000", -- 0x18D: RET
|
||||
"000011" & X"C00", -- 0x18E: MOV R00, 0xC0
|
||||
"111011" & X"218", -- 0x18F: CALL 0x218
|
||||
"111011" & X"199", -- 0x190: CALL 0x199
|
||||
"111110" & X"000", -- 0x191: RET
|
||||
"111100" & X"001", -- 0x192: PUSH R01
|
||||
"111011" & X"1F4", -- 0x193: CALL 0x1F4
|
||||
"111011" & X"22F", -- 0x194: CALL 0x22F
|
||||
"000010" & X"010", -- 0x195: MOV R00, R01
|
||||
"111011" & X"22F", -- 0x196: CALL 0x22F
|
||||
"111101" & X"001", -- 0x197: POP R01
|
||||
"111110" & X"000", -- 0x198: RET
|
||||
"111100" & X"000", -- 0x199: PUSH R00
|
||||
"101000" & X"0A0", -- 0x19A: XIN R00, (0x0A)
|
||||
"111011" & X"192", -- 0x19B: CALL 0x192
|
||||
"101000" & X"090", -- 0x19C: XIN R00, (0x09)
|
||||
"111011" & X"192", -- 0x19D: CALL 0x192
|
||||
"101000" & X"080", -- 0x19E: XIN R00, (0x08)
|
||||
"111011" & X"192", -- 0x19F: CALL 0x192
|
||||
"111101" & X"000", -- 0x1A0: POP R00
|
||||
"111110" & X"000", -- 0x1A1: RET
|
||||
"111100" & X"000", -- 0x1A2: PUSH R00
|
||||
"010001" & X"031", -- 0x1A3: ADD R01, 0x03
|
||||
"001001" & X"010", -- 0x1A4: MOVC R00, (R01)
|
||||
"111011" & X"192", -- 0x1A5: CALL 0x192
|
||||
"010101" & X"011", -- 0x1A6: DEC R01
|
||||
"001001" & X"010", -- 0x1A7: MOVC R00, (R01)
|
||||
"111011" & X"192", -- 0x1A8: CALL 0x192
|
||||
"010101" & X"011", -- 0x1A9: DEC R01
|
||||
"001001" & X"010", -- 0x1AA: MOVC R00, (R01)
|
||||
"111011" & X"192", -- 0x1AB: CALL 0x192
|
||||
"010101" & X"011", -- 0x1AC: DEC R01
|
||||
"001001" & X"010", -- 0x1AD: MOVC R00, (R01)
|
||||
"111011" & X"192", -- 0x1AE: CALL 0x192
|
||||
"111101" & X"000", -- 0x1AF: POP R00
|
||||
"111110" & X"000", -- 0x1B0: RET
|
||||
"111100" & X"000", -- 0x1B1: PUSH R00
|
||||
"000011" & X"C00", -- 0x1B2: MOV R00, 0xC0
|
||||
"111011" & X"218", -- 0x1B3: CALL 0x218
|
||||
"000101" & X"870", -- 0x1B4: MOVX R00, (0x87)
|
||||
"111011" & X"192", -- 0x1B5: CALL 0x192
|
||||
"000101" & X"860", -- 0x1B6: MOVX R00, (0x86)
|
||||
"111011" & X"192", -- 0x1B7: CALL 0x192
|
||||
"000101" & X"850", -- 0x1B8: MOVX R00, (0x85)
|
||||
"111011" & X"192", -- 0x1B9: CALL 0x192
|
||||
"000101" & X"840", -- 0x1BA: MOVX R00, (0x84)
|
||||
"111011" & X"192", -- 0x1BB: CALL 0x192
|
||||
"000101" & X"830", -- 0x1BC: MOVX R00, (0x83)
|
||||
"111011" & X"192", -- 0x1BD: CALL 0x192
|
||||
"000101" & X"820", -- 0x1BE: MOVX R00, (0x82)
|
||||
"111011" & X"192", -- 0x1BF: CALL 0x192
|
||||
"000101" & X"810", -- 0x1C0: MOVX R00, (0x81)
|
||||
"111011" & X"192", -- 0x1C1: CALL 0x192
|
||||
"000101" & X"800", -- 0x1C2: MOVX R00, (0x80)
|
||||
"111011" & X"192", -- 0x1C3: CALL 0x192
|
||||
"111101" & X"000", -- 0x1C4: POP R00
|
||||
"111110" & X"000", -- 0x1C5: RET
|
||||
"111100" & X"000", -- 0x1C6: PUSH R00
|
||||
"000011" & X"0D0", -- 0x1C7: MOV R00, 0x0D
|
||||
"100100" & X"130", -- 0x1C8: XOUT (0x13), R00
|
||||
"000011" & X"1E0", -- 0x1C9: MOV R00, 0x1E
|
||||
"001101" & X"5E0", -- 0x1CA: MOVC (0x5E), R00
|
||||
"001101" & X"5F0", -- 0x1CB: MOVC (0x5F), R00
|
||||
"000011" & X"E80", -- 0x1CC: MOV R00, 0xE8
|
||||
"001101" & X"600", -- 0x1CD: MOVC (0x60), R00
|
||||
"000011" & X"030", -- 0x1CE: MOV R00, 0x03
|
||||
"001101" & X"610", -- 0x1CF: MOVC (0x61), R00
|
||||
"111101" & X"000", -- 0x1D0: POP R00
|
||||
"111110" & X"000", -- 0x1D1: RET
|
||||
"111100" & X"001", -- 0x1D2: PUSH R01
|
||||
"111100" & X"002", -- 0x1D3: PUSH R02
|
||||
"111100" & X"003", -- 0x1D4: PUSH R03
|
||||
"001010" & X"602", -- 0x1D5: MOVC R02, (0x60)
|
||||
"001010" & X"613", -- 0x1D6: MOVC R03, (0x61)
|
||||
"001010" & X"5E1", -- 0x1D7: MOVC R01, (0x5E)
|
||||
"001010" & X"5F0", -- 0x1D8: MOVC R00, (0x5F)
|
||||
"001110" & X"010", -- 0x1D9: CMP R00, R01
|
||||
"111001" & X"1E6", -- 0x1DA: JEQ 0x1E6
|
||||
"001001" & X"010", -- 0x1DB: MOVC R00, (R01)
|
||||
"010001" & X"011", -- 0x1DC: INC R01
|
||||
"001111" & X"5E1", -- 0x1DD: CMP R01, 0x5E
|
||||
"111010" & X"1E0", -- 0x1DE: JNE 0x1E0
|
||||
"000011" & X"1E1", -- 0x1DF: MOV R01, 0x1E
|
||||
"001101" & X"5E1", -- 0x1E0: MOVC (0x5E), R01
|
||||
"010101" & X"000", -- 0x1E1: CLRC
|
||||
"111101" & X"003", -- 0x1E2: POP R03
|
||||
"111101" & X"002", -- 0x1E3: POP R02
|
||||
"111101" & X"001", -- 0x1E4: POP R01
|
||||
"111110" & X"000", -- 0x1E5: RET
|
||||
"111011" & X"2A7", -- 0x1E6: CALL 0x2A7
|
||||
"010101" & X"012", -- 0x1E7: DEC R02
|
||||
"010111" & X"003", -- 0x1E8: SUBC R03, 0x00
|
||||
"110010" & X"1D8", -- 0x1E9: JNZ 0x1D8
|
||||
"001111" & X"002", -- 0x1EA: TST R02
|
||||
"110010" & X"1D8", -- 0x1EB: JNZ 0x1D8
|
||||
"101011" & X"000", -- 0x1EC: SETC
|
||||
"110000" & X"1E2", -- 0x1ED: JMP 0x1E2
|
||||
"011001" & X"0F0", -- 0x1EE: AND R00, 0x0F
|
||||
"001111" & X"0A0", -- 0x1EF: CMP R00, 0x0A
|
||||
"110101" & X"1F2", -- 0x1F0: JLT 0x1F2
|
||||
"010001" & X"070", -- 0x1F1: ADD R00, 0x07
|
||||
"010001" & X"300", -- 0x1F2: ADD R00, 0x30
|
||||
"111110" & X"000", -- 0x1F3: RET
|
||||
"111100" & X"000", -- 0x1F4: PUSH R00
|
||||
"111011" & X"1EE", -- 0x1F5: CALL 0x1EE
|
||||
"000010" & X"001", -- 0x1F6: MOV R01, R00
|
||||
"111101" & X"000", -- 0x1F7: POP R00
|
||||
"101010" & X"000", -- 0x1F8: SWAP R00
|
||||
"111011" & X"1EE", -- 0x1F9: CALL 0x1EE
|
||||
"111110" & X"000", -- 0x1FA: RET
|
||||
"000011" & X"002", -- 0x1FB: MOV R02, 0x00
|
||||
"000011" & X"030", -- 0x1FC: MOV R00, 0x03
|
||||
"111011" & X"247", -- 0x1FD: CALL 0x247
|
||||
"111011" & X"2A0", -- 0x1FE: CALL 0x2A0
|
||||
"000011" & X"002", -- 0x1FF: MOV R02, 0x00
|
||||
"000011" & X"030", -- 0x200: MOV R00, 0x03
|
||||
"111011" & X"247", -- 0x201: CALL 0x247
|
||||
"111011" & X"2A0", -- 0x202: CALL 0x2A0
|
||||
"000011" & X"002", -- 0x203: MOV R02, 0x00
|
||||
"000011" & X"020", -- 0x204: MOV R00, 0x02
|
||||
"111011" & X"247", -- 0x205: CALL 0x247
|
||||
"111011" & X"2A7", -- 0x206: CALL 0x2A7
|
||||
"000011" & X"280", -- 0x207: MOV R00, 0x28
|
||||
"111011" & X"218", -- 0x208: CALL 0x218
|
||||
"000011" & X"0C0", -- 0x209: MOV R00, 0x0C
|
||||
"111011" & X"218", -- 0x20A: CALL 0x218
|
||||
"000011" & X"060", -- 0x20B: MOV R00, 0x06
|
||||
"111011" & X"218", -- 0x20C: CALL 0x218
|
||||
"000011" & X"010", -- 0x20D: MOV R00, 0x01
|
||||
"111011" & X"218", -- 0x20E: CALL 0x218
|
||||
"111110" & X"000", -- 0x20F: RET
|
||||
"111100" & X"000", -- 0x210: PUSH R00
|
||||
"111011" & X"23B", -- 0x211: CALL 0x23B
|
||||
"011001" & X"800", -- 0x212: AND R00, 0x80
|
||||
"110001" & X"216", -- 0x213: JZ 0x216
|
||||
"111011" & X"2BE", -- 0x214: CALL 0x2BE
|
||||
"110000" & X"211", -- 0x215: JMP 0x211
|
||||
"111101" & X"000", -- 0x216: POP R00
|
||||
"111110" & X"000", -- 0x217: RET
|
||||
"111100" & X"002", -- 0x218: PUSH R02
|
||||
"000011" & X"002", -- 0x219: MOV R02, 0x00
|
||||
"111011" & X"234", -- 0x21A: CALL 0x234
|
||||
"111101" & X"002", -- 0x21B: POP R02
|
||||
"111110" & X"000", -- 0x21C: RET
|
||||
"111100" & X"000", -- 0x21D: PUSH R00
|
||||
"000100" & X"010", -- 0x21E: MOVX R00, (R01)
|
||||
"010001" & X"011", -- 0x21F: INC R01
|
||||
"001111" & X"000", -- 0x220: TST R00
|
||||
"110001" & X"224", -- 0x221: JZ 0x224
|
||||
"111011" & X"22F", -- 0x222: CALL 0x22F
|
||||
"110000" & X"21E", -- 0x223: JMP 0x21E
|
||||
"111101" & X"000", -- 0x224: POP R00
|
||||
"111110" & X"000", -- 0x225: RET
|
||||
"111100" & X"000", -- 0x226: PUSH R00
|
||||
"001001" & X"010", -- 0x227: MOVC R00, (R01)
|
||||
"010001" & X"011", -- 0x228: INC R01
|
||||
"001111" & X"000", -- 0x229: TST R00
|
||||
"110001" & X"22D", -- 0x22A: JZ 0x22D
|
||||
"111011" & X"22F", -- 0x22B: CALL 0x22F
|
||||
"110000" & X"227", -- 0x22C: JMP 0x227
|
||||
"111101" & X"000", -- 0x22D: POP R00
|
||||
"111110" & X"000", -- 0x22E: RET
|
||||
"111100" & X"002", -- 0x22F: PUSH R02
|
||||
"000011" & X"402", -- 0x230: MOV R02, 0x40
|
||||
"111011" & X"234", -- 0x231: CALL 0x234
|
||||
"111101" & X"002", -- 0x232: POP R02
|
||||
"111110" & X"000", -- 0x233: RET
|
||||
"111011" & X"210", -- 0x234: CALL 0x210
|
||||
"111100" & X"000", -- 0x235: PUSH R00
|
||||
"101010" & X"000", -- 0x236: SWAP R00
|
||||
"111011" & X"247", -- 0x237: CALL 0x247
|
||||
"111101" & X"000", -- 0x238: POP R00
|
||||
"111011" & X"247", -- 0x239: CALL 0x247
|
||||
"111110" & X"000", -- 0x23A: RET
|
||||
"111100" & X"002", -- 0x23B: PUSH R02
|
||||
"000011" & X"002", -- 0x23C: MOV R02, 0x00
|
||||
"111011" & X"240", -- 0x23D: CALL 0x240
|
||||
"111101" & X"002", -- 0x23E: POP R02
|
||||
"111110" & X"000", -- 0x23F: RET
|
||||
"111011" & X"25A", -- 0x240: CALL 0x25A
|
||||
"101010" & X"000", -- 0x241: SWAP R00
|
||||
"111100" & X"000", -- 0x242: PUSH R00
|
||||
"111011" & X"25A", -- 0x243: CALL 0x25A
|
||||
"111101" & X"002", -- 0x244: POP R02
|
||||
"011010" & X"020", -- 0x245: OR R00, R02
|
||||
"111110" & X"000", -- 0x246: RET
|
||||
"111100" & X"001", -- 0x247: PUSH R01
|
||||
"011001" & X"0F0", -- 0x248: AND R00, 0x0F
|
||||
"000010" & X"001", -- 0x249: MOV R01, R00
|
||||
"011010" & X"021", -- 0x24A: OR R01, R02
|
||||
"100100" & X"031", -- 0x24B: XOUT (0x03), R01
|
||||
"111011" & X"2BE", -- 0x24C: CALL 0x2BE
|
||||
"000010" & X"001", -- 0x24D: MOV R01, R00
|
||||
"011010" & X"021", -- 0x24E: OR R01, R02
|
||||
"011011" & X"801", -- 0x24F: OR R01, 0x80
|
||||
"100100" & X"031", -- 0x250: XOUT (0x03), R01
|
||||
"111011" & X"2BE", -- 0x251: CALL 0x2BE
|
||||
"000010" & X"001", -- 0x252: MOV R01, R00
|
||||
"011010" & X"021", -- 0x253: OR R01, R02
|
||||
"100100" & X"031", -- 0x254: XOUT (0x03), R01
|
||||
"111011" & X"2BE", -- 0x255: CALL 0x2BE
|
||||
"011011" & X"201", -- 0x256: OR R01, 0x20
|
||||
"100100" & X"031", -- 0x257: XOUT (0x03), R01
|
||||
"111101" & X"001", -- 0x258: POP R01
|
||||
"111110" & X"000", -- 0x259: RET
|
||||
"111100" & X"001", -- 0x25A: PUSH R01
|
||||
"000011" & X"201", -- 0x25B: MOV R01, 0x20
|
||||
"011010" & X"021", -- 0x25C: OR R01, R02
|
||||
"100100" & X"031", -- 0x25D: XOUT (0x03), R01
|
||||
"111011" & X"2BE", -- 0x25E: CALL 0x2BE
|
||||
"000011" & X"201", -- 0x25F: MOV R01, 0x20
|
||||
"011010" & X"021", -- 0x260: OR R01, R02
|
||||
"011011" & X"801", -- 0x261: OR R01, 0x80
|
||||
"100100" & X"031", -- 0x262: XOUT (0x03), R01
|
||||
"111011" & X"2BE", -- 0x263: CALL 0x2BE
|
||||
"101000" & X"030", -- 0x264: XIN R00, (0x03)
|
||||
"011001" & X"0F0", -- 0x265: AND R00, 0x0F
|
||||
"000011" & X"201", -- 0x266: MOV R01, 0x20
|
||||
"011010" & X"021", -- 0x267: OR R01, R02
|
||||
"100100" & X"031", -- 0x268: XOUT (0x03), R01
|
||||
"111011" & X"2BE", -- 0x269: CALL 0x2BE
|
||||
"111101" & X"001", -- 0x26A: POP R01
|
||||
"111110" & X"000", -- 0x26B: RET
|
||||
"111100" & X"000", -- 0x26C: PUSH R00
|
||||
"000011" & X"020", -- 0x26D: MOV R00, 0x02
|
||||
"100100" & X"0E0", -- 0x26E: XOUT (0x0E), R00
|
||||
"111101" & X"000", -- 0x26F: POP R00
|
||||
"111110" & X"000", -- 0x270: RET
|
||||
"111100" & X"000", -- 0x271: PUSH R00
|
||||
"000011" & X"010", -- 0x272: MOV R00, 0x01
|
||||
"100100" & X"0E0", -- 0x273: XOUT (0x0E), R00
|
||||
"111101" & X"000", -- 0x274: POP R00
|
||||
"111110" & X"000", -- 0x275: RET
|
||||
"111011" & X"28C", -- 0x276: CALL 0x28C
|
||||
"100100" & X"0C1", -- 0x277: XOUT (0x0C), R01
|
||||
"100100" & X"0B0", -- 0x278: XOUT (0x0B), R00
|
||||
"111110" & X"000", -- 0x279: RET
|
||||
"111011" & X"28C", -- 0x27A: CALL 0x28C
|
||||
"100100" & X"0D0", -- 0x27B: XOUT (0x0D), R00
|
||||
"111110" & X"000", -- 0x27C: RET
|
||||
"111100" & X"000", -- 0x27D: PUSH R00
|
||||
"000100" & X"010", -- 0x27E: MOVX R00, (R01)
|
||||
"010001" & X"011", -- 0x27F: INC R01
|
||||
"001111" & X"000", -- 0x280: TST R00
|
||||
"110001" & X"284", -- 0x281: JZ 0x284
|
||||
"111011" & X"27A", -- 0x282: CALL 0x27A
|
||||
"110000" & X"27E", -- 0x283: JMP 0x27E
|
||||
"111101" & X"000", -- 0x284: POP R00
|
||||
"111110" & X"000", -- 0x285: RET
|
||||
"111011" & X"26C", -- 0x286: CALL 0x26C
|
||||
"111011" & X"27D", -- 0x287: CALL 0x27D
|
||||
"111110" & X"000", -- 0x288: RET
|
||||
"111011" & X"27D", -- 0x289: CALL 0x27D
|
||||
"111011" & X"26C", -- 0x28A: CALL 0x26C
|
||||
"111110" & X"000", -- 0x28B: RET
|
||||
"111100" & X"000", -- 0x28C: PUSH R00
|
||||
"101000" & X"0E0", -- 0x28D: XIN R00, (0x0E)
|
||||
"011001" & X"020", -- 0x28E: AND R00, 0x02
|
||||
"110001" & X"28D", -- 0x28F: JZ 0x28D
|
||||
"111101" & X"000", -- 0x290: POP R00
|
||||
"111110" & X"000", -- 0x291: RET
|
||||
"111100" & X"00F", -- 0x292: PUSH R15
|
||||
"000011" & X"0AF", -- 0x293: MOV R15, 0x0A
|
||||
"111011" & X"299", -- 0x294: CALL 0x299
|
||||
"010101" & X"01F", -- 0x295: DEC R15
|
||||
"110010" & X"294", -- 0x296: JNZ 0x294
|
||||
"111101" & X"00F", -- 0x297: POP R15
|
||||
"111110" & X"000", -- 0x298: RET
|
||||
"111100" & X"00F", -- 0x299: PUSH R15
|
||||
"000011" & X"0AF", -- 0x29A: MOV R15, 0x0A
|
||||
"111011" & X"2A0", -- 0x29B: CALL 0x2A0
|
||||
"010101" & X"01F", -- 0x29C: DEC R15
|
||||
"110010" & X"29B", -- 0x29D: JNZ 0x29B
|
||||
"111101" & X"00F", -- 0x29E: POP R15
|
||||
"111110" & X"000", -- 0x29F: RET
|
||||
"111100" & X"00F", -- 0x2A0: PUSH R15
|
||||
"000011" & X"0AF", -- 0x2A1: MOV R15, 0x0A
|
||||
"111011" & X"2A7", -- 0x2A2: CALL 0x2A7
|
||||
"010101" & X"01F", -- 0x2A3: DEC R15
|
||||
"110010" & X"2A2", -- 0x2A4: JNZ 0x2A2
|
||||
"111101" & X"00F", -- 0x2A5: POP R15
|
||||
"111110" & X"000", -- 0x2A6: RET
|
||||
"111100" & X"00F", -- 0x2A7: PUSH R15
|
||||
"000011" & X"0AF", -- 0x2A8: MOV R15, 0x0A
|
||||
"111011" & X"2AE", -- 0x2A9: CALL 0x2AE
|
||||
"010101" & X"01F", -- 0x2AA: DEC R15
|
||||
"110010" & X"2A9", -- 0x2AB: JNZ 0x2A9
|
||||
"111101" & X"00F", -- 0x2AC: POP R15
|
||||
"111110" & X"000", -- 0x2AD: RET
|
||||
"111100" & X"00F", -- 0x2AE: PUSH R15
|
||||
"000011" & X"0AF", -- 0x2AF: MOV R15, 0x0A
|
||||
"111011" & X"2B5", -- 0x2B0: CALL 0x2B5
|
||||
"010101" & X"01F", -- 0x2B1: DEC R15
|
||||
"110010" & X"2B0", -- 0x2B2: JNZ 0x2B0
|
||||
"111101" & X"00F", -- 0x2B3: POP R15
|
||||
"111110" & X"000", -- 0x2B4: RET
|
||||
"111100" & X"00F", -- 0x2B5: PUSH R15
|
||||
"000011" & X"63F", -- 0x2B6: MOV R15, 0x63
|
||||
"000000" & X"000", -- 0x2B7: NOP
|
||||
"000000" & X"000", -- 0x2B8: NOP
|
||||
"000000" & X"000", -- 0x2B9: NOP
|
||||
"010101" & X"01F", -- 0x2BA: DEC R15
|
||||
"110010" & X"2B7", -- 0x2BB: JNZ 0x2B7
|
||||
"111101" & X"00F", -- 0x2BC: POP R15
|
||||
"111110" & X"000", -- 0x2BD: RET
|
||||
"111100" & X"00F", -- 0x2BE: PUSH R15
|
||||
"000011" & X"09F", -- 0x2BF: MOV R15, 0x09
|
||||
"000000" & X"000", -- 0x2C0: NOP
|
||||
"000000" & X"000", -- 0x2C1: NOP
|
||||
"000000" & X"000", -- 0x2C2: NOP
|
||||
"010101" & X"01F", -- 0x2C3: DEC R15
|
||||
"110010" & X"2C0", -- 0x2C4: JNZ 0x2C0
|
||||
"111101" & X"00F", -- 0x2C5: POP R15
|
||||
"111110" & X"000", -- 0x2C6: RET
|
||||
"111100" & X"001", -- 0x2C7: PUSH R01
|
||||
"101000" & X"061", -- 0x2C8: XIN R01, (0x06)
|
||||
"011001" & X"021", -- 0x2C9: AND R01, 0x02
|
||||
"110010" & X"2C8", -- 0x2CA: JNZ 0x2C8
|
||||
"100100" & X"020", -- 0x2CB: XOUT (0x02), R00
|
||||
"111101" & X"001", -- 0x2CC: POP R01
|
||||
"111110" & X"000", -- 0x2CD: RET
|
||||
"111100" & X"001", -- 0x2CE: PUSH R01
|
||||
"101000" & X"061", -- 0x2CF: XIN R01, (0x06)
|
||||
"011001" & X"101", -- 0x2D0: AND R01, 0x10
|
||||
"110001" & X"2CF", -- 0x2D1: JZ 0x2CF
|
||||
"101000" & X"020", -- 0x2D2: XIN R00, (0x02)
|
||||
"111101" & X"001", -- 0x2D3: POP R01
|
||||
"111110" & X"000" -- 0x2D4: RET
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= imem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end vga_test;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,317 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
ENTITY xrom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in dmem_addr_t;
|
||||
dout : out dmem_data_t
|
||||
);
|
||||
END xrom;
|
||||
|
||||
ARCHITECTURE vga_test OF xrom IS
|
||||
|
||||
type xmem_rom_t is array (0 to 255) of dmem_data_t;
|
||||
|
||||
-- Assembled from vga_test.jsm
|
||||
constant xmem_rom : xmem_rom_t :=
|
||||
(
|
||||
X"0D", -- 0x00
|
||||
X"0A", -- 0x01
|
||||
X"00", -- 0x02
|
||||
X"53", -- 0x03
|
||||
X"44", -- 0x04
|
||||
X"52", -- 0x05
|
||||
X"41", -- 0x06
|
||||
X"4D", -- 0x07
|
||||
X"20", -- 0x08
|
||||
X"54", -- 0x09
|
||||
X"65", -- 0x0A
|
||||
X"73", -- 0x0B
|
||||
X"74", -- 0x0C
|
||||
X"00", -- 0x0D
|
||||
X"43", -- 0x0E
|
||||
X"6C", -- 0x0F
|
||||
X"65", -- 0x10
|
||||
X"61", -- 0x11
|
||||
X"72", -- 0x12
|
||||
X"69", -- 0x13
|
||||
X"6E", -- 0x14
|
||||
X"67", -- 0x15
|
||||
X"20", -- 0x16
|
||||
X"53", -- 0x17
|
||||
X"44", -- 0x18
|
||||
X"52", -- 0x19
|
||||
X"41", -- 0x1A
|
||||
X"4D", -- 0x1B
|
||||
X"00", -- 0x1C
|
||||
X"57", -- 0x1D
|
||||
X"72", -- 0x1E
|
||||
X"69", -- 0x1F
|
||||
X"74", -- 0x20
|
||||
X"69", -- 0x21
|
||||
X"6E", -- 0x22
|
||||
X"67", -- 0x23
|
||||
X"20", -- 0x24
|
||||
X"53", -- 0x25
|
||||
X"44", -- 0x26
|
||||
X"52", -- 0x27
|
||||
X"41", -- 0x28
|
||||
X"4D", -- 0x29
|
||||
X"00", -- 0x2A
|
||||
X"52", -- 0x2B
|
||||
X"65", -- 0x2C
|
||||
X"61", -- 0x2D
|
||||
X"64", -- 0x2E
|
||||
X"69", -- 0x2F
|
||||
X"6E", -- 0x30
|
||||
X"67", -- 0x31
|
||||
X"20", -- 0x32
|
||||
X"53", -- 0x33
|
||||
X"44", -- 0x34
|
||||
X"52", -- 0x35
|
||||
X"41", -- 0x36
|
||||
X"4D", -- 0x37
|
||||
X"00", -- 0x38
|
||||
X"52", -- 0x39
|
||||
X"65", -- 0x3A
|
||||
X"61", -- 0x3B
|
||||
X"64", -- 0x3C
|
||||
X"69", -- 0x3D
|
||||
X"6E", -- 0x3E
|
||||
X"67", -- 0x3F
|
||||
X"20", -- 0x40
|
||||
X"42", -- 0x41
|
||||
X"69", -- 0x42
|
||||
X"74", -- 0x43
|
||||
X"6D", -- 0x44
|
||||
X"61", -- 0x45
|
||||
X"70", -- 0x46
|
||||
X"00", -- 0x47
|
||||
X"56", -- 0x48
|
||||
X"65", -- 0x49
|
||||
X"72", -- 0x4A
|
||||
X"69", -- 0x4B
|
||||
X"66", -- 0x4C
|
||||
X"79", -- 0x4D
|
||||
X"20", -- 0x4E
|
||||
X"4F", -- 0x4F
|
||||
X"4B", -- 0x50
|
||||
X"00", -- 0x51
|
||||
X"46", -- 0x52
|
||||
X"61", -- 0x53
|
||||
X"69", -- 0x54
|
||||
X"6C", -- 0x55
|
||||
X"65", -- 0x56
|
||||
X"64", -- 0x57
|
||||
X"20", -- 0x58
|
||||
X"61", -- 0x59
|
||||
X"74", -- 0x5A
|
||||
X"20", -- 0x5B
|
||||
X"00", -- 0x5C
|
||||
X"2E", -- 0x5D
|
||||
X"00", -- 0x5E
|
||||
X"00", -- 0x5F
|
||||
X"00", -- 0x60
|
||||
X"00", -- 0x61
|
||||
X"00", -- 0x62
|
||||
X"00", -- 0x63
|
||||
X"00", -- 0x64
|
||||
X"00", -- 0x65
|
||||
X"00", -- 0x66
|
||||
X"00", -- 0x67
|
||||
X"00", -- 0x68
|
||||
X"00", -- 0x69
|
||||
X"00", -- 0x6A
|
||||
X"00", -- 0x6B
|
||||
X"00", -- 0x6C
|
||||
X"00", -- 0x6D
|
||||
X"00", -- 0x6E
|
||||
X"00", -- 0x6F
|
||||
X"00", -- 0x70
|
||||
X"00", -- 0x71
|
||||
X"00", -- 0x72
|
||||
X"00", -- 0x73
|
||||
X"00", -- 0x74
|
||||
X"00", -- 0x75
|
||||
X"00", -- 0x76
|
||||
X"00", -- 0x77
|
||||
X"00", -- 0x78
|
||||
X"00", -- 0x79
|
||||
X"00", -- 0x7A
|
||||
X"00", -- 0x7B
|
||||
X"00", -- 0x7C
|
||||
X"00", -- 0x7D
|
||||
X"00", -- 0x7E
|
||||
X"00", -- 0x7F
|
||||
X"00", -- 0x80
|
||||
X"00", -- 0x81
|
||||
X"00", -- 0x82
|
||||
X"00", -- 0x83
|
||||
X"00", -- 0x84
|
||||
X"00", -- 0x85
|
||||
X"00", -- 0x86
|
||||
X"00", -- 0x87
|
||||
X"00", -- 0x88
|
||||
X"00", -- 0x89
|
||||
X"00", -- 0x8A
|
||||
X"00", -- 0x8B
|
||||
X"00", -- 0x8C
|
||||
X"00", -- 0x8D
|
||||
X"00", -- 0x8E
|
||||
X"00", -- 0x8F
|
||||
X"00", -- 0x90
|
||||
X"00", -- 0x91
|
||||
X"00", -- 0x92
|
||||
X"00", -- 0x93
|
||||
X"00", -- 0x94
|
||||
X"00", -- 0x95
|
||||
X"00", -- 0x96
|
||||
X"00", -- 0x97
|
||||
X"00", -- 0x98
|
||||
X"00", -- 0x99
|
||||
X"00", -- 0x9A
|
||||
X"00", -- 0x9B
|
||||
X"00", -- 0x9C
|
||||
X"00", -- 0x9D
|
||||
X"00", -- 0x9E
|
||||
X"00", -- 0x9F
|
||||
X"00", -- 0xA0
|
||||
X"00", -- 0xA1
|
||||
X"00", -- 0xA2
|
||||
X"00", -- 0xA3
|
||||
X"00", -- 0xA4
|
||||
X"00", -- 0xA5
|
||||
X"00", -- 0xA6
|
||||
X"00", -- 0xA7
|
||||
X"00", -- 0xA8
|
||||
X"00", -- 0xA9
|
||||
X"00", -- 0xAA
|
||||
X"00", -- 0xAB
|
||||
X"00", -- 0xAC
|
||||
X"00", -- 0xAD
|
||||
X"00", -- 0xAE
|
||||
X"00", -- 0xAF
|
||||
X"00", -- 0xB0
|
||||
X"00", -- 0xB1
|
||||
X"00", -- 0xB2
|
||||
X"00", -- 0xB3
|
||||
X"00", -- 0xB4
|
||||
X"00", -- 0xB5
|
||||
X"00", -- 0xB6
|
||||
X"00", -- 0xB7
|
||||
X"00", -- 0xB8
|
||||
X"00", -- 0xB9
|
||||
X"00", -- 0xBA
|
||||
X"00", -- 0xBB
|
||||
X"00", -- 0xBC
|
||||
X"00", -- 0xBD
|
||||
X"00", -- 0xBE
|
||||
X"00", -- 0xBF
|
||||
X"00", -- 0xC0
|
||||
X"00", -- 0xC1
|
||||
X"00", -- 0xC2
|
||||
X"00", -- 0xC3
|
||||
X"00", -- 0xC4
|
||||
X"00", -- 0xC5
|
||||
X"00", -- 0xC6
|
||||
X"00", -- 0xC7
|
||||
X"00", -- 0xC8
|
||||
X"00", -- 0xC9
|
||||
X"00", -- 0xCA
|
||||
X"00", -- 0xCB
|
||||
X"00", -- 0xCC
|
||||
X"00", -- 0xCD
|
||||
X"00", -- 0xCE
|
||||
X"00", -- 0xCF
|
||||
X"00", -- 0xD0
|
||||
X"00", -- 0xD1
|
||||
X"00", -- 0xD2
|
||||
X"00", -- 0xD3
|
||||
X"00", -- 0xD4
|
||||
X"00", -- 0xD5
|
||||
X"00", -- 0xD6
|
||||
X"00", -- 0xD7
|
||||
X"00", -- 0xD8
|
||||
X"00", -- 0xD9
|
||||
X"00", -- 0xDA
|
||||
X"00", -- 0xDB
|
||||
X"00", -- 0xDC
|
||||
X"00", -- 0xDD
|
||||
X"00", -- 0xDE
|
||||
X"00", -- 0xDF
|
||||
X"00", -- 0xE0
|
||||
X"00", -- 0xE1
|
||||
X"00", -- 0xE2
|
||||
X"00", -- 0xE3
|
||||
X"00", -- 0xE4
|
||||
X"00", -- 0xE5
|
||||
X"00", -- 0xE6
|
||||
X"00", -- 0xE7
|
||||
X"00", -- 0xE8
|
||||
X"00", -- 0xE9
|
||||
X"00", -- 0xEA
|
||||
X"00", -- 0xEB
|
||||
X"00", -- 0xEC
|
||||
X"00", -- 0xED
|
||||
X"00", -- 0xEE
|
||||
X"00", -- 0xEF
|
||||
X"00", -- 0xF0
|
||||
X"00", -- 0xF1
|
||||
X"00", -- 0xF2
|
||||
X"00", -- 0xF3
|
||||
X"00", -- 0xF4
|
||||
X"00", -- 0xF5
|
||||
X"00", -- 0xF6
|
||||
X"00", -- 0xF7
|
||||
X"00", -- 0xF8
|
||||
X"00", -- 0xF9
|
||||
X"00", -- 0xFA
|
||||
X"00", -- 0xFB
|
||||
X"00", -- 0xFC
|
||||
X"00", -- 0xFD
|
||||
X"00", -- 0xFE
|
||||
X"00" -- 0xFF
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= xmem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end vga_test;
|
||||
|
||||
@@ -0,0 +1,413 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: loadable ROM
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library UNISIM;
|
||||
use UNISIM.VComponents.all;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
ENTITY xrom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in dmem_addr_t;
|
||||
dout : out dmem_data_t
|
||||
);
|
||||
|
||||
END xrom;
|
||||
|
||||
ARCHITECTURE loadable OF xrom IS
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
|
||||
-- Assembled from vga_test.jsm
|
||||
type xmem_rom_t is array (0 to 255) of dmem_data_t;
|
||||
signal xmem_rom : xmem_rom_t :=
|
||||
(
|
||||
X"0D", -- 0x00
|
||||
X"0A", -- 0x01
|
||||
X"00", -- 0x02
|
||||
X"53", -- 0x03
|
||||
X"44", -- 0x04
|
||||
X"52", -- 0x05
|
||||
X"41", -- 0x06
|
||||
X"4D", -- 0x07
|
||||
X"20", -- 0x08
|
||||
X"54", -- 0x09
|
||||
X"65", -- 0x0A
|
||||
X"73", -- 0x0B
|
||||
X"74", -- 0x0C
|
||||
X"00", -- 0x0D
|
||||
X"43", -- 0x0E
|
||||
X"6C", -- 0x0F
|
||||
X"65", -- 0x10
|
||||
X"61", -- 0x11
|
||||
X"72", -- 0x12
|
||||
X"69", -- 0x13
|
||||
X"6E", -- 0x14
|
||||
X"67", -- 0x15
|
||||
X"20", -- 0x16
|
||||
X"53", -- 0x17
|
||||
X"44", -- 0x18
|
||||
X"52", -- 0x19
|
||||
X"41", -- 0x1A
|
||||
X"4D", -- 0x1B
|
||||
X"00", -- 0x1C
|
||||
X"57", -- 0x1D
|
||||
X"72", -- 0x1E
|
||||
X"69", -- 0x1F
|
||||
X"74", -- 0x20
|
||||
X"69", -- 0x21
|
||||
X"6E", -- 0x22
|
||||
X"67", -- 0x23
|
||||
X"20", -- 0x24
|
||||
X"53", -- 0x25
|
||||
X"44", -- 0x26
|
||||
X"52", -- 0x27
|
||||
X"41", -- 0x28
|
||||
X"4D", -- 0x29
|
||||
X"00", -- 0x2A
|
||||
X"52", -- 0x2B
|
||||
X"65", -- 0x2C
|
||||
X"61", -- 0x2D
|
||||
X"64", -- 0x2E
|
||||
X"69", -- 0x2F
|
||||
X"6E", -- 0x30
|
||||
X"67", -- 0x31
|
||||
X"20", -- 0x32
|
||||
X"53", -- 0x33
|
||||
X"44", -- 0x34
|
||||
X"52", -- 0x35
|
||||
X"41", -- 0x36
|
||||
X"4D", -- 0x37
|
||||
X"00", -- 0x38
|
||||
X"52", -- 0x39
|
||||
X"65", -- 0x3A
|
||||
X"61", -- 0x3B
|
||||
X"64", -- 0x3C
|
||||
X"69", -- 0x3D
|
||||
X"6E", -- 0x3E
|
||||
X"67", -- 0x3F
|
||||
X"20", -- 0x40
|
||||
X"42", -- 0x41
|
||||
X"69", -- 0x42
|
||||
X"74", -- 0x43
|
||||
X"6D", -- 0x44
|
||||
X"61", -- 0x45
|
||||
X"70", -- 0x46
|
||||
X"00", -- 0x47
|
||||
X"56", -- 0x48
|
||||
X"65", -- 0x49
|
||||
X"72", -- 0x4A
|
||||
X"69", -- 0x4B
|
||||
X"66", -- 0x4C
|
||||
X"79", -- 0x4D
|
||||
X"20", -- 0x4E
|
||||
X"4F", -- 0x4F
|
||||
X"4B", -- 0x50
|
||||
X"00", -- 0x51
|
||||
X"46", -- 0x52
|
||||
X"61", -- 0x53
|
||||
X"69", -- 0x54
|
||||
X"6C", -- 0x55
|
||||
X"65", -- 0x56
|
||||
X"64", -- 0x57
|
||||
X"20", -- 0x58
|
||||
X"61", -- 0x59
|
||||
X"74", -- 0x5A
|
||||
X"20", -- 0x5B
|
||||
X"00", -- 0x5C
|
||||
X"2E", -- 0x5D
|
||||
X"00", -- 0x5E
|
||||
X"00", -- 0x5F
|
||||
X"00", -- 0x60
|
||||
X"00", -- 0x61
|
||||
X"00", -- 0x62
|
||||
X"00", -- 0x63
|
||||
X"00", -- 0x64
|
||||
X"00", -- 0x65
|
||||
X"00", -- 0x66
|
||||
X"00", -- 0x67
|
||||
X"00", -- 0x68
|
||||
X"00", -- 0x69
|
||||
X"00", -- 0x6A
|
||||
X"00", -- 0x6B
|
||||
X"00", -- 0x6C
|
||||
X"00", -- 0x6D
|
||||
X"00", -- 0x6E
|
||||
X"00", -- 0x6F
|
||||
X"00", -- 0x70
|
||||
X"00", -- 0x71
|
||||
X"00", -- 0x72
|
||||
X"00", -- 0x73
|
||||
X"00", -- 0x74
|
||||
X"00", -- 0x75
|
||||
X"00", -- 0x76
|
||||
X"00", -- 0x77
|
||||
X"00", -- 0x78
|
||||
X"00", -- 0x79
|
||||
X"00", -- 0x7A
|
||||
X"00", -- 0x7B
|
||||
X"00", -- 0x7C
|
||||
X"00", -- 0x7D
|
||||
X"00", -- 0x7E
|
||||
X"00", -- 0x7F
|
||||
X"00", -- 0x80
|
||||
X"00", -- 0x81
|
||||
X"00", -- 0x82
|
||||
X"00", -- 0x83
|
||||
X"00", -- 0x84
|
||||
X"00", -- 0x85
|
||||
X"00", -- 0x86
|
||||
X"00", -- 0x87
|
||||
X"00", -- 0x88
|
||||
X"00", -- 0x89
|
||||
X"00", -- 0x8A
|
||||
X"00", -- 0x8B
|
||||
X"00", -- 0x8C
|
||||
X"00", -- 0x8D
|
||||
X"00", -- 0x8E
|
||||
X"00", -- 0x8F
|
||||
X"00", -- 0x90
|
||||
X"00", -- 0x91
|
||||
X"00", -- 0x92
|
||||
X"00", -- 0x93
|
||||
X"00", -- 0x94
|
||||
X"00", -- 0x95
|
||||
X"00", -- 0x96
|
||||
X"00", -- 0x97
|
||||
X"00", -- 0x98
|
||||
X"00", -- 0x99
|
||||
X"00", -- 0x9A
|
||||
X"00", -- 0x9B
|
||||
X"00", -- 0x9C
|
||||
X"00", -- 0x9D
|
||||
X"00", -- 0x9E
|
||||
X"00", -- 0x9F
|
||||
X"00", -- 0xA0
|
||||
X"00", -- 0xA1
|
||||
X"00", -- 0xA2
|
||||
X"00", -- 0xA3
|
||||
X"00", -- 0xA4
|
||||
X"00", -- 0xA5
|
||||
X"00", -- 0xA6
|
||||
X"00", -- 0xA7
|
||||
X"00", -- 0xA8
|
||||
X"00", -- 0xA9
|
||||
X"00", -- 0xAA
|
||||
X"00", -- 0xAB
|
||||
X"00", -- 0xAC
|
||||
X"00", -- 0xAD
|
||||
X"00", -- 0xAE
|
||||
X"00", -- 0xAF
|
||||
X"00", -- 0xB0
|
||||
X"00", -- 0xB1
|
||||
X"00", -- 0xB2
|
||||
X"00", -- 0xB3
|
||||
X"00", -- 0xB4
|
||||
X"00", -- 0xB5
|
||||
X"00", -- 0xB6
|
||||
X"00", -- 0xB7
|
||||
X"00", -- 0xB8
|
||||
X"00", -- 0xB9
|
||||
X"00", -- 0xBA
|
||||
X"00", -- 0xBB
|
||||
X"00", -- 0xBC
|
||||
X"00", -- 0xBD
|
||||
X"00", -- 0xBE
|
||||
X"00", -- 0xBF
|
||||
X"00", -- 0xC0
|
||||
X"00", -- 0xC1
|
||||
X"00", -- 0xC2
|
||||
X"00", -- 0xC3
|
||||
X"00", -- 0xC4
|
||||
X"00", -- 0xC5
|
||||
X"00", -- 0xC6
|
||||
X"00", -- 0xC7
|
||||
X"00", -- 0xC8
|
||||
X"00", -- 0xC9
|
||||
X"00", -- 0xCA
|
||||
X"00", -- 0xCB
|
||||
X"00", -- 0xCC
|
||||
X"00", -- 0xCD
|
||||
X"00", -- 0xCE
|
||||
X"00", -- 0xCF
|
||||
X"00", -- 0xD0
|
||||
X"00", -- 0xD1
|
||||
X"00", -- 0xD2
|
||||
X"00", -- 0xD3
|
||||
X"00", -- 0xD4
|
||||
X"00", -- 0xD5
|
||||
X"00", -- 0xD6
|
||||
X"00", -- 0xD7
|
||||
X"00", -- 0xD8
|
||||
X"00", -- 0xD9
|
||||
X"00", -- 0xDA
|
||||
X"00", -- 0xDB
|
||||
X"00", -- 0xDC
|
||||
X"00", -- 0xDD
|
||||
X"00", -- 0xDE
|
||||
X"00", -- 0xDF
|
||||
X"00", -- 0xE0
|
||||
X"00", -- 0xE1
|
||||
X"00", -- 0xE2
|
||||
X"00", -- 0xE3
|
||||
X"00", -- 0xE4
|
||||
X"00", -- 0xE5
|
||||
X"00", -- 0xE6
|
||||
X"00", -- 0xE7
|
||||
X"00", -- 0xE8
|
||||
X"00", -- 0xE9
|
||||
X"00", -- 0xEA
|
||||
X"00", -- 0xEB
|
||||
X"00", -- 0xEC
|
||||
X"00", -- 0xED
|
||||
X"00", -- 0xEE
|
||||
X"00", -- 0xEF
|
||||
X"00", -- 0xF0
|
||||
X"00", -- 0xF1
|
||||
X"00", -- 0xF2
|
||||
X"00", -- 0xF3
|
||||
X"00", -- 0xF4
|
||||
X"00", -- 0xF5
|
||||
X"00", -- 0xF6
|
||||
X"00", -- 0xF7
|
||||
X"00", -- 0xF8
|
||||
X"00", -- 0xF9
|
||||
X"00", -- 0xFA
|
||||
X"00", -- 0xFB
|
||||
X"00", -- 0xFC
|
||||
X"00", -- 0xFD
|
||||
X"00", -- 0xFE
|
||||
X"00" -- 0xFF
|
||||
);
|
||||
|
||||
signal jtag_ld_clk : STD_LOGIC;
|
||||
signal jtag_ld_we : STD_LOGIC;
|
||||
signal jtag_ld_addr : dmem_addr_t;
|
||||
signal jtag_ld_dout : dmem_data_t;
|
||||
signal jtag_ld_din : dmem_data_t;
|
||||
signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
|
||||
signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
|
||||
signal user_regi, user_rego : unsigned (15 downto 0);
|
||||
constant id : unsigned (15 downto 0) := X"BEEF";
|
||||
|
||||
begin
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- Virtex-4: JTAG Loader
|
||||
--------------------------------------------------------------------------
|
||||
i00_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_clk1,
|
||||
I => bs_clk0
|
||||
);
|
||||
|
||||
i01_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_update1,
|
||||
I => bs_update0
|
||||
);
|
||||
|
||||
BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4
|
||||
generic map
|
||||
(
|
||||
JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
|
||||
)
|
||||
port map
|
||||
(
|
||||
CAPTURE => bs_capture, -- CAPTURE output from TAP controller
|
||||
DRCK => bs_clk0, -- Data register output for USER functions
|
||||
RESET => bs_rst, -- Reset output from TAP controller
|
||||
SEL => bs_sel, -- USER active output
|
||||
SHIFT => bs_shift, -- SHIFT output from TAP controller
|
||||
TDI => bs_tdi, -- TDI output from TAP controller
|
||||
UPDATE => bs_update0, -- UPDATE output from TAP controller
|
||||
TDO => bs_tdo -- Data input for USER function
|
||||
);
|
||||
|
||||
jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1);
|
||||
jtag_ld_din <= user_regi(dmem_data_t'left downto 0);
|
||||
jtag_ld_clk <= bs_update1;
|
||||
jtag_ld_we <= bs_sel;
|
||||
|
||||
sipo:
|
||||
process (bs_rst, bs_clk1, bs_tdi, bs_shift)
|
||||
begin
|
||||
if bs_rst = '1' then
|
||||
user_regi <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
piso:
|
||||
process (bs_rst, bs_clk1, bs_shift, user_rego)
|
||||
begin
|
||||
bs_tdo <= user_rego(0);
|
||||
if bs_rst = '1' then
|
||||
user_rego <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
|
||||
else
|
||||
user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout;
|
||||
-- user_rego <= id;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- ROM Read/Write
|
||||
--------------------------------------------------------------------------
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= xmem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
PROM_WRITE:
|
||||
process(jtag_ld_clk, jtag_ld_we)
|
||||
begin
|
||||
if rising_edge(jtag_ld_clk) then
|
||||
if jtag_ld_we = '1' then
|
||||
xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
|
||||
else
|
||||
jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
end loadable;
|
||||
@@ -0,0 +1 @@
|
||||
work
|
||||
@@ -0,0 +1,34 @@
|
||||
vhdl work "../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/vga_types.vhd"
|
||||
vhdl work "../../src/systest/sdram_config.vhd"
|
||||
vhdl work "../../../../lib/misc/utils_pkg.vhd"
|
||||
vhdl work "../../../../lib/FIFO/src/gray_counter.vhd"
|
||||
vhdl work "../../../../lib/CPUs/JCpu/src/core/cpu_pkg.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/vga_sync.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/dpram.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_types.vhd"
|
||||
vhdl work "../../../../lib/FIFO/src/sync_fifo_ctrl.vhd"
|
||||
vhdl work "../../../../lib/FIFO/src/async_fifo_ctrl.vhd"
|
||||
vhdl work "../../src/systest/vga_test_irom_ld.vhdl"
|
||||
vhdl work "../../../../lib/uart/kcuart_tx.vhd"
|
||||
vhdl work "../../../../lib/uart/kcuart_rx.vhd"
|
||||
vhdl work "../../../../lib/uart/bbfifo_16x8.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/vga_timing.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/linefifo.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/clkgen_virtex4.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_cmd.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/reset_virtex4.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/fifo_sync.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/ddr_phy_virtex4.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/clockgen_virtex4.vhd"
|
||||
vhdl work "../../src/systest/vga_test_xrom_ld.vhdl"
|
||||
vhdl work "../../src/systest/cpu_embedded.vhd"
|
||||
vhdl work "../../../../lib/uart/uart_tx.vhd"
|
||||
vhdl work "../../../../lib/uart/uart_rx.vhd"
|
||||
vhdl work "../../../../lib/misc/lcd_port.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/vga_backend.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/char_gen.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_top.vhd"
|
||||
vhdl work "../../src/systest/systest.vhd"
|
||||
@@ -0,0 +1,337 @@
|
||||
#
|
||||
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
|
||||
# SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
|
||||
# XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
# AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
|
||||
# OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
|
||||
# IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
|
||||
# AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
|
||||
# FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
|
||||
# WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
|
||||
# IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
|
||||
# REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
|
||||
# INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
# FOR A PARTICULAR PURPOSE.
|
||||
#
|
||||
# (c) Copyright 2005 Xilinx, Inc.
|
||||
# All rights reserved.
|
||||
#
|
||||
|
||||
CONFIG STEPPING = "ES";
|
||||
|
||||
# Bus clock nets
|
||||
NET "clk" TNM_NET = "clk";
|
||||
TIMESPEC "TS_clk" = PERIOD "clk" 9.9 ns HIGH 50 %;
|
||||
|
||||
NET "inst_vga_backend/inst_clkgen/vga_clk0" TNM_NET = "vga_clk";
|
||||
TIMESPEC TS_unrelate = FROM clk TO vga_clk TIG;
|
||||
|
||||
NET "sys_clk_in" LOC = "AE14";
|
||||
#NET sys_clk_in IOSTANDARD = LVCMOS33;
|
||||
NET "sys_rst_n_in" LOC = "D6";
|
||||
NET sys_rst_n_in PULLUP;
|
||||
NET "sys_rst_n_in" TIG;
|
||||
NET "rst" TIG;
|
||||
|
||||
# Locate DCM/BUFG - Tools can probably figure them out automatically
|
||||
# but just LOC them down to be safe
|
||||
#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_0 LOC = DCM_ADV_X0Y2;
|
||||
#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_1 LOC = DCM_ADV_X0Y1;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
// Misc Board Signals
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
NET sys_error<0> LOC = V6;
|
||||
NET sys_error<1> LOC = L24;
|
||||
#NET sys_error<*> IOSTANDARD = LVCMOS33;
|
||||
NET sys_error<*> DRIVE = 2;
|
||||
NET sys_error<*> TIG;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
// RS-232
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
NET sys_rx LOC = W2;
|
||||
#NET sys_rx IOSTANDARD = LVCMOS33;
|
||||
NET sys_rx TIG;
|
||||
NET "sys_tx" LOC = "W1";
|
||||
#NET sys_tx IOSTANDARD = LVCMOS33;
|
||||
NET "sys_tx" TIG;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
// Buttons, LEDs, and DIP Switches
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
# GPLED 0-3
|
||||
NET "sys_led<0>" LOC = "G5"; #GPLED0
|
||||
NET "sys_led<1>" LOC = "G6"; #GPLED1
|
||||
NET "sys_led<2>" LOC = "A11"; #GPLED2
|
||||
NET "sys_led<3>" LOC = "A12"; #GPLED3
|
||||
# North-East-South-West-Center LEDs
|
||||
NET "sys_led<4>" LOC = "F9"; # W LED
|
||||
NET "sys_led<5>" LOC = "E2"; # N LED
|
||||
NET "sys_led<6>" LOC = "E10"; # E LED
|
||||
NET "sys_led<7>" LOC = "A5"; # S LED
|
||||
NET "sys_led<8>" LOC = "C6"; # C LED
|
||||
NET "sys_led<*>" TIG;
|
||||
NET "sys_led<*>" SLEW = SLOW;
|
||||
NET "sys_led<*>" DRIVE = 2;
|
||||
#NET "sys_led<*>" IOSTANDARD = LVCMOS33;
|
||||
# North-East-South-West-Center Buttons
|
||||
NET "sys_btn<0>" LOC = "E9"; # W Button
|
||||
NET "sys_btn<1>" LOC = "E7"; # N Button
|
||||
NET "sys_btn<2>" LOC = "F10"; # E Button
|
||||
NET "sys_btn<3>" LOC = "A6"; # S Button
|
||||
NET "sys_btn<4>" LOC = "B6"; # C Button
|
||||
NET "sys_btn<*>" TIG;
|
||||
NET "sys_btn<*>" PULLDOWN;
|
||||
#NET "sys_btn<*>" IOSTANDARD = LVCMOS33;
|
||||
# Dip Switches 1-8
|
||||
NET "sys_dip<7>" LOC = "U24"; # DIP SW 8
|
||||
NET "sys_dip<6>" LOC = "U25"; # DIP SW 7
|
||||
NET "sys_dip<5>" LOC = "V23"; # DIP SW 6
|
||||
NET "sys_dip<4>" LOC = "U23"; # DIP SW 5
|
||||
NET "sys_dip<3>" LOC = "U26"; # DIP SW 4
|
||||
NET "sys_dip<2>" LOC = "T26"; # DIP SW 3
|
||||
NET "sys_dip<1>" LOC = "R19"; # DIP SW 2
|
||||
NET "sys_dip<0>" LOC = "R20"; # DIP SW 1
|
||||
NET "sys_dip<*>" PULLDOWN;
|
||||
#NET "sys_dip<*>" IOSTANDARD = LVCMOS33;
|
||||
NET "sys_dip<*>" TIG;
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
// LCD
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
NET sys_lcd_e LOC = AE13; # LCD_E
|
||||
#NET sys_lcd_e IOSTANDARD = LVCMOS33;
|
||||
NET sys_lcd_e SLEW = SLOW;
|
||||
NET sys_lcd_e DRIVE = 2;
|
||||
NET sys_lcd_e TIG;
|
||||
NET sys_lcd_rs LOC = AC17; # LCD_RS
|
||||
#NET sys_lcd_rs IOSTANDARD = LVCMOS33;
|
||||
NET sys_lcd_rs SLEW = SLOW;
|
||||
NET sys_lcd_rs DRIVE = 2;
|
||||
NET sys_lcd_rs TIG;
|
||||
NET sys_lcd_rw LOC = AB17; # LCD_RW
|
||||
#NET sys_lcd_rw IOSTANDARD = LVCMOS33;
|
||||
NET sys_lcd_rw SLEW = SLOW;
|
||||
NET sys_lcd_rw DRIVE = 2;
|
||||
NET sys_lcd_rw TIG;
|
||||
NET sys_lcd_d<3> LOC = AF12; # LCD_DB7
|
||||
NET sys_lcd_d<2> LOC = AE12; # LCD_DB6
|
||||
NET sys_lcd_d<1> LOC = AC10; # LCD_DB5
|
||||
NET sys_lcd_d<0> LOC = AB10; # LCD_DB4
|
||||
#NET sys_lcd_d<*> IOSTANDARD = LVCMOS33;
|
||||
NET sys_lcd_d<*> SLEW = SLOW;
|
||||
NET sys_lcd_d<*> DRIVE = 2;
|
||||
NET sys_lcd_d<*> PULLDOWN;
|
||||
NET sys_lcd_d<*> TIG;
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# IO Pad Location Constraints / Properties for DDR Controllers
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
NET sys_sdr_a_q<0> LOC = C26; # DDR_A0
|
||||
NET sys_sdr_a_q<1> LOC = E17; # DDR_A1
|
||||
NET sys_sdr_a_q<2> LOC = D18; # DDR_A2
|
||||
NET sys_sdr_a_q<3> LOC = C19; # DDR_A3
|
||||
NET sys_sdr_a_q<4> LOC = F17; # DDR_A4
|
||||
NET sys_sdr_a_q<5> LOC = B18; # DDR_A5
|
||||
NET sys_sdr_a_q<6> LOC = B20; # DDR_A6
|
||||
NET sys_sdr_a_q<7> LOC = C20; # DDR_A7
|
||||
NET sys_sdr_a_q<8> LOC = D20; # DDR_A8
|
||||
NET sys_sdr_a_q<9> LOC = C21; # DDR_A9
|
||||
NET sys_sdr_a_q<10> LOC = A18; # DDR_A10
|
||||
NET sys_sdr_a_q<11> LOC = B21; # DDR_A11
|
||||
NET sys_sdr_a_q<12> LOC = A24; # DDR_A12
|
||||
NET sys_sdr_ba_q<0> LOC = B12; # DDR_BA0
|
||||
NET sys_sdr_ba_q<1> LOC = A16; # DDR_BA1
|
||||
NET sys_sdr_cas_qn LOC = F23; # DDR_CAS_N
|
||||
NET sys_sdr_cke_q LOC = G22; # DDR_CKE
|
||||
NET sys_sdr_cs_qn LOC = G21; # DDR_CS_N
|
||||
NET sys_sdr_ras_qn LOC = F24; # DDR_RAS_N
|
||||
NET sys_sdr_we_qn LOC = A23; # DDR_WE_N
|
||||
|
||||
NET sys_sdr_clk_p LOC = A10; # DDR_CK1_P
|
||||
NET sys_sdr_clk_fb LOC = B13; # DDR_CK1_P (FEEDBACK)
|
||||
NET sys_sdr_clk_n LOC = B10; # DDR_CK1_N
|
||||
|
||||
NET sys_sdr_dm_q<0> LOC = G19; # DDR_DM0
|
||||
NET sys_sdr_dm_q<1> LOC = G24; # DDR_DM1
|
||||
NET sys_sdr_dm_q<2> LOC = G20; # DDR_DM2
|
||||
NET sys_sdr_dm_q<3> LOC = C22; # DDR_DM3
|
||||
|
||||
NET sys_sdr_dqs_q<0> LOC = D25; # DDR_DQS0
|
||||
NET sys_sdr_dqs_q<1> LOC = G18; # DDR_DQS1
|
||||
NET sys_sdr_dqs_q<2> LOC = G17; # DDR_DQS2
|
||||
NET sys_sdr_dqs_q<3> LOC = D26; # DDR_DQS3
|
||||
|
||||
NET sys_sdr_data<0> LOC = H20; # DDR_D0
|
||||
NET sys_sdr_data<1> LOC = E23; # DDR_D1
|
||||
NET sys_sdr_data<2> LOC = H26; # DDR_D2
|
||||
NET sys_sdr_data<3> LOC = H22; # DDR_D3
|
||||
NET sys_sdr_data<4> LOC = E25; # DDR_D4
|
||||
NET sys_sdr_data<5> LOC = E26; # DDR_D5
|
||||
NET sys_sdr_data<6> LOC = F26; # DDR_D6
|
||||
NET sys_sdr_data<7> LOC = E24; # DDR_D7
|
||||
NET sys_sdr_data<8> LOC = E20; # DDR_D8
|
||||
NET sys_sdr_data<9> LOC = A22; # DDR_D9
|
||||
NET sys_sdr_data<10> LOC = C23; # DDR_D10
|
||||
NET sys_sdr_data<11> LOC = C24; # DDR_D11
|
||||
NET sys_sdr_data<12> LOC = A20; # DDR_D12
|
||||
NET sys_sdr_data<13> LOC = A21; # DDR_D13
|
||||
NET sys_sdr_data<14> LOC = D24; # DDR_D14
|
||||
NET sys_sdr_data<15> LOC = E18; # DDR_D15
|
||||
NET sys_sdr_data<16> LOC = F18; # DDR_D16
|
||||
NET sys_sdr_data<17> LOC = A19; # DDR_D17
|
||||
NET sys_sdr_data<18> LOC = F19; # DDR_D18
|
||||
NET sys_sdr_data<19> LOC = B23; # DDR_D19
|
||||
NET sys_sdr_data<20> LOC = E21; # DDR_D20
|
||||
NET sys_sdr_data<21> LOC = D22; # DDR_D21
|
||||
NET sys_sdr_data<22> LOC = D23; # DDR_D22
|
||||
NET sys_sdr_data<23> LOC = B24; # DDR_D23
|
||||
NET sys_sdr_data<24> LOC = E22; # DDR_D24
|
||||
NET sys_sdr_data<25> LOC = F20; # DDR_D25
|
||||
NET sys_sdr_data<26> LOC = H23; # DDR_D26
|
||||
NET sys_sdr_data<27> LOC = G25; # DDR_D27
|
||||
NET sys_sdr_data<28> LOC = G26; # DDR_D28
|
||||
NET sys_sdr_data<29> LOC = H25; # DDR_D29
|
||||
NET sys_sdr_data<30> LOC = H24; # DDR_D30
|
||||
NET sys_sdr_data<31> LOC = H21; # DDR_D31
|
||||
|
||||
NET sys_sdr_a_q<*> IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_a_q<*> FAST;
|
||||
|
||||
NET sys_sdr_ba_q<*> IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_ba_q<*> FAST;
|
||||
|
||||
NET sys_sdr_cas_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_cas_qn FAST;
|
||||
|
||||
NET sys_sdr_cke_q IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_cke_q FAST;
|
||||
|
||||
NET sys_sdr_clk_p IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_clk_p FAST;
|
||||
NET sys_sdr_clk_fb IOSTANDARD = LVCMOS25;
|
||||
NET sys_sdr_clk_fb IOBDELAY = NONE;
|
||||
NET sys_sdr_clk_n IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_clk_n FAST;
|
||||
|
||||
NET sys_sdr_cas_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_cas_qn FAST;
|
||||
|
||||
NET sys_sdr_cs_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_cs_qn FAST;
|
||||
|
||||
NET sys_sdr_ras_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_ras_qn FAST;
|
||||
|
||||
NET sys_sdr_we_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_we_qn FAST;
|
||||
|
||||
NET sys_sdr_dqs_q<*> IOSTANDARD = SSTL2_II;
|
||||
NET sys_sdr_dqs_q<*> IOBDELAY = NONE;
|
||||
NET sys_sdr_dqs_q<*> FAST;
|
||||
|
||||
NET sys_sdr_dm_q<*> IOSTANDARD = SSTL2_II;
|
||||
NET sys_sdr_dm_q<*> IOBDELAY = NONE;
|
||||
NET sys_sdr_dm_q<*> FAST;
|
||||
|
||||
NET sys_sdr_data<*> IOSTANDARD = SSTL2_II;
|
||||
NET sys_sdr_data<*> IOBDELAY = NONE;
|
||||
NET sys_sdr_data<*> FAST;
|
||||
|
||||
#NET "sys_sdr_data<*>" OFFSET=OUT 2.5 ns BEFORE "sys_sdr_clk_n";
|
||||
|
||||
|
||||
# Timing Constraint for DDR Feedback Clock
|
||||
NET sys_sdr_clk_fb FEEDBACK = 1 ns NET sys_sdr_clk_p;
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# IO Pad Location Constraints / Properties for TFT VGA LCD Controller
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
NET sys_vga_blue<0> LOC = M21; # VGA_B0
|
||||
NET sys_vga_blue<1> LOC = M26; # VGA_B1
|
||||
NET sys_vga_blue<2> LOC = L26; # VGA_B2
|
||||
NET sys_vga_blue<3> LOC = C5; # VGA_B3
|
||||
NET sys_vga_blue<4> LOC = C7; # VGA_B4
|
||||
NET sys_vga_blue<5> LOC = B7; # VGA_B5
|
||||
NET sys_vga_blue<6> LOC = G8; # VGA_B6
|
||||
NET sys_vga_blue<7> LOC = F8; # VGA_B7
|
||||
#NET sys_vga_blue<*> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_blue<*> SLEW = FAST;
|
||||
NET sys_vga_blue<*> DRIVE = 8;
|
||||
|
||||
NET sys_vga_clk LOC = AF8;
|
||||
NET sys_vga_clk IOSTANDARD = LVDCI_25;
|
||||
NET sys_vga_clk SLEW = FAST;
|
||||
NET sys_vga_clk DRIVE = 8;
|
||||
|
||||
NET sys_vga_green<0> LOC = M22; # VGA_G0
|
||||
NET sys_vga_green<1> LOC = M23; # VGA_G1
|
||||
NET sys_vga_green<2> LOC = M20; # VGA_G2
|
||||
NET sys_vga_green<3> LOC = E4; # VGA_G3
|
||||
NET sys_vga_green<4> LOC = D3; # VGA_G4
|
||||
NET sys_vga_green<5> LOC = H7; # VGA_G5
|
||||
NET sys_vga_green<6> LOC = H8; # VGA_G6
|
||||
NET sys_vga_green<7> LOC = C1; # VGA_G7
|
||||
#NET sys_vga_green<*> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_green<*> SLEW = FAST;
|
||||
NET sys_vga_green<*> DRIVE = 8;
|
||||
|
||||
NET sys_vga_hsync LOC = C10;
|
||||
NET sys_vga_hsync SLEW = FAST;
|
||||
NET sys_vga_hsync DRIVE = 8;
|
||||
#NET sys_vga_hsync IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET sys_vga_red<0> LOC = N23; #VGA_R0
|
||||
NET sys_vga_red<1> LOC = N24; #VGA_R1
|
||||
NET sys_vga_red<2> LOC = N25; #VGA_R2
|
||||
NET sys_vga_red<3> LOC = C2; #VGA_R3
|
||||
NET sys_vga_red<4> LOC = G7; #VGA_R4
|
||||
NET sys_vga_red<5> LOC = F7; #VGA_R5
|
||||
NET sys_vga_red<6> LOC = E5; #VGA_R6
|
||||
NET sys_vga_red<7> LOC = E6; #VGA_R7
|
||||
#NET sys_vga_red<*> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_red<*> SLEW = FAST;
|
||||
NET sys_vga_red<*> DRIVE = 8;
|
||||
|
||||
NET sys_vga_vsync LOC = A8;
|
||||
NET sys_vga_vsync SLEW = FAST;
|
||||
NET sys_vga_vsync DRIVE = 8;
|
||||
#NET sys_vga_vsync IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET sys_vga_blank_n LOC = M24;
|
||||
NET sys_vga_blank_n SLEW = FAST;
|
||||
NET sys_vga_blank_n DRIVE = 8;
|
||||
#NET sys_vga_blank_n IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET sys_vga_sync_n LOC = L23;
|
||||
NET sys_vga_sync_n SLEW = FAST;
|
||||
NET sys_vga_sync_n DRIVE = 8;
|
||||
#NET sys_vga_sync_n IOSTANDARD = LVCMOS33;
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# IO Pad Location Constraints / Properties for PS/2 Ports
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
#Keyboard
|
||||
NET sys_keyb_clk LOC = D2;
|
||||
NET sys_keyb_clk SLEW = SLOW;
|
||||
NET sys_keyb_clk DRIVE = 2;
|
||||
NET sys_keyb_clk TIG;
|
||||
NET sys_keyb_data LOC = G9;
|
||||
NET sys_keyb_data SLEW = SLOW;
|
||||
NET sys_keyb_data DRIVE = 2;
|
||||
NET sys_keyb_data TIG;
|
||||
|
||||
#Mouse
|
||||
NET sys_mouse_clk LOC = B14;
|
||||
NET sys_mouse_clk SLEW = SLOW;
|
||||
NET sys_mouse_clk DRIVE = 2;
|
||||
NET sys_mouse_clk TIG;
|
||||
NET sys_mouse_data LOC = C14;
|
||||
NET sys_mouse_data SLEW = SLOW;
|
||||
NET sys_mouse_data DRIVE = 2;
|
||||
NET sys_mouse_data TIG;
|
||||
|
||||
@@ -0,0 +1,33 @@
|
||||
-w
|
||||
-g DebugBitstream:No
|
||||
-g Binary:no
|
||||
-g CRC:Enable
|
||||
-g ConfigRate:4
|
||||
-g CclkPin:PullUp
|
||||
-g M0Pin:PullUp
|
||||
-g M1Pin:PullUp
|
||||
-g M2Pin:PullUp
|
||||
-g ProgPin:PullUp
|
||||
-g DonePin:PullUp
|
||||
-g InitPin:Pullup
|
||||
-g CsPin:Pullup
|
||||
-g DinPin:Pullup
|
||||
-g BusyPin:Pullup
|
||||
-g RdWrPin:Pullup
|
||||
-g TckPin:PullUp
|
||||
-g TdiPin:PullUp
|
||||
-g TdoPin:PullUp
|
||||
-g TmsPin:PullUp
|
||||
-g UnusedPin:PullDown
|
||||
-g UserID:0xBEEFBABE
|
||||
-g DCIUpdateMode:AsRequired
|
||||
-g StartUpClk:JtagClk
|
||||
-g DONE_cycle:4
|
||||
-g GTS_cycle:5
|
||||
-g GWE_cycle:6
|
||||
-g LCK_cycle:NoWait
|
||||
-g Match_cycle:Auto
|
||||
-g Security:None
|
||||
-g DonePipe:No
|
||||
-g DriveDone:No
|
||||
-g Encrypt:No
|
||||
@@ -0,0 +1,59 @@
|
||||
set -tmpdir "./xst/projnav.tmp"
|
||||
set -xsthdpdir "./xst"
|
||||
run
|
||||
-ifn systest.prj
|
||||
-ifmt mixed
|
||||
-ofn systest
|
||||
-ofmt NGC
|
||||
-p xc4vsx35-10-ff668
|
||||
-top systest
|
||||
-opt_mode Speed
|
||||
-opt_level 1
|
||||
-power NO
|
||||
-iuc NO
|
||||
-lso systest.lso
|
||||
-keep_hierarchy NO
|
||||
-rtlview Yes
|
||||
-glob_opt AllClockNets
|
||||
-read_cores YES
|
||||
-write_timing_constraints NO
|
||||
-cross_clock_analysis NO
|
||||
-hierarchy_separator /
|
||||
-bus_delimiter <>
|
||||
-case maintain
|
||||
-slice_utilization_ratio 100
|
||||
-bram_utilization_ratio 100
|
||||
-dsp_utilization_ratio 100
|
||||
-verilog2001 YES
|
||||
-fsm_extract YES -fsm_encoding Auto
|
||||
-safe_implementation No
|
||||
-fsm_style lut
|
||||
-ram_extract Yes
|
||||
-ram_style Auto
|
||||
-rom_extract Yes
|
||||
-mux_style Auto
|
||||
-decoder_extract YES
|
||||
-priority_extract YES
|
||||
-shreg_extract YES
|
||||
-shift_extract YES
|
||||
-xor_collapse YES
|
||||
-rom_style Auto
|
||||
-auto_bram_packing NO
|
||||
-mux_extract YES
|
||||
-resource_sharing YES
|
||||
-async_to_sync NO
|
||||
-use_dsp48 auto
|
||||
-iobuf YES
|
||||
-max_fanout 500
|
||||
-bufg 32
|
||||
-bufr 24
|
||||
-register_duplication YES
|
||||
-register_balancing No
|
||||
-slice_packing YES
|
||||
-optimize_primitives NO
|
||||
-use_clock_enable Auto
|
||||
-use_sync_set Auto
|
||||
-use_sync_reset Auto
|
||||
-iob auto
|
||||
-equivalent_register_removal NO
|
||||
-slice_utilization_ratio_maxmargin 5
|
||||
Reference in New Issue
Block a user