Initial version
Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@756 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
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## NOTE: Do not edit this file.
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##
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vlib work
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# RAMS
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vcom -explicit -93 "../../../misc/dpram_2w2r1c_sim.vhd"
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vcom -explicit -93 "../../../misc/dpram_2w2r.vhd"
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vcom -explicit -93 "../../../misc/dpram_1w2r1c_sim.vhd"
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vcom -explicit -93 "../../../misc/dpram_1w1r.vhd"
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vcom -explicit -93 "../../../misc/dpram_1w1r1c_sim.vhd"
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vcom -explicit -93 "../../../misc/dpram_1w1r2c_sim.vhd"
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vcom -explicit -93 "../../../misc/dpram_2w2r2c_sim.vhd"
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# FIFOS
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vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
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vcom -explicit -93 "../../../FIFO/src/gray_counter.vhd"
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vcom -explicit -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
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vcom -explicit -93 "../../../FIFO/src/fifo_sync.vhd"
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vcom -explicit -93 "../../../FIFO/src/fifo_async_ctrl.vhd"
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vcom -explicit -93 "../../../FIFO/src/fifo_async.vhd"
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# UART
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vcom -explicit -93 "../../../uart/bbfifo_16x8.vhd"
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vcom -explicit -93 "../../../uart/kcuart_rx.vhd"
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vcom -explicit -93 "../../../uart/kcuart_tx.vhd"
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vcom -explicit -93 "../../../uart/uart_rx.vhd"
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vcom -explicit -93 "../../../uart/uart_tx.vhd"
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vcom -explicit -93 "../../../uart/uart_wb.vhd"
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# GPIO
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vcom -explicit -93 "../../../misc/gpio_wb.vhd"
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# Async port
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vcom -explicit -93 "../../../misc/async_types.vhd"
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vcom -explicit -93 "../../../misc/async_port_wb.vhd"
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vcom -explicit -93 "../src/async_defs.vhd"
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# ROM
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vcom -explicit -93 "../src/bootloader.ROM.vhd"
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vcom -explicit -93 "../../../misc/rom_wb.vhd"
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# MIPS
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vcom -explicit -93 "../syn/ise101/netgen/synthesis/mips_top_synthesis.vhd"
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vcom -explicit -93 "../src/mips_top_syn.vhd"
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vcom -explicit -93 "../src/tb_mips_top.vhd"
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vsim -t 1ps -lib work tb_mips_top
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do {tb_mips_top_syn.wdo}
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view wave
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view structure
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view signals
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run 1500us
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onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate -divider {TOP interface}
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add wave -noupdate -format Logic /tb_mips_top/nmi
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add wave -noupdate -format Logic /tb_mips_top/rst
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add wave -noupdate -format Logic /tb_mips_top/clk
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add wave -noupdate -format Literal /tb_mips_top/debug
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add wave -noupdate -format Logic /tb_mips_top/stb_o
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add wave -noupdate -format Logic /tb_mips_top/ack_i
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add wave -noupdate -format Logic /tb_mips_top/srdy_i
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/addr_o
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dat_i
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dat_o
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add wave -noupdate -format Logic /tb_mips_top/we_o
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add wave -noupdate -format Literal /tb_mips_top/sel_o
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add wave -noupdate -format Logic /tb_mips_top/cyc_o
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add wave -noupdate -format Logic /tb_mips_top/mrdy_o
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add wave -noupdate -format Literal /tb_mips_top/int
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add wave -noupdate -divider BIU
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add wave -noupdate -divider {External components}
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add wave -noupdate -format Logic /tb_mips_top/clk
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo0
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo1
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpi0
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpi1
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add wave -noupdate -format Logic /tb_mips_top/inst_uart/tx_complete
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add wave -noupdate -format Logic /tb_mips_top/inst_uart/tx_empty
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add wave -noupdate -format Literal /tb_mips_top/inst_uart/uart_status_port
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add wave -noupdate -format Logic /tb_mips_top/rx
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add wave -noupdate -format Logic /tb_mips_top/tx
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add wave -noupdate -divider {Interrupt Timer}
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_gpio/timer_cnt
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_gpio/timer_cmp
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add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_en
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add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_inten
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add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_irq
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add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_ovl
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add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_irq_ack
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add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_cmp_we
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_gpio/reg_data_wr
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add wave -noupdate -format Logic /tb_mips_top/clk
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add wave -noupdate -format Logic /tb_mips_top/clk
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add wave -noupdate -format Literal /tb_mips_top/mem_area
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add wave -noupdate -format Literal /tb_mips_top/inst_flash_port/s
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add wave -noupdate -format Logic /tb_mips_top/inst_flash_port/ack
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add wave -noupdate -format Logic /tb_mips_top/stb_o
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add wave -noupdate -format Logic /tb_mips_top/srdy_i
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add wave -noupdate -format Logic /tb_mips_top/we_o
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add wave -noupdate -format Logic /tb_mips_top/inst_flash_port/we_i_r
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/addr_o
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_flash_port/addr_i_r
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add wave -noupdate -format Logic /tb_mips_top/inst_flash_port/page_mode_en
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add wave -noupdate -format Logic /tb_mips_top/inst_flash_port/rdy
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_a
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_d
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add wave -noupdate -format Logic /tb_mips_top/ack_i
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add wave -noupdate -format Logic /tb_mips_top/flash_cs_n
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add wave -noupdate -format Logic /tb_mips_top/flash_we_n
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add wave -noupdate -format Logic /tb_mips_top/flash_oe_n
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add wave -noupdate -format Literal /tb_mips_top/flash_be_n
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram_a
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram_d
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add wave -noupdate -format Logic /tb_mips_top/ack_i
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add wave -noupdate -format Logic /tb_mips_top/sram_cs_n
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add wave -noupdate -format Literal /tb_mips_top/sram_wr_n
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add wave -noupdate -format Logic /tb_mips_top/sram_oe_n
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add wave -noupdate -format Literal /tb_mips_top/sram_be_n
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add wave -noupdate -format Logic /tb_mips_top/inst_sram_port/page_mode_en_r
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add wave -noupdate -format Logic /tb_mips_top/inst_sram_port/do_page_read
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add wave -noupdate -format Logic /tb_mips_top/inst_sram_port/rdy
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add wave -noupdate -format Literal /tb_mips_top/inst_sram_port/s
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add wave -noupdate -divider ALU
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add wave -noupdate -format Logic /tb_mips_top/clk
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add wave -noupdate -divider PC
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add wave -noupdate -format Logic /tb_mips_top/clk
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add wave -noupdate -divider COP0
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add wave -noupdate -divider Pipestages
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add wave -noupdate -format Logic /tb_mips_top/clk
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add wave -noupdate -format Logic /tb_mips_top/clk
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add wave -noupdate -format Logic /tb_mips_top/clk
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add wave -noupdate -format Logic /tb_mips_top/clk
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add wave -noupdate -divider I-Cache
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add wave -noupdate -format Logic /tb_mips_top/clk
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add wave -noupdate -divider D-Cache
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add wave -noupdate -format Logic /tb_mips_top/rst
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add wave -noupdate -format Logic /tb_mips_top/clk
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo0
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo1
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {Cursor {521186431 ps} 0}
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configure wave -namecolwidth 188
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configure wave -valuecolwidth 100
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configure wave -justifyvalue left
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configure wave -signalnamewidth 1
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configure wave -snapdistance 10
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configure wave -datasetprefix 0
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configure wave -rowmargin 4
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configure wave -childrowmargin 2
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configure wave -gridoffset 0
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configure wave -gridperiod 100
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configure wave -griddelta 40
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configure wave -timeline 1
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update
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WaveRestoreZoom {168108075 ps} {1570099575 ps}
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--------------------------------------------------------------------------
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-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
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-- This file: JIPS top file
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--
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-- Copyright (C) 2008 J. Ahrensfeld
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-- For questions and ideas, please contact the author at jens@jayfield.org
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--
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--------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.ALL;
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library work;
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use work.mips_types.all;
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entity mips_top is
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Generic
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(
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icache_size : natural := 8192; -- words
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icache_line : natural := 8; -- words
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dcache_size : natural := 4096; -- words
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dcache_line : natural := 8 -- words
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);
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Port
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(
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debug : out unsigned(1 downto 0);
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eb : in STD_LOGIC;
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nmi : in STD_LOGIC;
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cpu_clk : in STD_LOGIC;
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RST_I : in STD_LOGIC;
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CLK_I : in STD_LOGIC;
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ACK_I : in STD_LOGIC;
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SRDY_I : in STD_LOGIC;
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ADDR_O : out unsigned(31 downto 0);
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DAT_I : in unsigned(31 downto 0);
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DAT_O : out unsigned(31 downto 0);
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WE_O : out STD_LOGIC;
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SEL_O : out unsigned(3 downto 0);
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CYC_O : out STD_LOGIC;
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STB_O : out STD_LOGIC;
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MRDY_O : out STD_LOGIC;
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INT : in unsigned (5 downto 0)
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);
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end mips_top;
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architecture rtl of mips_top is
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signal SEL_O_SLV : STD_LOGIC_VECTOR (3 downto 0);
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signal DAT_O_SLV : STD_LOGIC_VECTOR (31 downto 0);
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signal ADDR_O_SLV : STD_LOGIC_VECTOR (31 downto 0);
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signal DEBUG_SLV : STD_LOGIC_VECTOR (1 downto 0);
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begin
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SEL_O <= unsigned(SEL_O_SLV);
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DAT_O <= unsigned(DAT_O_SLV);
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ADDR_O <= unsigned(ADDR_O_SLV);
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DEBUG <= unsigned(DEBUG_SLV);
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inst_mips_top_syn : entity work.mips_top_syn
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PORT MAP
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(
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RST_I => RST_I,
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eb => eb,
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WE_O => WE_O,
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CYC_O => CYC_O,
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cpu_clk => cpu_clk,
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ACK_I => ACK_I,
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nmi => nmi,
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STB_O => STB_O,
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CLK_I => CLK_I,
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MRDY_O => MRDY_O,
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SRDY_I => SRDY_I,
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debug => DEBUG_SLV,
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DAT_O => DAT_O_SLV,
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SEL_O => SEL_O_SLV,
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ADDR_O => ADDR_O_SLV,
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DAT_I => STD_LOGIC_VECTOR(DAT_I),
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INT => STD_LOGIC_VECTOR(INT)
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);
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end rtl;
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