diff --git a/lib/CPUs/MIPS/sim/tb_mips_top_syn.fdo b/lib/CPUs/MIPS/sim/tb_mips_top_syn.fdo new file mode 100644 index 0000000..4c72deb --- /dev/null +++ b/lib/CPUs/MIPS/sim/tb_mips_top_syn.fdo @@ -0,0 +1,55 @@ +## NOTE: Do not edit this file. +## +vlib work + +# RAMS +vcom -explicit -93 "../../../misc/dpram_2w2r1c_sim.vhd" +vcom -explicit -93 "../../../misc/dpram_2w2r.vhd" +vcom -explicit -93 "../../../misc/dpram_1w2r1c_sim.vhd" +vcom -explicit -93 "../../../misc/dpram_1w1r.vhd" +vcom -explicit -93 "../../../misc/dpram_1w1r1c_sim.vhd" + +vcom -explicit -93 "../../../misc/dpram_1w1r2c_sim.vhd" +vcom -explicit -93 "../../../misc/dpram_2w2r2c_sim.vhd" + + +# FIFOS +vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd" +vcom -explicit -93 "../../../FIFO/src/gray_counter.vhd" +vcom -explicit -93 "../../../FIFO/src/fifo_sync_ctrl.vhd" +vcom -explicit -93 "../../../FIFO/src/fifo_sync.vhd" +vcom -explicit -93 "../../../FIFO/src/fifo_async_ctrl.vhd" +vcom -explicit -93 "../../../FIFO/src/fifo_async.vhd" + +# UART +vcom -explicit -93 "../../../uart/bbfifo_16x8.vhd" +vcom -explicit -93 "../../../uart/kcuart_rx.vhd" +vcom -explicit -93 "../../../uart/kcuart_tx.vhd" +vcom -explicit -93 "../../../uart/uart_rx.vhd" +vcom -explicit -93 "../../../uart/uart_tx.vhd" +vcom -explicit -93 "../../../uart/uart_wb.vhd" + +# GPIO +vcom -explicit -93 "../../../misc/gpio_wb.vhd" + +# Async port +vcom -explicit -93 "../../../misc/async_types.vhd" +vcom -explicit -93 "../../../misc/async_port_wb.vhd" +vcom -explicit -93 "../src/async_defs.vhd" + +# ROM +vcom -explicit -93 "../src/bootloader.ROM.vhd" +vcom -explicit -93 "../../../misc/rom_wb.vhd" + +# MIPS + +vcom -explicit -93 "../syn/ise101/netgen/synthesis/mips_top_synthesis.vhd" +vcom -explicit -93 "../src/mips_top_syn.vhd" + +vcom -explicit -93 "../src/tb_mips_top.vhd" +vsim -t 1ps -lib work tb_mips_top +do {tb_mips_top_syn.wdo} +view wave +view structure +view signals +run 1500us diff --git a/lib/CPUs/MIPS/sim/tb_mips_top_syn.wdo b/lib/CPUs/MIPS/sim/tb_mips_top_syn.wdo new file mode 100644 index 0000000..1dde5b7 --- /dev/null +++ b/lib/CPUs/MIPS/sim/tb_mips_top_syn.wdo @@ -0,0 +1,104 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -divider {TOP interface} +add wave -noupdate -format Logic /tb_mips_top/nmi +add wave -noupdate -format Logic /tb_mips_top/rst +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -format Literal /tb_mips_top/debug +add wave -noupdate -format Logic /tb_mips_top/stb_o +add wave -noupdate -format Logic /tb_mips_top/ack_i +add wave -noupdate -format Logic /tb_mips_top/srdy_i +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/addr_o +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dat_i +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dat_o +add wave -noupdate -format Logic /tb_mips_top/we_o +add wave -noupdate -format Literal /tb_mips_top/sel_o +add wave -noupdate -format Logic /tb_mips_top/cyc_o +add wave -noupdate -format Logic /tb_mips_top/mrdy_o +add wave -noupdate -format Literal /tb_mips_top/int +add wave -noupdate -divider BIU +add wave -noupdate -divider {External components} +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo0 +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo1 +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpi0 +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpi1 +add wave -noupdate -format Logic /tb_mips_top/inst_uart/tx_complete +add wave -noupdate -format Logic /tb_mips_top/inst_uart/tx_empty +add wave -noupdate -format Literal /tb_mips_top/inst_uart/uart_status_port +add wave -noupdate -format Logic /tb_mips_top/rx +add wave -noupdate -format Logic /tb_mips_top/tx +add wave -noupdate -divider {Interrupt Timer} +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_gpio/timer_cnt +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_gpio/timer_cmp +add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_en +add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_inten +add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_irq +add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_ovl +add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_irq_ack +add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_cmp_we +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_gpio/reg_data_wr +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -format Literal /tb_mips_top/mem_area +add wave -noupdate -format Literal /tb_mips_top/inst_flash_port/s +add wave -noupdate -format Logic /tb_mips_top/inst_flash_port/ack +add wave -noupdate -format Logic /tb_mips_top/stb_o +add wave -noupdate -format Logic /tb_mips_top/srdy_i +add wave -noupdate -format Logic /tb_mips_top/we_o +add wave -noupdate -format Logic /tb_mips_top/inst_flash_port/we_i_r +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/addr_o +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_flash_port/addr_i_r +add wave -noupdate -format Logic /tb_mips_top/inst_flash_port/page_mode_en +add wave -noupdate -format Logic /tb_mips_top/inst_flash_port/rdy +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_a +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_d +add wave -noupdate -format Logic /tb_mips_top/ack_i +add wave -noupdate -format Logic /tb_mips_top/flash_cs_n +add wave -noupdate -format Logic /tb_mips_top/flash_we_n +add wave -noupdate -format Logic /tb_mips_top/flash_oe_n +add wave -noupdate -format Literal /tb_mips_top/flash_be_n +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram_a +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram_d +add wave -noupdate -format Logic /tb_mips_top/ack_i +add wave -noupdate -format Logic /tb_mips_top/sram_cs_n +add wave -noupdate -format Literal /tb_mips_top/sram_wr_n +add wave -noupdate -format Logic /tb_mips_top/sram_oe_n +add wave -noupdate -format Literal /tb_mips_top/sram_be_n +add wave -noupdate -format Logic /tb_mips_top/inst_sram_port/page_mode_en_r +add wave -noupdate -format Logic /tb_mips_top/inst_sram_port/do_page_read +add wave -noupdate -format Logic /tb_mips_top/inst_sram_port/rdy +add wave -noupdate -format Literal /tb_mips_top/inst_sram_port/s +add wave -noupdate -divider ALU +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -divider PC +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -divider COP0 +add wave -noupdate -divider Pipestages +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -divider I-Cache +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -divider D-Cache +add wave -noupdate -format Logic /tb_mips_top/rst +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo0 +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo1 +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {Cursor {521186431 ps} 0} +configure wave -namecolwidth 188 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 100 +configure wave -griddelta 40 +configure wave -timeline 1 +update +WaveRestoreZoom {168108075 ps} {1570099575 ps} diff --git a/lib/CPUs/MIPS/src/mips_top_syn.vhd b/lib/CPUs/MIPS/src/mips_top_syn.vhd new file mode 100644 index 0000000..c7c99e8 --- /dev/null +++ b/lib/CPUs/MIPS/src/mips_top_syn.vhd @@ -0,0 +1,100 @@ +-------------------------------------------------------------------------- +-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL +-- This file: JIPS top file +-- +-- Copyright (C) 2008 J. Ahrensfeld +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +-- +-- For questions and ideas, please contact the author at jens@jayfield.org +-- +-------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +library work; +use work.mips_types.all; + +entity mips_top is + Generic + ( + icache_size : natural := 8192; -- words + icache_line : natural := 8; -- words + dcache_size : natural := 4096; -- words + dcache_line : natural := 8 -- words + ); + Port + ( + debug : out unsigned(1 downto 0); + eb : in STD_LOGIC; + nmi : in STD_LOGIC; + cpu_clk : in STD_LOGIC; + RST_I : in STD_LOGIC; + CLK_I : in STD_LOGIC; + ACK_I : in STD_LOGIC; + SRDY_I : in STD_LOGIC; + ADDR_O : out unsigned(31 downto 0); + DAT_I : in unsigned(31 downto 0); + DAT_O : out unsigned(31 downto 0); + WE_O : out STD_LOGIC; + SEL_O : out unsigned(3 downto 0); + CYC_O : out STD_LOGIC; + STB_O : out STD_LOGIC; + MRDY_O : out STD_LOGIC; + INT : in unsigned (5 downto 0) + ); + +end mips_top; + +architecture rtl of mips_top is + + signal SEL_O_SLV : STD_LOGIC_VECTOR (3 downto 0); + signal DAT_O_SLV : STD_LOGIC_VECTOR (31 downto 0); + signal ADDR_O_SLV : STD_LOGIC_VECTOR (31 downto 0); + signal DEBUG_SLV : STD_LOGIC_VECTOR (1 downto 0); + +begin + + SEL_O <= unsigned(SEL_O_SLV); + DAT_O <= unsigned(DAT_O_SLV); + ADDR_O <= unsigned(ADDR_O_SLV); + DEBUG <= unsigned(DEBUG_SLV); + +inst_mips_top_syn : entity work.mips_top_syn + PORT MAP + ( + RST_I => RST_I, + eb => eb, + WE_O => WE_O, + CYC_O => CYC_O, + cpu_clk => cpu_clk, + ACK_I => ACK_I, + nmi => nmi, + STB_O => STB_O, + CLK_I => CLK_I, + MRDY_O => MRDY_O, + SRDY_I => SRDY_I, + debug => DEBUG_SLV, + DAT_O => DAT_O_SLV, + SEL_O => SEL_O_SLV, + ADDR_O => ADDR_O_SLV, + DAT_I => STD_LOGIC_VECTOR(DAT_I), + INT => STD_LOGIC_VECTOR(INT) + ); + + + +end rtl;