jens
e5f5e1d0e3
Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@756 cc03376c-175c-47c8-b038-4cd826a8556b
101 lines
2.7 KiB
VHDL
101 lines
2.7 KiB
VHDL
--------------------------------------------------------------------------
|
|
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
|
|
-- This file: JIPS top file
|
|
--
|
|
-- Copyright (C) 2008 J. Ahrensfeld
|
|
--
|
|
-- This program is free software: you can redistribute it and/or modify
|
|
-- it under the terms of the GNU General Public License as published by
|
|
-- the Free Software Foundation, either version 3 of the License, or
|
|
-- (at your option) any later version.
|
|
--
|
|
-- This program is distributed in the hope that it will be useful,
|
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
-- GNU General Public License for more details.
|
|
--
|
|
-- You should have received a copy of the GNU General Public License
|
|
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
|
--
|
|
-- For questions and ideas, please contact the author at jens@jayfield.org
|
|
--
|
|
--------------------------------------------------------------------------
|
|
|
|
library IEEE;
|
|
use IEEE.STD_LOGIC_1164.ALL;
|
|
use IEEE.numeric_std.ALL;
|
|
|
|
library work;
|
|
use work.mips_types.all;
|
|
|
|
entity mips_top is
|
|
Generic
|
|
(
|
|
icache_size : natural := 8192; -- words
|
|
icache_line : natural := 8; -- words
|
|
dcache_size : natural := 4096; -- words
|
|
dcache_line : natural := 8 -- words
|
|
);
|
|
Port
|
|
(
|
|
debug : out unsigned(1 downto 0);
|
|
eb : in STD_LOGIC;
|
|
nmi : in STD_LOGIC;
|
|
cpu_clk : in STD_LOGIC;
|
|
RST_I : in STD_LOGIC;
|
|
CLK_I : in STD_LOGIC;
|
|
ACK_I : in STD_LOGIC;
|
|
SRDY_I : in STD_LOGIC;
|
|
ADDR_O : out unsigned(31 downto 0);
|
|
DAT_I : in unsigned(31 downto 0);
|
|
DAT_O : out unsigned(31 downto 0);
|
|
WE_O : out STD_LOGIC;
|
|
SEL_O : out unsigned(3 downto 0);
|
|
CYC_O : out STD_LOGIC;
|
|
STB_O : out STD_LOGIC;
|
|
MRDY_O : out STD_LOGIC;
|
|
INT : in unsigned (5 downto 0)
|
|
);
|
|
|
|
end mips_top;
|
|
|
|
architecture rtl of mips_top is
|
|
|
|
signal SEL_O_SLV : STD_LOGIC_VECTOR (3 downto 0);
|
|
signal DAT_O_SLV : STD_LOGIC_VECTOR (31 downto 0);
|
|
signal ADDR_O_SLV : STD_LOGIC_VECTOR (31 downto 0);
|
|
signal DEBUG_SLV : STD_LOGIC_VECTOR (1 downto 0);
|
|
|
|
begin
|
|
|
|
SEL_O <= unsigned(SEL_O_SLV);
|
|
DAT_O <= unsigned(DAT_O_SLV);
|
|
ADDR_O <= unsigned(ADDR_O_SLV);
|
|
DEBUG <= unsigned(DEBUG_SLV);
|
|
|
|
inst_mips_top_syn : entity work.mips_top_syn
|
|
PORT MAP
|
|
(
|
|
RST_I => RST_I,
|
|
eb => eb,
|
|
WE_O => WE_O,
|
|
CYC_O => CYC_O,
|
|
cpu_clk => cpu_clk,
|
|
ACK_I => ACK_I,
|
|
nmi => nmi,
|
|
STB_O => STB_O,
|
|
CLK_I => CLK_I,
|
|
MRDY_O => MRDY_O,
|
|
SRDY_I => SRDY_I,
|
|
debug => DEBUG_SLV,
|
|
DAT_O => DAT_O_SLV,
|
|
SEL_O => SEL_O_SLV,
|
|
ADDR_O => ADDR_O_SLV,
|
|
DAT_I => STD_LOGIC_VECTOR(DAT_I),
|
|
INT => STD_LOGIC_VECTOR(INT)
|
|
);
|
|
|
|
|
|
|
|
end rtl;
|