From e349fbcecf28eac0a03188b88c28685a94f0aed0 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Fri, 26 Apr 2013 10:42:07 +0000 Subject: [PATCH] - SDR-Clock now derived from clk_in, instead of sys_clk_fx Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@948 cc03376c-175c-47c8-b038-4cd826a8556b --- projects/mips_sys/src/clockgen_virtex4.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/mips_sys/src/clockgen_virtex4.vhd b/projects/mips_sys/src/clockgen_virtex4.vhd index 85ca4a5..b2ed5a0 100644 --- a/projects/mips_sys/src/clockgen_virtex4.vhd +++ b/projects/mips_sys/src/clockgen_virtex4.vhd @@ -231,7 +231,7 @@ inst_DCM_SDRCLK_0 : DCM_BASE CLKFX180 => open, -- 180 degree CLK synthesis out LOCKED => sdr0_lock, -- DCM LOCK status output CLKFB => sdr0_clk_fb_in, -- DCM clock feedback - CLKIN => sys_clkfx_bufg, -- Clock input (from IBUFG, BUFG or DCM) + CLKIN => sys_clk0_bufg, -- Clock input (from IBUFG, BUFG or DCM) RST => dcm_rst(1) -- DCM asynchronous reset input );