diff --git a/projects/mips_sys/src/clockgen_virtex4.vhd b/projects/mips_sys/src/clockgen_virtex4.vhd
index 85ca4a5..b2ed5a0 100644
--- a/projects/mips_sys/src/clockgen_virtex4.vhd
+++ b/projects/mips_sys/src/clockgen_virtex4.vhd
@@ -231,7 +231,7 @@ inst_DCM_SDRCLK_0 : DCM_BASE
 		CLKFX180 => open, -- 180 degree CLK synthesis out
 		LOCKED => sdr0_lock,     -- DCM LOCK status output
 		CLKFB => sdr0_clk_fb_in,       -- DCM clock feedback
-		CLKIN => sys_clkfx_bufg,       -- Clock input (from IBUFG, BUFG or DCM)
+		CLKIN => sys_clk0_bufg,       -- Clock input (from IBUFG, BUFG or DCM)
 		RST => dcm_rst(1)            -- DCM asynchronous reset input
 	);