diff --git a/lib/CPUs/MIPS/sim/tb_mips_top.fdo b/lib/CPUs/MIPS/sim/tb_mips_top.fdo index 811b0b8..9a51503 100644 --- a/lib/CPUs/MIPS/sim/tb_mips_top.fdo +++ b/lib/CPUs/MIPS/sim/tb_mips_top.fdo @@ -1,18 +1,35 @@ ## NOTE: Do not edit this file. ## vlib work + +# Misc vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd" + +# RAMS +vcom -explicit -93 "../../../misc/dpram_2w2r.vhd" +vcom -explicit -93 "../../../misc/dpram_1w1r.vhd" +vcom -explicit -93 "../../../misc/dpram_1w1r_dist.vhd" + +# FIFOS +vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd" +vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd" +vcom -explicit -93 "../../../FIFO/src/fifo_sync_dist.vhd" + +# MIPS vcom -explicit -93 "../src/core/mips_types.vhd" vcom -explicit -93 "../src/core/mips_instr.vhd" vcom -explicit -93 "../src/core/mips_idecode_rom.vhd" vcom -explicit -93 "../src/core/mips_reg.vhd" vcom -explicit -93 "../src/core/mips_shifter.vhd" vcom -explicit -93 "../src/core/mips_alu.vhd" +vcom -explicit -93 "../src/core/mips_muldiv.vhd" +vcom -explicit -93 "../src/core/mips_cop.vhd" +vcom -explicit -93 "../src/core/icache.vhd" +vcom -explicit -93 "../src/core/dcache.vhd" +vcom -explicit -93 "../src/core/mips_bui.vhd" vcom -explicit -93 "../src/core/mips_bcu.vhd" vcom -explicit -93 "../src/core/mips_pipeline.vhd" vcom -explicit -93 "../src/core/mips_top.vhd" -vcom -explicit -93 "../asm/fibonacci.vhd" -vcom -explicit -93 "../src/ram.vhd" vcom -explicit -93 "../src/tb_mips_top.vhd" vsim -t 1ps -lib work tb_mips_top do {tb_mips_top.wdo} diff --git a/lib/CPUs/MIPS/sim/tb_mips_top.wdo b/lib/CPUs/MIPS/sim/tb_mips_top.wdo index 833e5af..4b62a91 100644 --- a/lib/CPUs/MIPS/sim/tb_mips_top.wdo +++ b/lib/CPUs/MIPS/sim/tb_mips_top.wdo @@ -1,40 +1,31 @@ onerror {resume} quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_mips_top/rst -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Logic /tb_mips_top/cpu_halt -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/irom_data -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/irom_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_din -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_dout -add wave -noupdate -format Logic /tb_mips_top/dmem_re -add wave -noupdate -format Logic /tb_mips_top/dmem_we -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_ram/sram +add wave -noupdate -divider {TOP interface} +add wave -noupdate -format Literal /tb_mips_top/debug +add wave -noupdate -format Logic /tb_mips_top/rst_i +add wave -noupdate -format Logic /tb_mips_top/clk_i +add wave -noupdate -format Logic /tb_mips_top/ack_i +add wave -noupdate -format Logic /tb_mips_top/srdy_i +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/addr_o +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dat_i +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dat_o +add wave -noupdate -format Logic /tb_mips_top/we_o +add wave -noupdate -format Literal /tb_mips_top/sel_o +add wave -noupdate -format Logic /tb_mips_top/cyc_o +add wave -noupdate -format Logic /tb_mips_top/stb_o +add wave -noupdate -format Logic /tb_mips_top/mrdy_o +add wave -noupdate -format Literal /tb_mips_top/int add wave -noupdate -divider ALU add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/hdu -add wave -noupdate -format Logic /tb_mips_top/clk add wave -noupdate -divider PC add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/pc -add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/exception -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/stall add wave -noupdate -divider PC -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/if_stage -add wave -noupdate -format Logic /tb_mips_top/clk add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/id_stage -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_din add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/ex_stage -add wave -noupdate -format Logic /tb_mips_top/clk add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/mem_stage -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_din add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/wb_stage -add wave -noupdate -format Logic /tb_mips_top/clk TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {0 ps} 0} +WaveRestoreCursors {{Cursor 1} {21313433 ps} 0} configure wave -namecolwidth 188 configure wave -valuecolwidth 100 configure wave -justifyvalue left diff --git a/lib/CPUs/MIPS/src/tb_mips_top.vhd b/lib/CPUs/MIPS/src/tb_mips_top.vhd index 0bf5fed..5b171a7 100644 --- a/lib/CPUs/MIPS/src/tb_mips_top.vhd +++ b/lib/CPUs/MIPS/src/tb_mips_top.vhd @@ -37,136 +37,78 @@ END tb_mips_top; ARCHITECTURE behavior OF tb_mips_top IS COMPONENT mips_top - Port + PORT ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - halt : in STD_LOGIC; - imem_din : in unsigned (WORD_WIDTH-1 downto 0); - imem_addr : out unsigned (WORD_WIDTH-1 downto 0); - dmem_we : out STD_LOGIC; - dmem_re : out STD_LOGIC; - dmem_din : in unsigned (WORD_WIDTH-1 downto 0); - dmem_dout : out unsigned (WORD_WIDTH-1 downto 0); - dmem_addr : out unsigned (WORD_WIDTH-1 downto 0) - - ); - END COMPONENT; - - COMPONENT rom - Port - ( - clk : in STD_LOGIC; - addr : in word_t; - dout : out word_t - ); - END COMPONENT; - - COMPONENT ram - Generic - ( - word_addr_width : integer - ); - Port - ( - clk : in STD_LOGIC; - we : in STD_LOGIC; - addr : in word_t; - din : in word_t; - dout : out word_t + debug : out unsigned(1 downto 0); + RST_I : in STD_LOGIC; + CLK_I : in STD_LOGIC; + ACK_I : in STD_LOGIC; + SRDY_I : in STD_LOGIC; + ADDR_O : out word_t; + DAT_I : in word_t; + DAT_O : out word_t; + WE_O : out STD_LOGIC; + SEL_O : out unsigned(3 downto 0); + CYC_O : out STD_LOGIC; + STB_O : out STD_LOGIC; + MRDY_O : out STD_LOGIC; + INT : in unsigned (5 downto 0) ); END COMPONENT; constant CLK_PERIOD : time := 10 ns; - signal rst : std_logic := '1'; - signal clk : std_logic := '1'; - signal cpu_halt : std_logic; - signal irom_data : word_t := (others => '-'); - signal irom_addr : word_t; - signal dmem_din : word_t := (others => '-'); - signal dmem_dout : word_t; - signal dmem_addr : word_t; - signal dmem_we : std_logic; - signal dmem_re : std_logic; + signal debug : unsigned(1 downto 0); + signal RST_I : STD_LOGIC := '1'; + signal CLK_I : STD_LOGIC := '0'; + signal ACK_I : STD_LOGIC := '0'; + signal SRDY_I : STD_LOGIC := '0'; + signal ADDR_O : word_t; + signal DAT_I : word_t := (others => '0'); + signal DAT_O : word_t; + signal WE_O : STD_LOGIC; + signal SEL_O : unsigned(3 downto 0); + signal CYC_O : STD_LOGIC; + signal STB_O : STD_LOGIC; + signal MRDY_O : STD_LOGIC; + signal INT : unsigned (5 downto 0) := (others => '0'); BEGIN uut: mips_top - PORT MAP( - rst => rst, - clk => clk, - halt => cpu_halt, - imem_din => irom_data, - imem_addr => irom_addr, - dmem_we => dmem_we, - dmem_re => dmem_re, - dmem_din => dmem_din, - dmem_dout => dmem_dout, - dmem_addr => dmem_addr - ); - -inst_rom: rom PORT MAP ( - clk => clk, - addr => irom_addr, - dout => irom_data - ); - -inst_ram: ram - GENERIC MAP - ( - word_addr_width => 6 - ) - PORT MAP - ( - clk => clk, - we => dmem_we, - addr => dmem_addr, - din => dmem_dout, - dout => dmem_din + debug => debug, + RST_I => RST_I, + CLK_I => CLK_I, + ACK_I => ACK_I, + SRDY_I => SRDY_I, + ADDR_O => ADDR_O, + DAT_I => DAT_I, + DAT_O => DAT_O, + WE_O => WE_O, + SEL_O => SEL_O, + CYC_O => CYC_O, + STB_O => STB_O, + MRDY_O => MRDY_O, + INT => INT ); CLK_GEN: process begin wait for CLK_PERIOD/2; - clk <= not clk; - end process; - -HLT_GEN: - process(rst, clk) - subtype cnt_t is natural range 0 to 2; - variable cnt : cnt_t; - begin - if rst = '1' then - cnt := cnt_t'high; - cpu_halt <= '0'; - elsif rising_edge(clk) then - cpu_halt <= '0'; - if cnt /= 0 then - cnt := cnt - 1; - else - cnt := cnt_t'high; - cpu_halt <= '1'; - end if; - end if; + CLK_I <= not CLK_I; end process; STIMULUS: process begin --- for i in 0 to instr_name_array'length-1 loop --- fprint(RESULT, L,"%d %s\n", fo(i), instr_name_array(i)); --- end loop; wait for 3*CLK_PERIOD; - wait until rising_edge(clk); - rst <= '0'; - wait for 2*CLK_PERIOD; - --- assert false report "Test finished" severity error; + wait until rising_edge(CLK_I); + RST_I <= '0'; + wait; end process;