diff --git a/lib/filter/src/delay_line.vhd b/lib/filter/src/delay_line.vhd
index 45edf19..00aa13c 100644
--- a/lib/filter/src/delay_line.vhd
+++ b/lib/filter/src/delay_line.vhd
@@ -40,6 +40,7 @@ Generic
 );
 Port
 (
+	rst			: in std_logic;
 	clk			: in std_logic;
 	ce			: in std_logic;
 	shift_en	: in std_logic;
@@ -49,7 +50,7 @@ Port
 );
 end delay_line;
 
-architecture Behavioral of delay_line is
+architecture reg_based of delay_line is
 
 	-------------------------------------------------------------------------------
 	subtype word_t is sfixed(shi(nbits, nbits_frac) downto slo(nbits, nbits_frac));
@@ -79,4 +80,65 @@ shift_register:
 	-- Finished instantiation
 	----------------------------------------
 	
-end Behavioral;
+end reg_based;
+
+architecture ram_based of delay_line is
+
+	-------------------------------------------------------------------------------
+	signal count : natural range 0 to ntaps-1;
+	signal addr_w : unsigned(NextExpBaseTwo(ntaps)-1 downto 0);
+	signal addr_r : unsigned(NextExpBaseTwo(ntaps)-1 downto 0);
+	signal ram_w : unsigned(nbits-1 downto 0);
+	signal ram_r : unsigned(nbits-1 downto 0);
+
+	-------------------------------------------------------------------------------
+begin
+
+	addr_w	<= to_unsigned(count, addr_w'length);
+	addr_r	<= addr_w + not to_unsigned(delay, addr_w'length);
+	
+	ram_w	<= unsigned(din);
+	dout	<= sfixed(ram_r);
+
+counter:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				count <= 0;
+			elsif ce = '1' then
+				if shift_en = '1' then
+					if count /= ntaps-1 then
+						count <= count + 1;
+					else
+						count <= 0;
+					end if;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	inst_dpram_1w1r: entity work.dpram_1w1r
+	GENERIC MAP
+	(
+		addr_width	=> NextExpBaseTwo(ntaps),
+		data_width	=> nbits
+	)
+	PORT MAP (
+		clka	=> clk,
+		clkb	=> clk,
+		en_a	=> ce,
+		en_b	=> ce,
+		we_a	=> shift_en,
+		addr_a	=> addr_w,
+		addr_b	=> addr_r,
+		din_a	=> ram_w,
+		dout_b	=> ram_r
+	);
+	
+
+	----------------------------------------
+	-- Finished instantiation
+	----------------------------------------
+	
+end ram_based;