From 989fe72ddbd9e47f9da36af743cda834aee964f7 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Fri, 30 Oct 2009 10:49:15 +0000 Subject: [PATCH] - read-page cycle is minimum 2 cycles - change assertion check: Read page pulse length must be greater than one Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@563 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/misc/async_port_wb.vhd | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/misc/async_port_wb.vhd b/lib/misc/async_port_wb.vhd index 1c5d3c3..26fa4af 100644 --- a/lib/misc/async_port_wb.vhd +++ b/lib/misc/async_port_wb.vhd @@ -1,5 +1,5 @@ ----------------------------------------------------------------------- --- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.8 2009-10-29 22:56:20 Jens Exp $ +-- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.9 2009-10-30 10:49:15 Jens Exp $ ----------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; @@ -74,7 +74,7 @@ architecture Behavioral of async_port_wb is ASSERT async_timespec.ncyc_pulse_rd > 0 report "Read pulse length must be greater than zero!" severity failure; ASSERT async_timespec.ncyc_pulse_wr > 0 report "Write pulse length must be greater than zero!" severity failure; - ASSERT (not async_timespec.can_page_rd OR (async_timespec.ncyc_pulse_page_rd > 0)) report "Read page pulse length must be greater than zero!" severity failure; + ASSERT (not async_timespec.can_page_rd OR (async_timespec.ncyc_pulse_page_rd > 1)) report "Read page pulse length must be greater than one!" severity failure; SRDY_O <= CYC_I and rdyo; en <= CYC_I and STB_I;