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- FIFO: control extra read register using generic "add_extra_read_register". Default = false

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git-svn-id: http://moon:8086/svn/vhdl/trunk@1614 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2021-03-31 10:18:26 +00:00
parent 556dc410f5
commit 9360547eab
2 changed files with 29 additions and 5 deletions
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lib/FIFO/src/fifo_async.vhd
+15 -3
View File
@@ -35,8 +35,8 @@ entity fifo_async is
almost_empty_thresh : integer := 2; almost_empty_thresh : integer := 2;
allow_full_writes : boolean := false; allow_full_writes : boolean := false;
allow_empty_reads : boolean := false; allow_empty_reads : boolean := false;
do_last_read_update : boolean := true do_last_read_update : boolean := true;
add_extra_read_register : boolean := false
); );
Port Port
( (
@@ -65,6 +65,9 @@ architecture Behavioral of fifo_async is
begin begin
gen_extra_regs:
if add_extra_read_register generate
inst_reg_stage: entity work.reg_stage inst_reg_stage: entity work.reg_stage
GENERIC MAP GENERIC MAP
( (
@@ -85,7 +88,8 @@ begin
fifo_rd <= not reg_full; fifo_rd <= not reg_full;
fifo_empty <= not reg_vld; fifo_empty <= not reg_vld;
reg_we <= not fifo_empty_s; reg_we <= not fifo_empty_s;
end generate;
inst_fifo_async_stage: entity work.fifo_async_stage inst_fifo_async_stage: entity work.fifo_async_stage
GENERIC MAP GENERIC MAP
( (
@@ -113,5 +117,13 @@ begin
); );
gen_no_extra_regs:
if not add_extra_read_register generate
fifo_rd <= re;
fifo_empty <= fifo_empty_s;
data_r <= fifo_dout;
end generate;
end Behavioral; end Behavioral;
lib/FIFO/src/fifo_sync.vhd
+14 -2
View File
@@ -35,8 +35,8 @@ entity fifo_sync is
almost_empty_thresh : integer := 2; almost_empty_thresh : integer := 2;
allow_full_writes : boolean := false; allow_full_writes : boolean := false;
allow_empty_reads : boolean := false; allow_empty_reads : boolean := false;
do_last_read_update : boolean := true do_last_read_update : boolean := true;
add_extra_read_register : boolean := false
); );
Port Port
( (
@@ -64,6 +64,9 @@ architecture Behavioral of fifo_sync is
begin begin
gen_extra_regs:
if add_extra_read_register generate
inst_reg_stage: entity work.reg_stage inst_reg_stage: entity work.reg_stage
GENERIC MAP GENERIC MAP
( (
@@ -84,6 +87,7 @@ begin
fifo_rd <= not reg_full; fifo_rd <= not reg_full;
fifo_empty <= not reg_vld; fifo_empty <= not reg_vld;
reg_we <= not fifo_empty_s; reg_we <= not fifo_empty_s;
end generate;
inst_fifo_sync_stage: entity work.fifo_sync_stage inst_fifo_sync_stage: entity work.fifo_sync_stage
GENERIC MAP GENERIC MAP
@@ -111,5 +115,13 @@ begin
); );
gen_no_extra_regs:
if not add_extra_read_register generate
fifo_rd <= re;
fifo_empty <= fifo_empty_s;
data_r <= fifo_dout;
end generate;
end Behavioral; end Behavioral;