jens
9360547eab
git-svn-id: http://moon:8086/svn/vhdl/trunk@1614 cc03376c-175c-47c8-b038-4cd826a8556b
130 lines
3.3 KiB
VHDL
130 lines
3.3 KiB
VHDL
-------------------------------------------------------------------------
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-- Project: FIFO, generic FIFOs written in VHDL
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-- Release 1
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--
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-- Copyright (C) 2007 J. Ahrensfeld
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--
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-- This library is free software; you can redistribute it and/or
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-- modify it under the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either
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-- version 2.1 of the License, or (at your option) any later version.
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--
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-- This library is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- Lesser General Public License for more details.
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--
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-- You should have received a copy of the GNU Lesser General Public
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-- License along with this library; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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--
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-- For questions and ideas, please contact the author at jens@jayfield.org
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--
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-----------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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entity fifo_async is
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Generic
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(
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addr_width : natural := 3;
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data_width : natural := 8;
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almost_full_thresh : integer := 6;
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almost_empty_thresh : integer := 2;
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allow_full_writes : boolean := false;
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allow_empty_reads : boolean := false;
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do_last_read_update : boolean := true;
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add_extra_read_register : boolean := false
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);
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Port
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(
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rst : in STD_LOGIC;
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clk_w : in STD_LOGIC;
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clk_r : in STD_LOGIC;
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we : in STD_LOGIC;
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re : in STD_LOGIC;
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fifo_full : out STD_LOGIC;
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fifo_empty : out STD_LOGIC;
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fifo_afull : out STD_LOGIC;
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fifo_aempty : out STD_LOGIC;
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data_w : in unsigned (data_width-1 downto 0);
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data_r : out unsigned (data_width-1 downto 0)
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);
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end fifo_async;
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architecture Behavioral of fifo_async is
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signal reg_we : STD_LOGIC;
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signal reg_vld : STD_LOGIC;
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signal reg_full : STD_LOGIC;
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signal fifo_dout : unsigned (data_width-1 downto 0);
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signal fifo_rd : STD_LOGIC;
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signal fifo_empty_s : STD_LOGIC;
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begin
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gen_extra_regs:
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if add_extra_read_register generate
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inst_reg_stage: entity work.reg_stage
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GENERIC MAP
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(
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data_width => data_width
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)
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PORT MAP
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(
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rst => rst,
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clk => clk_r,
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we => reg_we,
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re => re,
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din => fifo_dout,
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dout => data_r,
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full => reg_full,
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vld_dout => reg_vld
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);
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fifo_rd <= not reg_full;
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fifo_empty <= not reg_vld;
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reg_we <= not fifo_empty_s;
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end generate;
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inst_fifo_async_stage: entity work.fifo_async_stage
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GENERIC MAP
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(
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data_width => data_width,
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addr_width => addr_width,
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almost_full_thresh => almost_full_thresh,
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almost_empty_thresh => almost_empty_thresh,
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allow_full_writes => allow_full_writes,
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allow_empty_reads => allow_empty_reads,
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do_last_read_update => do_last_read_update
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)
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PORT MAP
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(
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rst => rst,
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clk_w => clk_w,
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clk_r => clk_r,
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we => we,
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re => fifo_rd,
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data_w => data_w,
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data_r => fifo_dout,
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fifo_full => fifo_full,
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fifo_empty => fifo_empty_s,
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fifo_afull => fifo_afull,
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fifo_aempty => fifo_aempty
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);
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gen_no_extra_regs:
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if not add_extra_read_register generate
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fifo_rd <= re;
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fifo_empty <= fifo_empty_s;
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data_r <= fifo_dout;
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end generate;
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end Behavioral;
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