From 9360547eab0ea8802c22d112ba9297e0c2f890ea Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Wed, 31 Mar 2021 10:18:26 +0000 Subject: [PATCH] - FIFO: control extra read register using generic "add_extra_read_register". Default = false git-svn-id: http://moon:8086/svn/vhdl/trunk@1614 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/FIFO/src/fifo_async.vhd | 18 +++++++++++++++--- lib/FIFO/src/fifo_sync.vhd | 16 ++++++++++++++-- 2 files changed, 29 insertions(+), 5 deletions(-) diff --git a/lib/FIFO/src/fifo_async.vhd b/lib/FIFO/src/fifo_async.vhd index e00b732..4e6c1ba 100644 --- a/lib/FIFO/src/fifo_async.vhd +++ b/lib/FIFO/src/fifo_async.vhd @@ -35,8 +35,8 @@ entity fifo_async is almost_empty_thresh : integer := 2; allow_full_writes : boolean := false; allow_empty_reads : boolean := false; - do_last_read_update : boolean := true - + do_last_read_update : boolean := true; + add_extra_read_register : boolean := false ); Port ( @@ -65,6 +65,9 @@ architecture Behavioral of fifo_async is begin +gen_extra_regs: +if add_extra_read_register generate + inst_reg_stage: entity work.reg_stage GENERIC MAP ( @@ -85,7 +88,8 @@ begin fifo_rd <= not reg_full; fifo_empty <= not reg_vld; reg_we <= not fifo_empty_s; - +end generate; + inst_fifo_async_stage: entity work.fifo_async_stage GENERIC MAP ( @@ -113,5 +117,13 @@ begin ); +gen_no_extra_regs: +if not add_extra_read_register generate + + fifo_rd <= re; + fifo_empty <= fifo_empty_s; + data_r <= fifo_dout; +end generate; + end Behavioral; diff --git a/lib/FIFO/src/fifo_sync.vhd b/lib/FIFO/src/fifo_sync.vhd index c85002f..ee1706e 100644 --- a/lib/FIFO/src/fifo_sync.vhd +++ b/lib/FIFO/src/fifo_sync.vhd @@ -35,8 +35,8 @@ entity fifo_sync is almost_empty_thresh : integer := 2; allow_full_writes : boolean := false; allow_empty_reads : boolean := false; - do_last_read_update : boolean := true - + do_last_read_update : boolean := true; + add_extra_read_register : boolean := false ); Port ( @@ -64,6 +64,9 @@ architecture Behavioral of fifo_sync is begin +gen_extra_regs: +if add_extra_read_register generate + inst_reg_stage: entity work.reg_stage GENERIC MAP ( @@ -84,6 +87,7 @@ begin fifo_rd <= not reg_full; fifo_empty <= not reg_vld; reg_we <= not fifo_empty_s; +end generate; inst_fifo_sync_stage: entity work.fifo_sync_stage GENERIC MAP @@ -111,5 +115,13 @@ begin ); +gen_no_extra_regs: +if not add_extra_read_register generate + + fifo_rd <= re; + fifo_empty <= fifo_empty_s; + data_r <= fifo_dout; +end generate; + end Behavioral;