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vhdl/projects/mips_sys/ise101/mips_sys/mips_sys.par
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jens 7f780a37a5 - added mips_sys full flow 
git-svn-id: http://moon:8086/svn/vhdl/trunk@1129 cc03376c-175c-47c8-b038-4cd826a8556b
2015-05-20 21:54:44 +00:00

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Release 10.1.03 par K.39 (lin64)
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
callisto:: Wed May 20 23:17:06 2015
par -w -intstyle xflow -ol high -xe n -t 1 mips_sys_map.ncd mips_sys.ncd
mips_sys.pcf
Constraints file: mips_sys.pcf.
Loading device for application Rf_Device from file '4vsx35.nph' in environment /home/jens/Xilinx/10.1/ISE.
"mips_sys" is an NCD, version 3.2, device xc4vsx35, package ff668, speed -10
This design is using the default stepping level (major silicon revision) for this device (1). Unless your design is
targeted at devices of this stepping level, it is recommended that you explicitly specify the stepping level of the
parts you will be using. This will allow the tools to take advantage of any available performance and functional
enhancements for this device. The latest stepping level for this device is '2'. Additional information on "stepping
level" is available at support.xilinx.com.
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For
the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". For a
balance between the fastest runtime and best performance, set the effort level to "med".
WARNING:Timing:3262 - Feedback on DCM or PLL inst_clockgen/inst_DCM_SDRCLK_0 forms an incomplete loop. The Tdcmino
calculation will be invalid. If the DCM or PLL uses external feedback, please apply the FEEDBACK constraint to
indicate the external board delay. Consult the Constraints Guide for further information on how to apply the FEEDBACK
constraint.
Device speed data version: "PRODUCTION 1.68 2008-07-25".
Device Utilization Summary:
Number of BSCANs 1 out of 4 25%
Number of BUFGs 14 out of 32 43%
Number of DCM_ADVs 4 out of 8 50%
Number of ILOGICs 93 out of 448 20%
Number of External IOBs 248 out of 448 55%
Number of LOCed IOBs 0 out of 248 0%
Number of OLOGICs 192 out of 448 42%
Number of RAMB16s 74 out of 192 38%
Number of Slices 7737 out of 15360 50%
Number of SLICEMs 660 out of 7680 8%
Overall effort level (-ol): High
Router effort level (-rl): High
Starting Router
Phase 1: 60308 unrouted; REAL time: 10 secs
Phase 2: 51172 unrouted; REAL time: 11 secs
Phase 3: 18782 unrouted; REAL time: 17 secs
Phase 4: 18782 unrouted; (446154) REAL time: 17 secs
Phase 5: 19345 unrouted; (932) REAL time: 26 secs
Phase 6: 0 unrouted; (8225) REAL time: 48 secs
Updating file: mips_sys.ncd with current fully routed design.
Phase 7: 0 unrouted; (96274) REAL time: 2 mins 53 secs
Phase 8: 0 unrouted; (20056) REAL time: 3 mins 18 secs
Phase 9: 0 unrouted; (20056) REAL time: 3 mins 32 secs
Phase 10: 0 unrouted; (20056) REAL time: 3 mins 32 secs
Phase 11: 0 unrouted; (3379) REAL time: 4 mins 19 secs
Phase 12: 0 unrouted; (3379) REAL time: 4 mins 25 secs
Phase 13: 0 unrouted; (3379) REAL time: 4 mins 33 secs
Total REAL time to Router completion: 4 mins 33 secs
Total CPU time to Router completion: 4 mins 32 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| CLK_O |BUFGCTRL_X0Y25| No | 2958 | 0.637 | 3.123 |
+---------------------+--------------+------+------+------------+-------------+
| sys_clk_in_IBUFG |BUFGCTRL_X0Y27| No | 59 | 0.315 | 2.895 |
+---------------------+--------------+------+------+------------+-------------+
| cpu_clk |BUFGCTRL_X0Y22| No | 1778 | 0.512 | 2.999 |
+---------------------+--------------+------+------+------------+-------------+
| sdram_clk270 |BUFGCTRL_X0Y16| No | 36 | 0.165 | 3.041 |
+---------------------+--------------+------+------+------------+-------------+
| sdram_clk270var |BUFGCTRL_X0Y20| No | 32 | 0.040 | 3.041 |
+---------------------+--------------+------+------+------------+-------------+
|sys_phy_rx_clk_BUFGP | | | | | |
| |BUFGCTRL_X0Y24| No | 240 | 0.398 | 2.916 |
+---------------------+--------------+------+------+------------+-------------+
| vga_clk |BUFGCTRL_X0Y17| No | 184 | 0.448 | 3.000 |
+---------------------+--------------+------+------+------------+-------------+
|sys_ac97_bit_clk_IBU | | | | | |
| F |BUFGCTRL_X0Y10| No | 245 | 0.401 | 3.040 |
+---------------------+--------------+------+------+------------+-------------+
|inst_rom_wb/inst_rom | | | | | |
| /bs_clk1 |BUFGCTRL_X0Y31| No | 73 | 0.292 | 2.948 |
+---------------------+--------------+------+------+------------+-------------+
|inst_rom_wb/inst_rom | | | | | |
| /bs_update1 |BUFGCTRL_X0Y30| No | 4 | 0.228 | 2.940 |
+---------------------+--------------+------+------+------------+-------------+
| sdram_clk0 |BUFGCTRL_X0Y28| No | 231 | 0.508 | 2.994 |
+---------------------+--------------+------+------+------------+-------------+
|sys_phy_tx_clk_BUFGP | | | | | |
| |BUFGCTRL_X0Y18| No | 218 | 0.526 | 3.014 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
Timing Score: 0
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no
requested value.
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net CLK | SETUP | N/A| 9.905ns| N/A| 0
_O | HOLD | 0.396ns| | 0| 0
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net sys | SETUP | N/A| 3.644ns| N/A| 0
_clk_in_IBUFG | HOLD | 0.496ns| | 0| 0
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net cpu | SETUP | N/A| 10.524ns| N/A| 0
_clk | HOLD | 0.337ns| | 0| 0
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net sys | SETUP | N/A| 6.548ns| N/A| 0
_phy_rx_clk_BUFGP | HOLD | 0.353ns| | 0| 0
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net vga | SETUP | N/A| 8.243ns| N/A| 0
_clk | HOLD | 0.320ns| | 0| 0
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net sys | SETUP | N/A| 5.804ns| N/A| 0
_ac97_bit_clk_IBUF | HOLD | 0.483ns| | 0| 0
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net ins | SETUP | N/A| 1.935ns| N/A| 0
t_rom_wb/inst_rom/bs_clk1 | HOLD | 0.480ns| | 0| 0
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net sdr | SETUP | N/A| 8.766ns| N/A| 0
am_clk0 | HOLD | 0.503ns| | 0| 0
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net sys | SETUP | N/A| 4.574ns| N/A| 0
_phy_tx_clk_BUFGP | HOLD | 0.342ns| | 0| 0
------------------------------------------------------------------------------------------------------
Derived Constraint Report
Derived Constraints for CLK_O
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|CLK_O | 10.895ns| 9.905ns| N/A| 0| 0| 1632145| 0|
| inst_clockgen/sdr0_clk0 | 10.895ns| N/A| N/A| 0| 0| 0| 0|
| inst_clockgen/sdr0_clk270 | 10.895ns| N/A| N/A| 0| 0| 0| 0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
constraint does not cover any paths or that it has no requested value.
Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 5 mins 50 secs
Total CPU time to PAR completion: 5 mins 49 secs
Peak Memory Usage: 898 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 1
Number of info messages: 2
Writing design to file mips_sys.ncd
PAR done!
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