diff --git a/lib/CPUs/MIPS/syn/ise101/Makefile b/lib/CPUs/MIPS/syn/ise101/Makefile index 7072c68..b5d39bb 100644 --- a/lib/CPUs/MIPS/syn/ise101/Makefile +++ b/lib/CPUs/MIPS/syn/ise101/Makefile @@ -1,12 +1,15 @@ .PHONY: clean -all: mips_top.ngc +all: netlist -PREQ := mips_top.prj mips_top.xst mips_top.lso +PRJ := mips_top +PREQ := $(PRJ).prj $(PRJ).xst $(PRJ).lso DIRS := ./xst/tmp -mips_top.ngc: $(DIRS) $(PREQ) - xst -ifn mips_top.xst -intstyle xflow +netlist: $(PRJ).ngc + +$(PRJ).ngc: $(DIRS) $(PREQ) + xst -ifn $(PRJ).xst -intstyle xflow $(DIRS): mkdir -p $(DIRS) @@ -15,10 +18,10 @@ clean: rm -rf ./xst rm -rf ./xlnx_auto_0_xdb rm -f xlnx_auto_0.ise - rm -f mips_top.ngc - rm -f mips_top.ngr - rm -f mips_top.srp - rm -f mips_top_xst.xrpt + rm -f $(PRJ).ngc + rm -f $(PRJ).ngr + rm -f $(PRJ).srp + rm -f $(PRJ)_xst.xrpt diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys.par b/projects/mips_sys/ise101/mips_sys/mips_sys.par index 20658d1..5ce277d 100644 --- a/projects/mips_sys/ise101/mips_sys/mips_sys.par +++ b/projects/mips_sys/ise101/mips_sys/mips_sys.par @@ -1,20 +1,33 @@ -Release 10.1.03 par K.39 (nt) +Release 10.1.03 par K.39 (lin64) Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. -JUPITER:: Tue Mar 09 13:07:50 2010 +callisto:: Wed May 20 23:17:06 2015 -par -w -intstyle ise -ol high -xe n -t 1 mips_sys_map.ncd mips_sys.ncd +par -w -intstyle xflow -ol high -xe n -t 1 mips_sys_map.ncd mips_sys.ncd mips_sys.pcf Constraints file: mips_sys.pcf. -Loading device for application Rf_Device from file '4vsx35.nph' in environment C:\Programme\Xilinx101\ISE. +Loading device for application Rf_Device from file '4vsx35.nph' in environment /home/jens/Xilinx/10.1/ISE. "mips_sys" is an NCD, version 3.2, device xc4vsx35, package ff668, speed -10 -The STEPPING level for this design is ES. +This design is using the default stepping level (major silicon revision) for this device (1). Unless your design is +targeted at devices of this stepping level, it is recommended that you explicitly specify the stepping level of the +parts you will be using. This will allow the tools to take advantage of any available performance and functional +enhancements for this device. The latest stepping level for this device is '2'. Additional information on "stepping +level" is available at support.xilinx.com. Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) +INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par + -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all + internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For + the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". For a + balance between the fastest runtime and best performance, set the effort level to "med". +WARNING:Timing:3262 - Feedback on DCM or PLL inst_clockgen/inst_DCM_SDRCLK_0 forms an incomplete loop. The Tdcmino + calculation will be invalid. If the DCM or PLL uses external feedback, please apply the FEEDBACK constraint to + indicate the external board delay. Consult the Constraints Guide for further information on how to apply the FEEDBACK + constraint. Device speed data version: "PRODUCTION 1.68 2008-07-25". @@ -23,61 +36,54 @@ Device speed data version: "PRODUCTION 1.68 2008-07-25". Device Utilization Summary: Number of BSCANs 1 out of 4 25% - Number of BUFGs 12 out of 32 37% + Number of BUFGs 14 out of 32 43% Number of DCM_ADVs 4 out of 8 50% - Number of ILOGICs 99 out of 448 22% - Number of External IOBs 226 out of 448 50% - Number of LOCed IOBs 226 out of 226 100% + Number of ILOGICs 93 out of 448 20% + Number of External IOBs 248 out of 448 55% + Number of LOCed IOBs 0 out of 248 0% - Number of OLOGICs 182 out of 448 40% - Number of RAMB16s 51 out of 192 26% - Number of Slices 5907 out of 15360 38% - Number of SLICEMs 543 out of 7680 7% + Number of OLOGICs 192 out of 448 42% + Number of RAMB16s 74 out of 192 38% + Number of Slices 7737 out of 15360 50% + Number of SLICEMs 660 out of 7680 8% Overall effort level (-ol): High Router effort level (-rl): High -Starting initial Timing Analysis. REAL time: 14 secs -Finished initial Timing Analysis. REAL time: 15 secs - Starting Router -Phase 1: 47928 unrouted; REAL time: 16 secs +Phase 1: 60308 unrouted; REAL time: 10 secs -Phase 2: 40960 unrouted; REAL time: 17 secs +Phase 2: 51172 unrouted; REAL time: 11 secs -Phase 3: 15655 unrouted; REAL time: 24 secs +Phase 3: 18782 unrouted; REAL time: 17 secs -Phase 4: 15655 unrouted; (245197) REAL time: 24 secs +Phase 4: 18782 unrouted; (446154) REAL time: 17 secs -Phase 5: 16281 unrouted; (4341) REAL time: 27 secs +Phase 5: 19345 unrouted; (932) REAL time: 26 secs -Phase 6: 16339 unrouted; (710) REAL time: 28 secs - -Phase 7: 0 unrouted; (9891) REAL time: 53 secs +Phase 6: 0 unrouted; (8225) REAL time: 48 secs Updating file: mips_sys.ncd with current fully routed design. -Phase 8: 0 unrouted; (9891) REAL time: 1 mins 4 secs +Phase 7: 0 unrouted; (96274) REAL time: 2 mins 53 secs -Phase 9: 0 unrouted; (5549) REAL time: 1 mins 14 secs +Phase 8: 0 unrouted; (20056) REAL time: 3 mins 18 secs -Phase 10: 0 unrouted; (5549) REAL time: 1 mins 21 secs +Phase 9: 0 unrouted; (20056) REAL time: 3 mins 32 secs -Updating file: mips_sys.ncd with current fully routed design. +Phase 10: 0 unrouted; (20056) REAL time: 3 mins 32 secs -Phase 11: 0 unrouted; (5549) REAL time: 2 mins 23 secs +Phase 11: 0 unrouted; (3379) REAL time: 4 mins 19 secs -Phase 12: 0 unrouted; (1304) REAL time: 2 mins 58 secs +Phase 12: 0 unrouted; (3379) REAL time: 4 mins 25 secs -Phase 13: 0 unrouted; (1304) REAL time: 3 mins 2 secs +Phase 13: 0 unrouted; (3379) REAL time: 4 mins 33 secs -Phase 14: 0 unrouted; (1304) REAL time: 3 mins 7 secs - -Total REAL time to Router completion: 3 mins 9 secs -Total CPU time to Router completion: 3 mins 3 secs +Total REAL time to Router completion: 4 mins 33 secs +Total CPU time to Router completion: 4 mins 32 secs Partition Implementation Status ------------------------------- @@ -95,28 +101,34 @@ Generating Clock Report +---------------------+--------------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +---------------------+--------------+------+------+------------+-------------+ -| cpu_clk |BUFGCTRL_X0Y12| No | 1610 | 0.400 | 4.025 | +| CLK_O |BUFGCTRL_X0Y25| No | 2958 | 0.637 | 3.123 | +---------------------+--------------+------+------+------------+-------------+ -| CLK_O | BUFGCTRL_X0Y2| No | 2256 | 0.541 | 3.930 | +| sys_clk_in_IBUFG |BUFGCTRL_X0Y27| No | 59 | 0.315 | 2.895 | +---------------------+--------------+------+------+------------+-------------+ -|inst_rom_wb/inst_rom | | | | | | -| /bs_clk1 | BUFGCTRL_X0Y0| No | 76 | 0.190 | 3.686 | +| cpu_clk |BUFGCTRL_X0Y22| No | 1778 | 0.512 | 2.999 | +---------------------+--------------+------+------+------------+-------------+ -| vga_clk |BUFGCTRL_X0Y11| No | 167 | 0.408 | 3.881 | +| sdram_clk270 |BUFGCTRL_X0Y16| No | 36 | 0.165 | 3.041 | +---------------------+--------------+------+------+------------+-------------+ -| sdram_clk0 |BUFGCTRL_X0Y31| No | 227 | 0.492 | 3.933 | +| sdram_clk270var |BUFGCTRL_X0Y20| No | 32 | 0.040 | 3.041 | ++---------------------+--------------+------+------+------------+-------------+ +|sys_phy_rx_clk_BUFGP | | | | | | +| |BUFGCTRL_X0Y24| No | 240 | 0.398 | 2.916 | ++---------------------+--------------+------+------+------------+-------------+ +| vga_clk |BUFGCTRL_X0Y17| No | 184 | 0.448 | 3.000 | +---------------------+--------------+------+------+------------+-------------+ |sys_ac97_bit_clk_IBU | | | | | | -| F | BUFGCTRL_X0Y8| No | 251 | 0.428 | 3.823 | -+---------------------+--------------+------+------+------------+-------------+ -| sys_clk_in_IBUFG | BUFGCTRL_X0Y1| No | 55 | 0.205 | 3.675 | -+---------------------+--------------+------+------+------------+-------------+ -| sdram_clk270 |BUFGCTRL_X0Y16| No | 68 | 0.158 | 3.932 | -+---------------------+--------------+------+------+------------+-------------+ -| sdram_clk270var |BUFGCTRL_X0Y28| No | 32 | 0.025 | 3.930 | +| F |BUFGCTRL_X0Y10| No | 245 | 0.401 | 3.040 | +---------------------+--------------+------+------+------------+-------------+ |inst_rom_wb/inst_rom | | | | | | -| /bs_update1 |BUFGCTRL_X0Y26| No | 4 | 0.044 | 3.631 | +| /bs_clk1 |BUFGCTRL_X0Y31| No | 73 | 0.292 | 2.948 | ++---------------------+--------------+------+------+------------+-------------+ +|inst_rom_wb/inst_rom | | | | | | +| /bs_update1 |BUFGCTRL_X0Y30| No | 4 | 0.228 | 2.940 | ++---------------------+--------------+------+------+------------+-------------+ +| sdram_clk0 |BUFGCTRL_X0Y28| No | 231 | 0.508 | 2.994 | ++---------------------+--------------+------+------+------------+-------------+ +|sys_phy_tx_clk_BUFGP | | | | | | +| |BUFGCTRL_X0Y18| No | 218 | 0.526 | 3.014 | +---------------------+--------------+------+------+------------+-------------+ * Net Skew is the difference between the minimum and maximum routing @@ -124,20 +136,7 @@ only delays for the net. Note this is different from Clock Skew which is reported in TRCE timing report. Clock Skew is the difference between the minimum and maximum path delays which includes logic delays. -Timing Score: 1304 - -WARNING:Par:62 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in - your design. - - Review the timing report using Timing Analyzer (In ISE select "Post-Place & - Route Static Timing Report"). Go to the failing constraint(s) and select - the "Timing Improvement Wizard" link for suggestions to correct each problem. - - Try the Design Goal and Strategies for Timing Performance (In ISE select Project -> Design Goals & Strategies) to - ensure the best options are set in the tools for timing closure. - - Use the Xilinx "SmartXplorer" script to try special combinations of - options known to produce very good results. +Timing Score: 0 INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value. @@ -148,31 +147,48 @@ Asterisk (*) preceding a constraint indicates it was not met. Constraint | Check | Worst Case | Best Case | Timing | Timing | | Slack | Achievable | Errors | Score ------------------------------------------------------------------------------------------------------ -* TS_clk = PERIOD TIMEGRP "sys_clk" 9.9 ns | SETUP | -0.293ns| 10.193ns| 9| 1107 - HIGH 50% | HOLD | 0.365ns| | 0| 0 + Autotimespec constraint for clock net CLK | SETUP | N/A| 9.905ns| N/A| 0 + _O | HOLD | 0.396ns| | 0| 0 ------------------------------------------------------------------------------------------------------ -* TS_cpu_clk = PERIOD TIMEGRP "cpu_clk" 9.9 | SETUP | -0.197ns| 10.294ns| 1| 197 - ns HIGH 50% | HOLD | 0.346ns| | 0| 0 + Autotimespec constraint for clock net sys | SETUP | N/A| 3.644ns| N/A| 0 + _clk_in_IBUFG | HOLD | 0.496ns| | 0| 0 ------------------------------------------------------------------------------------------------------ - TS_sdram_clk = PERIOD TIMEGRP "sdram_clk" | SETUP | 0.170ns| 7.330ns| 0| 0 - 7.5 ns HIGH 50% | HOLD | 0.513ns| | 0| 0 + Autotimespec constraint for clock net cpu | SETUP | N/A| 10.524ns| N/A| 0 + _clk | HOLD | 0.337ns| | 0| 0 ------------------------------------------------------------------------------------------------------ - TS_vga_clk = PERIOD TIMEGRP "vga_clk" 8 n | SETUP | 0.386ns| 7.614ns| 0| 0 - s HIGH 50% | HOLD | 0.514ns| | 0| 0 + Autotimespec constraint for clock net sys | SETUP | N/A| 6.548ns| N/A| 0 + _phy_rx_clk_BUFGP | HOLD | 0.353ns| | 0| 0 ------------------------------------------------------------------------------------------------------ - NET "sys_ac97_bit_clk_IBUF1" PERIOD = 80 | SETUP | 36.650ns| 6.700ns| 0| 0 - ns HIGH 50% | HOLD | 0.518ns| | 0| 0 + Autotimespec constraint for clock net vga | SETUP | N/A| 8.243ns| N/A| 0 + _clk | HOLD | 0.320ns| | 0| 0 ------------------------------------------------------------------------------------------------------ - TSACBITCLK = PERIOD TIMEGRP "ac97_clk" 80 | SETUP | 74.716ns| 5.284ns| 0| 0 - ns HIGH 50% | HOLD | 0.802ns| | 0| 0 + Autotimespec constraint for clock net sys | SETUP | N/A| 5.804ns| N/A| 0 + _ac97_bit_clk_IBUF | HOLD | 0.483ns| | 0| 0 ------------------------------------------------------------------------------------------------------ - PATH "TS_unrelate_SDRAM_path" TIG | SETUP | N/A| 9.594ns| N/A| 0 + Autotimespec constraint for clock net ins | SETUP | N/A| 1.935ns| N/A| 0 + t_rom_wb/inst_rom/bs_clk1 | HOLD | 0.480ns| | 0| 0 ------------------------------------------------------------------------------------------------------ - PATH "TS_unrelate_VGA_path" TIG | SETUP | N/A| 6.138ns| N/A| 0 + Autotimespec constraint for clock net sdr | SETUP | N/A| 8.766ns| N/A| 0 + am_clk0 | HOLD | 0.503ns| | 0| 0 +------------------------------------------------------------------------------------------------------ + Autotimespec constraint for clock net sys | SETUP | N/A| 4.574ns| N/A| 0 + _phy_tx_clk_BUFGP | HOLD | 0.342ns| | 0| 0 ------------------------------------------------------------------------------------------------------ -2 constraints not met. +Derived Constraint Report +Derived Constraints for CLK_O ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +| | Period | Actual Period | Timing Errors | Paths Analyzed | +| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| +| | | Direct | Derivative | Direct | Derivative | Direct | Derivative | ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +|CLK_O | 10.895ns| 9.905ns| N/A| 0| 0| 1632145| 0| +| inst_clockgen/sdr0_clk0 | 10.895ns| N/A| N/A| 0| 0| 0| 0| +| inst_clockgen/sdr0_clk270 | 10.895ns| N/A| N/A| 0| 0| 0| 0| ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ + +All constraints were met. INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value. @@ -181,18 +197,17 @@ Generating Pad Report. All signals are completely routed. -Total REAL time to PAR completion: 3 mins 18 secs -Total CPU time to PAR completion: 3 mins 9 secs +Total REAL time to PAR completion: 5 mins 50 secs +Total CPU time to PAR completion: 5 mins 49 secs -Peak Memory Usage: 428 MB +Peak Memory Usage: 898 MB Placer: Placement generated during map. Routing: Completed - No errors found. -Timing: Completed - 10 errors found. Number of error messages: 0 Number of warning messages: 1 -Number of info messages: 1 +Number of info messages: 2 Writing design to file mips_sys.ncd diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys.xst b/projects/mips_sys/ise101/mips_sys/mips_sys.xst index 84ac4f4..d3b37b3 100644 --- a/projects/mips_sys/ise101/mips_sys/mips_sys.xst +++ b/projects/mips_sys/ise101/mips_sys/mips_sys.xst @@ -17,7 +17,6 @@ run -rtlview Yes -glob_opt AllClockNets -read_cores YES --sd { "../../../../lib/CPUs/MIPS/syn/ise101/netgen/synthesis" } -write_timing_constraints NO -cross_clock_analysis NO -hierarchy_separator / diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys_map.mrp b/projects/mips_sys/ise101/mips_sys/mips_sys_map.mrp index 7ea5658..39c74dc 100644 --- a/projects/mips_sys/ise101/mips_sys/mips_sys_map.mrp +++ b/projects/mips_sys/ise101/mips_sys/mips_sys_map.mrp @@ -1,82 +1,58 @@ -Release 10.1.03 Map K.39 (nt) +Release 10.1.03 Map K.39 (lin64) Xilinx Mapping Report File for Design 'mips_sys' Design Information ------------------ -Command Line : map -ise W:/vhdl/projects/mips_sys/ise101/mips_sys/mips_sys.ise -intstyle ise -p xc4vsx35-ff668-10 --timing -logic_opt on -ol high -xe n -t 1 -register_duplication -global_opt on -retiming on -equivalent_register_removal -on -cm area -pr b -k 4 -power off -o mips_sys_map.ncd mips_sys.ngd mips_sys.pcf +Command Line : map -intstyle xflow -p xc4vsx35-ff668-10 -timing -logic_opt on +-ol high -xe n -t 1 -register_duplication -global_opt on -retiming on +-equivalent_register_removal on -cm area -pr b -k 4 -power off -o +mips_sys_map.ncd mips_sys.ngd mips_sys.pcf Target Device : xc4vsx35 Target Package : ff668 Target Speed : -10 Stepping Level : ES -Mapper Version : virtex4 -- $Revision: 1.5 $ -Mapped Date : Tue Mar 09 12:59:05 2010 +Mapper Version : virtex4 -- $Revision: 1.46.12.2 $ +Mapped Date : Wed May 20 23:49:58 2015 Design Summary -------------- -Number of errors: 0 -Number of warnings: 68 -Logic Utilization: - Number of Slice Flip Flops: 5,422 out of 30,720 17% - Number of 4 input LUTs: 8,643 out of 30,720 28% -Logic Distribution: - Number of occupied Slices: 5,907 out of 15,360 38% - Number of Slices containing only related logic: 5,907 out of 5,907 100% - Number of Slices containing unrelated logic: 0 out of 5,907 0% - *See NOTES below for an explanation of the effects of unrelated logic. - Total Number of 4 input LUTs: 9,032 out of 30,720 29% - Number used as logic: 7,643 - Number used as a route-thru: 389 - Number used for Dual Port RAMs: 792 - (Two LUTs used per Dual Port RAM) - Number used as Shift registers: 208 - Number of bonded IOBs: 226 out of 448 50% - IOB Flip Flops: 350 - IOB Dual-Data Rate Flops: 42 - Number of BUFG/BUFGCTRLs: 12 out of 32 37% - Number used as BUFGs: 12 - Number of FIFO16/RAMB16s: 51 out of 192 26% - Number used as RAMB16s: 51 - Number of DCM_ADVs: 4 out of 8 50% - Number of BSCAN_VIRTEX4s: 1 out of 4 25% - -Peak Memory Usage: 530 MB -Total REAL time to MAP completion: 8 mins 27 secs -Total CPU time to MAP completion: 8 mins 9 secs - -Table of Contents ------------------ -Section 1 - Errors -Section 2 - Warnings -Section 3 - Informational -Section 4 - Removed Logic Summary -Section 5 - Removed Logic -Section 6 - IOB Properties -Section 7 - RPMs -Section 8 - Guide Report -Section 9 - Area Group and Partition Summary -Section 10 - Modular Design Summary -Section 11 - Timing Report -Section 12 - Configuration String Information -Section 13 - Control Set Information -Section 14 - Utilization by Hierarchy +Number of errors : 2 +Number of warnings : 74 Section 1 - Errors ------------------ +ERROR:Place:539 - The design has objects that are constrained to a set of sites. + The number of objects constrained (3738) of type LUT is too large for the + number of available sites (that are not prohibited and not already taken by + other locked components) of this type in this set (3709) . + The following constraints are causing this issue: + COMPGRP "AG_inst_mips_top.SLICE" LOCATE = SITE "SLICE_X0Y53:SLICE_X39Y0" + LEVEL 4 + Encountered an infeasibility when trying to place 7047 components to 8640 + sites. + LUTM ( 3) Comps 611 Sites 2160 AvailEmptySites 2160. Reserved 611 + sites for LUTM comps. + FFM ( 4) Comps 611 Sites 2160 AvailEmptySites 2160. Reserved 611 + sites for FFM comps. + LUT ( 1) Comps 3738 Sites 4320 AvailEmptySites 3709. Reserved 3738 + sites for LUT comps. + FF ( 2) Comps 2087 Sites 4320 AvailEmptySites 3709. Reserved 2087 + sites for FF comps. + +ERROR:Pack:1654 - The timing-driven packing phase encountered an error. Section 2 - Warnings -------------------- -WARNING:LIT:421 - DIB0 should be connected if WRITE_WIDTH_B is set to 18 (RAMB16 - symbol "inst_mips_top/inst_biu/inst_icache/inst_tag_ram/Mram_RAM1"). -WARNING:LIT:243 - Logical network sys_usb_d_15_IOBUF/N2 has no load. -WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 167 +WARNING:LIT:421 - DIB0 should be connected if WRITE_WIDTH_B is set to 9 (RAMB16 + symbol "inst_rom_wb/inst_rom/Mram_word_array3"). +WARNING:LIT:243 - Logical network sys_phy_int_IBUF has no load. +WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 176 more times for the following (max. 5 shown): + sys_phy_col_IBUF, + sys_phy_crs_IBUF, + sys_usb_d_15_IOBUF/N2, sys_usb_d_15_IOBUF/N3, - sys_usb_d_14_IOBUF/N2, - sys_usb_d_14_IOBUF/N3, - sys_usb_d_13_IOBUF/N2, - sys_usb_d_13_IOBUF/N3 + sys_usb_d_14_IOBUF/N2 To see the details of these warning messages, please use the -detail switch. WARNING:Pack:2549 - The register "inst_uart_wb_1/inst_uart_tx/kcuart/pipeline_serial" has the property @@ -88,229 +64,233 @@ WARNING:Pack:2549 - The register IOB=TRUE, but was not packed into the OLOGIC component. The output signal for register symbol inst_uart_wb_1/inst_uart_tx/kcuart/pipeline_serial requires general routing. +WARNING:Pack:2548 - The register + "inst_emac_top_jb/inst_emac_rx/inst_sipo_8bit/shift_cnt_pipe_1" has the + property IOB=TRUE, but was not packed into the ILOGIC component. The ILOGIC + component already contains an IFF1. WARNING:Pack:2549 - The register "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_1" has the property IOB=TRUE, but was not packed into the OLOGIC component. The OLOGIC SR signal "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not - match the ILOGIC SR signal "N0_765". - -WARNING:Pack:2549 - The register - "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_2" has - the property IOB=TRUE, but was not packed into the OLOGIC component. The - OLOGIC SR signal - "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not - match the ILOGIC SR signal "N0_763". - -WARNING:Pack:2549 - The register - "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_3" has - the property IOB=TRUE, but was not packed into the OLOGIC component. The - OLOGIC SR signal - "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not - match the ILOGIC SR signal "N0_761". - -WARNING:Pack:2549 - The register - "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_4" has - the property IOB=TRUE, but was not packed into the OLOGIC component. The - OLOGIC SR signal - "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not - match the ILOGIC SR signal "N0_759". - -WARNING:Pack:2549 - The register - "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_5" has - the property IOB=TRUE, but was not packed into the OLOGIC component. The - OLOGIC SR signal - "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not - match the ILOGIC SR signal "N0_757". - -WARNING:Pack:2549 - The register - "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_6" has - the property IOB=TRUE, but was not packed into the OLOGIC component. The - OLOGIC SR signal - "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not - match the ILOGIC SR signal "N0_755". - -WARNING:Pack:2549 - The register - "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_7" has - the property IOB=TRUE, but was not packed into the OLOGIC component. The - OLOGIC SR signal - "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not - match the ILOGIC SR signal "N0_753". - -WARNING:Pack:2549 - The register - "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_8" has - the property IOB=TRUE, but was not packed into the OLOGIC component. The - OLOGIC SR signal - "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not - match the ILOGIC SR signal "N0_751". - -WARNING:Pack:2549 - The register - "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_9" has - the property IOB=TRUE, but was not packed into the OLOGIC component. The - OLOGIC SR signal - "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not - match the ILOGIC SR signal "N0_749". - -WARNING:Pack:2549 - The register - "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_10" has - the property IOB=TRUE, but was not packed into the OLOGIC component. The - OLOGIC SR signal - "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not - match the ILOGIC SR signal "N0_747". - -WARNING:Pack:2549 - The register - "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_11" has - the property IOB=TRUE, but was not packed into the OLOGIC component. The - OLOGIC SR signal - "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not - match the ILOGIC SR signal "N0_745". - -WARNING:Pack:2549 - The register - "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_12" has - the property IOB=TRUE, but was not packed into the OLOGIC component. The - OLOGIC SR signal - "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not - match the ILOGIC SR signal "N0_743". - -WARNING:Pack:2549 - The register - "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_13" has - the property IOB=TRUE, but was not packed into the OLOGIC component. The - OLOGIC SR signal - "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not - match the ILOGIC SR signal "N0_741". - -WARNING:Pack:2549 - The register - "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_21" has - the property IOB=TRUE, but was not packed into the OLOGIC component. The - OLOGIC SR signal - "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not - match the ILOGIC SR signal "N0_725". - -WARNING:Pack:2549 - The register - "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_14" has - the property IOB=TRUE, but was not packed into the OLOGIC component. The - OLOGIC SR signal - "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not - match the ILOGIC SR signal "N0_739". - -WARNING:Pack:2549 - The register - "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_22" has - the property IOB=TRUE, but was not packed into the OLOGIC component. The - OLOGIC SR signal - "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not - match the ILOGIC SR signal "N0_723". - -WARNING:Pack:2549 - The register - "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_23" has - the property IOB=TRUE, but was not packed into the OLOGIC component. The - OLOGIC SR signal - "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not - match the ILOGIC SR signal "N0_721". - -WARNING:Pack:2549 - The register - "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_15" has - the property IOB=TRUE, but was not packed into the OLOGIC component. The - OLOGIC SR signal - "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not - match the ILOGIC SR signal "N0_737". - -WARNING:Pack:2549 - The register - "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_31" has - the property IOB=TRUE, but was not packed into the OLOGIC component. The - OLOGIC SR signal - "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not - match the ILOGIC SR signal "N0_705". - -WARNING:Pack:2549 - The register - "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_24" has - the property IOB=TRUE, but was not packed into the OLOGIC component. The - OLOGIC SR signal - "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not - match the ILOGIC SR signal "N0_719". - -WARNING:Pack:2549 - The register - "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_16" has - the property IOB=TRUE, but was not packed into the OLOGIC component. The - OLOGIC SR signal - "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not - match the ILOGIC SR signal "N0_735". - -WARNING:Pack:2549 - The register - "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_32" has - the property IOB=TRUE, but was not packed into the OLOGIC component. The - OLOGIC SR signal - "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not match the ILOGIC SR signal "N0_703". +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_2" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_701". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_3" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_699". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_4" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_697". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_5" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_695". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_6" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_693". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_7" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_691". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_8" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_689". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_9" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_687". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_10" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_685". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_11" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_683". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_12" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_681". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_13" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_679". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_21" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_663". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_14" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_677". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_22" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_661". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_23" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_659". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_15" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_675". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_31" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_643". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_24" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_657". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_16" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_673". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_32" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_641". + WARNING:Pack:2549 - The register "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_25" has the property IOB=TRUE, but was not packed into the OLOGIC component. The OLOGIC SR signal "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not - match the ILOGIC SR signal "N0_717". + match the ILOGIC SR signal "N0_655". WARNING:Pack:2549 - The register "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_17" has the property IOB=TRUE, but was not packed into the OLOGIC component. The OLOGIC SR signal "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not - match the ILOGIC SR signal "N0_733". + match the ILOGIC SR signal "N0_671". WARNING:Pack:2549 - The register "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_18" has the property IOB=TRUE, but was not packed into the OLOGIC component. The OLOGIC SR signal "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not - match the ILOGIC SR signal "N0_731". + match the ILOGIC SR signal "N0_669". WARNING:Pack:2549 - The register "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_26" has the property IOB=TRUE, but was not packed into the OLOGIC component. The OLOGIC SR signal "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not - match the ILOGIC SR signal "N0_715". + match the ILOGIC SR signal "N0_653". WARNING:Pack:2549 - The register "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_19" has the property IOB=TRUE, but was not packed into the OLOGIC component. The OLOGIC SR signal "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not - match the ILOGIC SR signal "N0_729". + match the ILOGIC SR signal "N0_667". WARNING:Pack:2549 - The register "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_27" has the property IOB=TRUE, but was not packed into the OLOGIC component. The OLOGIC SR signal "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not - match the ILOGIC SR signal "N0_713". + match the ILOGIC SR signal "N0_651". WARNING:Pack:2549 - The register "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_20" has the property IOB=TRUE, but was not packed into the OLOGIC component. The OLOGIC SR signal "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not - match the ILOGIC SR signal "N0_727". + match the ILOGIC SR signal "N0_665". WARNING:Pack:2549 - The register "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_28" has the property IOB=TRUE, but was not packed into the OLOGIC component. The OLOGIC SR signal "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not - match the ILOGIC SR signal "N0_711". + match the ILOGIC SR signal "N0_649". WARNING:Pack:2549 - The register "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_29" has the property IOB=TRUE, but was not packed into the OLOGIC component. The OLOGIC SR signal "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not - match the ILOGIC SR signal "N0_709". + match the ILOGIC SR signal "N0_647". WARNING:Pack:2549 - The register "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_30" has the property IOB=TRUE, but was not packed into the OLOGIC component. The OLOGIC SR signal "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not - match the ILOGIC SR signal "N0_707". + match the ILOGIC SR signal "N0_645". WARNING:Pack:2549 - The register "inst_ps2_wb_0/inst_ps2_core/ps2_data_tx" has the property IOB=TRUE, but was not packed into the OLOGIC component. The @@ -352,9 +332,13 @@ WARNING:Pack:2549 - The register the property IOB=TRUE, but was not packed into the OLOGIC component. Register inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/dqs_zen_0_1 set/reset disagrees with another register in the OLOGIC component. +WARNING:Pack:2549 - The register "inst_gpio_wb/gpio_0_dir_reg_30" has the + property IOB=TRUE, but was not packed into the OLOGIC component. Register + inst_gpio_wb/gpio_0_dir_reg_30 set/reset disagrees with another register in + the OLOGIC component. WARNING:Pack:2549 - The register "inst_ps2_wb_0/inst_ps2_core/ps2_clk_tx" has the property IOB=TRUE, but was not packed into the OLOGIC component. The - OLOGIC SR signal "N25" does not match the ILOGIC SR signal + OLOGIC SR signal "N27" does not match the ILOGIC SR signal "inst_ps2_phy_0/Inst_debounce_clk/output_and0000". The OLOGIC REV signal "inst_ps2_wb_0/inst_ps2_core/read_cs_FSM_FFd3" does not match the ILOGIC REV signal @@ -362,7 +346,7 @@ WARNING:Pack:2549 - The register "inst_ps2_wb_0/inst_ps2_core/ps2_clk_tx" has WARNING:Pack:2549 - The register "inst_ps2_wb_0/inst_ps2_core/ps2_clk_tx_1" has the property IOB=TRUE, but was not packed into the OLOGIC component. The - OLOGIC SR signal "N25" does not match the ILOGIC SR signal + OLOGIC SR signal "N27" does not match the ILOGIC SR signal "inst_ps2_phy_0/Inst_debounce_clk/output_and0000". The OLOGIC REV signal "inst_ps2_wb_0/inst_ps2_core/read_cs_FSM_FFd3" does not match the ILOGIC REV signal @@ -370,7 +354,7 @@ WARNING:Pack:2549 - The register "inst_ps2_wb_0/inst_ps2_core/ps2_clk_tx_1" has WARNING:Pack:2549 - The register "inst_ps2_wb_1/inst_ps2_core/ps2_clk_tx" has the property IOB=TRUE, but was not packed into the OLOGIC component. The - OLOGIC SR signal "N21" does not match the ILOGIC SR signal + OLOGIC SR signal "N23" does not match the ILOGIC SR signal "inst_ps2_phy_1/Inst_debounce_clk/output_and0000". The OLOGIC REV signal "inst_ps2_wb_1/inst_ps2_core/read_cs_FSM_FFd3" does not match the ILOGIC REV signal @@ -378,158 +362,150 @@ WARNING:Pack:2549 - The register "inst_ps2_wb_1/inst_ps2_core/ps2_clk_tx" has WARNING:Pack:2549 - The register "inst_ps2_wb_1/inst_ps2_core/ps2_clk_tx_1" has the property IOB=TRUE, but was not packed into the OLOGIC component. The - OLOGIC SR signal "N21" does not match the ILOGIC SR signal + OLOGIC SR signal "N23" does not match the ILOGIC SR signal "inst_ps2_phy_1/Inst_debounce_clk/output_and0000". The OLOGIC REV signal "inst_ps2_wb_1/inst_ps2_core/read_cs_FSM_FFd3" does not match the ILOGIC REV signal "inst_ps2_phy_1/Inst_debounce_clk/output_and0001". -WARNING:Pack:2548 - The register "inst_gpio_wb/gpi1_reg_7" has the property - IOB=TRUE, but was not packed into the ILOGIC component. The ILOGIC component - already contains an IFF1. +WARNING:Pack:2549 - The register "inst_gpio_wb/gpio_0_dir_reg_0" has the + property IOB=TRUE, but was not packed into the OLOGIC component. Register + inst_gpio_wb/gpio_0_dir_reg_0 set/reset disagrees with another register in + the OLOGIC component. +WARNING:Pack:2549 - The register "inst_gpio_wb/gpio_0_dir_reg_1" has the + property IOB=TRUE, but was not packed into the OLOGIC component. Register + inst_gpio_wb/gpio_0_dir_reg_1 set/reset disagrees with another register in + the OLOGIC component. +WARNING:Pack:2549 - The register "inst_gpio_wb/gpio_0_dir_reg_2" has the + property IOB=TRUE, but was not packed into the OLOGIC component. Register + inst_gpio_wb/gpio_0_dir_reg_2 set/reset disagrees with another register in + the OLOGIC component. +WARNING:Pack:2549 - The register "inst_gpio_wb/gpio_0_dir_reg_3" has the + property IOB=TRUE, but was not packed into the OLOGIC component. Register + inst_gpio_wb/gpio_0_dir_reg_3 set/reset disagrees with another register in + the OLOGIC component. +WARNING:Pack:2549 - The register "inst_gpio_wb/gpio_0_dir_reg_4" has the + property IOB=TRUE, but was not packed into the OLOGIC component. Register + inst_gpio_wb/gpio_0_dir_reg_4 set/reset disagrees with another register in + the OLOGIC component. +WARNING:Pack:2549 - The register "inst_gpio_wb/gpio_0_dir_reg_5" has the + property IOB=TRUE, but was not packed into the OLOGIC component. Register + inst_gpio_wb/gpio_0_dir_reg_5 set/reset disagrees with another register in + the OLOGIC component. +WARNING:Pack:2549 - The register "inst_gpio_wb/gpio_0_dir_reg_6" has the + property IOB=TRUE, but was not packed into the OLOGIC component. Register + inst_gpio_wb/gpio_0_dir_reg_6 set/reset disagrees with another register in + the OLOGIC component. +WARNING:Pack:2549 - The register "inst_gpio_wb/gpio_0_dir_reg_7" has the + property IOB=TRUE, but was not packed into the OLOGIC component. Register + inst_gpio_wb/gpio_0_dir_reg_7 set/reset disagrees with another register in + the OLOGIC component. +WARNING:Pack:2549 - The register "inst_gpio_wb/gpio_0_dir_reg_8" has the + property IOB=TRUE, but was not packed into the OLOGIC component. Register + inst_gpio_wb/gpio_0_dir_reg_8 set/reset disagrees with another register in + the OLOGIC component. WARNING:Pack:266 - The function generator - inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000026 failed to + inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom0000131 failed to merge with F5 multiplexer inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000026_f6/MUXF5.I1 . Tried to combine two collections of symbols from different layers. The alignment requirements of the two layers conflict. The design will exhibit suboptimal timing. WARNING:Pack:266 - The function generator - inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000028 failed to + inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom0000112 failed to merge with F5 multiplexer inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000011_f6/MUXF5.I0 . Tried to combine two collections of symbols from different layers. The alignment requirements of the two layers conflict. The design will exhibit suboptimal timing. WARNING:Pack:266 - The function generator - inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom0000231 failed to - merge with F5 multiplexer - inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000016_f6/MUXF5.I1 - . Tried to combine two collections of symbols from different layers. The - alignment requirements of the two layers conflict. The design will exhibit - suboptimal timing. -WARNING:Pack:266 - The function generator - inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000024 failed to + inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom0000151 failed to merge with F5 multiplexer inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000024_f6/MUXF5.I1 . Tried to combine two collections of symbols from different layers. The alignment requirements of the two layers conflict. The design will exhibit suboptimal timing. WARNING:Pack:266 - The function generator - inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000032 failed to + inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000016 failed to + merge with F5 multiplexer + inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000016_f6/MUXF5.I1 + . Tried to combine two collections of symbols from different layers. The + alignment requirements of the two layers conflict. The design will exhibit + suboptimal timing. +WARNING:Pack:266 - The function generator + inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000071 failed to merge with F5 multiplexer inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom00007_f6/MUXF5.I0. Tried to combine two collections of symbols from different layers. The alignment requirements of the two layers conflict. The design will exhibit suboptimal timing. WARNING:Pack:266 - The function generator - inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000030 failed to + inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000091 failed to merge with F5 multiplexer inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000030_f6/MUXF5.I1 . Tried to combine two collections of symbols from different layers. The alignment requirements of the two layers conflict. The design will exhibit suboptimal timing. WARNING:Pack:266 - The function generator - inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom0000351 failed to + inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom00004 failed to merge with F5 multiplexer inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000035_f6/MUXF5.I0 . Tried to combine two collections of symbols from different layers. The alignment requirements of the two layers conflict. The design will exhibit suboptimal timing. WARNING:Pack:266 - The function generator - inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000034 failed to + inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000051 failed to merge with F5 multiplexer inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom00005_f6/MUXF5.I0. Tried to combine two collections of symbols from different layers. The alignment requirements of the two layers conflict. The design will exhibit suboptimal timing. WARNING:Pack:266 - The function generator - inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom0000271 failed to + inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000012 failed to merge with F5 multiplexer inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000012_f6/MUXF5.I1 . Tried to combine two collections of symbols from different layers. The alignment requirements of the two layers conflict. The design will exhibit suboptimal timing. WARNING:Pack:266 - The function generator - inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom0000251 failed to - merge with F5 multiplexer - inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000025_f6/MUXF5.I0 - . Tried to combine two collections of symbols from different layers. The - alignment requirements of the two layers conflict. The design will exhibit - suboptimal timing. -WARNING:Pack:266 - The function generator - inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom0000331 failed to + inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom00006 failed to merge with F5 multiplexer inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000033_f6/MUXF5.I0 . Tried to combine two collections of symbols from different layers. The alignment requirements of the two layers conflict. The design will exhibit suboptimal timing. WARNING:Pack:266 - The function generator - inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000036 failed to + inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000014 failed to + merge with F5 multiplexer + inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000025_f6/MUXF5.I0 + . Tried to combine two collections of symbols from different layers. The + alignment requirements of the two layers conflict. The design will exhibit + suboptimal timing. +WARNING:Pack:266 - The function generator + inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000031 failed to merge with F5 multiplexer inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom00003_f6/MUXF5.I0. Tried to combine two collections of symbols from different layers. The alignment requirements of the two layers conflict. The design will exhibit suboptimal timing. WARNING:Pack:266 - The function generator - inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom0000312 failed to + inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom00008 failed to merge with F5 multiplexer inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom00008_f6/MUXF5.I1. Tried to combine two collections of symbols from different layers. The alignment requirements of the two layers conflict. The design will exhibit suboptimal timing. WARNING:Pack:266 - The function generator - inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom0000291 failed to + inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000010 failed to merge with F5 multiplexer inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000010_f6/MUXF5.I1 . Tried to combine two collections of symbols from different layers. The alignment requirements of the two layers conflict. The design will exhibit suboptimal timing. -WARNING:Place:838 - An IO Bus with more than one IO standard is found. - Components associated with this bus are as follows: - Comp: sys_vga_blue<0> IOSTANDARD = LVCMOS33 - Comp: sys_vga_blue<1> IOSTANDARD = LVCMOS33 - Comp: sys_vga_blue<2> IOSTANDARD = LVCMOS33 - Comp: sys_vga_blue<3> IOSTANDARD = LVCMOS25 - Comp: sys_vga_blue<4> IOSTANDARD = LVCMOS25 - Comp: sys_vga_blue<5> IOSTANDARD = LVCMOS25 - Comp: sys_vga_blue<6> IOSTANDARD = LVCMOS25 - Comp: sys_vga_blue<7> IOSTANDARD = LVCMOS25 - - -WARNING:Place:838 - An IO Bus with more than one IO standard is found. - Components associated with this bus are as follows: - Comp: sys_vga_green<0> IOSTANDARD = LVCMOS33 - Comp: sys_vga_green<1> IOSTANDARD = LVCMOS33 - Comp: sys_vga_green<2> IOSTANDARD = LVCMOS33 - Comp: sys_vga_green<3> IOSTANDARD = LVCMOS25 - Comp: sys_vga_green<4> IOSTANDARD = LVCMOS25 - Comp: sys_vga_green<5> IOSTANDARD = LVCMOS25 - Comp: sys_vga_green<6> IOSTANDARD = LVCMOS25 - Comp: sys_vga_green<7> IOSTANDARD = LVCMOS25 - - -WARNING:Place:838 - An IO Bus with more than one IO standard is found. - Components associated with this bus are as follows: - Comp: sys_vga_red<0> IOSTANDARD = LVCMOS33 - Comp: sys_vga_red<1> IOSTANDARD = LVCMOS33 - Comp: sys_vga_red<2> IOSTANDARD = LVCMOS33 - Comp: sys_vga_red<3> IOSTANDARD = LVCMOS25 - Comp: sys_vga_red<4> IOSTANDARD = LVCMOS25 - Comp: sys_vga_red<5> IOSTANDARD = LVCMOS25 - Comp: sys_vga_red<6> IOSTANDARD = LVCMOS25 - Comp: sys_vga_red<7> IOSTANDARD = LVCMOS25 - - -WARNING:PhysDesignRules:1236 - Unknown DCM_ADV feedback loop. The signal sys_sdr_clk_fb_IBUFG on the CLKFB pin of - DCM_ADV comp inst_clockgen/inst_DCM_SDRCLK_0 was driven by an IOB site but the signal loop could not be traced back - to the CLK0 pin of comp inst_clockgen/inst_DCM_SDRCLK_0. The signal out the CLK0 pin must drive an IOB input pin with - programming out to the PAD. Section 3 - Informational ------------------------- -INFO:MapLib:564 - The following environment variables are currently set: -INFO:MapLib:591 - XIL_MAP_LOCWARN Value: 1 +INFO:MapLib:562 - No environment variables are currently set. INFO:MapLib:159 - Net Timing constraints on signal sys_ac97_bit_clk are pushed forward through input buffer. INFO:MapLib:797 - Your design is targeting LX/SX Production Step 0/1/ES devices. @@ -541,20 +517,12 @@ INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) -INFO:Pack:1679 - FLOP symbol "inst_mips_top/inst_pipeline/EX_stage.reg_b_3_REPLICA_0" (Output Signal = - inst_mips_top/inst_pipeline/EX_stage.reg_b_3_REPLICA_0) was replicated from FLOP symbol - "inst_mips_top/inst_pipeline/EX_stage.reg_b_3" (Output Signal = inst_mips_top/inst_pipeline/EX_stage.reg_b_3) -INFO:Pack:1650 - Map created a placed design. -INFO:PhysDesignRules:1437 - To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of - the DCM_ADV comp inst_clockgen/inst_DCM_VGA_FX, consult the device Data Sheet. -INFO:PhysDesignRules:1437 - To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of - the DCM_ADV comp inst_clockgen/inst_DCM_SYS_FX, consult the device Data Sheet. Section 4 - Removed Logic Summary --------------------------------- - 168 block(s) removed + 174 block(s) removed 4 block(s) optimized away - 168 signal(s) removed + 174 signal(s) removed Section 5 - Removed Logic ------------------------- @@ -665,6 +633,10 @@ The signal "sys_flash_d_1_IOBUF/N2" is sourceless and has been removed. The signal "sys_flash_d_1_IOBUF/N3" is sourceless and has been removed. The signal "sys_flash_d_0_IOBUF/N2" is sourceless and has been removed. The signal "sys_flash_d_0_IOBUF/N3" is sourceless and has been removed. +The signal "sys_phy_tx_clk_BUFGP/N2" is sourceless and has been removed. +The signal "sys_phy_tx_clk_BUFGP/N3" is sourceless and has been removed. +The signal "sys_phy_rx_clk_BUFGP/N2" is sourceless and has been removed. +The signal "sys_phy_rx_clk_BUFGP/N3" is sourceless and has been removed. The signal "inst_ps2_phy_1/IOBUF_inst_ps2_data/N2" is sourceless and has been removed. The signal "inst_ps2_phy_1/IOBUF_inst_ps2_data/N3" is sourceless and has been @@ -681,6 +653,8 @@ The signal "inst_ps2_phy_0/IOBUF_inst_ps2_clk/N2" is sourceless and has been removed. The signal "inst_ps2_phy_0/IOBUF_inst_ps2_clk/N3" is sourceless and has been removed. +The signal "sys_phy_mdio_IOBUF/N2" is sourceless and has been removed. +The signal "sys_phy_mdio_IOBUF/N3" is sourceless and has been removed. The signal "sys_sdr_data_31_IOBUF/N2" is sourceless and has been removed. The signal "sys_sdr_data_31_IOBUF/N3" is sourceless and has been removed. The signal "sys_sdr_data_30_IOBUF/N2" is sourceless and has been removed. @@ -817,6 +791,12 @@ Unused block "sys_flash_d_8_IOBUF/XST_GND" (ZERO) removed. Unused block "sys_flash_d_8_IOBUF/XST_VCC" (ONE) removed. Unused block "sys_flash_d_9_IOBUF/XST_GND" (ZERO) removed. Unused block "sys_flash_d_9_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_phy_mdio_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_phy_mdio_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_phy_rx_clk_BUFGP/XST_GND" (ZERO) removed. +Unused block "sys_phy_rx_clk_BUFGP/XST_VCC" (ONE) removed. +Unused block "sys_phy_tx_clk_BUFGP/XST_GND" (ZERO) removed. +Unused block "sys_phy_tx_clk_BUFGP/XST_VCC" (ONE) removed. Unused block "sys_sdr_data_0_IOBUF/XST_GND" (ZERO) removed. Unused block "sys_sdr_data_0_IOBUF/XST_VCC" (ONE) removed. Unused block "sys_sdr_data_10_IOBUF/XST_GND" (ZERO) removed. @@ -923,870 +903,3 @@ VCC inst_mips_top/XST_VCC To enable printing of redundant blocks removed and signals merged, set the detailed map report option and rerun map. - -Section 6 - IOB Properties --------------------------- - -+-------------------------------------------------------------------------------------------------------------------------------------------------+ -| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB | -| | | | | Strength | Rate | | | Delay | -+-------------------------------------------------------------------------------------------------------------------------------------------------+ -| sys_ac97_bit_clk | IOB | INPUT | LVCMOS33 | | | | | | -| sys_ac97_sdata_in | IOB | INPUT | LVCMOS33 | | | IFF1 | | | -| sys_ac97_sdata_out | IOB | OUTPUT | LVCMOS25 | 12 | FAST | OFF1 | | | -| sys_ac97_ssync | IOB | OUTPUT | LVCMOS25 | 12 | FAST | OFF1 | | | -| sys_btn<0> | IOB | INPUT | LVCMOS25 | | | IFF1 | PULLDOWN | | -| sys_btn<1> | IOB | INPUT | LVCMOS25 | | | IFF1 | PULLDOWN | | -| sys_btn<2> | IOB | INPUT | LVCMOS25 | | | IFF1 | PULLDOWN | | -| sys_btn<3> | IOB | INPUT | LVCMOS25 | | | IFF1 | PULLDOWN | | -| sys_btn<4> | IOB | INPUT | LVCMOS25 | | | IFF1 | PULLDOWN | | -| sys_clk_in | IOB | INPUT | LVCMOS33 | | | | | | -| sys_dip<0> | IOB | INPUT | LVCMOS33 | | | IFF1 | PULLDOWN | | -| sys_dip<1> | IOB | INPUT | LVCMOS33 | | | IFF1 | PULLDOWN | | -| sys_dip<2> | IOB | INPUT | LVCMOS33 | | | IFF1 | PULLDOWN | | -| sys_dip<3> | IOB | INPUT | LVCMOS33 | | | IFF1 | PULLDOWN | | -| sys_dip<4> | IOB | INPUT | LVCMOS33 | | | IFF1 | PULLDOWN | | -| sys_dip<5> | IOB | INPUT | LVCMOS33 | | | IFF1 | PULLDOWN | | -| sys_dip<6> | IOB | INPUT | LVCMOS33 | | | IFF1 | PULLDOWN | | -| sys_dip<7> | IOB | INPUT | LVCMOS33 | | | IFF1 | PULLDOWN | | -| sys_error<0> | IOB | OUTPUT | LVCMOS33 | 2 | SLOW | OFF1 | | | -| sys_error<1> | IOB | OUTPUT | LVCMOS33 | 2 | SLOW | OFF1 | | | -| sys_flash_a<0> | IOB | OUTPUT | LVDCI_33 | | | | | | -| sys_flash_a<1> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | -| sys_flash_a<2> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | -| sys_flash_a<3> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | -| sys_flash_a<4> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | -| sys_flash_a<5> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | -| sys_flash_a<6> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | -| sys_flash_a<7> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | -| sys_flash_a<8> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | -| sys_flash_a<9> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | -| sys_flash_a<10> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | -| sys_flash_a<11> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | -| sys_flash_a<12> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | -| sys_flash_a<13> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | -| sys_flash_a<14> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | -| sys_flash_a<15> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | -| sys_flash_a<16> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | -| sys_flash_a<17> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | -| sys_flash_a<18> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | -| sys_flash_a<19> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | -| sys_flash_a<20> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | -| sys_flash_a<21> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | -| sys_flash_a<22> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | -| sys_flash_a<23> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | -| sys_flash_a<24> | IOB | OUTPUT | LVDCI_33 | | | | | | -| sys_flash_ac97_rstn | IOB | OUTPUT | LVCMOS33 | 8 | FAST | | | | -| sys_flash_byten | IOB | OUTPUT | LVCMOS33 | 8 | FAST | | | | -| sys_flash_ce | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | -| sys_flash_d<0> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_flash_d<1> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_flash_d<2> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_flash_d<3> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_flash_d<4> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_flash_d<5> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_flash_d<6> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_flash_d<7> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_flash_d<8> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_flash_d<9> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_flash_d<10> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_flash_d<11> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_flash_d<12> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_flash_d<13> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_flash_d<14> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_flash_d<15> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_flash_d<16> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_flash_d<17> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_flash_d<18> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_flash_d<19> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_flash_d<20> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_flash_d<21> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_flash_d<22> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_flash_d<23> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_flash_d<24> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_flash_d<25> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_flash_d<26> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_flash_d<27> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_flash_d<28> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_flash_d<29> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_flash_d<30> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_flash_d<31> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_flash_rdn | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | -| sys_flash_wrn | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | -| sys_lcd_d<0> | IOB | OUTPUT | LVCMOS33 | 2 | SLOW | | PULLDOWN | | -| sys_lcd_d<1> | IOB | OUTPUT | LVCMOS33 | 2 | SLOW | | PULLDOWN | | -| sys_lcd_d<2> | IOB | OUTPUT | LVCMOS33 | 2 | SLOW | | PULLDOWN | | -| sys_lcd_d<3> | IOB | OUTPUT | LVCMOS33 | 2 | SLOW | | PULLDOWN | | -| sys_lcd_e | IOB | OUTPUT | LVCMOS33 | 2 | SLOW | | | | -| sys_lcd_rs | IOB | OUTPUT | LVCMOS33 | 2 | SLOW | | | | -| sys_lcd_rw | IOB | OUTPUT | LVCMOS33 | 2 | SLOW | | | | -| sys_led<0> | IOB | OUTPUT | LVCMOS25 | 2 | SLOW | OFF1 | | | -| sys_led<1> | IOB | OUTPUT | LVCMOS25 | 2 | SLOW | OFF1 | | | -| sys_led<2> | IOB | OUTPUT | LVCMOS25 | 2 | SLOW | OFF1 | | | -| sys_led<3> | IOB | OUTPUT | LVCMOS25 | 2 | SLOW | OFF1 | | | -| sys_led<4> | IOB | OUTPUT | LVCMOS25 | 2 | SLOW | OFF1 | | | -| sys_led<5> | IOB | OUTPUT | LVCMOS25 | 2 | SLOW | OFF1 | | | -| sys_led<6> | IOB | OUTPUT | LVCMOS25 | 2 | SLOW | OFF1 | | | -| sys_led<7> | IOB | OUTPUT | LVCMOS25 | 2 | SLOW | OFF1 | | | -| sys_led<8> | IOB | OUTPUT | LVCMOS25 | 2 | SLOW | OFF1 | | | -| sys_ps2_0_clk | IOB | BIDIR | LVCMOS25 | 2 | SLOW | IFF1 | | | -| sys_ps2_0_data | IOB | BIDIR | LVCMOS25 | 2 | SLOW | IFF1 | | | -| sys_ps2_1_clk | IOB | BIDIR | LVCMOS25 | 2 | SLOW | IFF1 | | | -| sys_ps2_1_data | IOB | BIDIR | LVCMOS25 | 2 | SLOW | IFF1 | | | -| sys_rst_n_in | IOB | INPUT | LVCMOS25 | | | | PULLUP | | -| sys_sdr_a_q<0> | IOB | OUTPUT | SSTL2_I | | | OFF1 | | | -| sys_sdr_a_q<1> | IOB | OUTPUT | SSTL2_I | | | OFF1 | | | -| sys_sdr_a_q<2> | IOB | OUTPUT | SSTL2_I | | | OFF1 | | | -| sys_sdr_a_q<3> | IOB | OUTPUT | SSTL2_I | | | OFF1 | | | -| sys_sdr_a_q<4> | IOB | OUTPUT | SSTL2_I | | | OFF1 | | | -| sys_sdr_a_q<5> | IOB | OUTPUT | SSTL2_I | | | OFF1 | | | -| sys_sdr_a_q<6> | IOB | OUTPUT | SSTL2_I | | | OFF1 | | | -| sys_sdr_a_q<7> | IOB | OUTPUT | SSTL2_I | | | OFF1 | | | -| sys_sdr_a_q<8> | IOB | OUTPUT | SSTL2_I | | | OFF1 | | | -| sys_sdr_a_q<9> | IOB | OUTPUT | SSTL2_I | | | OFF1 | | | -| sys_sdr_a_q<10> | IOB | OUTPUT | SSTL2_I | | | OFF1 | | | -| sys_sdr_a_q<11> | IOB | OUTPUT | SSTL2_I | | | OFF1 | | | -| sys_sdr_a_q<12> | IOB | OUTPUT | SSTL2_I | | | OFF1 | | | -| sys_sdr_ba_q<0> | IOB | OUTPUT | SSTL2_I | | | OFF1 | | | -| sys_sdr_ba_q<1> | IOB | OUTPUT | SSTL2_I | | | OFF1 | | | -| sys_sdr_cas_qn | IOB | OUTPUT | SSTL2_I | | | OFF1 | | | -| sys_sdr_cke_q | IOB | OUTPUT | SSTL2_I | | | OFF1 | | | -| sys_sdr_clk_fb | IOB | INPUT | LVCMOS25 | | | | | | -| sys_sdr_clk_n | IOB | OUTPUT | SSTL2_I | | | OFF1 | | | -| | ODDR:OPPOSITE | | | | | OFF2 | | | -| | | | | | | OFFDDRA | | | -| sys_sdr_clk_p | IOB | OUTPUT | SSTL2_I | | | OFF1 | | | -| | ODDR:OPPOSITE | | | | | OFF2 | | | -| | | | | | | OFFDDRA | | | -| sys_sdr_cs_qn | IOB | OUTPUT | SSTL2_I | | | OFF1 | | | -| sys_sdr_data<0> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | -| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | -| | | | | | | IFF4 | | | -| | | | | | | OFF1 | | | -| | | | | | | OFF2 | | | -| | | | | | | OFF3 | | | -| | | | | | | OFFDDRB | | | -| sys_sdr_data<1> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | -| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | -| | | | | | | IFF4 | | | -| | | | | | | OFF1 | | | -| | | | | | | OFF2 | | | -| | | | | | | OFF3 | | | -| | | | | | | OFFDDRB | | | -| sys_sdr_data<2> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | -| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | -| | | | | | | IFF4 | | | -| | | | | | | OFF1 | | | -| | | | | | | OFF2 | | | -| | | | | | | OFF3 | | | -| | | | | | | OFFDDRB | | | -| sys_sdr_data<3> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | -| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | -| | | | | | | IFF4 | | | -| | | | | | | OFF1 | | | -| | | | | | | OFF2 | | | -| | | | | | | OFF3 | | | -| | | | | | | OFFDDRB | | | -| sys_sdr_data<4> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | -| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | -| | | | | | | IFF4 | | | -| | | | | | | OFF1 | | | -| | | | | | | OFF2 | | | -| | | | | | | OFF3 | | | -| | | | | | | OFFDDRB | | | -| sys_sdr_data<5> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | -| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | -| | | | | | | IFF4 | | | -| | | | | | | OFF1 | | | -| | | | | | | OFF2 | | | -| | | | | | | OFF3 | | | -| | | | | | | OFFDDRB | | | -| sys_sdr_data<6> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | -| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | -| | | | | | | IFF4 | | | -| | | | | | | OFF1 | | | -| | | | | | | OFF2 | | | -| | | | | | | OFF3 | | | -| | | | | | | OFFDDRB | | | -| sys_sdr_data<7> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | -| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | -| | | | | | | IFF4 | | | -| | | | | | | OFF1 | | | -| | | | | | | OFF2 | | | -| | | | | | | OFF3 | | | -| | | | | | | OFFDDRB | | | -| sys_sdr_data<8> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | -| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | -| | | | | | | IFF4 | | | -| | | | | | | OFF1 | | | -| | | | | | | OFF2 | | | -| | | | | | | OFF3 | | | -| | | | | | | OFFDDRB | | | -| sys_sdr_data<9> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | -| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | -| | | | | | | IFF4 | | | -| | | | | | | OFF1 | | | -| | | | | | | OFF2 | | | -| | | | | | | OFF3 | | | -| | | | | | | OFFDDRB | | | -| sys_sdr_data<10> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | -| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | -| | | | | | | IFF4 | | | -| | | | | | | OFF1 | | | -| | | | | | | OFF2 | | | -| | | | | | | OFF3 | | | -| | | | | | | OFFDDRB | | | -| sys_sdr_data<11> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | -| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | -| | | | | | | IFF4 | | | -| | | | | | | OFF1 | | | -| | | | | | | OFF2 | | | -| | | | | | | OFF3 | | | -| | | | | | | OFFDDRB | | | -| sys_sdr_data<12> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | -| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | -| | | | | | | IFF4 | | | -| | | | | | | OFF1 | | | -| | | | | | | OFF2 | | | -| | | | | | | OFF3 | | | -| | | | | | | OFFDDRB | | | -| sys_sdr_data<13> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | -| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | -| | | | | | | IFF4 | | | -| | | | | | | OFF1 | | | -| | | | | | | OFF2 | | | -| | | | | | | OFF3 | | | -| | | | | | | OFFDDRB | | | -| sys_sdr_data<14> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | -| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | -| | | | | | | IFF4 | | | -| | | | | | | OFF1 | | | -| | | | | | | OFF2 | | | -| | | | | | | OFF3 | | | -| | | | | | | OFFDDRB | | | -| sys_sdr_data<15> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | -| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | -| | | | | | | IFF4 | | | -| | | | | | | OFF1 | | | -| | | | | | | OFF2 | | | -| | | | | | | OFF3 | | | -| | | | | | | OFFDDRB | | | -| sys_sdr_data<16> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | -| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | -| | | | | | | IFF4 | | | -| | | | | | | OFF1 | | | -| | | | | | | OFF2 | | | -| | | | | | | OFF3 | | | -| | | | | | | OFFDDRB | | | -| sys_sdr_data<17> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | -| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | -| | | | | | | IFF4 | | | -| | | | | | | OFF1 | | | -| | | | | | | OFF2 | | | -| | | | | | | OFF3 | | | -| | | | | | | OFFDDRB | | | -| sys_sdr_data<18> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | -| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | -| | | | | | | IFF4 | | | -| | | | | | | OFF1 | | | -| | | | | | | OFF2 | | | -| | | | | | | OFF3 | | | -| | | | | | | OFFDDRB | | | -| sys_sdr_data<19> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | -| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | -| | | | | | | IFF4 | | | -| | | | | | | OFF1 | | | -| | | | | | | OFF2 | | | -| | | | | | | OFF3 | | | -| | | | | | | OFFDDRB | | | -| sys_sdr_data<20> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | -| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | -| | | | | | | IFF4 | | | -| | | | | | | OFF1 | | | -| | | | | | | OFF2 | | | -| | | | | | | OFF3 | | | -| | | | | | | OFFDDRB | | | -| sys_sdr_data<21> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | -| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | -| | | | | | | IFF4 | | | -| | | | | | | OFF1 | | | -| | | | | | | OFF2 | | | -| | | | | | | OFF3 | | | -| | | | | | | OFFDDRB | | | -| sys_sdr_data<22> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | -| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | -| | | | | | | IFF4 | | | -| | | | | | | OFF1 | | | -| | | | | | | OFF2 | | | -| | | | | | | OFF3 | | | -| | | | | | | OFFDDRB | | | -| sys_sdr_data<23> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | -| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | -| | | | | | | IFF4 | | | -| | | | | | | OFF1 | | | -| | | | | | | OFF2 | | | -| | | | | | | OFF3 | | | -| | | | | | | OFFDDRB | | | -| sys_sdr_data<24> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | -| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | -| | | | | | | IFF4 | | | -| | | | | | | OFF1 | | | -| | | | | | | OFF2 | | | -| | | | | | | OFF3 | | | -| | | | | | | OFFDDRB | | | -| sys_sdr_data<25> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | -| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | -| | | | | | | IFF4 | | | -| | | | | | | OFF1 | | | -| | | | | | | OFF2 | | | -| | | | | | | OFF3 | | | -| | | | | | | OFFDDRB | | | -| sys_sdr_data<26> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | -| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | -| | | | | | | IFF4 | | | -| | | | | | | OFF1 | | | -| | | | | | | OFF2 | | | -| | | | | | | OFF3 | | | -| | | | | | | OFFDDRB | | | -| sys_sdr_data<27> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | -| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | -| | | | | | | IFF4 | | | -| | | | | | | OFF1 | | | -| | | | | | | OFF2 | | | -| | | | | | | OFF3 | | | -| | | | | | | OFFDDRB | | | -| sys_sdr_data<28> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | -| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | -| | | | | | | IFF4 | | | -| | | | | | | OFF1 | | | -| | | | | | | OFF2 | | | -| | | | | | | OFF3 | | | -| | | | | | | OFFDDRB | | | -| sys_sdr_data<29> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | -| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | -| | | | | | | IFF4 | | | -| | | | | | | OFF1 | | | -| | | | | | | OFF2 | | | -| | | | | | | OFF3 | | | -| | | | | | | OFFDDRB | | | -| sys_sdr_data<30> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | -| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | -| | | | | | | IFF4 | | | -| | | | | | | OFF1 | | | -| | | | | | | OFF2 | | | -| | | | | | | OFF3 | | | -| | | | | | | OFFDDRB | | | -| sys_sdr_data<31> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | -| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | -| | | | | | | IFF4 | | | -| | | | | | | OFF1 | | | -| | | | | | | OFF2 | | | -| | | | | | | OFF3 | | | -| | | | | | | OFFDDRB | | | -| sys_sdr_dm_q<0> | IOB | OUTPUT | SSTL2_II | | | OFF1 | | | -| | ODDR:SAME | | | | | OFF2 | | | -| | | | | | | OFF3 | | | -| | | | | | | OFFDDRB | | | -| sys_sdr_dm_q<1> | IOB | OUTPUT | SSTL2_II | | | OFF1 | | | -| | ODDR:SAME | | | | | OFF2 | | | -| | | | | | | OFF3 | | | -| | | | | | | OFFDDRB | | | -| sys_sdr_dm_q<2> | IOB | OUTPUT | SSTL2_II | | | OFF1 | | | -| | ODDR:SAME | | | | | OFF2 | | | -| | | | | | | OFF3 | | | -| | | | | | | OFFDDRB | | | -| sys_sdr_dm_q<3> | IOB | OUTPUT | SSTL2_II | | | OFF1 | | | -| | ODDR:SAME | | | | | OFF2 | | | -| | | | | | | OFF3 | | | -| | | | | | | OFFDDRB | | | -| sys_sdr_dqs_q<0> | IOB | OUTPUT | SSTL2_II | | | OFF1 | | | -| | ODDR:OPPOSITE | | | | | OFF2 | | | -| | | | | | | OFFDDRA | | | -| sys_sdr_dqs_q<1> | IOB | OUTPUT | SSTL2_II | | | OFF1 | | | -| | ODDR:OPPOSITE | | | | | OFF2 | | | -| | | | | | | OFFDDRA | | | -| sys_sdr_dqs_q<2> | IOB | OUTPUT | SSTL2_II | | | OFF1 | | | -| | ODDR:OPPOSITE | | | | | OFF2 | | | -| | | | | | | OFFDDRA | | | -| sys_sdr_dqs_q<3> | IOB | OUTPUT | SSTL2_II | | | OFF1 | | | -| | ODDR:OPPOSITE | | | | | OFF2 | | | -| | | | | | | OFFDDRA | | | -| sys_sdr_ras_qn | IOB | OUTPUT | SSTL2_I | | | OFF1 | | | -| sys_sdr_we_qn | IOB | OUTPUT | SSTL2_I | | | OFF1 | | | -| sys_uart0_rx | IOB | INPUT | LVCMOS33 | | | IFF1 | | | -| sys_uart0_tx | IOB | OUTPUT | LVCMOS33 | 12 | SLOW | OFF1 | | | -| sys_uart1_rx | IOB | INPUT | LVCMOS33 | | | | | | -| sys_uart1_tx | IOB | OUTPUT | LVCMOS33 | 12 | SLOW | | | | -| sys_uart2_rx | IOB | INPUT | LVCMOS33 | | | | | | -| sys_uart2_tx | IOB | OUTPUT | LVCMOS33 | 12 | SLOW | | | | -| sys_uart3_rx | IOB | INPUT | LVCMOS33 | | | | | | -| sys_uart3_tx | IOB | OUTPUT | LVCMOS33 | 12 | SLOW | | | | -| sys_usb_a<0> | IOB | OUTPUT | LVCMOS33 | 12 | SLOW | OFF1 | | | -| sys_usb_a<1> | IOB | OUTPUT | LVCMOS33 | 12 | SLOW | OFF1 | | | -| sys_usb_csn | IOB | OUTPUT | LVCMOS33 | 8 | FAST | OFF1 | | | -| sys_usb_d<0> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_usb_d<1> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_usb_d<2> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_usb_d<3> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_usb_d<4> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_usb_d<5> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_usb_d<6> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_usb_d<7> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_usb_d<8> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_usb_d<9> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_usb_d<10> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_usb_d<11> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_usb_d<12> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_usb_d<13> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_usb_d<14> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_usb_d<15> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | | -| | | | | | | OFF1 | | | -| | | | | | | TFF1 | | | -| sys_usb_int | IOB | INPUT | LVCMOS33 | | | | PULLDOWN | | -| sys_usb_rdn | IOB | OUTPUT | LVCMOS33 | 8 | FAST | OFF1 | | | -| sys_usb_rstn | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | -| sys_usb_wrn | IOB | OUTPUT | LVCMOS33 | 8 | FAST | OFF1 | | | -| sys_vga_blank_n | IOB | OUTPUT | LVCMOS33 | 8 | FAST | | | | -| sys_vga_blue<0> | IOB | OUTPUT | LVCMOS33 | 8 | FAST | OFF1 | | | -| sys_vga_blue<1> | IOB | OUTPUT | LVCMOS33 | 8 | FAST | OFF1 | | | -| sys_vga_blue<2> | IOB | OUTPUT | LVCMOS33 | 8 | FAST | OFF1 | | | -| sys_vga_blue<3> | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | | -| sys_vga_blue<4> | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | | -| sys_vga_blue<5> | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | | -| sys_vga_blue<6> | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | | -| sys_vga_blue<7> | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | | -| sys_vga_clk | IOB | OUTPUT | LVDCI_33 | | | | | | -| sys_vga_green<0> | IOB | OUTPUT | LVCMOS33 | 8 | FAST | OFF1 | | | -| sys_vga_green<1> | IOB | OUTPUT | LVCMOS33 | 8 | FAST | OFF1 | | | -| sys_vga_green<2> | IOB | OUTPUT | LVCMOS33 | 8 | FAST | OFF1 | | | -| sys_vga_green<3> | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | | -| sys_vga_green<4> | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | | -| sys_vga_green<5> | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | | -| sys_vga_green<6> | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | | -| sys_vga_green<7> | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | | -| sys_vga_hsync | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | | -| sys_vga_red<0> | IOB | OUTPUT | LVCMOS33 | 8 | FAST | OFF1 | | | -| sys_vga_red<1> | IOB | OUTPUT | LVCMOS33 | 8 | FAST | OFF1 | | | -| sys_vga_red<2> | IOB | OUTPUT | LVCMOS33 | 8 | FAST | OFF1 | | | -| sys_vga_red<3> | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | | -| sys_vga_red<4> | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | | -| sys_vga_red<5> | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | | -| sys_vga_red<6> | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | | -| sys_vga_red<7> | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | | -| sys_vga_sync_n | IOB | OUTPUT | LVCMOS33 | 8 | FAST | | | | -| sys_vga_vsync | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | | -+-------------------------------------------------------------------------------------------------------------------------------------------------+ - -Section 7 - RPMs ----------------- - -Section 8 - Guide Report ------------------------- -Guide not run on this design. - -Section 9 - Area Group and Partition Summary --------------------------------------------- - -Partition Implementation Status -------------------------------- - - No Partitions were found in this design. - -------------------------------- - -Area Group Information ----------------------- - -Area Group "AG_inst_mips_top" - No COMPRESSION specified for Area Group "AG_inst_mips_top" - RANGE: SLICE_X0Y53:SLICE_X39Y0 - RANGE: -RAMB16_X0Y0:RAMB16_X0Y6,RAMB16_X1Y0:RAMB16_X1Y6,RAMB16_X2Y0:RAMB16_X2Y6,RAMB16_X -3Y0:RAMB16_X3Y6 - Area Group Logic Utilization: - Number of Slice Flip Flops: 1,962 out of 4,320 45% - Logic Distribution: - Number of occupied Slices: 2,157 out of 2,160 99% - Number of Slices containing only related logic: 2,157 out of 2,157 100% - Total Number of 4 input LUTs: 4,309 out of 4,320 99% - Number used as logic: 3,649 - Number used as route-thru: 49 - Number used as Dual Port RAMs: 586 - (Two LUTs used per Dual Port RAM) - Number used as Shift registers: 25 - Number of Block RAMs: 27 out of 28 96% - - -Section 10 - Modular Design Summary ------------------------------------ -Modular Design not used for this design. - -Section 11 - Timing Report --------------------------- -A logic-level (pre-route) timing report can be generated by using Xilinx static -timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the -mapped NCD and PCF files. Please note that this timing report will be generated -using estimated delay information. For accurate numbers, please generate a -timing report with the post Place and Route NCD file. - -For more information about the Timing Analyzer, consult the Xilinx Timing -Analyzer Reference Manual; for more information about TRCE, consult the Xilinx -Development System Reference Guide "TRACE" chapter. - -Section 12 - Configuration String Details ------------------------------------------ -Use the "-detail" map option to print out Configuration Strings - -Section 13 - Control Set Information ------------------------------------- -No control set information for this architecture. - -Section 14 - Utilization by Hierarchy -------------------------------------- -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -| Module | Partition | Slices | Slice Reg | LUTs | LUTRAM | BRAM/FIFO | DSP48 | BUFG | BUFIO | BUFR | DCM | Full Hierarchical Name | -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -| mips_sys/ | | 1376/8103 | 28/5422 | 845/9032 | 2/1000 | 0/51 | 0/0 | 2/12 | 0/0 | 0/0 | 0/4 | mips_sys | -| +inst_ac97_wb | | 181/823 | 118/672 | 186/631 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb | -| ++inst_ac_io | | 21/598 | 13/525 | 29/380 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io | -| +++inst_ac_in | | 254/260 | 258/262 | 98/103 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_in | -| ++++singleshot_inst1 | | 3/3 | 2/2 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_in/singleshot_inst1 | -| ++++singleshot_inst2 | | 3/3 | 2/2 | 3/3 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_in/singleshot_inst2 | -| +++inst_ac_out | | 314/317 | 248/250 | 246/248 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_out | -| ++++singleshot_inst1 | | 3/3 | 2/2 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_out/singleshot_inst1 | -| ++inst_tx_fifo | | 1/44 | 0/29 | 1/65 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_tx_fifo | -| +++inst_dpram_1w1r | | 0/0 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_tx_fifo/inst_dpram_1w1r | -| +++inst_fifo_sync_ctrl | | 43/43 | 29/29 | 64/64 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_tx_fifo/inst_fifo_sync_ctrl | -| +inst_clockgen | | 41/47 | 54/54 | 18/24 | 4/10 | 0/0 | 0/0 | 8/8 | 0/0 | 0/0 | 4/4 | mips_sys/inst_clockgen | -| ++Mshreg_reset_pipe0_19_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_clockgen/Mshreg_reset_pipe0_19_0 | -| ++Mshreg_reset_pipe0_19_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_clockgen/Mshreg_reset_pipe0_19_1 | -| ++Mshreg_reset_pipe1_19_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_clockgen/Mshreg_reset_pipe1_19_0 | -| ++Mshreg_reset_pipe1_19_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_clockgen/Mshreg_reset_pipe1_19_1 | -| ++Mshreg_reset_pipe2_19_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_clockgen/Mshreg_reset_pipe2_19_0 | -| ++Mshreg_reset_pipe2_19_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_clockgen/Mshreg_reset_pipe2_19_1 | -| +inst_flash_port | | 81/81 | 65/65 | 54/54 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_flash_port | -| +inst_gpio_wb | | 285/285 | 298/298 | 433/433 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_gpio_wb | -| +inst_mips_top | | 23/2822 | 22/1961 | 12/4222 | 2/611 | 0/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top | -| ++Mshreg_reset_delay_15 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/Mshreg_reset_delay_15 | -| ++Mshreg_reset_delay_19 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/Mshreg_reset_delay_19 | -| ++Mshreg_reset_delay_30 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/Mshreg_reset_delay_30 | -| ++inst_biu | | 177/800 | 97/570 | 211/936 | 0/350 | 0/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu | -| +++inst_bin_fifo | | 2/100 | 0/62 | 2/107 | 0/74 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo | -| ++++inst_dpram_1w1r | | 57/57 | 32/32 | 64/64 | 64/64 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r | -| ++++inst_fifo_async_ctrl | | 13/41 | 12/30 | 6/41 | 0/10 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl | -| +++++Mshreg_gcnt2_r_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_0 | -| +++++Mshreg_gcnt2_r_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_1 | -| +++++Mshreg_gcnt2_r_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_2 | -| +++++Mshreg_gcnt2_r_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_3 | -| +++++Mshreg_gcnt2_r_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_4 | -| +++++Mshreg_gcnt2_w_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_0 | -| +++++Mshreg_gcnt2_w_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_1 | -| +++++Mshreg_gcnt2_w_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_2 | -| +++++Mshreg_gcnt2_w_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_3 | -| +++++Mshreg_gcnt2_w_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_4 | -| +++++inst_gray_counter_r | | 10/10 | 9/9 | 13/13 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/inst_gray_counter_r | -| +++++inst_gray_counter_w | | 8/8 | 9/9 | 12/12 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/inst_gray_counter_w | -| +++inst_bout_fifo | | 3/146 | 0/97 | 3/179 | 0/144 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo | -| ++++inst_dpram_1w1r | | 102/102 | 67/67 | 134/134 | 134/134 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_dpram_1w1r | -| ++++inst_fifo_async_ctrl | | 12/41 | 12/30 | 6/42 | 0/10 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl | -| +++++Mshreg_gcnt2_r_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_0 | -| +++++Mshreg_gcnt2_r_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_1 | -| +++++Mshreg_gcnt2_r_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_2 | -| +++++Mshreg_gcnt2_r_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_3 | -| +++++Mshreg_gcnt2_r_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_4 | -| +++++Mshreg_gcnt2_w_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_0 | -| +++++Mshreg_gcnt2_w_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_1 | -| +++++Mshreg_gcnt2_w_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_2 | -| +++++Mshreg_gcnt2_w_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_3 | -| +++++Mshreg_gcnt2_w_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_4 | -| +++++inst_gray_counter_r | | 9/9 | 9/9 | 13/13 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_r | -| +++++inst_gray_counter_w | | 10/10 | 9/9 | 13/13 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_w | -| +++inst_dcache | | 172/172 | 156/156 | 155/155 | 0/0 | 0/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_dcache | -| ++++gen_data_ram[0].inst_data_ra | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_dcache/gen_data_ram[0].inst_data_ram | -| ++++gen_data_ram[1].inst_data_ra | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_dcache/gen_data_ram[1].inst_data_ram | -| ++++gen_data_ram[2].inst_data_ra | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_dcache/gen_data_ram[2].inst_data_ram | -| ++++gen_data_ram[3].inst_data_ra | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_dcache/gen_data_ram[3].inst_data_ram | -| ++++inst_tag_ram | | 0/0 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_dcache/inst_tag_ram | -| +++inst_icache | | 117/117 | 81/81 | 123/123 | 0/0 | 0/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_icache | -| ++++inst_data_ram | | 0/0 | 0/0 | 0/0 | 0/0 | 16/16 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_icache/inst_data_ram | -| ++++inst_tag_ram | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_icache/inst_tag_ram | -| +++inst_write_fifo | | 2/88 | 0/77 | 2/161 | 0/132 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_write_fifo | -| ++++inst_dpram_1w1r | | 66/66 | 66/66 | 132/132 | 132/132 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_write_fifo/inst_dpram_1w1r | -| ++++inst_fifo_sync_ctrl | | 20/20 | 11/11 | 27/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_write_fifo/inst_fifo_sync_ctrl | -| ++inst_cop | | 219/219 | 190/190 | 234/234 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_cop | -| ++inst_pipeline | | 880/1777 | 651/1179 | 1380/3037 | 0/256 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline | -| +++inst_alu | | 63/63 | 1/1 | 119/119 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_alu | -| +++inst_bcu | | 8/8 | 0/0 | 16/16 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_bcu | -| +++inst_muldiv | | 554/554 | 527/527 | 1028/1028 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_muldiv | -| +++inst_reg_dual | | 128/128 | 0/0 | 256/256 | 256/256 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_reg_dual | -| +++inst_shifter | | 144/144 | 0/0 | 238/238 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_shifter | -| +inst_ps2_phy_0 | | 0/10 | 0/10 | 0/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_0 | -| ++Inst_debounce_clk | | 5/5 | 5/5 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_0/Inst_debounce_clk | -| ++Inst_debounce_data | | 5/5 | 5/5 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_0/Inst_debounce_data | -| +inst_ps2_phy_1 | | 0/12 | 0/10 | 0/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_1 | -| ++Inst_debounce_clk | | 7/7 | 5/5 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_1/Inst_debounce_clk | -| ++Inst_debounce_data | | 5/5 | 5/5 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_1/Inst_debounce_data | -| +inst_ps2_wb_0 | | 33/159 | 30/139 | 23/169 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_wb_0 | -| ++inst_ps2_core | | 126/126 | 109/109 | 146/146 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_wb_0/inst_ps2_core | -| +inst_ps2_wb_1 | | 33/146 | 30/139 | 21/167 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_wb_1 | -| ++inst_ps2_core | | 113/113 | 109/109 | 146/146 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_wb_1/inst_ps2_core | -| +inst_rom_wb | | 1/77 | 1/99 | 1/53 | 0/2 | 0/4 | 0/0 | 0/2 | 0/0 | 0/0 | 0/0 | mips_sys/inst_rom_wb | -| ++inst_rom | | 76/76 | 98/98 | 52/52 | 2/2 | 4/4 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | mips_sys/inst_rom_wb/inst_rom | -| +inst_sdram_ctrl_frontend_wb | | 100/629 | 0/455 | 145/593 | 0/39 | 0/6 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb | -| ++inst_cat_fifo | | 2/15 | 0/13 | 2/23 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_cat_fifo | -| +++inst_dpram_1w1r | | 0/0 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_dpram_1w1r | -| +++inst_fifo_sync_ctrl | | 13/13 | 13/13 | 21/21 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_fifo_sync_ctrl | -| ++inst_read_fifo | | 2/50 | 0/36 | 2/54 | 0/12 | 0/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo | -| +++inst_dpram_1w1r | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_dpram_1w1r | -| +++inst_fifo_async_ctrl | | 17/48 | 14/36 | 10/52 | 0/12 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl | -| ++++Mshreg_gcnt2_r_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_0 | -| ++++Mshreg_gcnt2_r_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_1 | -| ++++Mshreg_gcnt2_r_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_2 | -| ++++Mshreg_gcnt2_r_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_3 | -| ++++Mshreg_gcnt2_r_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_4 | -| ++++Mshreg_gcnt2_r_5 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_5 | -| ++++Mshreg_gcnt2_w_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_0 | -| ++++Mshreg_gcnt2_w_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_1 | -| ++++Mshreg_gcnt2_w_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_2 | -| ++++Mshreg_gcnt2_w_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_3 | -| ++++Mshreg_gcnt2_w_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_4 | -| ++++Mshreg_gcnt2_w_5 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_5 | -| ++++inst_gray_counter_r | | 9/9 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/inst_gray_counter_r | -| ++++inst_gray_counter_w | | 10/10 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/inst_gray_counter_w | -| ++inst_sdram_ctrl | | 0/410 | 0/370 | 0/317 | 0/15 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl | -| +++inst_ddr_phy | | 167/168 | 216/216 | 2/3 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy | -| ++++Mshreg_u_tag_pipe_4_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/Mshreg_u_tag_pipe_4_0 | -| +++inst_sd_cmd_fifo | | 4/61 | 0/41 | 6/58 | 0/14 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo | -| ++++inst_dpram_1w1r | | 0/0 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r | -| ++++inst_fifo_async_ctrl | | 19/57 | 17/41 | 9/52 | 0/14 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl | -| +++++Mshreg_gcnt2_r_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_0 | -| +++++Mshreg_gcnt2_r_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_1 | -| +++++Mshreg_gcnt2_r_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_2 | -| +++++Mshreg_gcnt2_r_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_4 | -| +++++Mshreg_gcnt2_r_5 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_5 | -| +++++Mshreg_gcnt2_w_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_0 | -| +++++Mshreg_gcnt2_w_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_1 | -| +++++Mshreg_gcnt2_w_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_2 | -| +++++Mshreg_gcnt2_w_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_3 | -| +++++Mshreg_gcnt2_w_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_4 | -| +++++Mshreg_gcnt2_w_5 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_5 | -| +++++Mshreg_p2_3_BRB0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_p2_3_BRB0 | -| +++++Mshreg_p2_3_BRB1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_p2_3_BRB1 | -| +++++Mshreg_p2_3_BRB2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_p2_3_BRB2 | -| +++++inst_gray_counter_r | | 14/14 | 13/13 | 14/14 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r | -| +++++inst_gray_counter_w | | 10/10 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_w | -| +++inst_sdram_cmd | | 47/47 | 13/13 | 65/65 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd | -| +++inst_sdram_ctrl | | 134/134 | 100/100 | 191/191 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl | -| ++inst_write_fifo | | 3/54 | 0/36 | 3/54 | 0/12 | 0/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo | -| +++inst_dpram_1w1r | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_dpram_1w1r | -| +++inst_fifo_async_ctrl | | 18/51 | 14/36 | 9/51 | 0/12 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl | -| ++++Mshreg_gcnt2_r_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_0 | -| ++++Mshreg_gcnt2_r_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_1 | -| ++++Mshreg_gcnt2_r_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_2 | -| ++++Mshreg_gcnt2_r_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_3 | -| ++++Mshreg_gcnt2_r_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_4 | -| ++++Mshreg_gcnt2_r_5 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_5 | -| ++++Mshreg_gcnt2_w_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_0 | -| ++++Mshreg_gcnt2_w_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_1 | -| ++++Mshreg_gcnt2_w_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_2 | -| ++++Mshreg_gcnt2_w_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_3 | -| ++++Mshreg_gcnt2_w_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_4 | -| ++++Mshreg_gcnt2_w_5 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_5 | -| ++++inst_gray_counter_r | | 10/10 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/inst_gray_counter_r | -| ++++inst_gray_counter_w | | 11/11 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/inst_gray_counter_w | -| +inst_uart_wb_0 | | 61/109 | 64/106 | 43/111 | 0/36 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0 | -| ++inst_uart_rx | | 0/30 | 0/28 | 0/38 | 0/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_rx | -| +++buf | | 8/8 | 5/5 | 16/16 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_rx/buf | -| +++kcuart | | 22/22 | 23/23 | 22/22 | 19/19 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_rx/kcuart | -| ++inst_uart_tx | | 0/18 | 0/14 | 0/30 | 0/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_tx | -| +++buf | | 8/8 | 5/5 | 16/16 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_tx/buf | -| +++kcuart | | 10/10 | 9/9 | 14/14 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_tx/kcuart | -| +inst_uart_wb_1 | | 60/107 | 64/108 | 42/110 | 0/36 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1 | -| ++inst_uart_rx | | 0/28 | 0/29 | 0/38 | 0/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_rx | -| +++buf | | 8/8 | 5/5 | 16/16 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_rx/buf | -| +++kcuart | | 20/20 | 24/24 | 22/22 | 19/19 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_rx/kcuart | -| ++inst_uart_tx | | 0/19 | 0/15 | 0/30 | 0/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_tx | -| +++buf | | 8/8 | 5/5 | 16/16 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_tx/buf | -| +++kcuart | | 11/11 | 10/10 | 14/14 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_tx/kcuart | -| +inst_usb_port | | 36/36 | 27/27 | 31/31 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_usb_port | -| +inst_vga_frontend | | 762/1384 | 793/1251 | 762/1553 | 0/264 | 0/13 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend | -| ++inst_blitfifo | | 4/31 | 0/23 | 4/45 | 0/0 | 0/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_blitfifo | -| +++inst_dpram_1w1r | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_blitfifo/inst_dpram_1w1r | -| +++inst_fifo_sync_ctrl | | 27/27 | 23/23 | 41/41 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl | -| ++inst_bus_fifo | | 4/115 | 0/110 | 4/219 | 0/206 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_bus_fifo | -| +++inst_dpram_1w1r | | 103/103 | 103/103 | 206/206 | 206/206 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_bus_fifo/inst_dpram_1w1r | -| +++inst_fifo_sync_ctrl | | 8/8 | 7/7 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_bus_fifo/inst_fifo_sync_ctrl | -| ++inst_char_gen | | 202/214 | 126/126 | 240/252 | 0/12 | 0/4 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen | -| +++Mshreg_csr_posx_synced_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posx_synced_0 | -| +++Mshreg_csr_posx_synced_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posx_synced_1 | -| +++Mshreg_csr_posx_synced_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posx_synced_2 | -| +++Mshreg_csr_posx_synced_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posx_synced_3 | -| +++Mshreg_csr_posx_synced_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posx_synced_4 | -| +++Mshreg_csr_posx_synced_5 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posx_synced_5 | -| +++Mshreg_csr_posx_synced_6 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posx_synced_6 | -| +++Mshreg_csr_posy_synced_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posy_synced_0 | -| +++Mshreg_csr_posy_synced_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posy_synced_1 | -| +++Mshreg_csr_posy_synced_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posy_synced_2 | -| +++Mshreg_csr_posy_synced_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posy_synced_3 | -| +++Mshreg_csr_posy_synced_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posy_synced_4 | -| +++inst_ascii_ram | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/inst_ascii_ram | -| +++inst_char_rom | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/inst_char_rom | -| ++inst_linefifo | | 2/161 | 0/149 | 2/177 | 0/46 | 0/7 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo | -| +++inst_dpram_1w1r | | 0/0 | 0/0 | 0/0 | 0/0 | 7/7 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_dpram_1w1r | -| +++inst_fifo_async_ctrl | | 72/159 | 91/149 | 81/175 | 0/46 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl | -| ++++Mshreg_bcnt2_ar_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_0 | -| ++++Mshreg_bcnt2_ar_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_1 | -| ++++Mshreg_bcnt2_ar_10 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_10 | -| ++++Mshreg_bcnt2_ar_11 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_11 | -| ++++Mshreg_bcnt2_ar_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_2 | -| ++++Mshreg_bcnt2_ar_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_3 | -| ++++Mshreg_bcnt2_ar_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_4 | -| ++++Mshreg_bcnt2_ar_5 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_5 | -| ++++Mshreg_bcnt2_ar_6 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_6 | -| ++++Mshreg_bcnt2_ar_7 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_7 | -| ++++Mshreg_bcnt2_ar_8 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_8 | -| ++++Mshreg_bcnt2_ar_9 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_9 | -| ++++Mshreg_bcnt2_aw_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_0 | -| ++++Mshreg_bcnt2_aw_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_1 | -| ++++Mshreg_bcnt2_aw_10 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_10 | -| ++++Mshreg_bcnt2_aw_11 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_11 | -| ++++Mshreg_bcnt2_aw_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_2 | -| ++++Mshreg_bcnt2_aw_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_3 | -| ++++Mshreg_bcnt2_aw_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_4 | -| ++++Mshreg_bcnt2_aw_5 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_5 | -| ++++Mshreg_bcnt2_aw_6 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_6 | -| ++++Mshreg_bcnt2_aw_7 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_7 | -| ++++Mshreg_bcnt2_aw_8 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_8 | -| ++++Mshreg_bcnt2_aw_9 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_9 | -| ++++Mshreg_gcnt2_r_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_0 | -| ++++Mshreg_gcnt2_r_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_1 | -| ++++Mshreg_gcnt2_r_10 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_10 | -| ++++Mshreg_gcnt2_r_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_2 | -| ++++Mshreg_gcnt2_r_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_3 | -| ++++Mshreg_gcnt2_r_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_4 | -| ++++Mshreg_gcnt2_r_5 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_5 | -| ++++Mshreg_gcnt2_r_6 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_6 | -| ++++Mshreg_gcnt2_r_7 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_7 | -| ++++Mshreg_gcnt2_r_8 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_8 | -| ++++Mshreg_gcnt2_r_9 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_9 | -| ++++Mshreg_gcnt2_w_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_0 | -| ++++Mshreg_gcnt2_w_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_1 | -| ++++Mshreg_gcnt2_w_10 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_10 | -| ++++Mshreg_gcnt2_w_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_2 | -| ++++Mshreg_gcnt2_w_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_3 | -| ++++Mshreg_gcnt2_w_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_4 | -| ++++Mshreg_gcnt2_w_5 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_5 | -| ++++Mshreg_gcnt2_w_6 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_6 | -| ++++Mshreg_gcnt2_w_7 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_7 | -| ++++Mshreg_gcnt2_w_8 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_8 | -| ++++Mshreg_gcnt2_w_9 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_9 | -| ++++inst_gray_counter_r | | 20/20 | 23/23 | 24/24 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r | -| ++++inst_gray_counter_w | | 21/21 | 35/35 | 24/24 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w | -| ++inst_vga_backend | | 61/101 | 24/50 | 62/98 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_vga_backend | -| +++inst_vga_timing | | 0/40 | 0/26 | 0/36 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_vga_backend/inst_vga_timing | -| ++++inst_vga_sync_h | | 21/21 | 13/13 | 18/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h | -| ++++inst_vga_sync_v | | 19/19 | 13/13 | 18/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_v | -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - -* Slices can be packed with basic elements from multiple hierarchies. - Therefore, a slice will be counted in every hierarchical module - that each of its packed basic elements belong to. -** For each column, there are two numbers reported /. - is the number of elements that belong to that specific hierarchical module. - is the total number of elements from that hierarchical module and any lower level - hierarchical modules below. -*** The LUTRAM column counts all LUTs used as memory including RAM, ROM, and shift registers. diff --git a/projects/mips_sys/ise101/mips_sys/ucf/systest.ssram.ucf b/projects/mips_sys/ise101/mips_sys/ucf/mips_sys.ssram.ucf similarity index 100% rename from projects/mips_sys/ise101/mips_sys/ucf/systest.ssram.ucf rename to projects/mips_sys/ise101/mips_sys/ucf/mips_sys.ssram.ucf diff --git a/projects/mips_sys/ise101/mips_sys/ucf/systest.ucf b/projects/mips_sys/ise101/mips_sys/ucf/mips_sys.ucf similarity index 100% rename from projects/mips_sys/ise101/mips_sys/ucf/systest.ucf rename to projects/mips_sys/ise101/mips_sys/ucf/mips_sys.ucf