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git-svn-id: http://moon:8086/svn/vhdl/trunk@1430 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2021-03-21 12:20:54 +00:00
parent 2f7ab91e0d
commit 74e4af5fdf
12 changed files with 197 additions and 0 deletions
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projects/mips_top/constraints/mips_top.xcf
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BEGIN MODEL biu
INST inst_bin_fifo ram_style = distributed;
INST inst_bout_fifo ram_style = distributed;
INST inst_write_fifo ram_style = distributed;
END;
projects/mips_top/mips_netlist.ise
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projects/mips_top/mips_top.ise
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projects/mips_top/mips_top.lso
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work
projects/mips_top/mips_top.prj
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vhdl work "../../../../lib/misc/dpram_2w2r.vhd"
vhdl work "../../../../lib/misc/dpram_1w1r.vhd"
vhdl work "../../../../lib/FIFO/src/fifo_sync_ctrl.vhd"
vhdl work "../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_types.vhd"
vhdl work "../../../../lib/FIFO/src/fifo_sync.vhd"
vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_shifter.vhd"
vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_reg.vhd"
vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_muldiv.vhd"
vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_instr.vhd"
vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_icache.vhd"
vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_dcache.vhd"
vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_bcu.vhd"
vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_alu.vhd"
vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_pipeline.vhd"
vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_cop.vhd"
vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_biu.vhd"
vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_top.vhd"
projects/mips_top/mips_top.xst
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set -tmpdir "W:/vhdl/projects/mips_sys/ise101/mips_top/xst/projnav.tmp"
set -xsthdpdir "W:/vhdl/projects/mips_sys/ise101/mips_top/xst"
run
-ifn mips_top.prj
-ifmt mixed
-ofn mips_top
-ofmt NGC
-p xc4vsx35-10-ff668
-top mips_top
-opt_mode Speed
-opt_level 1
-power NO
-uc "W:/vhdl/projects/mips_sys/ise101/mips_top/constraints/mips_top.xcf"
-iuc NO
-lso mips_top.lso
-keep_hierarchy NO
-netlist_hierarchy as_optimized
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis YES
-hierarchy_separator /
-bus_delimiter <>
-case maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-dsp_utilization_ratio 100
-verilog2001 YES
-fsm_extract YES -fsm_encoding Speed1
-safe_implementation No
-fsm_style lut
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-mux_style Auto
-decoder_extract YES
-priority_extract YES
-shreg_extract YES
-shift_extract YES
-xor_collapse YES
-rom_style Auto
-auto_bram_packing NO
-mux_extract YES
-resource_sharing YES
-async_to_sync NO
-use_dsp48 auto
-iobuf NO
-max_fanout 500
-bufg 32
-bufr 24
-register_duplication YES
-register_balancing No
-slice_packing YES
-optimize_primitives NO
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5
projects/mips_top/mips_top_vhdl.prj
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vhdl work "W:\vhdl\lib\misc\dpram_2w2r.vhd"
vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync_ctrl.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_shifter.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_reg.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_muldiv.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_instr.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_icache.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_dcache.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bcu.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_alu.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_pipeline.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_cop.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_biu.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_top.vhd"
projects/sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb.ise
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projects/sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb.lso
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work
projects/sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb.prj
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vhdl work "../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
vhdl work "../../src/sdram_config.vhd"
vhdl work "../../../../lib/FIFO/src/gray_counter.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd"
vhdl work "../../../../lib/misc/utils_pkg.vhd"
vhdl work "../../../../lib/FIFO/src/fifo_async_ctrl.vhd"
vhdl work "../../../../lib/FIFO/src/dpram_1w1r.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
vhdl work "../../../../lib/FIFO/src/fifo_sync_ctrl.vhd"
vhdl work "../../../../lib/FIFO/src/fifo_async.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
vhdl work "../../../../lib/FIFO/src/fifo_sync.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd"
projects/sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb.xst
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set -tmpdir "W:/vhdl/projects/mips_sys/ise101/sdram_ctrl_frontend64_wb/xst/projnav.tmp"
set -xsthdpdir "W:/vhdl/projects/mips_sys/ise101/sdram_ctrl_frontend64_wb/xst"
run
-ifn sdram_ctrl_frontend64_wb.prj
-ifmt mixed
-ofn sdram_ctrl_frontend64_wb
-ofmt NGC
-p xc4vsx35-10-ff668
-top sdram_ctrl_frontend64_wb
-opt_mode Speed
-opt_level 1
-power NO
-iuc NO
-lso sdram_ctrl_frontend64_wb.lso
-keep_hierarchy NO
-netlist_hierarchy as_optimized
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis YES
-hierarchy_separator /
-bus_delimiter <>
-case maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-dsp_utilization_ratio 100
-verilog2001 YES
-fsm_extract YES -fsm_encoding Speed1
-safe_implementation No
-fsm_style lut
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-mux_style Auto
-decoder_extract YES
-priority_extract YES
-shreg_extract YES
-shift_extract YES
-xor_collapse YES
-rom_style Auto
-auto_bram_packing NO
-mux_extract YES
-resource_sharing YES
-async_to_sync NO
-use_dsp48 auto
-iobuf NO
-max_fanout 500
-bufg 32
-bufr 24
-register_duplication YES
-register_balancing No
-slice_packing YES
-optimize_primitives NO
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5
projects/sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb_vhdl.prj
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vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
vhdl work "W:\vhdl\projects\mips_sys\src\sdram_config.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\gray_counter.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_types.vhd"
vhdl work "W:\vhdl\lib\misc\utils_pkg.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\fifo_async_ctrl.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\dpram_1w1r.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_cmd.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\reset_virtex4.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\ddr_phy_virtex4.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync_ctrl.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\fifo_async.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_top.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_frontend64_wb.vhd"