diff --git a/projects/mips_top/constraints/mips_top.xcf b/projects/mips_top/constraints/mips_top.xcf
new file mode 100644
index 0000000..a11b28c
--- /dev/null
+++ b/projects/mips_top/constraints/mips_top.xcf
@@ -0,0 +1,6 @@
+BEGIN MODEL biu
+	INST inst_bin_fifo ram_style = distributed;
+	INST inst_bout_fifo ram_style = distributed;
+	INST inst_write_fifo ram_style = distributed;
+END;
+
diff --git a/projects/mips_top/mips_netlist.ise b/projects/mips_top/mips_netlist.ise
new file mode 100644
index 0000000..0291f74
Binary files /dev/null and b/projects/mips_top/mips_netlist.ise differ
diff --git a/projects/mips_top/mips_top.ise b/projects/mips_top/mips_top.ise
new file mode 100644
index 0000000..f56bc07
Binary files /dev/null and b/projects/mips_top/mips_top.ise differ
diff --git a/projects/mips_top/mips_top.lso b/projects/mips_top/mips_top.lso
new file mode 100644
index 0000000..22de730
--- /dev/null
+++ b/projects/mips_top/mips_top.lso
@@ -0,0 +1 @@
+work
diff --git a/projects/mips_top/mips_top.prj b/projects/mips_top/mips_top.prj
new file mode 100644
index 0000000..2774d8c
--- /dev/null
+++ b/projects/mips_top/mips_top.prj
@@ -0,0 +1,18 @@
+vhdl work "../../../../lib/misc/dpram_2w2r.vhd"
+vhdl work "../../../../lib/misc/dpram_1w1r.vhd"
+vhdl work "../../../../lib/FIFO/src/fifo_sync_ctrl.vhd"
+vhdl work "../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
+vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_types.vhd"
+vhdl work "../../../../lib/FIFO/src/fifo_sync.vhd"
+vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_shifter.vhd"
+vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_reg.vhd"
+vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_muldiv.vhd"
+vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_instr.vhd"
+vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_icache.vhd"
+vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_dcache.vhd"
+vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_bcu.vhd"
+vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_alu.vhd"
+vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_pipeline.vhd"
+vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_cop.vhd"
+vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_biu.vhd"
+vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_top.vhd"
diff --git a/projects/mips_top/mips_top.xst b/projects/mips_top/mips_top.xst
new file mode 100644
index 0000000..0f426f5
--- /dev/null
+++ b/projects/mips_top/mips_top.xst
@@ -0,0 +1,61 @@
+set -tmpdir "W:/vhdl/projects/mips_sys/ise101/mips_top/xst/projnav.tmp"
+set -xsthdpdir "W:/vhdl/projects/mips_sys/ise101/mips_top/xst"
+run
+-ifn mips_top.prj
+-ifmt mixed
+-ofn mips_top
+-ofmt NGC
+-p xc4vsx35-10-ff668
+-top mips_top
+-opt_mode Speed
+-opt_level 1
+-power NO
+-uc "W:/vhdl/projects/mips_sys/ise101/mips_top/constraints/mips_top.xcf"
+-iuc NO
+-lso mips_top.lso
+-keep_hierarchy NO
+-netlist_hierarchy as_optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis YES
+-hierarchy_separator /
+-bus_delimiter <>
+-case maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-dsp_utilization_ratio 100
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Speed1
+-safe_implementation No
+-fsm_style lut
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-mux_style Auto
+-decoder_extract YES
+-priority_extract YES
+-shreg_extract YES
+-shift_extract YES
+-xor_collapse YES
+-rom_style Auto
+-auto_bram_packing NO
+-mux_extract YES
+-resource_sharing YES
+-async_to_sync NO
+-use_dsp48 auto
+-iobuf NO
+-max_fanout 500
+-bufg 32
+-bufr 24
+-register_duplication YES
+-register_balancing No
+-slice_packing YES
+-optimize_primitives NO
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
diff --git a/projects/mips_top/mips_top_vhdl.prj b/projects/mips_top/mips_top_vhdl.prj
new file mode 100644
index 0000000..bd9579e
--- /dev/null
+++ b/projects/mips_top/mips_top_vhdl.prj
@@ -0,0 +1,18 @@
+vhdl work "W:\vhdl\lib\misc\dpram_2w2r.vhd"
+vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync_ctrl.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_shifter.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_reg.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_muldiv.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_instr.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_icache.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_dcache.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bcu.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_alu.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_pipeline.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_cop.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_biu.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_top.vhd"
diff --git a/projects/sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb.ise b/projects/sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb.ise
new file mode 100644
index 0000000..11cf5d2
Binary files /dev/null and b/projects/sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb.ise differ
diff --git a/projects/sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb.lso b/projects/sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb.lso
new file mode 100644
index 0000000..22de730
--- /dev/null
+++ b/projects/sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb.lso
@@ -0,0 +1 @@
+work
diff --git a/projects/sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb.prj b/projects/sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb.prj
new file mode 100644
index 0000000..990dfac
--- /dev/null
+++ b/projects/sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb.prj
@@ -0,0 +1,16 @@
+vhdl work "../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
+vhdl work "../../src/sdram_config.vhd"
+vhdl work "../../../../lib/FIFO/src/gray_counter.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd"
+vhdl work "../../../../lib/misc/utils_pkg.vhd"
+vhdl work "../../../../lib/FIFO/src/fifo_async_ctrl.vhd"
+vhdl work "../../../../lib/FIFO/src/dpram_1w1r.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
+vhdl work "../../../../lib/FIFO/src/fifo_sync_ctrl.vhd"
+vhdl work "../../../../lib/FIFO/src/fifo_async.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
+vhdl work "../../../../lib/FIFO/src/fifo_sync.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd"
diff --git a/projects/sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb.xst b/projects/sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb.xst
new file mode 100644
index 0000000..5e320b0
--- /dev/null
+++ b/projects/sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb.xst
@@ -0,0 +1,60 @@
+set -tmpdir "W:/vhdl/projects/mips_sys/ise101/sdram_ctrl_frontend64_wb/xst/projnav.tmp"
+set -xsthdpdir "W:/vhdl/projects/mips_sys/ise101/sdram_ctrl_frontend64_wb/xst"
+run
+-ifn sdram_ctrl_frontend64_wb.prj
+-ifmt mixed
+-ofn sdram_ctrl_frontend64_wb
+-ofmt NGC
+-p xc4vsx35-10-ff668
+-top sdram_ctrl_frontend64_wb
+-opt_mode Speed
+-opt_level 1
+-power NO
+-iuc NO
+-lso sdram_ctrl_frontend64_wb.lso
+-keep_hierarchy NO
+-netlist_hierarchy as_optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis YES
+-hierarchy_separator /
+-bus_delimiter <>
+-case maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-dsp_utilization_ratio 100
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Speed1
+-safe_implementation No
+-fsm_style lut
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-mux_style Auto
+-decoder_extract YES
+-priority_extract YES
+-shreg_extract YES
+-shift_extract YES
+-xor_collapse YES
+-rom_style Auto
+-auto_bram_packing NO
+-mux_extract YES
+-resource_sharing YES
+-async_to_sync NO
+-use_dsp48 auto
+-iobuf NO
+-max_fanout 500
+-bufg 32
+-bufr 24
+-register_duplication YES
+-register_balancing No
+-slice_packing YES
+-optimize_primitives NO
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
diff --git a/projects/sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb_vhdl.prj b/projects/sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb_vhdl.prj
new file mode 100644
index 0000000..ab6ecf7
--- /dev/null
+++ b/projects/sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb_vhdl.prj
@@ -0,0 +1,16 @@
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
+vhdl work "W:\vhdl\projects\mips_sys\src\sdram_config.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\gray_counter.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_types.vhd"
+vhdl work "W:\vhdl\lib\misc\utils_pkg.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_async_ctrl.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\dpram_1w1r.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_cmd.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\reset_virtex4.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\ddr_phy_virtex4.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync_ctrl.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_async.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_top.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_frontend64_wb.vhd"