- added
git-svn-id: http://moon:8086/svn/vhdl/trunk@1429 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -0,0 +1 @@
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work vconfig.vhdl
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@@ -0,0 +1,5 @@
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do vconfig_tb.fdo
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delete wave *
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do wave.do
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restart -force
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run 6000ns -all
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@@ -0,0 +1,10 @@
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# Auto generated by Project Navigator for Modelsim
|
||||
vlib work
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||||
|
||||
vcom -93 -explicit vconfig.vhdl
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||||
## You need to generate your own stimuli
|
||||
vsim -t 1ps vconfig
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||||
view wave
|
||||
add wave *
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||||
view structure
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||||
view signals
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||||
@@ -0,0 +1 @@
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work
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@@ -0,0 +1 @@
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||||
vhdl work vconfig.vhdl
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,183 @@
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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||||
-- Uncomment the following lines to use the declarations that are
|
||||
-- provided for instantiating Xilinx primitive components.
|
||||
--library UNISIM;
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||||
--use UNISIM.VComponents.all;
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||||
|
||||
entity vconfig is
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||||
Port ( RES : in std_logic;
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nINIT_B : in std_logic;
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||||
CLK : in std_logic;
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DONE : in std_logic;
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CCLK : out std_logic;
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CCLK_PRESCALER : in std_logic_vector(5 downto 0);
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||||
LOAD_PRESCALER : in std_logic;
|
||||
DIN : in std_logic_vector(31 downto 0);
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DOUT : out std_logic;
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||||
LOAD_SREG : in std_logic;
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||||
BUF_IS_EMPTY : inout std_logic);
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||||
end vconfig;
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||||
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||||
architecture Behavioral of vconfig is
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constant nbits : integer := 32;
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constant nBufs : integer := 2;
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type t_config_state is (CFG_STOP, CFG_INIT, CFG_RUN);
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type t_buf is array (0 to nBufs-1) of std_logic_vector (nBits-1 downto 0);
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||||
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signal REG: t_buf;
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signal count, CLK_SCALE: integer range 0 to 63;
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signal SHIFT_CNT: integer range 0 to nbits-1;
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signal state, next_state : t_config_state;
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||||
signal SCLK, SHIFT_EN : STD_LOGIC;
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signal buf_depth: integer range 0 to 2;
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signal tempID, readBufId, writeBufId : integer range 0 to nBufs-1;
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||||
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||||
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begin
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||||
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-- 4-bit loadable serial-in and serial-out shift register
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-- CLK: in STD_LOGIC;
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-- DIN: in STD_LOGIC;
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-- LOAD: in STD_LOGIC;
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-- LOAD_DATA: in STD_LOGIC_VECTOR(3 downto 0);
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-- DOUT: out STD_LOGIC;
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||||
process (RES, SCLK, state, nINIT_B, DONE, REG, BUF_IS_EMPTY)
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begin
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if (RES = '1') then
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CCLK <= '1';
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SHIFT_EN <= '0';
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||||
DOUT <= 'Z';
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else
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case state is
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when CFG_STOP =>
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||||
SHIFT_EN <= '0';
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||||
CCLK <= '1';
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||||
if (DONE = '0' and BUF_IS_EMPTY = '0') then
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next_state <= CFG_INIT;
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||||
else
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||||
next_state <= CFG_STOP;
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||||
end if;
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||||
|
||||
when CFG_INIT =>
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||||
CCLK <= SCLK;
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next_state <= CFG_RUN;
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||||
|
||||
when CFG_RUN =>
|
||||
SHIFT_EN <= '1';
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||||
CCLK <= SCLK;
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||||
if (DONE = '1' or nINIT_B = '0' or BUF_IS_EMPTY = '1') then
|
||||
next_state <= CFG_STOP;
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||||
else
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||||
next_state <= CFG_RUN;
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end if;
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||||
end case;
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||||
if (nINIT_B = '1') then
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||||
DOUT <= STD_LOGIC(REG(readBufId)(nbits-1));
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||||
else
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||||
DOUT <= 'Z';
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||||
end if;
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||||
end if;
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||||
|
||||
end process;
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||||
|
||||
sreg:
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||||
process(RES, SCLK, REG, DIN, LOAD_SREG, SHIFT_EN, SHIFT_CNT)
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||||
begin
|
||||
if (RES = '1') then
|
||||
BUF_IS_EMPTY <= '1';
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||||
SHIFT_CNT <= 0;
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||||
writeBufId <= 0;
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||||
readBufId <= 0;
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||||
buf_depth <= 0;
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||||
|
||||
elsif (LOAD_SREG = '1') then
|
||||
REG(writeBufId) <= DIN;
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||||
|
||||
if (SHIFT_EN = '0') then
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||||
SHIFT_CNT <= nbits-1;
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||||
end if;
|
||||
|
||||
if (buf_depth = nbufs) then
|
||||
buf_depth <= buf_depth ;
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||||
else
|
||||
buf_depth <= buf_depth + 1;
|
||||
end if;
|
||||
|
||||
else
|
||||
if SCLK='0' and SCLK'event then
|
||||
if SHIFT_EN = '1' then
|
||||
REG(readBufId)(nbits-1 downto 0) <= REG(readBufId)(nbits-2 downto 0) & '0';
|
||||
if (SHIFT_CNT = 0) then
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||||
if (buf_depth = 0) then
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writeBufId <= 0;
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readBufId <= 0;
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||||
else
|
||||
SHIFT_CNT <= nbits-1;
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tempID <= readBufID;
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||||
readBufID <= writeBufId;
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||||
writeBufId <= tempID;
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||||
buf_depth <= buf_depth - 1;
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||||
end if;
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||||
else
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||||
SHIFT_CNT <= SHIFT_CNT - 1;
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||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
if (SHIFT_CNT = 0 and buf_depth = 1) then
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||||
BUF_IS_EMPTY <= '1';
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||||
else
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||||
BUF_IS_EMPTY <= '0';
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||||
end if;
|
||||
end process;
|
||||
|
||||
-- 4-bit synchronous counter with count enable,
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||||
-- asynchronous reset
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||||
-- CLK: in STD_LOGIC;
|
||||
-- RESET: in STD_LOGIC;
|
||||
-- CE, LOAD, DIR: in STD_LOGIC;
|
||||
-- DIN: in STD_LOGIC_VECTOR(3 downto 0);
|
||||
-- COUNT: inout STD_LOGIC_VECTOR(3 downto 0);
|
||||
cfg_state_gen:
|
||||
process(RES, SCLK, next_state)
|
||||
begin
|
||||
if (RES = '1') then
|
||||
state <= CFG_STOP;
|
||||
elsif SCLK='1' and SCLK'event then
|
||||
state <= next_state;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
clk_prescaler:
|
||||
process (RES, CLK, CCLK_PRESCALER, LOAD_PRESCALER)
|
||||
begin
|
||||
if (RES = '1') then
|
||||
SCLK <= '1';
|
||||
CLK_SCALE <= 1;
|
||||
COUNT <= CLK_SCALE;
|
||||
|
||||
elsif (LOAD_PRESCALER = '1') then
|
||||
CLK_SCALE <= CONV_INTEGER(CCLK_PRESCALER);
|
||||
|
||||
elsif CLK='1' and CLK'event then
|
||||
if (COUNT = 1) then
|
||||
SCLK <= not SCLK;
|
||||
|
||||
COUNT <= CLK_SCALE;
|
||||
else
|
||||
COUNT <= COUNT - 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
@@ -0,0 +1,54 @@
|
||||
|
||||
#PINLOCK_BEGIN
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||||
|
||||
#Sun May 02 01:57:09 2004
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||||
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||||
NET "CLK" LOC = "S:PIN30";
|
||||
NET "DIN<0>" LOC = "S:PIN94";
|
||||
NET "DIN<10>" LOC = "S:PIN132";
|
||||
NET "DIN<11>" LOC = "S:PIN12";
|
||||
NET "DIN<12>" LOC = "S:PIN124";
|
||||
NET "DIN<13>" LOC = "S:PIN85";
|
||||
NET "DIN<14>" LOC = "S:PIN118";
|
||||
NET "DIN<15>" LOC = "S:PIN82";
|
||||
NET "DIN<16>" LOC = "S:PIN139";
|
||||
NET "DIN<17>" LOC = "S:PIN40";
|
||||
NET "DIN<18>" LOC = "S:PIN6";
|
||||
NET "DIN<19>" LOC = "S:PIN115";
|
||||
NET "DIN<1>" LOC = "S:PIN35";
|
||||
NET "DIN<20>" LOC = "S:PIN134";
|
||||
NET "DIN<21>" LOC = "S:PIN76";
|
||||
NET "DIN<22>" LOC = "S:PIN136";
|
||||
NET "DIN<23>" LOC = "S:PIN13";
|
||||
NET "DIN<24>" LOC = "S:PIN103";
|
||||
NET "DIN<25>" LOC = "S:PIN112";
|
||||
NET "DIN<26>" LOC = "S:PIN59";
|
||||
NET "DIN<27>" LOC = "S:PIN88";
|
||||
NET "DIN<28>" LOC = "S:PIN101";
|
||||
NET "DIN<29>" LOC = "S:PIN25";
|
||||
NET "DIN<2>" LOC = "S:PIN93";
|
||||
NET "DIN<30>" LOC = "S:PIN38";
|
||||
NET "DIN<31>" LOC = "S:PIN91";
|
||||
NET "DIN<3>" LOC = "S:PIN21";
|
||||
NET "DIN<4>" LOC = "S:PIN143";
|
||||
NET "DIN<5>" LOC = "S:PIN28";
|
||||
NET "DIN<6>" LOC = "S:PIN24";
|
||||
NET "DIN<7>" LOC = "S:PIN44";
|
||||
NET "DIN<8>" LOC = "S:PIN104";
|
||||
NET "DIN<9>" LOC = "S:PIN140";
|
||||
NET "DONE" LOC = "S:PIN48";
|
||||
NET "LOAD_PRESCALER" LOC = "S:PIN74";
|
||||
NET "LOAD_SREG" LOC = "S:PIN64";
|
||||
NET "RES" LOC = "S:PIN98";
|
||||
NET "VCLK_PRESCALER<0>" LOC = "S:PIN11";
|
||||
NET "VCLK_PRESCALER<1>" LOC = "S:PIN97";
|
||||
NET "VCLK_PRESCALER<2>" LOC = "S:PIN133";
|
||||
NET "VCLK_PRESCALER<3>" LOC = "S:PIN7";
|
||||
NET "VCLK_PRESCALER<4>" LOC = "S:PIN138";
|
||||
NET "VCLK_PRESCALER<5>" LOC = "S:PIN142";
|
||||
NET "nINIT_B" LOC = "S:PIN10";
|
||||
NET "DOUT" LOC = "S:PIN79";
|
||||
NET "SCLK" LOC = "S:PIN9";
|
||||
NET "VCLK" LOC = "S:PIN50";
|
||||
NET "dummy_out" LOC = "S:PIN117";
|
||||
#PINLOCK_END
|
||||
@@ -0,0 +1,13 @@
|
||||
## NOTE: Do not edit this file.
|
||||
## Autogenerated by ProjNav (creatfdo.tcl) on Wed May 05 21:50:05 Westeuropäische Sommerzeit 2004
|
||||
##
|
||||
vlib work
|
||||
vcom -93 -explicit vconfig.vhdl
|
||||
vcom -93 -explicit vconfig_tb.vhd
|
||||
vsim -t 1ps -lib work vconfig_tb
|
||||
do vconfig_tb.udo
|
||||
view wave
|
||||
add wave *
|
||||
view structure
|
||||
view signals
|
||||
run 6000ns
|
||||
@@ -0,0 +1,15 @@
|
||||
## NOTE: Do not edit this file.
|
||||
## Auto generated by Project Navigator for VHDL Post-PAR Simulation
|
||||
##
|
||||
vlib work
|
||||
## Compile Post-PAR Model for Module vconfig
|
||||
vcom -87 -explicit vconfig_timesim.vhd
|
||||
vcom -93 -explicit vconfig_tb.vhd
|
||||
vsim -t 1ps -sdfmax /UUT=vconfig_timesim.sdf -lib work vconfig_tb
|
||||
do vconfig_tb.udo
|
||||
view wave
|
||||
add wave *
|
||||
view structure
|
||||
view signals
|
||||
run 6000ns
|
||||
## End
|
||||
@@ -0,0 +1,4 @@
|
||||
-- ProjNav VHDL simulation template: vconfig_tb.udo
|
||||
-- You may edit this file after the line that starts with
|
||||
-- '-- START' to customize your simulation
|
||||
-- START user-defined simulation commands
|
||||
@@ -0,0 +1,129 @@
|
||||
|
||||
-- VHDL Test Bench Created from source file vconfig.vhd -- 20:20:01 05/01/2004
|
||||
--
|
||||
-- Notes:
|
||||
-- This testbench has been automatically generated using types std_logic and
|
||||
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
|
||||
-- that these types always be used for the top-level I/O of a design in order
|
||||
-- to guarantee that the testbench will bind correctly to the post-implementation
|
||||
-- simulation model.
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.numeric_std.ALL;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
ENTITY vconfig_tb IS
|
||||
END vconfig_tb;
|
||||
|
||||
ARCHITECTURE behavior OF vconfig_tb IS
|
||||
|
||||
COMPONENT vconfig
|
||||
PORT(
|
||||
RES : IN std_logic;
|
||||
nINIT_B : IN std_logic;
|
||||
CLK : IN std_logic;
|
||||
DONE : IN std_logic;
|
||||
CCLK : OUT std_logic;
|
||||
CCLK_PRESCALER : IN std_logic_vector(5 downto 0);
|
||||
LOAD_PRESCALER : in std_logic;
|
||||
DIN : IN std_logic_vector(31 downto 0);
|
||||
DOUT : OUT std_logic;
|
||||
BUF_IS_EMPTY : inout std_logic;
|
||||
LOAD_SREG : IN std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
SIGNAL RES : std_logic := '1';
|
||||
SIGNAL nINIT_B : std_logic := '0';
|
||||
SIGNAL CLK : std_logic := '0';
|
||||
SIGNAL DONE : std_logic := '1';
|
||||
SIGNAL CCLK : std_logic;
|
||||
SIGNAL CCLK_PRESCALER : std_logic_vector(5 downto 0);
|
||||
SIGNAL LOAD_PRESCALER : std_logic := '0';
|
||||
SIGNAL DOUT : std_logic;
|
||||
SIGNAL DIN : std_logic_vector(31 downto 0);
|
||||
SIGNAL LOAD_SREG : std_logic := '0';
|
||||
SIGNAL BUF_IS_EMPTY : std_logic;
|
||||
|
||||
constant ClockPeriod : Time := 16.667 ns;
|
||||
constant CFG_PRESCALE: integer range 0 to 63 := 2;
|
||||
|
||||
BEGIN
|
||||
|
||||
uut: vconfig PORT MAP(
|
||||
RES => RES,
|
||||
nINIT_B => nINIT_B,
|
||||
CLK => CLK,
|
||||
DONE => DONE,
|
||||
CCLK => CCLK,
|
||||
CCLK_PRESCALER => CCLK_PRESCALER,
|
||||
LOAD_PRESCALER => LOAD_PRESCALER,
|
||||
DOUT => DOUT,
|
||||
DIN => DIN,
|
||||
BUF_IS_EMPTY => BUF_IS_EMPTY,
|
||||
LOAD_SREG => LOAD_SREG
|
||||
);
|
||||
|
||||
busclock: process
|
||||
begin
|
||||
CLK <= '1';
|
||||
loop
|
||||
wait for (ClockPeriod / 2);
|
||||
CLK <= not CLK;
|
||||
end loop;
|
||||
end process;
|
||||
|
||||
-- *** Test Bench - User Defined Section ***
|
||||
tb : PROCESS
|
||||
BEGIN
|
||||
|
||||
wait for 5*ClockPeriod;
|
||||
RES <= '0';
|
||||
|
||||
wait for 5*ClockPeriod;
|
||||
CCLK_PRESCALER <= CONV_STD_LOGIC_VECTOR(CFG_PRESCALE,6);
|
||||
|
||||
wait for 1.5*ClockPeriod;
|
||||
LOAD_PRESCALER <= '1';
|
||||
|
||||
wait for 1*ClockPeriod;
|
||||
LOAD_PRESCALER <= '0';
|
||||
|
||||
wait for 1*ClockPeriod;
|
||||
DIN <= X"BAA34569";
|
||||
|
||||
wait for 1.5*ClockPeriod;
|
||||
LOAD_SREG <= '1';
|
||||
|
||||
wait for 1.0*ClockPeriod;
|
||||
LOAD_SREG <= '0';
|
||||
|
||||
wait for 5*ClockPeriod;
|
||||
DONE <= '0';
|
||||
|
||||
wait for 2*ClockPeriod;
|
||||
nINIT_B <= '1';
|
||||
|
||||
wait for 30.0*real(CFG_PRESCALE)*ClockPeriod*2;
|
||||
|
||||
DIN <= X"8654F41B";
|
||||
|
||||
wait for 1.5*ClockPeriod;
|
||||
LOAD_SREG <= '1';
|
||||
|
||||
wait for 2.0*ClockPeriod;
|
||||
LOAD_SREG <= '0';
|
||||
|
||||
wait for 29.0*real(CFG_PRESCALE)*ClockPeriod*2;
|
||||
DONE <= '1';
|
||||
|
||||
wait for 10.0*ClockPeriod;
|
||||
nINIT_B <= '0';
|
||||
|
||||
wait; -- will wait forever
|
||||
END PROCESS;
|
||||
-- *** End Test Bench - User Defined Section ***
|
||||
|
||||
END;
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,40 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -format Logic /vconfig_tb/uut/res
|
||||
add wave -noupdate -format Logic /vconfig_tb/uut/ninit_b
|
||||
add wave -noupdate -format Logic /vconfig_tb/uut/clk
|
||||
add wave -noupdate -format Logic /vconfig_tb/uut/done
|
||||
add wave -noupdate -format Logic /vconfig_tb/uut/cclk
|
||||
add wave -noupdate -format Literal /vconfig_tb/uut/cclk_prescaler
|
||||
add wave -noupdate -format Logic /vconfig_tb/uut/load_prescaler
|
||||
add wave -noupdate -format Literal /vconfig_tb/uut/din
|
||||
add wave -noupdate -format Logic /vconfig_tb/uut/dout
|
||||
add wave -noupdate -format Logic /vconfig_tb/uut/load_sreg
|
||||
add wave -noupdate -format Logic /vconfig_tb/uut/buf_is_empty
|
||||
add wave -noupdate -format Literal /vconfig_tb/uut/reg
|
||||
add wave -noupdate -format Literal /vconfig_tb/uut/count
|
||||
add wave -noupdate -format Literal /vconfig_tb/uut/clk_scale
|
||||
add wave -noupdate -format Literal /vconfig_tb/uut/shift_cnt
|
||||
add wave -noupdate -format Literal /vconfig_tb/uut/state
|
||||
add wave -noupdate -format Literal /vconfig_tb/uut/next_state
|
||||
add wave -noupdate -format Logic /vconfig_tb/uut/sclk
|
||||
add wave -noupdate -format Logic /vconfig_tb/uut/shift_en
|
||||
add wave -noupdate -format Literal /vconfig_tb/uut/buf_depth
|
||||
add wave -noupdate -format Literal /vconfig_tb/uut/tempid
|
||||
add wave -noupdate -format Literal /vconfig_tb/uut/readbufid
|
||||
add wave -noupdate -format Literal /vconfig_tb/uut/writebufid
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {2809539 ps} 0}
|
||||
WaveRestoreZoom {1356698 ps} {12202906 ps}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
Binary file not shown.
@@ -0,0 +1 @@
|
||||
work
|
||||
@@ -0,0 +1 @@
|
||||
vhdl work "main_top.vhdl"
|
||||
@@ -0,0 +1,86 @@
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Uncomment the following lines to use the declarations that are
|
||||
-- provided for instantiating Xilinx primitive components.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity main_top is
|
||||
Port ( clk : in std_logic;
|
||||
resn : in std_logic;
|
||||
a : in std_logic_vector(31 downto 0);
|
||||
d : inout std_logic_vector(31 downto 0);
|
||||
wen : in std_logic;
|
||||
csn : in std_logic);
|
||||
end main_top;
|
||||
|
||||
architecture Behavioral of main_top is
|
||||
|
||||
type t_reg is array (31 downto 0) of std_logic ;
|
||||
signal reg_a, reg_b, reg_c : t_reg;
|
||||
signal cs_a, cs_b, cs_c, CI, CO : std_logic;
|
||||
signal dmuxo : std_logic_vector(31 downto 0);
|
||||
signal mux_ctrl : std_logic_vector (3 downto 0);
|
||||
signal AA,BB,S31: std_logic_vector(32-1 downto 0);
|
||||
signal sum : std_logic_vector(32 downto 0);
|
||||
signal zeros: std_logic_vector(32-1 downto 0) := (others => '0');
|
||||
|
||||
begin
|
||||
|
||||
mux_ctrl <= a(7 downto 4);
|
||||
|
||||
dmuxo <= std_logic_vector(reg_a) when (mux_ctrl = X"0") else
|
||||
std_logic_vector(reg_b) when (mux_ctrl = X"1") else
|
||||
std_logic_vector(reg_c) when (mux_ctrl = X"2") else
|
||||
X"12345678";
|
||||
|
||||
cs_a <= '1' when (mux_ctrl = X"0" and csn = '0') else '0';
|
||||
cs_b <= '1' when (mux_ctrl = X"1" and csn = '0') else '0';
|
||||
cs_c <= '1' when (mux_ctrl = X"2" and csn = '0') else '0';
|
||||
|
||||
CI <= wen;
|
||||
AA <= dmuxo when (wen = '1' and csn = '0') else (31 downto 0 => 'Z');
|
||||
BB <=a;
|
||||
d <= S31;
|
||||
|
||||
write_reg_a: process (clk, wen, cs_a, d)
|
||||
begin
|
||||
|
||||
if clk'event and clk = '0' then
|
||||
if (wen = '0' and cs_a = '1') then
|
||||
reg_a <= t_reg(d);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
write_reg_b: process (clk, wen, cs_b, d)
|
||||
begin
|
||||
|
||||
if clk'event and clk = '0' then
|
||||
if (wen = '0' and cs_b = '1') then
|
||||
reg_b <= t_reg(d);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
write_reg_c: process (clk, wen, cs_c, d)
|
||||
begin
|
||||
|
||||
if clk'event and clk = '0' then
|
||||
if (wen = '0' and cs_c = '1') then
|
||||
reg_c <= t_reg(d);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (CI, AA, BB, sum)
|
||||
begin
|
||||
sum <= ('0' & AA) + ('0' & BB) + (zeros & CI);
|
||||
S31 <= sum(32-1 downto 0);
|
||||
CO <= sum(32);
|
||||
|
||||
end process;
|
||||
end Behavioral;
|
||||
@@ -0,0 +1,53 @@
|
||||
set -tmpdir ./xst/projnav.tmp
|
||||
set -xsthdpdir ./xst
|
||||
run
|
||||
-ifn main_top.prj
|
||||
-ifmt mixed
|
||||
-ofn main_top
|
||||
-ofmt NGC
|
||||
-p xc3s50-5-tq144
|
||||
-top main_top
|
||||
-opt_mode Speed
|
||||
-opt_level 1
|
||||
-iuc NO
|
||||
-lso main_top.lso
|
||||
-keep_hierarchy NO
|
||||
-rtlview Yes
|
||||
-glob_opt AllClockNets
|
||||
-read_cores YES
|
||||
-write_timing_constraints NO
|
||||
-cross_clock_analysis NO
|
||||
-hierarchy_separator _
|
||||
-bus_delimiter <>
|
||||
-case maintain
|
||||
-slice_utilization_ratio 100
|
||||
-verilog2001 YES
|
||||
-fsm_extract YES -fsm_encoding Auto
|
||||
-safe_implementation No
|
||||
-fsm_style lut
|
||||
-ram_extract Yes
|
||||
-ram_style Auto
|
||||
-rom_extract Yes
|
||||
-mux_style Auto
|
||||
-decoder_extract YES
|
||||
-priority_extract YES
|
||||
-shreg_extract YES
|
||||
-shift_extract YES
|
||||
-xor_collapse YES
|
||||
-rom_style Auto
|
||||
-mux_extract YES
|
||||
-resource_sharing YES
|
||||
-mult_style auto
|
||||
-iobuf YES
|
||||
-max_fanout 500
|
||||
-bufg 8
|
||||
-register_duplication YES
|
||||
-register_balancing No
|
||||
-slice_packing YES
|
||||
-optimize_primitives NO
|
||||
-use_clock_enable Yes
|
||||
-use_sync_set Yes
|
||||
-use_sync_reset Yes
|
||||
-iob auto
|
||||
-equivalent_register_removal YES
|
||||
-slice_utilization_ratio_maxmargin 5
|
||||
@@ -0,0 +1,13 @@
|
||||
## NOTE: Do not edit this file.
|
||||
## Autogenerated by ProjNav (creatfdo.tcl) on Wed Jun 02 00:28:35 Westeuropäische Sommerzeit 2004
|
||||
##
|
||||
vlib work
|
||||
vcom -93 -explicit main_top.vhdl
|
||||
vcom -93 -explicit main_top_tb.vhd
|
||||
vsim -t 1ps -lib work main_top_main_top_tb_vhd_tb
|
||||
do main_top_main_top_tb_vhd_tb.udo
|
||||
view wave
|
||||
add wave *
|
||||
view structure
|
||||
view signals
|
||||
run 1000ns
|
||||
@@ -0,0 +1,15 @@
|
||||
## NOTE: Do not edit this file.
|
||||
## Auto generated by Project Navigator for VHDL Post-Translate Simulation
|
||||
##
|
||||
vlib work
|
||||
## Compile Post-Translate Model for Module main_top
|
||||
vcom -87 -explicit main_top_translate.vhd
|
||||
vcom -93 -explicit main_top_tb.vhd
|
||||
vsim -t 1ps -lib work main_top_main_top_tb_vhd_tb
|
||||
do main_top_main_top_tb_vhd_tb.udo
|
||||
view wave
|
||||
add wave *
|
||||
view structure
|
||||
view signals
|
||||
run 1000ns
|
||||
## End
|
||||
@@ -0,0 +1,15 @@
|
||||
## NOTE: Do not edit this file.
|
||||
## Auto generated by Project Navigator for VHDL Post-PAR Simulation
|
||||
##
|
||||
vlib work
|
||||
## Compile Post-PAR Model for Module main_top
|
||||
vcom -87 -explicit main_top_timesim.vhd
|
||||
vcom -93 -explicit main_top_tb.vhd
|
||||
vsim -t 1ps -sdfmax /UUT=main_top_timesim.sdf -lib work main_top_main_top_tb_vhd_tb
|
||||
do main_top_main_top_tb_vhd_tb.udo
|
||||
view wave
|
||||
add wave *
|
||||
view structure
|
||||
view signals
|
||||
run 1000ns
|
||||
## End
|
||||
@@ -0,0 +1,4 @@
|
||||
-- ProjNav VHDL simulation template: main_top_main_top_tb_vhd_tb.udo
|
||||
-- You may edit this file after the line that starts with
|
||||
-- '-- START' to customize your simulation
|
||||
-- START user-defined simulation commands
|
||||
@@ -0,0 +1,134 @@
|
||||
|
||||
-- VHDL Test Bench Created from source file main_top.vhd -- 00:26:28 06/02/2004
|
||||
--
|
||||
-- Notes:
|
||||
-- This testbench has been automatically generated using types std_logic and
|
||||
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
|
||||
-- that these types always be used for the top-level I/O of a design in order
|
||||
-- to guarantee that the testbench will bind correctly to the post-implementation
|
||||
-- simulation model.
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY main_top_main_top_tb_vhd_tb IS
|
||||
END main_top_main_top_tb_vhd_tb;
|
||||
|
||||
ARCHITECTURE behavior OF main_top_main_top_tb_vhd_tb IS
|
||||
|
||||
COMPONENT main_top
|
||||
PORT(
|
||||
clk : IN std_logic;
|
||||
resn : IN std_logic;
|
||||
a : IN std_logic_vector(31 downto 0);
|
||||
wen : IN std_logic;
|
||||
csn : IN std_logic;
|
||||
d : INOUT std_logic_vector(31 downto 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
SIGNAL clk : std_logic;
|
||||
SIGNAL resn : std_logic;
|
||||
SIGNAL a : std_logic_vector(31 downto 0);
|
||||
SIGNAL d : std_logic_vector(31 downto 0);
|
||||
SIGNAL wen : std_logic;
|
||||
SIGNAL csn : std_logic;
|
||||
|
||||
constant ClockPeriod : Time := 25 ns;
|
||||
|
||||
BEGIN
|
||||
|
||||
uut: main_top PORT MAP(
|
||||
clk => clk,
|
||||
resn => resn,
|
||||
a => a,
|
||||
d => d,
|
||||
wen => wen,
|
||||
csn => csn
|
||||
);
|
||||
|
||||
|
||||
clockgen: process
|
||||
begin
|
||||
clk <= '1';
|
||||
loop
|
||||
wait for (ClockPeriod / 2);
|
||||
clk <= not clk;
|
||||
end loop;
|
||||
end process;
|
||||
|
||||
-- *** Test Bench - User Defined Section ***
|
||||
tb : PROCESS
|
||||
BEGIN
|
||||
wait for 8*ClockPeriod;
|
||||
|
||||
resn <= '1';
|
||||
wait for 4*ClockPeriod;
|
||||
|
||||
wen <= '0';
|
||||
|
||||
a <= X"00000000";
|
||||
wait for 1*ClockPeriod;
|
||||
d <= X"AAAAAAAA";
|
||||
csn <= '0';
|
||||
wait for 1*ClockPeriod;
|
||||
csn <= '1';
|
||||
|
||||
a <= X"00000010";
|
||||
wait for 1*ClockPeriod;
|
||||
d <= X"BBBBBBBB";
|
||||
csn <= '0';
|
||||
wait for 1*ClockPeriod;
|
||||
csn <= '1';
|
||||
|
||||
a <= X"00000020";
|
||||
wait for 1*ClockPeriod;
|
||||
d <= X"CCCCCCCC";
|
||||
csn <= '0';
|
||||
wait for 1*ClockPeriod;
|
||||
csn <= '1';
|
||||
|
||||
a <= X"00000030";
|
||||
wait for 1*ClockPeriod;
|
||||
d <= X"DDDDDDDD";
|
||||
csn <= '0';
|
||||
wait for 1*ClockPeriod;
|
||||
csn <= '1';
|
||||
|
||||
wait for 8*ClockPeriod;
|
||||
wen <= '1';
|
||||
|
||||
a <= X"00000000";
|
||||
wait for 1*ClockPeriod;
|
||||
d <= (31 downto 0 => 'Z');
|
||||
csn <= '0';
|
||||
wait for 1*ClockPeriod;
|
||||
csn <= '1';
|
||||
|
||||
a <= X"00000010";
|
||||
wait for 1*ClockPeriod;
|
||||
d <= (31 downto 0 => 'Z');
|
||||
csn <= '0';
|
||||
wait for 1*ClockPeriod;
|
||||
csn <= '1';
|
||||
|
||||
a <= X"00000020";
|
||||
wait for 1*ClockPeriod;
|
||||
d <= (31 downto 0 => 'Z');
|
||||
csn <= '0';
|
||||
wait for 1*ClockPeriod;
|
||||
csn <= '1';
|
||||
|
||||
a <= X"00000030";
|
||||
wait for 1*ClockPeriod;
|
||||
d <= (31 downto 0 => 'Z');
|
||||
csn <= '0';
|
||||
wait for 1*ClockPeriod;
|
||||
csn <= '1';
|
||||
|
||||
wait; -- will wait forever
|
||||
END PROCESS;
|
||||
-- *** End Test Bench - User Defined Section ***
|
||||
|
||||
END;
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1 @@
|
||||
work main_top.vhdl
|
||||
@@ -0,0 +1,28 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -format Logic /main_top_main_top_tb_vhd_tb/clk
|
||||
add wave -noupdate -format Logic /main_top_main_top_tb_vhd_tb/resn
|
||||
add wave -noupdate -format Literal -radix hexadecimal /main_top_main_top_tb_vhd_tb/a
|
||||
add wave -noupdate -format Literal -radix hexadecimal /main_top_main_top_tb_vhd_tb/d
|
||||
add wave -noupdate -format Logic /main_top_main_top_tb_vhd_tb/wen
|
||||
add wave -noupdate -format Logic /main_top_main_top_tb_vhd_tb/csn
|
||||
add wave -noupdate -format Literal -radix hexadecimal /main_top_main_top_tb_vhd_tb/uut/reg_a
|
||||
add wave -noupdate -format Literal -radix hexadecimal /main_top_main_top_tb_vhd_tb/uut/reg_b
|
||||
add wave -noupdate -format Literal -radix hexadecimal /main_top_main_top_tb_vhd_tb/uut/reg_c
|
||||
add wave -noupdate -format Literal -radix hexadecimal /main_top_main_top_tb_vhd_tb/uut/dmuxo
|
||||
add wave -noupdate -format Literal -radix hexadecimal /main_top_main_top_tb_vhd_tb/uut/mux_ctrl
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {684150 ps} 0}
|
||||
WaveRestoreZoom {356007 ps} {1033895 ps}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
@@ -0,0 +1,50 @@
|
||||
# -------------------------------------------------
|
||||
# Global options
|
||||
# -------------------------------------------------
|
||||
LANG_STD := 93c
|
||||
IEEE_STD := standard
|
||||
WORK_PATH := work
|
||||
SOURCE_PATH := src
|
||||
LIB_PATH := ../lib
|
||||
|
||||
# -------------------------------------------------
|
||||
# Target options
|
||||
# -------------------------------------------------
|
||||
TARGET := tb_eval_fixed_ja
|
||||
SOURCES :=
|
||||
|
||||
# -------------------------------------------------
|
||||
GHDL_OPT := --workdir=$(WORK_PATH) --std=$(LANG_STD) --ieee=$(IEEE_STD)
|
||||
|
||||
# -------------------------------------------------
|
||||
all: elaborate
|
||||
|
||||
.PHONY: syntax
|
||||
syntax:
|
||||
ghdl -s $(GHDL_OPT) $(SOURCE_PATH)/*.vhd
|
||||
|
||||
import:
|
||||
ghdl -i $(GHDL_OPT) $(LIB_PATH)/*.vhd
|
||||
|
||||
analyze: import
|
||||
ghdl -a $(GHDL_OPT) $(LIB_PATH)/*.vhd $(SOURCE_PATH)/*.vhd
|
||||
|
||||
anaborate: import
|
||||
ghdl -c $(GHDL_OPT) $(LIB_PATH)/*.vhd $(SOURCE_PATH)/*.vhd -e $(TARGET)
|
||||
|
||||
makeunit: import
|
||||
ghdl -m $(GHDL_OPT) $(TARGET)
|
||||
|
||||
elaborate: analyze
|
||||
ghdl -e $(GHDL_OPT) $(TARGET)
|
||||
|
||||
run: elaborate
|
||||
ghdl -r $(GHDL_OPT) $(TARGET)
|
||||
|
||||
# -------------------------------------------------
|
||||
.PHONY: clean
|
||||
clean:
|
||||
rm -rf $(TARGET)
|
||||
cd $(WORK_PATH); rm -rf *.o *.cf
|
||||
|
||||
# -------------------------------------------------
|
||||
@@ -0,0 +1 @@
|
||||
work
|
||||
@@ -0,0 +1,2 @@
|
||||
vhdl work "W:/vhdl/lib/src/fixed_ja/fixed_ja.vhd"
|
||||
vhdl work "W:/vhdl/projects/eval_fixed_ja/src/eval_fixed_ja_syn.vhd"
|
||||
@@ -0,0 +1,55 @@
|
||||
set -tmpdir ./xst/projnav.tmp
|
||||
set -xsthdpdir ./xst
|
||||
run
|
||||
-ifn eval_fixed_ja.prj
|
||||
-ifmt mixed
|
||||
-ofn eval_fixed_ja
|
||||
-ofmt NGC
|
||||
-p xc4vsx35-10-ff668
|
||||
-top eval_fixed_ja
|
||||
-opt_mode Speed
|
||||
-opt_level 1
|
||||
-iuc NO
|
||||
-lso eval_fixed_ja.lso
|
||||
-keep_hierarchy NO
|
||||
-rtlview Yes
|
||||
-glob_opt AllClockNets
|
||||
-read_cores YES
|
||||
-write_timing_constraints NO
|
||||
-cross_clock_analysis NO
|
||||
-hierarchy_separator /
|
||||
-bus_delimiter <>
|
||||
-case maintain
|
||||
-slice_utilization_ratio 100
|
||||
-dsp_utilization_ratio 100
|
||||
-verilog2001 YES
|
||||
-fsm_extract YES -fsm_encoding Auto
|
||||
-safe_implementation No
|
||||
-fsm_style lut
|
||||
-ram_extract Yes
|
||||
-ram_style Auto
|
||||
-rom_extract Yes
|
||||
-mux_style Auto
|
||||
-decoder_extract YES
|
||||
-priority_extract YES
|
||||
-shreg_extract YES
|
||||
-shift_extract YES
|
||||
-xor_collapse YES
|
||||
-rom_style Auto
|
||||
-mux_extract YES
|
||||
-resource_sharing YES
|
||||
-use_dsp48 auto
|
||||
-iobuf YES
|
||||
-max_fanout 500
|
||||
-bufg 32
|
||||
-bufr 24
|
||||
-register_duplication YES
|
||||
-register_balancing No
|
||||
-slice_packing YES
|
||||
-optimize_primitives NO
|
||||
-use_clock_enable Auto
|
||||
-use_sync_set Auto
|
||||
-use_sync_reset Auto
|
||||
-iob auto
|
||||
-equivalent_register_removal YES
|
||||
-slice_utilization_ratio_maxmargin 5
|
||||
Binary file not shown.
@@ -0,0 +1,15 @@
|
||||
## NOTE: Do not edit this file.
|
||||
## Autogenerated by ProjNav (creatfdo.tcl) on Tue May 22 21:51:13 Westeuropäische Sommerzeit 2007
|
||||
##
|
||||
vlib work
|
||||
vcom -explicit -93 "W:/vhdl/lib/src/fixed_ja/fixed_ja.vhd"
|
||||
vcom -explicit -93 "W:/vhdl/lib/src/fixed_ja/fixed_ja_body.vhd"
|
||||
vcom -explicit -93 "W:/vhdl/projects/eval_fixed_ja/src/eval_fixed_ja_syn.vhd"
|
||||
vcom -explicit -93 "W:/vhdl/projects/eval_fixed_ja/src/tb_eval_fixed_ja_syn.vhd"
|
||||
vsim -t 1ps -lib work tb_eval_fixed_ja_vhd
|
||||
do {tb_eval_fixed_ja_vhd.udo}
|
||||
view wave
|
||||
add wave *
|
||||
view structure
|
||||
view signals
|
||||
run 1000ns
|
||||
@@ -0,0 +1,4 @@
|
||||
-- ProjNav VHDL simulation template: tb_eval_fixed_ja_vhd.udo
|
||||
-- You may edit this file after the line that starts with
|
||||
-- '-- START' to customize your simulation
|
||||
-- START user-defined simulation commands
|
||||
Binary file not shown.
@@ -0,0 +1 @@
|
||||
work
|
||||
@@ -0,0 +1,2 @@
|
||||
vhdl ieee_proposed "C:/Programme/Xilinx9/vhdl/src/ieee_proposed/fixed_pkg_c.vhd"
|
||||
vhdl work "../src/eval_fixed_ja_syn.vhd"
|
||||
@@ -0,0 +1,59 @@
|
||||
set -tmpdir "./xst/projnav.tmp"
|
||||
set -xsthdpdir "./xst"
|
||||
run
|
||||
-ifn eval_fixed_ja.prj
|
||||
-ifmt mixed
|
||||
-ofn eval_fixed_ja
|
||||
-ofmt NGC
|
||||
-p xc4vsx35-10-ff668
|
||||
-top eval_fixed_ja
|
||||
-opt_mode Speed
|
||||
-opt_level 1
|
||||
-power NO
|
||||
-iuc NO
|
||||
-lso eval_fixed_ja.lso
|
||||
-keep_hierarchy NO
|
||||
-rtlview Yes
|
||||
-glob_opt AllClockNets
|
||||
-read_cores YES
|
||||
-write_timing_constraints NO
|
||||
-cross_clock_analysis NO
|
||||
-hierarchy_separator /
|
||||
-bus_delimiter <>
|
||||
-case maintain
|
||||
-slice_utilization_ratio 100
|
||||
-bram_utilization_ratio 100
|
||||
-dsp_utilization_ratio 100
|
||||
-verilog2001 YES
|
||||
-fsm_extract YES -fsm_encoding Auto
|
||||
-safe_implementation No
|
||||
-fsm_style lut
|
||||
-ram_extract Yes
|
||||
-ram_style Auto
|
||||
-rom_extract Yes
|
||||
-mux_style Auto
|
||||
-decoder_extract YES
|
||||
-priority_extract YES
|
||||
-shreg_extract YES
|
||||
-shift_extract YES
|
||||
-xor_collapse YES
|
||||
-rom_style Auto
|
||||
-auto_bram_packing NO
|
||||
-mux_extract YES
|
||||
-resource_sharing YES
|
||||
-async_to_sync NO
|
||||
-use_dsp48 auto
|
||||
-iobuf YES
|
||||
-max_fanout 500
|
||||
-bufg 32
|
||||
-bufr 24
|
||||
-register_duplication YES
|
||||
-register_balancing No
|
||||
-slice_packing YES
|
||||
-optimize_primitives NO
|
||||
-use_clock_enable Auto
|
||||
-use_sync_set Auto
|
||||
-use_sync_reset Auto
|
||||
-iob auto
|
||||
-equivalent_register_removal YES
|
||||
-slice_utilization_ratio_maxmargin 5
|
||||
@@ -0,0 +1,2 @@
|
||||
vhdl ieee_proposed "C:\Programme\Xilinx9\vhdl\src\ieee_proposed\fixed_pkg_c.vhd"
|
||||
vhdl work "H:\vhdl\projects\eval_fixed_ja\src\eval_fixed_ja_syn.vhd"
|
||||
@@ -0,0 +1,15 @@
|
||||
## NOTE: Do not edit this file.
|
||||
## Autogenerated by ProjNav (creatfdo.tcl) on Thu May 24 11:58:33 Westeuropäische Normalzeit 2007
|
||||
##
|
||||
vlib work
|
||||
vlib ieee_proposed
|
||||
vcom -explicit -93 -work ieee_proposed "C:/Programme/Xilinx9/vhdl/src/ieee_proposed/fixed_pkg_c.vhd"
|
||||
vcom -explicit -93 "../src/eval_fixed_ja_syn.vhd"
|
||||
vcom -explicit -93 "../src/tb_eval_fixed_ja_syn.vhd"
|
||||
vsim -t 1ps -lib work tb_eval_fixed_ja_vhd
|
||||
view wave
|
||||
add wave *
|
||||
do {tb_eval_fixed_ja_vhd.udo}
|
||||
view structure
|
||||
view signals
|
||||
run 1000ns
|
||||
@@ -0,0 +1,15 @@
|
||||
## NOTE: Do not edit this file.
|
||||
## Auto generated by Project Navigator for Post-Translate Simulation
|
||||
##
|
||||
vlib work
|
||||
## Compile Post-Translate Model
|
||||
vcom -explicit -93 "netgen/translate/eval_fixed_ja_translate.vhd"
|
||||
vcom -explicit -93 "../src/tb_eval_fixed_ja_syn.vhd"
|
||||
vsim -t 1ps -lib work tb_eval_fixed_ja_vhd
|
||||
do {tb_eval_fixed_ja_vhd.udo}
|
||||
view wave
|
||||
add wave *
|
||||
view structure
|
||||
view signals
|
||||
run 1000ns
|
||||
## End
|
||||
@@ -0,0 +1,4 @@
|
||||
-- ProjNav VHDL simulation template: tb_eval_fixed_ja_vhd.udo
|
||||
-- You may edit this file after the line that starts with
|
||||
-- '-- START' to customize your simulation
|
||||
-- START user-defined simulation commands
|
||||
@@ -0,0 +1,12 @@
|
||||
vlib work
|
||||
vcom -explicit -93 "../lib/fixed_ja.vhd"
|
||||
vcom -explicit -93 "../lib/fixed_ja_body.vhd"
|
||||
vcom -explicit -93 "../lib/PCK_FIO_1993.vhd"
|
||||
vcom -explicit -93 "../lib/PCK_FIO_1993_BODY.vhd"
|
||||
vcom -explicit -93 "src/tb_eval_fixed_ja.vhd"
|
||||
vsim -t 1ps -lib work tb_eval_fixed_ja
|
||||
#do {wave.do}
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
run 1000ns
|
||||
@@ -0,0 +1,107 @@
|
||||
## Generated SDC file "eval_fixed_ja.out.sdc"
|
||||
|
||||
## Copyright (C) 1991-2008 Altera Corporation
|
||||
## Your use of Altera Corporation's design tools, logic functions
|
||||
## and other software and tools, and its AMPP partner logic
|
||||
## functions, and any output files from any of the foregoing
|
||||
## (including device programming or simulation files), and any
|
||||
## associated documentation or information are expressly subject
|
||||
## to the terms and conditions of the Altera Program License
|
||||
## Subscription Agreement, Altera MegaCore Function License
|
||||
## Agreement, or other applicable license agreement, including,
|
||||
## without limitation, that your use is for the sole purpose of
|
||||
## programming logic devices manufactured by Altera and sold by
|
||||
## Altera or its authorized distributors. Please refer to the
|
||||
## applicable agreement for further details.
|
||||
|
||||
|
||||
## VENDOR "Altera"
|
||||
## PROGRAM "Quartus II"
|
||||
## VERSION "Version 8.1 Build 163 10/28/2008 SJ Web Edition"
|
||||
|
||||
## DATE "Thu Dec 18 22:26:14 2008"
|
||||
|
||||
##
|
||||
## DEVICE "EP3C25Q240C8"
|
||||
##
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Time Information
|
||||
#**************************************************************
|
||||
|
||||
set_time_format -unit ns -decimal_places 3
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Create Clock
|
||||
#**************************************************************
|
||||
|
||||
create_clock -name {ccc} -period 10.000 -waveform { 0.000 5.000 } [get_ports {clk}]
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Create Generated Clock
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Latency
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Uncertainty
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Input Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Output Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Groups
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set False Path
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Multicycle Path
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Maximum Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Minimum Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Input Transition
|
||||
#**************************************************************
|
||||
|
||||
@@ -0,0 +1,23 @@
|
||||
# Copyright (C) 1991-2008 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
|
||||
|
||||
|
||||
QUARTUS_VERSION = "8.1"
|
||||
DATE = "10:27:40 December 18, 2008"
|
||||
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "eval_fixed_ja"
|
||||
@@ -0,0 +1,47 @@
|
||||
# Copyright (C) 1991-2008 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
|
||||
|
||||
# The default values for assignments are stored in the file
|
||||
# eval_fixed_ja_assignment_defaults.qdf
|
||||
# If this file doesn't exist, and for assignments not listed, see file
|
||||
# assignment_defaults.qdf
|
||||
|
||||
# Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus II software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
|
||||
|
||||
set_global_assignment -name FAMILY "Cyclone III"
|
||||
set_global_assignment -name DEVICE EP3C25Q240C8
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY eval_fixed_ja
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:27:40 DECEMBER 18, 2008"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION 8.1
|
||||
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
|
||||
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
|
||||
set_global_assignment -name ASSIGNMENT_GROUP_MEMBER clk -section_id clock
|
||||
set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON
|
||||
set_global_assignment -name SDC_FILE eval_fixed_ja.out.sdc
|
||||
set_global_assignment -name VHDL_FILE ../../../lib/fixed/fixed_pkg_c.vhd
|
||||
set_global_assignment -name VHDL_FILE ../src/eval_fixed_ja_syn.vhd
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
|
||||
@@ -0,0 +1,29 @@
|
||||
[ProjectWorkspace]
|
||||
ptn_Child1=Frames
|
||||
[ProjectWorkspace.Frames]
|
||||
ptn_Child1=ChildFrames
|
||||
[ProjectWorkspace.Frames.ChildFrames]
|
||||
ptn_Child1=Document-0
|
||||
ptn_Child2=Document-1
|
||||
ptn_Child3=Document-2
|
||||
ptn_Child4=Document-3
|
||||
[ProjectWorkspace.Frames.ChildFrames.Document-2]
|
||||
ptn_Child1=ViewFrame-0
|
||||
[ProjectWorkspace.Frames.ChildFrames.Document-2.ViewFrame-0]
|
||||
DocPathName=eval_fixed_ja.sdc
|
||||
DocumentCLSID={c5dd978f-562d-48b1-a72f-0e9994df79df}
|
||||
IsChildFrameDetached=False
|
||||
IsActiveChildFrame=False
|
||||
ptn_Child1=StateMap
|
||||
[ProjectWorkspace.Frames.ChildFrames.Document-2.ViewFrame-0.StateMap]
|
||||
AFC_IN_REPORT=False
|
||||
[ProjectWorkspace.Frames.ChildFrames.Document-3]
|
||||
ptn_Child1=ViewFrame-0
|
||||
[ProjectWorkspace.Frames.ChildFrames.Document-3.ViewFrame-0]
|
||||
DocPathName=eval_fixed_ja.out.sdc
|
||||
DocumentCLSID={c5dd978f-562d-48b1-a72f-0e9994df79df}
|
||||
IsChildFrameDetached=False
|
||||
IsActiveChildFrame=False
|
||||
ptn_Child1=StateMap
|
||||
[ProjectWorkspace.Frames.ChildFrames.Document-3.ViewFrame-0.StateMap]
|
||||
AFC_IN_REPORT=False
|
||||
@@ -0,0 +1,56 @@
|
||||
###########################################################################
|
||||
#
|
||||
# Generated by : Version 8.1 Build 163 10/28/2008 SJ Web Edition
|
||||
#
|
||||
# Project : eval_fixed_ja
|
||||
# Revision : eval_fixed_ja
|
||||
#
|
||||
# Date : Thu Dec 18 22:17:10 Westeuropäische Normalzeit 2008
|
||||
#
|
||||
###########################################################################
|
||||
|
||||
|
||||
# WARNING: Expected ENABLE_CLOCK_LATENCY to be set to 'ON', but it is set to 'OFF'
|
||||
# In SDC, create_generated_clock auto-generates clock latency
|
||||
#
|
||||
# ------------------------------------------
|
||||
#
|
||||
# Create generated clocks based on PLLs
|
||||
derive_pll_clocks -use_tan_name
|
||||
#
|
||||
# ------------------------------------------
|
||||
|
||||
# ** Clock Latency
|
||||
# -------------
|
||||
|
||||
# ** Clock Uncertainty
|
||||
# -----------------
|
||||
|
||||
# ** Multicycles
|
||||
# -----------
|
||||
# ** Cuts
|
||||
# ----
|
||||
|
||||
# ** Input/Output Delays
|
||||
# -------------------
|
||||
|
||||
|
||||
|
||||
|
||||
# ** Tpd requirements
|
||||
# ----------------
|
||||
|
||||
# ** Setup/Hold Relationships
|
||||
# ------------------------
|
||||
|
||||
# ** Tsu/Th requirements
|
||||
# -------------------
|
||||
|
||||
|
||||
# ** Tco/MinTco requirements
|
||||
# -----------------------
|
||||
|
||||
|
||||
|
||||
# ---------------------------------------------
|
||||
|
||||
@@ -0,0 +1,876 @@
|
||||
Fixed Point Library Testbench 0.1
|
||||
----------------------
|
||||
Without saturation
|
||||
----------------------
|
||||
|
||||
* No rounding
|
||||
|
||||
U: 101.0011 => 01.0011 ...passed
|
||||
U: 1.001101 => 001. ...passed
|
||||
U: 101.01 => 1.0 ...passed
|
||||
U: 1010.1 => 10. ...passed
|
||||
U: 101.11 => 101. ...passed
|
||||
U: .11 => 0. ...passed
|
||||
U: .1011 => 0.10 ...passed
|
||||
U: 0.0000000001 => 0. ...passed
|
||||
U: 1.0000000001 => 1.0 ...passed
|
||||
U: 1.0000000001 => 1. ...passed
|
||||
U: 10.000000001 => 10.000 ...passed
|
||||
U: 1. => 1.00000000000000000 ...passed
|
||||
U: 0. => 0.00000000000000000 ...passed
|
||||
U: 1. => .000000000000000000 ...passed
|
||||
U: 0. => .000000000000000000 ...passed
|
||||
U: 10.101 => 010.1010 ...passed
|
||||
U: 10.101 => 10.10 ...passed
|
||||
U: 10.101 => 10.1010 ...passed
|
||||
S: 101.0011 => 01.0011 ...passed
|
||||
S: -1.001101 => -001. ...passed
|
||||
S: -101.01 => -1.0 ...passed
|
||||
S: 1010.1 => 10. ...passed
|
||||
S: 101.11 => 101. ...passed
|
||||
S: -.11 => 0. ...passed
|
||||
S: -.1011 => -0.10 ...passed
|
||||
S: 0.0000000001 => 0. ...passed
|
||||
S: -1.0000000001 => -1.0 ...passed
|
||||
S: -1.0000000001 => -1. ...passed
|
||||
S: -10.000000001 => -10.000 ...passed
|
||||
S: 1. => 1.00000000000000000 ...passed
|
||||
S: 0. => 0.00000000000000000 ...passed
|
||||
S: 1. => .000000000000000000 ...passed
|
||||
S: 0. => .000000000000000000 ...passed
|
||||
S: 10.101 => 010.1010 ...passed
|
||||
S: -10.101 => -10.10 ...passed
|
||||
S: 10.101 => 10.1010 ...passed
|
||||
|
||||
* Round to zero
|
||||
|
||||
U: 101.0011 => 01.0011 ...passed
|
||||
U: 1.001101 => 001. ...passed
|
||||
U: 101.01 => 1.0 ...passed
|
||||
U: 1010.1 => 10. ...passed
|
||||
U: 101.11 => 101. ...passed
|
||||
U: .11 => 0. ...passed
|
||||
U: .1011 => 0.10 ...passed
|
||||
U: 0.0000000001 => 0. ...passed
|
||||
U: 1.0000000001 => 1.0 ...passed
|
||||
U: 1.0000000001 => 1. ...passed
|
||||
U: 10.000000001 => 10.000 ...passed
|
||||
U: 1. => 1.00000000000000000 ...passed
|
||||
U: 0. => 0.00000000000000000 ...passed
|
||||
U: 1. => .000000000000000000 ...passed
|
||||
U: 0. => .000000000000000000 ...passed
|
||||
U: 10.101 => 010.1010 ...passed
|
||||
U: 10.101 => 10.10 ...passed
|
||||
U: 10.101 => 10.1010 ...passed
|
||||
S: 101.0011 => 01.0011 ...passed
|
||||
S: -1.001101 => -001. ...passed
|
||||
S: -101.01 => -1.0 ...passed
|
||||
S: 1010.1 => 10. ...passed
|
||||
S: 101.11 => 101. ...passed
|
||||
S: -.11 => 0. ...passed
|
||||
S: -.1011 => -0.10 ...passed
|
||||
S: 0.0000000001 => 0. ...passed
|
||||
S: -1.0000000001 => -1.0 ...passed
|
||||
S: -1.0000000001 => -1. ...passed
|
||||
S: -10.000000001 => -10.000 ...passed
|
||||
S: 1. => 1.00000000000000000 ...passed
|
||||
S: 0. => 0.00000000000000000 ...passed
|
||||
S: 1. => .000000000000000000 ...passed
|
||||
S: 0. => .000000000000000000 ...passed
|
||||
S: 10.101 => 010.1010 ...passed
|
||||
S: -10.101 => -10.10 ...passed
|
||||
S: 10.101 => 10.1010 ...passed
|
||||
|
||||
* Round to infinity
|
||||
|
||||
U: 101.0011 => 01.0011 ...passed
|
||||
U: 1.001101 => 010. ...passed
|
||||
U: 101.01 => 1.1 ...passed
|
||||
U: 1010.1 => 11. ...passed
|
||||
U: 101.11 => 110. ...passed
|
||||
U: .11 => 1. ...passed
|
||||
U: .1011 => 0.11 ...passed
|
||||
U: 0.0000000001 => 1. ...passed
|
||||
U: 1.0000000001 => 1.1 ...passed
|
||||
U: 1.0000000001 => 0. ...passed
|
||||
U: 10.000000001 => 10.001 ...passed
|
||||
U: 1. => 1.00000000000000000 ...passed
|
||||
U: 0. => 0.00000000000000000 ...passed
|
||||
U: 1. => .000000000000000000 ...passed
|
||||
U: 0. => .000000000000000000 ...passed
|
||||
U: 10.101 => 010.1010 ...passed
|
||||
U: 10.101 => 10.11 ...passed
|
||||
U: 10.101 => 10.1010 ...passed
|
||||
S: 101.0011 => 01.0011 ...passed
|
||||
S: -10.001101 => -010. ...passed
|
||||
S: -101.01 => -1.0 ...passed
|
||||
S: 1010.1 => 11. ...passed
|
||||
S: 101.11 => 110. ...passed
|
||||
S: -.11 => 0. ...passed
|
||||
S: -.1011 => -0.10 ...passed
|
||||
S: 0.0000000001 => 1. ...passed
|
||||
S: -1.0000000001 => -1.0 ...passed
|
||||
S: 1.0000000001 => 0. ...passed
|
||||
S: -10.000000001 => -10.000 ...passed
|
||||
S: 1. => 1.00000000000000000 ...passed
|
||||
S: 0. => 0.00000000000000000 ...passed
|
||||
S: 1. => .000000000000000000 ...passed
|
||||
S: 0. => .000000000000000000 ...passed
|
||||
S: 10.101 => 010.1010 ...passed
|
||||
S: -10.101 => -10.10 ...passed
|
||||
S: 10.101 => 10.1010 ...passed
|
||||
|
||||
* Round half up
|
||||
|
||||
U: 101.0011 => 01.0011 ...passed
|
||||
U: 1.001101 => 001. ...passed
|
||||
U: 101.01 => 1.1 ...passed
|
||||
U: 1010.1 => 11. ...passed
|
||||
U: 101.11 => 110. ...passed
|
||||
U: .11 => 1. ...passed
|
||||
U: .1011 => 0.11 ...passed
|
||||
U: 0.0000000001 => 0. ...passed
|
||||
U: 1.0000000001 => 1.0 ...passed
|
||||
U: 1.0000000001 => 1. ...passed
|
||||
U: 10.000000001 => 10.000 ...passed
|
||||
U: 1. => 1.00000000000000000 ...passed
|
||||
U: 0. => 0.00000000000000000 ...passed
|
||||
U: 1. => .000000000000000000 ...passed
|
||||
U: 0. => .000000000000000000 ...passed
|
||||
U: 10.101 => 010.1010 ...passed
|
||||
U: 10.101 => 10.11 ...passed
|
||||
U: 10.101 => 10.1010 ...passed
|
||||
S: 101.0011 => 01.0011 ...passed
|
||||
S: -10.001101 => -010. ...passed
|
||||
S: -101.01 => -1.0 ...passed
|
||||
S: 1010.1 => 11. ...passed
|
||||
S: 101.11 => 110. ...passed
|
||||
S: -.11 => -1. ...passed
|
||||
S: -.1011 => -0.11 ...passed
|
||||
S: 0.0000000001 => 0. ...passed
|
||||
S: -1.0000000001 => -1.0 ...passed
|
||||
S: 1.0000000001 => 1. ...passed
|
||||
S: -10.000000001 => -10.000 ...passed
|
||||
S: 1. => 1.00000000000000000 ...passed
|
||||
S: 0. => 0.00000000000000000 ...passed
|
||||
S: 1. => .000000000000000000 ...passed
|
||||
S: 0. => .000000000000000000 ...passed
|
||||
S: 10.101 => 010.1010 ...passed
|
||||
S: -10.1011 => -10.11 ...passed
|
||||
S: -10.101 => -10.10 ...passed
|
||||
S: -0.1111 => -0.111 ...passed
|
||||
S: -0.11110 => -0.111 ...passed
|
||||
S: -0.11111 => -1.000 ...passed
|
||||
|
||||
* Round convergent
|
||||
|
||||
U: 01.001 => 01.00 ...passed
|
||||
U: 01.0010 => 01.00 ...passed
|
||||
U: 01.0011 => 01.01 ...passed
|
||||
U: 01.011 => 01.10 ...passed
|
||||
U: 01.0110 => 01.10 ...passed
|
||||
U: 01.0111 => 01.10 ...passed
|
||||
S: 01.001 => 01.00 ...passed
|
||||
S: 01.0010 => 01.00 ...passed
|
||||
S: 01.0011 => 01.01 ...passed
|
||||
S: 01.011 => 01.10 ...passed
|
||||
S: 01.0110 => 01.10 ...passed
|
||||
S: 01.0111 => 01.10 ...passed
|
||||
S: -01.001 => -01.00 ...passed
|
||||
S: -01.0010 => -01.00 ...passed
|
||||
S: -01.0011 => -01.01 ...passed
|
||||
S: -01.011 => -01.10 ...passed
|
||||
S: -01.0110 => -01.10 ...passed
|
||||
S: -01.0111 => -01.10 ...passed
|
||||
|
||||
----------------------
|
||||
With saturation
|
||||
----------------------
|
||||
|
||||
* No rounding
|
||||
|
||||
U: 101.0011 => 11.1111 ...passed
|
||||
U: 1.001101 => 001. ...passed
|
||||
U: 101.01 => 1.1 ...passed
|
||||
U: 1010.1 => 11. ...passed
|
||||
U: 101.11 => 101. ...passed
|
||||
U: .11 => 0. ...passed
|
||||
U: .1011 => 0.10 ...passed
|
||||
U: 0.0000000001 => 0. ...passed
|
||||
U: 1.0000000001 => 1.0 ...passed
|
||||
U: 1.0000000001 => 1. ...passed
|
||||
U: 10.000000001 => 10.000 ...passed
|
||||
U: 1. => 1.00000000000000000 ...passed
|
||||
U: 0. => 0.00000000000000000 ...passed
|
||||
U: 1. => .111111111111111111 ...passed
|
||||
U: 0. => .000000000000000000 ...passed
|
||||
U: 10.101 => 010.1010 ...passed
|
||||
U: 10.101 => 10.10 ...passed
|
||||
U: 10.101 => 10.1010 ...passed
|
||||
U: 1.0000 => .11111 ...passed
|
||||
U: 01.000 => .11111 ...passed
|
||||
U: 11.000 => .11111 ...passed
|
||||
U: 0.1000 => .10000 ...passed
|
||||
U: 00.100 => .10000 ...passed
|
||||
U: 1.0001 => .11111 ...passed
|
||||
U: 01.001 => .11111 ...passed
|
||||
U: 01.010 => .11111 ...passed
|
||||
U: 11.001 => .11111 ...passed
|
||||
U: 0.1001 => .10010 ...passed
|
||||
U: 00.101 => .10100 ...passed
|
||||
U: 1.000000000000000001 => .111111111111111 ...passed
|
||||
U: 01.00000000000000001 => .111111111111111 ...passed
|
||||
U: 1.00000000000000 => .111111111111111 ...passed
|
||||
S: -101.0011 => -11.1111 ...passed
|
||||
S: 1.001101 => 001. ...passed
|
||||
S: 101.01 => 1.1 ...passed
|
||||
S: 1010.1 => 11. ...passed
|
||||
S: 101.11 => 101. ...passed
|
||||
S: .11 => 0. ...passed
|
||||
S: .1011 => 0.10 ...passed
|
||||
S: -0.0000000001 => 0. ...passed
|
||||
S: -1.0000000001 => -1.0 ...passed
|
||||
S: 1.0000000001 => 1. ...passed
|
||||
S: 10.000000001 => 10.000 ...passed
|
||||
S: 1. => 1.00000000000000000 ...passed
|
||||
S: 0. => 0.00000000000000000 ...passed
|
||||
S: -1. => -.111111111111111111 ...passed
|
||||
S: 0. => .000000000000000000 ...passed
|
||||
S: -10.101 => -010.1010 ...passed
|
||||
S: -10.101 => -10.10 ...passed
|
||||
S: -10.101 => -10.1010 ...passed
|
||||
S: -1.0000 => -.11111 ...passed
|
||||
S: -01.000 => -.11111 ...passed
|
||||
S: -11.000 => -.11111 ...passed
|
||||
S: -0.1000 => -.10000 ...passed
|
||||
S: -00.100 => -.10000 ...passed
|
||||
S: -1.0001 => -.11111 ...passed
|
||||
S: -01.001 => -.11111 ...passed
|
||||
S: -01.010 => -.11111 ...passed
|
||||
S: -11.001 => -.11111 ...passed
|
||||
S: -0.1001 => -.10010 ...passed
|
||||
S: -00.101 => -.10100 ...passed
|
||||
S: -1.000000000000000001 => -.111111111111111 ...passed
|
||||
S: -01.00000000000000001 => -.111111111111111 ...passed
|
||||
S: -1.00000000000000 => -.111111111111111 ...passed
|
||||
S: 1.000000000000000001 => .111111111111111 ...passed
|
||||
S: 01.00000000000000001 => .111111111111111 ...passed
|
||||
S: 1.00000000000000 => .111111111111111 ...passed
|
||||
S: 1.0000 => .11111 ...passed
|
||||
S: 01.000 => .11111 ...passed
|
||||
S: 0.1000 => .10000 ...passed
|
||||
S: 00.100 => .10000 ...passed
|
||||
|
||||
* Round to zero
|
||||
|
||||
U: 101.0011 => 11.1111 ...passed
|
||||
U: 1.001101 => 001. ...passed
|
||||
U: 101.01 => 1.1 ...passed
|
||||
U: 1010.1 => 11. ...passed
|
||||
U: 101.11 => 101. ...passed
|
||||
U: .11 => 0. ...passed
|
||||
U: .1011 => 0.10 ...passed
|
||||
U: 0.0000000001 => 0. ...passed
|
||||
U: 1.0000000001 => 1.0 ...passed
|
||||
U: 1.0000000001 => 1. ...passed
|
||||
U: 10.000000001 => 10.000 ...passed
|
||||
U: 1. => 1.00000000000000000 ...passed
|
||||
U: 0. => 0.00000000000000000 ...passed
|
||||
U: 1. => .111111111111111111 ...passed
|
||||
U: 0. => .000000000000000000 ...passed
|
||||
U: 10.101 => 010.1010 ...passed
|
||||
U: 10.101 => 10.10 ...passed
|
||||
U: 10.101 => 10.1010 ...passed
|
||||
U: 1.000000000000000001 => .111111111111111 ...passed
|
||||
U: 01.00000000000000001 => .111111111111111 ...passed
|
||||
U: 1.00000000000000 => .111111111111111 ...passed
|
||||
S: 101.0011 => 11.1111 ...passed
|
||||
S: 1.001101 => 001. ...passed
|
||||
S: 101.01 => 1.1 ...passed
|
||||
S: 1010.1 => 11. ...passed
|
||||
S: 101.11 => 101. ...passed
|
||||
S: .11 => 0. ...passed
|
||||
S: .1011 => 0.10 ...passed
|
||||
S: 0.0000000001 => 0. ...passed
|
||||
S: 1.0000000001 => 1.0 ...passed
|
||||
S: 1.0000000001 => 1. ...passed
|
||||
S: 10.000000001 => 10.000 ...passed
|
||||
S: 1. => 1.00000000000000000 ...passed
|
||||
S: 0. => 0.00000000000000000 ...passed
|
||||
S: 1. => .111111111111111111 ...passed
|
||||
S: 0. => .000000000000000000 ...passed
|
||||
S: 10.101 => 010.1010 ...passed
|
||||
S: 10.101 => 10.10 ...passed
|
||||
S: 10.101 => 10.1010 ...passed
|
||||
S: -1.000000000000000001 => -.111111111111111 ...passed
|
||||
S: -01.00000000000000001 => -.111111111111111 ...passed
|
||||
S: -1.00000000000000 => -.111111111111111 ...passed
|
||||
S: 1.000000000000000001 => .111111111111111 ...passed
|
||||
S: 01.00000000000000001 => .111111111111111 ...passed
|
||||
S: 1.00000000000000 => .111111111111111 ...passed
|
||||
S: 1.0000 => .11111 ...passed
|
||||
S: 01.000 => .11111 ...passed
|
||||
S: 0.1000 => .10000 ...passed
|
||||
S: 00.100 => .10000 ...passed
|
||||
|
||||
* Round to infinity
|
||||
|
||||
U: 101.0011 => 11.1111 ...passed
|
||||
U: 1.001101 => 010. ...passed
|
||||
U: 101.01 => 1.1 ...passed
|
||||
U: 1010.1 => 11. ...passed
|
||||
U: 101.11 => 110. ...passed
|
||||
U: .11 => 1. ...passed
|
||||
U: .1011 => 0.11 ...passed
|
||||
U: 0.0000000001 => 1. ...passed
|
||||
U: 1.0000000001 => 1.1 ...passed
|
||||
U: 1.0000000001 => 1. ...passed
|
||||
U: 10.000000001 => 10.001 ...passed
|
||||
U: 1. => 1.00000000000000000 ...passed
|
||||
U: 0. => 0.00000000000000000 ...passed
|
||||
U: 1. => .111111111111111111 ...passed
|
||||
U: 0. => .000000000000000000 ...passed
|
||||
U: 10.101 => 010.1010 ...passed
|
||||
U: 10.101 => 10.11 ...passed
|
||||
U: 10.101 => 10.1010 ...passed
|
||||
U: 1.000000000000000001 => .111111111111111 ...passed
|
||||
U: 01.00000000000000001 => .111111111111111 ...passed
|
||||
U: 1.00000000000000 => .111111111111111 ...passed
|
||||
S: 101.0011 => 11.1111 ...passed
|
||||
S: 1.001101 => 010. ...passed
|
||||
S: 101.01 => 1.1 ...passed
|
||||
S: 1010.1 => 11. ...passed
|
||||
S: 101.11 => 110. ...passed
|
||||
S: .11 => 1. ...passed
|
||||
S: .1011 => 0.11 ...passed
|
||||
S: 0.0000000001 => 1. ...passed
|
||||
S: 1.0000000001 => 1.1 ...passed
|
||||
S: 1.0000000001 => 1. ...passed
|
||||
S: 10.000000001 => 10.001 ...passed
|
||||
S: 1. => 1.00000000000000000 ...passed
|
||||
S: 0. => 0.00000000000000000 ...passed
|
||||
S: 1. => .111111111111111111 ...passed
|
||||
S: 0. => .000000000000000000 ...passed
|
||||
S: 10.101 => 010.1010 ...passed
|
||||
S: 10.101 => 10.11 ...passed
|
||||
S: 10.101 => 10.1010 ...passed
|
||||
S: -1.000000000000000001 => -.111111111111111 ...passed
|
||||
S: -01.00000000000000001 => -.111111111111111 ...passed
|
||||
S: -1.00000000000000 => -.111111111111111 ...passed
|
||||
S: 1.000000000000000001 => .111111111111111 ...passed
|
||||
S: 01.00000000000000001 => .111111111111111 ...passed
|
||||
S: 1.00000000000000 => .111111111111111 ...passed
|
||||
S: 1.0000 => .11111 ...passed
|
||||
S: 01.000 => .11111 ...passed
|
||||
S: 0.1000 => .10000 ...passed
|
||||
S: 00.100 => .10000 ...passed
|
||||
|
||||
* Round half up
|
||||
|
||||
U: 101.0011 => 11.1111 ...passed
|
||||
U: 1.001101 => 001. ...passed
|
||||
U: 101.01 => 1.1 ...passed
|
||||
U: 1010.1 => 11. ...passed
|
||||
U: 101.11 => 110. ...passed
|
||||
U: .11 => 1. ...passed
|
||||
U: .1011 => 0.11 ...passed
|
||||
U: 0.0000000001 => 0. ...passed
|
||||
U: 1.0000000001 => 1.0 ...passed
|
||||
U: 1.0000000001 => 1. ...passed
|
||||
U: 10.000000001 => 10.000 ...passed
|
||||
U: 1. => 1.00000000000000000 ...passed
|
||||
U: 0. => 0.00000000000000000 ...passed
|
||||
U: 1. => .111111111111111111 ...passed
|
||||
U: 0. => .000000000000000000 ...passed
|
||||
U: 10.101 => 010.1010 ...passed
|
||||
U: 10.101 => 10.11 ...passed
|
||||
U: 10.101 => 10.1010 ...passed
|
||||
U: 1.000000000000000001 => .111111111111111 ...passed
|
||||
U: 01.00000000000000001 => .111111111111111 ...passed
|
||||
U: 1.00000000000000 => .111111111111111 ...passed
|
||||
S: 101.0011 => 11.1111 ...passed
|
||||
S: 1.001101 => 001. ...passed
|
||||
S: 101.01 => 1.1 ...passed
|
||||
S: 1010.1 => 11. ...passed
|
||||
S: 101.11 => 110. ...passed
|
||||
S: -.11 => -1. ...passed
|
||||
S: -.1 => 0. ...passed
|
||||
S: .1011 => 0.11 ...passed
|
||||
S: 0.0000000001 => 0. ...passed
|
||||
S: 1.0000000001 => 1.0 ...passed
|
||||
S: 1.0000000001 => 1. ...passed
|
||||
S: 10.000000001 => 10.000 ...passed
|
||||
S: 1. => 1.00000000000000000 ...passed
|
||||
S: 0. => 0.00000000000000000 ...passed
|
||||
S: 1. => .111111111111111111 ...passed
|
||||
S: 0. => .000000000000000000 ...passed
|
||||
S: 10.101 => 010.1010 ...passed
|
||||
S: 10.101 => 10.11 ...passed
|
||||
S: 10.101 => 10.1010 ...passed
|
||||
S: -1.000000000000000000 => -.111111111111111 ...passed
|
||||
S: -1.000000000000000001 => -.111111111111111 ...passed
|
||||
S: -01.00000000000000000 => -.111111111111111 ...passed
|
||||
S: -01.00000000000000001 => -.111111111111111 ...passed
|
||||
S: -01.0000000000000 => -.111111111111111 ...passed
|
||||
S: -01.0000000000001 => -.111111111111111 ...passed
|
||||
S: -01.0000000000000 => -.11111111111111 ...passed
|
||||
S: -01.0000000000001 => -.11111111111111 ...passed
|
||||
S: -01.0000000000000 => -.1111111111111111 ...passed
|
||||
S: -01.0000000000001 => -.1111111111111111 ...passed
|
||||
S: -00.1111111111111 => -.111111111111100 ...passed
|
||||
S: -00.111111111111111 => -.11111111111111 ...passed
|
||||
S: -00.111111111111111 => -1.0000000000000 ...passed
|
||||
S: -1.000000000000000001 => -.111111111111111 ...passed
|
||||
S: -01.00000000000000001 => -.111111111111111 ...passed
|
||||
S: -1.0000000000000000001 => -.111111111111111 ...passed
|
||||
S: -01.000000000000000001 => -.111111111111111 ...passed
|
||||
S: -1.00000000000000000001 => -.111111111111111 ...passed
|
||||
S: -01.0000000000000000001 => -.111111111111111 ...passed
|
||||
S: -1.000000000000000000001 => -.111111111111111 ...passed
|
||||
S: -01.00000000000000000001 => -.111111111111111 ...passed
|
||||
S: -1.0000000000000000000001 => -.111111111111111 ...passed
|
||||
S: -01.000000000000000000001 => -.111111111111111 ...passed
|
||||
S: -1.000000000000000011 => -.111111111111111 ...passed
|
||||
S: -01.00000000000000011 => -.111111111111111 ...passed
|
||||
S: -1.0000000000000000011 => -.111111111111111 ...passed
|
||||
S: -01.000000000000000011 => -.111111111111111 ...passed
|
||||
S: -1.00000000000000000011 => -.111111111111111 ...passed
|
||||
S: -01.0000000000000000011 => -.111111111111111 ...passed
|
||||
S: -1.000000000000000000011 => -.111111111111111 ...passed
|
||||
S: -01.00000000000000000011 => -.111111111111111 ...passed
|
||||
S: -1.0000000000000000000011 => -.111111111111111 ...passed
|
||||
S: -01.000000000000000000011 => -.111111111111111 ...passed
|
||||
S: -1.00000000000000 => -.111111111111111 ...passed
|
||||
S: 1.0000 => .11111 ...passed
|
||||
S: 01.000 => .11111 ...passed
|
||||
S: 0.1000 => .10000 ...passed
|
||||
S: 00.100 => .10000 ...passed
|
||||
|
||||
U: .10000000 + .01000000 = 0.11000000 ...passed
|
||||
U: .01100000 + .01000000 = 0.10100000 ...passed
|
||||
U: 0.0110000 - .01000000 = 0.00100000 ...passed
|
||||
U: .10000000 + .01000000 = 0.11000000 ...passed
|
||||
U: .10000000 - .01000000 = .01000000 ...passed
|
||||
U: .01000000 + .01000000 = 0.10000000 ...passed
|
||||
U: .01000000 - .01000000 = .00000000 ...passed
|
||||
U: .0100 + 000.01000 = 000.10000 ...passed
|
||||
U: 1.0000 + 1.0000 = 10.0000 ...passed
|
||||
U: 0.1001 + 0.0110 = 00.1111 ...passed
|
||||
U: 0.0011 + 0.0110 = 00.1001 ...passed
|
||||
U: 0.1111 + 1.0001 = 10.0000 ...passed
|
||||
U: 10.0000 - 1.0000 = 01.0000 ...passed
|
||||
U: 00.1111 - 0.1001 = 00.0110 ...passed
|
||||
U: 00.1001 - 0.0011 = 00.0110 ...passed
|
||||
U: 10.0000 - 0.1111 = 01.0001 ...passed
|
||||
U: .10000000 * 100.10000 = 10.01000000000000 ...passed
|
||||
U: .10000000 * .10000000 = .0100000000000000 ...passed
|
||||
U: 0.1000000 * .10000000 = .0100000000000000 ...passed
|
||||
U: 0.1000000 * 0.1000000 = 00.01000000000000 ...passed
|
||||
U: 0.1000000 * .10000000 = .0100000000000000 ...passed
|
||||
U: 00.100000 * 0.1000000 = 000.0100000000000 ...passed
|
||||
U: 01.1000000 * .10000000 = 0.1100000000000000 ...passed
|
||||
U: .10000000 * 01.1000000 = 0.1100000000000000 ...passed
|
||||
U: 01.100000 * .100000000 = 0.1100000000000000 ...passed
|
||||
U: .100000000 * 01.100000 = 0.1100000000000000 ...passed
|
||||
S: .011 + .0100000 = 0.1010000 ...passed
|
||||
S: .0110000 - .0100000 = .0010000 ...passed
|
||||
S: .1000000 + .0100000 = 0.1100000 ...passed
|
||||
S: .1000000 - .0100000 = .0100000 ...passed
|
||||
S: .0100000 + .0100000 = 0.1000000 ...passed
|
||||
S: .0100000 - .0100000 = .0000000 ...passed
|
||||
S: .010 + 000.0100 = 000.1000 ...passed
|
||||
S: -.100 * 100.1000 = -10.010000000 ...passed
|
||||
S: -.1000000 * .1000000 = -.010000000000000 ...passed
|
||||
S: -0.100000 * .1000000 = -.010000000000000 ...passed
|
||||
S: -0.100000 * 0.100000 = -00.0100000000000 ...passed
|
||||
S: .100 * 100.1000 = 10.010000000 ...passed
|
||||
S: .1000000 * .1000000 = .010000000000000 ...passed
|
||||
S: 0.100000 * .1000000 = .010000000000000 ...passed
|
||||
S: 0.100000 * 0.100000 = 00.0100000000000 ...passed
|
||||
----------------------
|
||||
Arithmetic Test
|
||||
----------------------
|
||||
Test finished
|
||||
|
||||
|
||||
Positive ufixed
|
||||
1.000 sla 0 = 1.000
|
||||
1.000 sla 1 = 0.000
|
||||
1.000 sla 2 = 0.000
|
||||
1.000 sla 3 = 0.000
|
||||
1.000 sla 4 = 0.000
|
||||
|
||||
1.000 sla 0 = 1.000
|
||||
1.000 sla -1 = 0.100
|
||||
1.000 sla -2 = 0.010
|
||||
1.000 sla -3 = 0.001
|
||||
1.000 sla -4 = 0.000
|
||||
|
||||
1.000 sra 0 = 1.000
|
||||
1.000 sra 1 = 0.100
|
||||
1.000 sra 2 = 0.010
|
||||
1.000 sra 3 = 0.001
|
||||
1.000 sra 4 = 0.000
|
||||
|
||||
1.000 sra 0 = 1.000
|
||||
1.000 sra -1 = 0.000
|
||||
1.000 sra -2 = 0.000
|
||||
1.000 sra -3 = 0.000
|
||||
1.000 sra -4 = 0.000
|
||||
|
||||
Positive sfixed
|
||||
1.000 sla 0 = 1.000
|
||||
1.000 sla 1 = 0.000
|
||||
1.000 sla 2 = 0.000
|
||||
1.000 sla 3 = 0.000
|
||||
1.000 sla 4 = 0.000
|
||||
1.000 sla 5 = 0.000
|
||||
|
||||
1.000 sla 0 = 1.000
|
||||
1.000 sla -1 = 0.100
|
||||
1.000 sla -2 = 0.010
|
||||
1.000 sla -3 = 0.001
|
||||
1.000 sla -4 = 0.000
|
||||
1.000 sla -5 = 0.000
|
||||
|
||||
1.000 sra 0 = 1.000
|
||||
1.000 sra 1 = 0.100
|
||||
1.000 sra 2 = 0.010
|
||||
1.000 sra 3 = 0.001
|
||||
1.000 sra 4 = 0.000
|
||||
1.000 sra 5 = 0.000
|
||||
|
||||
1.000 sra 0 = 1.000
|
||||
1.000 sra -1 = 0.000
|
||||
1.000 sra -2 = 0.000
|
||||
1.000 sra -3 = 0.000
|
||||
1.000 sra -4 = 0.000
|
||||
1.000 sra -5 = 0.000
|
||||
|
||||
Negative sfixed
|
||||
-1.000 sla 0 = -1.000
|
||||
-1.000 sla 1 = -0.000
|
||||
-1.000 sla 2 = -0.000
|
||||
-1.000 sla 3 = -0.000
|
||||
-1.000 sla 4 = 0.000
|
||||
-1.000 sla 5 = 0.000
|
||||
|
||||
-1.000 sla 0 = -1.000
|
||||
-1.000 sla -1 = -0.100
|
||||
-1.000 sla -2 = -0.010
|
||||
-1.000 sla -3 = -0.001
|
||||
-1.000 sla -4 = 0.000
|
||||
-1.000 sla -5 = 0.000
|
||||
|
||||
-1.000 sra 0 = -1.000
|
||||
-1.000 sra 1 = -0.100
|
||||
-1.000 sra 2 = -0.010
|
||||
-1.000 sra 3 = -0.001
|
||||
-1.000 sra 4 = 0.000
|
||||
-1.000 sra 5 = 0.000
|
||||
|
||||
-1.000 sra 0 = -1.000
|
||||
-1.000 sra -1 = -0.000
|
||||
-1.000 sra -2 = -0.000
|
||||
-1.000 sra -3 = -0.000
|
||||
-1.000 sra -4 = 0.000
|
||||
-1.000 sra -5 = 0.000
|
||||
|
||||
Positive ufixed
|
||||
1.001 sla 0 = 1.001
|
||||
1.001 sla 1 = 0.010
|
||||
1.001 sla 2 = 0.100
|
||||
1.001 sla 3 = 1.000
|
||||
1.001 sla 4 = 0.000
|
||||
|
||||
1.001 sla 0 = 1.001
|
||||
1.001 sla -1 = 0.100
|
||||
1.001 sla -2 = 0.010
|
||||
1.001 sla -3 = 0.001
|
||||
1.001 sla -4 = 0.000
|
||||
|
||||
1.001 sra 0 = 1.001
|
||||
1.001 sra 1 = 0.100
|
||||
1.001 sra 2 = 0.010
|
||||
1.001 sra 3 = 0.001
|
||||
1.001 sra 4 = 0.000
|
||||
|
||||
1.001 sra 0 = 1.001
|
||||
1.001 sra -1 = 0.010
|
||||
1.001 sra -2 = 0.100
|
||||
1.001 sra -3 = 1.000
|
||||
1.001 sra -4 = 0.000
|
||||
|
||||
Positive sfixed
|
||||
1.001 sla 0 = 1.001
|
||||
1.001 sla 1 = 0.010
|
||||
1.001 sla 2 = 0.100
|
||||
1.001 sla 3 = 1.000
|
||||
1.001 sla 4 = 0.000
|
||||
1.001 sla 5 = 0.000
|
||||
|
||||
1.001 sla 0 = 1.001
|
||||
1.001 sla -1 = 0.100
|
||||
1.001 sla -2 = 0.010
|
||||
1.001 sla -3 = 0.001
|
||||
1.001 sla -4 = 0.000
|
||||
1.001 sla -5 = 0.000
|
||||
|
||||
1.001 sra 0 = 1.001
|
||||
1.001 sra 1 = 0.100
|
||||
1.001 sra 2 = 0.010
|
||||
1.001 sra 3 = 0.001
|
||||
1.001 sra 4 = 0.000
|
||||
1.001 sra 5 = 0.000
|
||||
|
||||
1.001 sra 0 = 1.001
|
||||
1.001 sra -1 = 0.010
|
||||
1.001 sra -2 = 0.100
|
||||
1.001 sra -3 = 1.000
|
||||
1.001 sra -4 = 0.000
|
||||
1.001 sra -5 = 0.000
|
||||
|
||||
Negative sfixed
|
||||
-1.001 sla 0 = -1.001
|
||||
-1.001 sla 1 = -0.010
|
||||
-1.001 sla 2 = -0.100
|
||||
-1.001 sla 3 = -1.000
|
||||
-1.001 sla 4 = 0.000
|
||||
-1.001 sla 5 = 0.000
|
||||
|
||||
-1.001 sla 0 = -1.001
|
||||
-1.001 sla -1 = -0.100
|
||||
-1.001 sla -2 = -0.010
|
||||
-1.001 sla -3 = -0.001
|
||||
-1.001 sla -4 = 0.000
|
||||
-1.001 sla -5 = 0.000
|
||||
|
||||
-1.001 sra 0 = -1.001
|
||||
-1.001 sra 1 = -0.100
|
||||
-1.001 sra 2 = -0.010
|
||||
-1.001 sra 3 = -0.001
|
||||
-1.001 sra 4 = 0.000
|
||||
-1.001 sra 5 = 0.000
|
||||
|
||||
-1.001 sra 0 = -1.001
|
||||
-1.001 sra -1 = -0.010
|
||||
-1.001 sra -2 = -0.100
|
||||
-1.001 sra -3 = -1.000
|
||||
-1.001 sra -4 = 0.000
|
||||
-1.001 sra -5 = 0.000
|
||||
Positive ufixed
|
||||
U'length = 10
|
||||
U'high(left) = -1(-1)
|
||||
U'low(right) = -10(-10)
|
||||
U'value = B.0100000000
|
||||
U'value = 2.5e-1
|
||||
|
||||
U'length = 10
|
||||
U'high(left) = -1(-1)
|
||||
U'low(right) = -10(-10)
|
||||
U'value = B.0100000000
|
||||
U'value = 2.5e-1
|
||||
|
||||
U'length = 10
|
||||
U'high(left) = -1(-1)
|
||||
U'low(right) = -10(-10)
|
||||
U'value = B.0100000000
|
||||
U'value = 2.5e-1
|
||||
|
||||
U'length = 10
|
||||
U'high(left) = 1(1)
|
||||
U'low(right) = -8(-8)
|
||||
U'value = B00.01000000
|
||||
U'value = 2.5e-1
|
||||
|
||||
U'length = 10
|
||||
U'high(left) = 0(0)
|
||||
U'low(right) = -9(-9)
|
||||
U'value = B0.010000000
|
||||
U'value = 2.5e-1
|
||||
|
||||
U'length = 10
|
||||
U'high(left) = 0(0)
|
||||
U'low(right) = -9(-9)
|
||||
U'value = B0.010000000
|
||||
U'value = 2.5e-1
|
||||
|
||||
Positive sfixed
|
||||
S'length = 10
|
||||
S'high(left) = 0(0)
|
||||
S'low(right) = -9(-9)
|
||||
S'value = B.010000000
|
||||
S'value = 2.5e-1
|
||||
|
||||
S'length = 10
|
||||
S'high(left) = 0(0)
|
||||
S'low(right) = -9(-9)
|
||||
S'value = B.010000000
|
||||
S'value = 2.5e-1
|
||||
|
||||
S'length = 10
|
||||
S'high(left) = 0(0)
|
||||
S'low(right) = -9(-9)
|
||||
S'value = B.010000000
|
||||
S'value = 2.5e-1
|
||||
|
||||
S'length = 10
|
||||
S'high(left) = 2(2)
|
||||
S'low(right) = -7(-7)
|
||||
S'value = B00.0100000
|
||||
S'value = 2.5e-1
|
||||
|
||||
S'length = 10
|
||||
S'high(left) = 1(1)
|
||||
S'low(right) = -8(-8)
|
||||
S'value = B0.01000000
|
||||
S'value = 2.5e-1
|
||||
|
||||
S'length = 10
|
||||
S'high(left) = 1(1)
|
||||
S'low(right) = -8(-8)
|
||||
S'value = B0.01000000
|
||||
S'value = 2.5e-1
|
||||
|
||||
Neg/Pos sfixed
|
||||
S'length = 10
|
||||
S'high(left) = 0(0)
|
||||
S'low(right) = -9(-9)
|
||||
S'value = B-.010000000
|
||||
S'value = -2.5e-1
|
||||
|
||||
S'length = 10
|
||||
S'high(left) = 0(0)
|
||||
S'low(right) = -9(-9)
|
||||
S'value = B-.010000000
|
||||
S'value = -2.5e-1
|
||||
|
||||
S'length = 10
|
||||
S'high(left) = 0(0)
|
||||
S'low(right) = -9(-9)
|
||||
S'value = B-.010000000
|
||||
S'value = -2.5e-1
|
||||
|
||||
S'length = 10
|
||||
S'high(left) = 2(2)
|
||||
S'low(right) = -7(-7)
|
||||
S'value = B-00.0100000
|
||||
S'value = -2.5e-1
|
||||
|
||||
S'length = 10
|
||||
S'high(left) = 1(1)
|
||||
S'low(right) = -8(-8)
|
||||
S'value = B-0.01000000
|
||||
S'value = -2.5e-1
|
||||
|
||||
S'length = 10
|
||||
S'high(left) = 1(1)
|
||||
S'low(right) = -8(-8)
|
||||
S'value = B-0.01000000
|
||||
S'value = -2.5e-1
|
||||
|
||||
Pos/Neg sfixed
|
||||
S'length = 10
|
||||
S'high(left) = 0(0)
|
||||
S'low(right) = -9(-9)
|
||||
S'value = B-.010000000
|
||||
S'value = -2.5e-1
|
||||
|
||||
S'length = 10
|
||||
S'high(left) = 0(0)
|
||||
S'low(right) = -9(-9)
|
||||
S'value = B-.010000000
|
||||
S'value = -2.5e-1
|
||||
|
||||
S'length = 10
|
||||
S'high(left) = 0(0)
|
||||
S'low(right) = -9(-9)
|
||||
S'value = B-.010000000
|
||||
S'value = -2.5e-1
|
||||
|
||||
S'length = 10
|
||||
S'high(left) = 2(2)
|
||||
S'low(right) = -7(-7)
|
||||
S'value = B-00.0100000
|
||||
S'value = -2.5e-1
|
||||
|
||||
S'length = 10
|
||||
S'high(left) = 1(1)
|
||||
S'low(right) = -8(-8)
|
||||
S'value = B-0.01000000
|
||||
S'value = -2.5e-1
|
||||
|
||||
S'length = 10
|
||||
S'high(left) = 1(1)
|
||||
S'low(right) = -8(-8)
|
||||
S'value = B-0.01000000
|
||||
S'value = -2.5e-1
|
||||
|
||||
Neg/Neg sfixed
|
||||
S'length = 10
|
||||
S'high(left) = 0(0)
|
||||
S'low(right) = -9(-9)
|
||||
S'value = B.010000000
|
||||
S'value = 2.5e-1
|
||||
|
||||
S'length = 10
|
||||
S'high(left) = 0(0)
|
||||
S'low(right) = -9(-9)
|
||||
S'value = B.010000000
|
||||
S'value = 2.5e-1
|
||||
|
||||
S'length = 10
|
||||
S'high(left) = 0(0)
|
||||
S'low(right) = -9(-9)
|
||||
S'value = B.010000000
|
||||
S'value = 2.5e-1
|
||||
|
||||
S'length = 10
|
||||
S'high(left) = 2(2)
|
||||
S'low(right) = -7(-7)
|
||||
S'value = B00.0100000
|
||||
S'value = 2.5e-1
|
||||
|
||||
S'length = 10
|
||||
S'high(left) = 1(1)
|
||||
S'low(right) = -8(-8)
|
||||
S'value = B0.01000000
|
||||
S'value = 2.5e-1
|
||||
|
||||
S'length = 10
|
||||
S'high(left) = 1(1)
|
||||
S'low(right) = -8(-8)
|
||||
S'value = B0.01000000
|
||||
S'value = 2.5e-1
|
||||
|
||||
Test 1.1001000:
|
||||
Test 1.100100:
|
||||
Test -1.100100:
|
||||
Test 00.011001:
|
||||
Test 00.01100:
|
||||
Test -00.01100:
|
||||
Integer Test 00.00000:
|
||||
R: Bit 11.110010:
|
||||
U: Bit 11.110010:
|
||||
S: Bit 11.110010:
|
||||
S: Bit 00.001110:
|
||||
S: Bit 3.50:
|
||||
S: Bit -242:
|
||||
S1'length = 130
|
||||
S1'high(left) = 13(13)
|
||||
S1'low(right) = -116(-116)
|
||||
S1'value = B0111101010101.01100010110111010011100101101101011111010101101000110100101010101010111011010000111011000110000101000001010010100111
|
||||
S1'value = 3.925386188115339e3
|
||||
|
||||
S2'length = 130
|
||||
S2'high(left) = 13(13)
|
||||
S2'low(right) = -116(-116)
|
||||
S2'value = B0010110111011.11100001100111000100101000110101111111101101000100001110010011100111000110110110010100101001010010100111100011000010
|
||||
S2'value = 1.467881291044409e3
|
||||
|
||||
R1'length = 260
|
||||
R1'high(left) = 26(26)
|
||||
R1'low(right) = -233(-233)
|
||||
R1'value = B00010101111110101111010000.11110010000101101010111100111010001101011101111110010111000100110100001101100001011110100000111111111110100001011011101000011010000101001110100001100100111111111100101000111011011011111100111000001011001111000010101111101110100011100
|
||||
R1'value = 5.762000945658637e6
|
||||
|
||||
@@ -0,0 +1,89 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 00:28:57 07/10/2006
|
||||
-- Design Name:
|
||||
-- Module Name: adder_registered - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
use IEEE.MATH_REAL.ALL;
|
||||
use std.textio.all; -- Imports the standard textio package.
|
||||
|
||||
library work;
|
||||
use work.fixed_ja.all;
|
||||
|
||||
---- Uncomment the following library declaration if instantiating
|
||||
---- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity eval_fixed_ja is
|
||||
Generic (
|
||||
nbits : integer := 32;
|
||||
nbits_int : integer := 2);
|
||||
end eval_fixed_ja;
|
||||
|
||||
architecture Behavioral of eval_fixed_ja is
|
||||
---------------------------------------------------------------------
|
||||
|
||||
type my_range is range 0 downto -10;
|
||||
|
||||
begin
|
||||
|
||||
process
|
||||
constant c1 : ufixed_t (0 downto -10) := "11111111000";
|
||||
constant c2 : ufixed_t := to_ufixed(3.141592654, nbits, 4);
|
||||
constant c3 : ufixed_t := to_ufixed(1.0/3.141592654, nbits, 1);
|
||||
variable t1 : ufixed_t (uproto(8,1)'range);
|
||||
variable L : line;
|
||||
|
||||
variable slv : string (15 downto 1) := (others => '-');
|
||||
constant jens : string (10 downto 7) := "JENS";
|
||||
|
||||
|
||||
begin
|
||||
|
||||
|
||||
-- slv := (1 => '1', 2 => 'J', jens'range => jens(jens'range), others => '1');
|
||||
|
||||
slv(jens'range) := "Jens";
|
||||
slv(jens'range) := jens;
|
||||
|
||||
print_info(c2, "c2");
|
||||
print_info(c3, "c3");
|
||||
|
||||
t1 := to_ufixed(c1, t1, round_to_zero, saturate);
|
||||
print_info(c1, "c1");
|
||||
print_info(t1, "t1");
|
||||
|
||||
t1 := to_ufixed(c1, t1, round_half_up, saturate);
|
||||
print_info(c1, "c1");
|
||||
print_info(t1, "t1");
|
||||
|
||||
print_info(to_ufixed(c2*c2, 32, 2, none, saturate), "c2*c2");
|
||||
print_info(to_ufixed(c2*c3, 32, 0, round_half_up, none), "c2*c3");
|
||||
|
||||
write (L, slv);
|
||||
writeline (output, L);
|
||||
|
||||
wait;
|
||||
end process;
|
||||
|
||||
---------------------------------------------------------------------
|
||||
end Behavioral;
|
||||
|
||||
@@ -0,0 +1,80 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 00:28:57 07/10/2006
|
||||
-- Design Name:
|
||||
-- Module Name: adder_registered - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library ieee_proposed;
|
||||
use ieee_proposed.fixed_pkg.all;
|
||||
use std.textio.all; -- Imports the standard textio package.
|
||||
|
||||
library work;
|
||||
|
||||
---- Uncomment the following library declaration if instantiating
|
||||
---- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity eval_fixed_ja is
|
||||
Generic (
|
||||
nbits : integer := 8;
|
||||
nbits_int : integer := 0
|
||||
);
|
||||
Port
|
||||
(
|
||||
srst : in std_logic;
|
||||
clk : in std_logic;
|
||||
di1 : in std_logic_vector(nbits-1 downto 0);
|
||||
di2 : in std_logic_vector(nbits-1 downto 0);
|
||||
in_valid : in std_logic;
|
||||
do : out std_logic_vector(nbits-1 downto 0);
|
||||
out_valid : out std_logic
|
||||
);
|
||||
|
||||
end eval_fixed_ja;
|
||||
|
||||
architecture Behavioral of eval_fixed_ja is
|
||||
signal op1, op2 : sfixed(nbits_int downto -(nbits-1));
|
||||
signal result : sfixed(2*nbits_int downto -(2*nbits-1));
|
||||
begin
|
||||
|
||||
op1 <= to_sfixed(di1, op1);
|
||||
op2 <= to_sfixed(di2, op2);
|
||||
|
||||
do <= to_slv(resize(result, op1, false, false));
|
||||
|
||||
---------------------------------------------------------------------
|
||||
process(srst, clk, in_valid, di1, di2)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if srst = '1' then
|
||||
result <= (others => '0');
|
||||
elsif in_valid = '1' then
|
||||
result <= op1 * op2;
|
||||
end if;
|
||||
out_valid <= in_valid;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
---------------------------------------------------------------------
|
||||
end Behavioral;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,104 @@
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 20:01:25 05/22/2007
|
||||
-- Design Name: eval_fixed_ja
|
||||
-- Module Name: H:/vhdl/projects/eval_fixed_ja/ise/tb_eval_fixed_ja.vhd
|
||||
-- Project Name: eval_fixed
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- VHDL Test Bench Created by ISE for module: eval_fixed_ja
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
-- Notes:
|
||||
-- This testbench has been automatically generated using types std_logic and
|
||||
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
|
||||
-- that these types always be used for the top-level I/O of a design in order
|
||||
-- to guarantee that the testbench will bind correctly to the post-implementation
|
||||
-- simulation model.
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.std_logic_unsigned.all;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY tb_eval_fixed_ja_vhd IS
|
||||
END tb_eval_fixed_ja_vhd;
|
||||
|
||||
ARCHITECTURE behavior OF tb_eval_fixed_ja_vhd IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
COMPONENT eval_fixed_ja
|
||||
PORT(
|
||||
srst : IN std_logic;
|
||||
clk : IN std_logic;
|
||||
di1 : IN std_logic_vector(7 downto 0);
|
||||
di2 : IN std_logic_vector(7 downto 0);
|
||||
in_valid : IN std_logic;
|
||||
do : OUT std_logic_vector(7 downto 0);
|
||||
out_valid : OUT std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--Inputs
|
||||
SIGNAL srst : std_logic := '1';
|
||||
SIGNAL clk : std_logic := '0';
|
||||
SIGNAL in_valid : std_logic := '0';
|
||||
SIGNAL di1 : std_logic_vector(7 downto 0) := (others=>'0');
|
||||
SIGNAL di2 : std_logic_vector(7 downto 0) := (others=>'0');
|
||||
|
||||
--Outputs
|
||||
SIGNAL do : std_logic_vector(7 downto 0);
|
||||
SIGNAL out_valid : std_logic;
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: eval_fixed_ja PORT MAP(
|
||||
srst => srst,
|
||||
clk => clk,
|
||||
di1 => di1,
|
||||
di2 => di2,
|
||||
in_valid => in_valid,
|
||||
do => do,
|
||||
out_valid => out_valid
|
||||
);
|
||||
|
||||
clk_gen : PROCESS
|
||||
BEGIN
|
||||
wait for 10 ns;
|
||||
clk <= not clk;
|
||||
END PROCESS;
|
||||
|
||||
tb : PROCESS
|
||||
BEGIN
|
||||
|
||||
-- Wait 100 ns for global reset to finish
|
||||
wait for 100 ns;
|
||||
srst <= '0';
|
||||
di1 <= X"40";
|
||||
di2 <= X"20";
|
||||
|
||||
wait for 20 ns;
|
||||
wait until rising_edge(clk);
|
||||
in_valid <= '1';
|
||||
wait until rising_edge(clk);
|
||||
in_valid <= '0';
|
||||
wait for 20 ns;
|
||||
|
||||
|
||||
-- Place stimulus here
|
||||
|
||||
wait; -- will wait forever
|
||||
END PROCESS;
|
||||
|
||||
END;
|
||||
@@ -0,0 +1,512 @@
|
||||
-1.992188e+000 0.000000e+000
|
||||
-1.984375e+000 0.000000e+000
|
||||
-1.976563e+000 0.000000e+000
|
||||
-1.968750e+000 0.000000e+000
|
||||
-1.960938e+000 -9.375000e-001
|
||||
-1.953125e+000 -9.375000e-001
|
||||
-1.945313e+000 -9.375000e-001
|
||||
-1.937500e+000 -9.375000e-001
|
||||
-1.929688e+000 -9.375000e-001
|
||||
-1.921875e+000 -9.375000e-001
|
||||
-1.914063e+000 -9.375000e-001
|
||||
-1.906250e+000 -9.375000e-001
|
||||
-1.898438e+000 -9.375000e-001
|
||||
-1.890625e+000 -9.375000e-001
|
||||
-1.882813e+000 -9.375000e-001
|
||||
-1.875000e+000 -9.375000e-001
|
||||
-1.867188e+000 -9.375000e-001
|
||||
-1.859375e+000 -9.375000e-001
|
||||
-1.851563e+000 -9.375000e-001
|
||||
-1.843750e+000 -9.375000e-001
|
||||
-1.835938e+000 -9.375000e-001
|
||||
-1.828125e+000 -9.375000e-001
|
||||
-1.820313e+000 -9.375000e-001
|
||||
-1.812500e+000 -9.375000e-001
|
||||
-1.804688e+000 -9.375000e-001
|
||||
-1.796875e+000 -9.375000e-001
|
||||
-1.789063e+000 -9.375000e-001
|
||||
-1.781250e+000 -9.375000e-001
|
||||
-1.773438e+000 -9.375000e-001
|
||||
-1.765625e+000 -9.375000e-001
|
||||
-1.757813e+000 -9.375000e-001
|
||||
-1.750000e+000 -9.375000e-001
|
||||
-1.742188e+000 -9.375000e-001
|
||||
-1.734375e+000 -9.375000e-001
|
||||
-1.726563e+000 -9.375000e-001
|
||||
-1.718750e+000 -9.375000e-001
|
||||
-1.710938e+000 -9.375000e-001
|
||||
-1.703125e+000 -9.375000e-001
|
||||
-1.695313e+000 -9.375000e-001
|
||||
-1.687500e+000 -9.375000e-001
|
||||
-1.679688e+000 -9.375000e-001
|
||||
-1.671875e+000 -9.375000e-001
|
||||
-1.664063e+000 -9.375000e-001
|
||||
-1.656250e+000 -9.375000e-001
|
||||
-1.648438e+000 -9.375000e-001
|
||||
-1.640625e+000 -9.375000e-001
|
||||
-1.632813e+000 -9.375000e-001
|
||||
-1.625000e+000 -9.375000e-001
|
||||
-1.617188e+000 -9.375000e-001
|
||||
-1.609375e+000 -9.375000e-001
|
||||
-1.601563e+000 -9.375000e-001
|
||||
-1.593750e+000 -9.375000e-001
|
||||
-1.585938e+000 -9.375000e-001
|
||||
-1.578125e+000 -9.375000e-001
|
||||
-1.570313e+000 -9.375000e-001
|
||||
-1.562500e+000 -9.375000e-001
|
||||
-1.554688e+000 -9.375000e-001
|
||||
-1.546875e+000 -9.375000e-001
|
||||
-1.539063e+000 -9.375000e-001
|
||||
-1.531250e+000 -9.375000e-001
|
||||
-1.523438e+000 -9.375000e-001
|
||||
-1.515625e+000 -9.375000e-001
|
||||
-1.507813e+000 -9.375000e-001
|
||||
-1.500000e+000 -9.375000e-001
|
||||
-1.492188e+000 -9.375000e-001
|
||||
-1.484375e+000 -9.375000e-001
|
||||
-1.476563e+000 -9.375000e-001
|
||||
-1.468750e+000 -9.375000e-001
|
||||
-1.460938e+000 -9.375000e-001
|
||||
-1.453125e+000 -9.375000e-001
|
||||
-1.445313e+000 -9.375000e-001
|
||||
-1.437500e+000 -9.375000e-001
|
||||
-1.429688e+000 -9.375000e-001
|
||||
-1.421875e+000 -9.375000e-001
|
||||
-1.414063e+000 -9.375000e-001
|
||||
-1.406250e+000 -9.375000e-001
|
||||
-1.398438e+000 -9.375000e-001
|
||||
-1.390625e+000 -9.375000e-001
|
||||
-1.382813e+000 -9.375000e-001
|
||||
-1.375000e+000 -9.375000e-001
|
||||
-1.367188e+000 -9.375000e-001
|
||||
-1.359375e+000 -9.375000e-001
|
||||
-1.351563e+000 -9.375000e-001
|
||||
-1.343750e+000 -9.375000e-001
|
||||
-1.335938e+000 -9.375000e-001
|
||||
-1.328125e+000 -9.375000e-001
|
||||
-1.320313e+000 -9.375000e-001
|
||||
-1.312500e+000 -9.375000e-001
|
||||
-1.304688e+000 -9.375000e-001
|
||||
-1.296875e+000 -9.375000e-001
|
||||
-1.289063e+000 -9.375000e-001
|
||||
-1.281250e+000 -9.375000e-001
|
||||
-1.273438e+000 -9.375000e-001
|
||||
-1.265625e+000 -9.375000e-001
|
||||
-1.257813e+000 -9.375000e-001
|
||||
-1.250000e+000 -9.375000e-001
|
||||
-1.242188e+000 -9.375000e-001
|
||||
-1.234375e+000 -9.375000e-001
|
||||
-1.226563e+000 -9.375000e-001
|
||||
-1.218750e+000 -9.375000e-001
|
||||
-1.210938e+000 -9.375000e-001
|
||||
-1.203125e+000 -9.375000e-001
|
||||
-1.195313e+000 -9.375000e-001
|
||||
-1.187500e+000 -9.375000e-001
|
||||
-1.179688e+000 -9.375000e-001
|
||||
-1.171875e+000 -9.375000e-001
|
||||
-1.164063e+000 -9.375000e-001
|
||||
-1.156250e+000 -9.375000e-001
|
||||
-1.148438e+000 -9.375000e-001
|
||||
-1.140625e+000 -9.375000e-001
|
||||
-1.132813e+000 -9.375000e-001
|
||||
-1.125000e+000 -9.375000e-001
|
||||
-1.117188e+000 -9.375000e-001
|
||||
-1.109375e+000 -9.375000e-001
|
||||
-1.101563e+000 -9.375000e-001
|
||||
-1.093750e+000 -9.375000e-001
|
||||
-1.085938e+000 -9.375000e-001
|
||||
-1.078125e+000 -9.375000e-001
|
||||
-1.070313e+000 -9.375000e-001
|
||||
-1.062500e+000 -9.375000e-001
|
||||
-1.054688e+000 -9.375000e-001
|
||||
-1.046875e+000 -9.375000e-001
|
||||
-1.039063e+000 -9.375000e-001
|
||||
-1.031250e+000 -9.375000e-001
|
||||
-1.023438e+000 -9.375000e-001
|
||||
-1.015625e+000 -9.375000e-001
|
||||
-1.007813e+000 -9.375000e-001
|
||||
-1.000000e+000 -9.375000e-001
|
||||
-9.921875e-001 -9.375000e-001
|
||||
-9.843750e-001 -9.375000e-001
|
||||
-9.765625e-001 -9.375000e-001
|
||||
-9.687500e-001 -9.375000e-001
|
||||
-9.609375e-001 -9.375000e-001
|
||||
-9.531250e-001 -9.375000e-001
|
||||
-9.453125e-001 -9.375000e-001
|
||||
-9.375000e-001 -9.375000e-001
|
||||
-9.296875e-001 -9.375000e-001
|
||||
-9.218750e-001 -9.375000e-001
|
||||
-9.140625e-001 -9.375000e-001
|
||||
-9.062500e-001 -9.375000e-001
|
||||
-8.984375e-001 -8.750000e-001
|
||||
-8.906250e-001 -8.750000e-001
|
||||
-8.828125e-001 -8.750000e-001
|
||||
-8.750000e-001 -8.750000e-001
|
||||
-8.671875e-001 -8.750000e-001
|
||||
-8.593750e-001 -8.750000e-001
|
||||
-8.515625e-001 -8.750000e-001
|
||||
-8.437500e-001 -8.750000e-001
|
||||
-8.359375e-001 -8.125000e-001
|
||||
-8.281250e-001 -8.125000e-001
|
||||
-8.203125e-001 -8.125000e-001
|
||||
-8.125000e-001 -8.125000e-001
|
||||
-8.046875e-001 -8.125000e-001
|
||||
-7.968750e-001 -8.125000e-001
|
||||
-7.890625e-001 -8.125000e-001
|
||||
-7.812500e-001 -8.125000e-001
|
||||
-7.734375e-001 -7.500000e-001
|
||||
-7.656250e-001 -7.500000e-001
|
||||
-7.578125e-001 -7.500000e-001
|
||||
-7.500000e-001 -7.500000e-001
|
||||
-7.421875e-001 -7.500000e-001
|
||||
-7.343750e-001 -7.500000e-001
|
||||
-7.265625e-001 -7.500000e-001
|
||||
-7.187500e-001 -7.500000e-001
|
||||
-7.109375e-001 -6.875000e-001
|
||||
-7.031250e-001 -6.875000e-001
|
||||
-6.953125e-001 -6.875000e-001
|
||||
-6.875000e-001 -6.875000e-001
|
||||
-6.796875e-001 -6.875000e-001
|
||||
-6.718750e-001 -6.875000e-001
|
||||
-6.640625e-001 -6.875000e-001
|
||||
-6.562500e-001 -6.875000e-001
|
||||
-6.484375e-001 -6.250000e-001
|
||||
-6.406250e-001 -6.250000e-001
|
||||
-6.328125e-001 -6.250000e-001
|
||||
-6.250000e-001 -6.250000e-001
|
||||
-6.171875e-001 -6.250000e-001
|
||||
-6.093750e-001 -6.250000e-001
|
||||
-6.015625e-001 -6.250000e-001
|
||||
-5.937500e-001 -6.250000e-001
|
||||
-5.859375e-001 -5.625000e-001
|
||||
-5.781250e-001 -5.625000e-001
|
||||
-5.703125e-001 -5.625000e-001
|
||||
-5.625000e-001 -5.625000e-001
|
||||
-5.546875e-001 -5.625000e-001
|
||||
-5.468750e-001 -5.625000e-001
|
||||
-5.390625e-001 -5.625000e-001
|
||||
-5.312500e-001 -5.625000e-001
|
||||
-5.234375e-001 -5.000000e-001
|
||||
-5.156250e-001 -5.000000e-001
|
||||
-5.078125e-001 -5.000000e-001
|
||||
-5.000000e-001 -5.000000e-001
|
||||
-4.921875e-001 -5.000000e-001
|
||||
-4.843750e-001 -5.000000e-001
|
||||
-4.765625e-001 -5.000000e-001
|
||||
-4.687500e-001 -5.000000e-001
|
||||
-4.609375e-001 -4.375000e-001
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||||
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|
||||
2.187500e-001 2.500000e-001
|
||||
2.265625e-001 2.500000e-001
|
||||
2.343750e-001 2.500000e-001
|
||||
2.421875e-001 2.500000e-001
|
||||
2.500000e-001 2.500000e-001
|
||||
2.578125e-001 2.500000e-001
|
||||
2.656250e-001 2.500000e-001
|
||||
2.734375e-001 2.500000e-001
|
||||
2.812500e-001 3.125000e-001
|
||||
2.890625e-001 3.125000e-001
|
||||
2.968750e-001 3.125000e-001
|
||||
3.046875e-001 3.125000e-001
|
||||
3.125000e-001 3.125000e-001
|
||||
3.203125e-001 3.125000e-001
|
||||
3.281250e-001 3.125000e-001
|
||||
3.359375e-001 3.125000e-001
|
||||
3.437500e-001 3.750000e-001
|
||||
3.515625e-001 3.750000e-001
|
||||
3.593750e-001 3.750000e-001
|
||||
3.671875e-001 3.750000e-001
|
||||
3.750000e-001 3.750000e-001
|
||||
3.828125e-001 3.750000e-001
|
||||
3.906250e-001 3.750000e-001
|
||||
3.984375e-001 3.750000e-001
|
||||
4.062500e-001 4.375000e-001
|
||||
4.140625e-001 4.375000e-001
|
||||
4.218750e-001 4.375000e-001
|
||||
4.296875e-001 4.375000e-001
|
||||
4.375000e-001 4.375000e-001
|
||||
4.453125e-001 4.375000e-001
|
||||
4.531250e-001 4.375000e-001
|
||||
4.609375e-001 4.375000e-001
|
||||
4.687500e-001 5.000000e-001
|
||||
4.765625e-001 5.000000e-001
|
||||
4.843750e-001 5.000000e-001
|
||||
4.921875e-001 5.000000e-001
|
||||
5.000000e-001 5.000000e-001
|
||||
5.078125e-001 5.000000e-001
|
||||
5.156250e-001 5.000000e-001
|
||||
5.234375e-001 5.000000e-001
|
||||
5.312500e-001 5.625000e-001
|
||||
5.390625e-001 5.625000e-001
|
||||
5.468750e-001 5.625000e-001
|
||||
5.546875e-001 5.625000e-001
|
||||
5.625000e-001 5.625000e-001
|
||||
5.703125e-001 5.625000e-001
|
||||
5.781250e-001 5.625000e-001
|
||||
5.859375e-001 5.625000e-001
|
||||
5.937500e-001 6.250000e-001
|
||||
6.015625e-001 6.250000e-001
|
||||
6.093750e-001 6.250000e-001
|
||||
6.171875e-001 6.250000e-001
|
||||
6.250000e-001 6.250000e-001
|
||||
6.328125e-001 6.250000e-001
|
||||
6.406250e-001 6.250000e-001
|
||||
6.484375e-001 6.250000e-001
|
||||
6.562500e-001 6.875000e-001
|
||||
6.640625e-001 6.875000e-001
|
||||
6.718750e-001 6.875000e-001
|
||||
6.796875e-001 6.875000e-001
|
||||
6.875000e-001 6.875000e-001
|
||||
6.953125e-001 6.875000e-001
|
||||
7.031250e-001 6.875000e-001
|
||||
7.109375e-001 6.875000e-001
|
||||
7.187500e-001 7.500000e-001
|
||||
7.265625e-001 7.500000e-001
|
||||
7.343750e-001 7.500000e-001
|
||||
7.421875e-001 7.500000e-001
|
||||
7.500000e-001 7.500000e-001
|
||||
7.578125e-001 7.500000e-001
|
||||
7.656250e-001 7.500000e-001
|
||||
7.734375e-001 7.500000e-001
|
||||
7.812500e-001 8.125000e-001
|
||||
7.890625e-001 8.125000e-001
|
||||
7.968750e-001 8.125000e-001
|
||||
8.046875e-001 8.125000e-001
|
||||
8.125000e-001 8.125000e-001
|
||||
8.203125e-001 8.125000e-001
|
||||
8.281250e-001 8.125000e-001
|
||||
8.359375e-001 8.125000e-001
|
||||
8.437500e-001 8.750000e-001
|
||||
8.515625e-001 8.750000e-001
|
||||
8.593750e-001 8.750000e-001
|
||||
8.671875e-001 8.750000e-001
|
||||
8.750000e-001 8.750000e-001
|
||||
8.828125e-001 8.750000e-001
|
||||
8.906250e-001 8.750000e-001
|
||||
8.984375e-001 8.750000e-001
|
||||
9.062500e-001 9.375000e-001
|
||||
9.140625e-001 9.375000e-001
|
||||
9.218750e-001 9.375000e-001
|
||||
9.296875e-001 9.375000e-001
|
||||
9.375000e-001 9.375000e-001
|
||||
9.453125e-001 9.375000e-001
|
||||
9.531250e-001 9.375000e-001
|
||||
9.609375e-001 9.375000e-001
|
||||
9.687500e-001 9.375000e-001
|
||||
9.765625e-001 9.375000e-001
|
||||
9.843750e-001 9.375000e-001
|
||||
9.921875e-001 9.375000e-001
|
||||
1.000000e+000 9.375000e-001
|
||||
1.007813e+000 9.375000e-001
|
||||
1.015625e+000 9.375000e-001
|
||||
1.023438e+000 9.375000e-001
|
||||
1.031250e+000 9.375000e-001
|
||||
1.039063e+000 9.375000e-001
|
||||
1.046875e+000 9.375000e-001
|
||||
1.054688e+000 9.375000e-001
|
||||
1.062500e+000 9.375000e-001
|
||||
1.070313e+000 9.375000e-001
|
||||
1.078125e+000 9.375000e-001
|
||||
1.085938e+000 9.375000e-001
|
||||
1.093750e+000 9.375000e-001
|
||||
1.101563e+000 9.375000e-001
|
||||
1.109375e+000 9.375000e-001
|
||||
1.117188e+000 9.375000e-001
|
||||
1.125000e+000 9.375000e-001
|
||||
1.132813e+000 9.375000e-001
|
||||
1.140625e+000 9.375000e-001
|
||||
1.148438e+000 9.375000e-001
|
||||
1.156250e+000 9.375000e-001
|
||||
1.164063e+000 9.375000e-001
|
||||
1.171875e+000 9.375000e-001
|
||||
1.179688e+000 9.375000e-001
|
||||
1.187500e+000 9.375000e-001
|
||||
1.195313e+000 9.375000e-001
|
||||
1.203125e+000 9.375000e-001
|
||||
1.210938e+000 9.375000e-001
|
||||
1.218750e+000 9.375000e-001
|
||||
1.226563e+000 9.375000e-001
|
||||
1.234375e+000 9.375000e-001
|
||||
1.242188e+000 9.375000e-001
|
||||
1.250000e+000 9.375000e-001
|
||||
1.257813e+000 9.375000e-001
|
||||
1.265625e+000 9.375000e-001
|
||||
1.273438e+000 9.375000e-001
|
||||
1.281250e+000 9.375000e-001
|
||||
1.289063e+000 9.375000e-001
|
||||
1.296875e+000 9.375000e-001
|
||||
1.304688e+000 9.375000e-001
|
||||
1.312500e+000 9.375000e-001
|
||||
1.320313e+000 9.375000e-001
|
||||
1.328125e+000 9.375000e-001
|
||||
1.335938e+000 9.375000e-001
|
||||
1.343750e+000 9.375000e-001
|
||||
1.351563e+000 9.375000e-001
|
||||
1.359375e+000 9.375000e-001
|
||||
1.367188e+000 9.375000e-001
|
||||
1.375000e+000 9.375000e-001
|
||||
1.382813e+000 9.375000e-001
|
||||
1.390625e+000 9.375000e-001
|
||||
1.398438e+000 9.375000e-001
|
||||
1.406250e+000 9.375000e-001
|
||||
1.414063e+000 9.375000e-001
|
||||
1.421875e+000 9.375000e-001
|
||||
1.429688e+000 9.375000e-001
|
||||
1.437500e+000 9.375000e-001
|
||||
1.445313e+000 9.375000e-001
|
||||
1.453125e+000 9.375000e-001
|
||||
1.460938e+000 9.375000e-001
|
||||
1.468750e+000 9.375000e-001
|
||||
1.476563e+000 9.375000e-001
|
||||
1.484375e+000 9.375000e-001
|
||||
1.492188e+000 9.375000e-001
|
||||
1.500000e+000 9.375000e-001
|
||||
1.507813e+000 9.375000e-001
|
||||
1.515625e+000 9.375000e-001
|
||||
1.523438e+000 9.375000e-001
|
||||
1.531250e+000 9.375000e-001
|
||||
1.539063e+000 9.375000e-001
|
||||
1.546875e+000 9.375000e-001
|
||||
1.554688e+000 9.375000e-001
|
||||
1.562500e+000 9.375000e-001
|
||||
1.570313e+000 9.375000e-001
|
||||
1.578125e+000 9.375000e-001
|
||||
1.585938e+000 9.375000e-001
|
||||
1.593750e+000 9.375000e-001
|
||||
1.601563e+000 9.375000e-001
|
||||
1.609375e+000 9.375000e-001
|
||||
1.617188e+000 9.375000e-001
|
||||
1.625000e+000 9.375000e-001
|
||||
1.632813e+000 9.375000e-001
|
||||
1.640625e+000 9.375000e-001
|
||||
1.648438e+000 9.375000e-001
|
||||
1.656250e+000 9.375000e-001
|
||||
1.664063e+000 9.375000e-001
|
||||
1.671875e+000 9.375000e-001
|
||||
1.679688e+000 9.375000e-001
|
||||
1.687500e+000 9.375000e-001
|
||||
1.695313e+000 9.375000e-001
|
||||
1.703125e+000 9.375000e-001
|
||||
1.710938e+000 9.375000e-001
|
||||
1.718750e+000 9.375000e-001
|
||||
1.726563e+000 9.375000e-001
|
||||
1.734375e+000 9.375000e-001
|
||||
1.742188e+000 9.375000e-001
|
||||
1.750000e+000 9.375000e-001
|
||||
1.757813e+000 9.375000e-001
|
||||
1.765625e+000 9.375000e-001
|
||||
1.773438e+000 9.375000e-001
|
||||
1.781250e+000 9.375000e-001
|
||||
1.789063e+000 9.375000e-001
|
||||
1.796875e+000 9.375000e-001
|
||||
1.804688e+000 9.375000e-001
|
||||
1.812500e+000 9.375000e-001
|
||||
1.820313e+000 9.375000e-001
|
||||
1.828125e+000 9.375000e-001
|
||||
1.835938e+000 9.375000e-001
|
||||
1.843750e+000 9.375000e-001
|
||||
1.851563e+000 9.375000e-001
|
||||
1.859375e+000 9.375000e-001
|
||||
1.867188e+000 9.375000e-001
|
||||
1.875000e+000 9.375000e-001
|
||||
1.882813e+000 9.375000e-001
|
||||
1.890625e+000 9.375000e-001
|
||||
1.898438e+000 9.375000e-001
|
||||
1.906250e+000 9.375000e-001
|
||||
1.914063e+000 9.375000e-001
|
||||
1.921875e+000 9.375000e-001
|
||||
1.929688e+000 9.375000e-001
|
||||
1.937500e+000 9.375000e-001
|
||||
1.945313e+000 9.375000e-001
|
||||
1.953125e+000 9.375000e-001
|
||||
1.960938e+000 9.375000e-001
|
||||
1.968750e+000 9.375000e-001
|
||||
1.976563e+000 9.375000e-001
|
||||
1.984375e+000 9.375000e-001
|
||||
1.992188e+000 9.375000e-001
|
||||
@@ -0,0 +1,12 @@
|
||||
vlib work
|
||||
vcom -explicit -93 "../../lib/src/fixed_ja/fixed_ja.vhd"
|
||||
vcom -explicit -93 "../../lib/src/fixed_ja/fixed_ja_body.vhd"
|
||||
vcom -explicit -93 "../../lib/src/PCK_FIO-2002.7/PCK_FIO_1993.vhd"
|
||||
vcom -explicit -93 "../../lib/src/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
|
||||
vcom -explicit -93 "src/tb_eval_fixed_ja.vhd"
|
||||
vsim -t 1ps -lib work tb_eval_fixed_ja
|
||||
#do {wave.do}
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
run 1000ns
|
||||
@@ -0,0 +1,14 @@
|
||||
% Read data
|
||||
[xu,yu] = TEXTREAD('sum_test_u.txt');
|
||||
[xs,ys] = TEXTREAD('sum_test_s.txt');
|
||||
|
||||
|
||||
close all;
|
||||
|
||||
plot(0:length(xu)-1, xu, 0:length(yu)-1, yu);
|
||||
grid;
|
||||
|
||||
figure;
|
||||
|
||||
plot(0:length(xs)-1, xs, 0:length(ys)-1, ys);
|
||||
grid;
|
||||
Binary file not shown.
@@ -0,0 +1,43 @@
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
package fifo_ctrl_pkg is
|
||||
|
||||
-- Constants
|
||||
-- Types
|
||||
|
||||
-- Functions
|
||||
function bin2gray(xb : unsigned) return unsigned;
|
||||
function gray2bin(xg : unsigned) return unsigned;
|
||||
|
||||
end fifo_ctrl_pkg;
|
||||
|
||||
package body fifo_ctrl_pkg is
|
||||
|
||||
function bin2gray(xb : unsigned) return unsigned is
|
||||
variable xg : unsigned(xb'left downto xb'right);
|
||||
begin
|
||||
|
||||
xg(xg'left) := xb(xb'left);
|
||||
for i in 1 to xb'left loop
|
||||
xg(xg'left-i) := xb(xb'left-i+1) xor xb(xb'left-i);
|
||||
end loop;
|
||||
|
||||
return xg;
|
||||
end bin2gray;
|
||||
|
||||
function gray2bin(xg : unsigned) return unsigned is
|
||||
variable xb : unsigned(xg'left downto xg'right);
|
||||
begin
|
||||
|
||||
xb(xb'left) := xg(xg'left);
|
||||
for i in 1 to xg'left loop
|
||||
xb(xb'left-i) := xb(xb'left-i+1) xor xg(xg'left-i);
|
||||
end loop;
|
||||
|
||||
return xb;
|
||||
end gray2bin;
|
||||
|
||||
end fifo_ctrl_pkg;
|
||||
|
||||
@@ -0,0 +1 @@
|
||||
work
|
||||
@@ -0,0 +1,3 @@
|
||||
vhdl work "fifo_ctrl_pkg.vhd"
|
||||
vhdl work "../../lib/FIFO/src/gray_counter.vhd"
|
||||
vhdl work "top.vhd"
|
||||
@@ -0,0 +1,60 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 15:55:59 09/18/2007
|
||||
-- Design Name:
|
||||
-- Module Name: top - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
---- Uncomment the following library declaration if instantiating
|
||||
---- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
LIBRARY WORK;
|
||||
USE WORK.FIFO_CTRL_PKG.ALL;
|
||||
|
||||
entity top is
|
||||
Port ( rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
gcnt : out unsigned (13 downto 0);
|
||||
bcnt : out unsigned (13 downto 0);
|
||||
gnxt : out unsigned (13 downto 0);
|
||||
bnxt : out unsigned (13 downto 0)
|
||||
);
|
||||
end top;
|
||||
|
||||
architecture Behavioral of top is
|
||||
|
||||
begin
|
||||
|
||||
inst_gray_counter : entity work.gray_counter
|
||||
generic map (width => 14)
|
||||
port map (
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
ce => ce,
|
||||
bcnt => bcnt,
|
||||
bnxt => bnxt,
|
||||
gcnt => gcnt,
|
||||
gnxt => gnxt
|
||||
);
|
||||
|
||||
end Behavioral;
|
||||
|
||||
@@ -0,0 +1,59 @@
|
||||
set -tmpdir "./xst/projnav.tmp"
|
||||
set -xsthdpdir "./xst"
|
||||
run
|
||||
-ifn top.prj
|
||||
-ifmt mixed
|
||||
-ofn top
|
||||
-ofmt NGC
|
||||
-p xc4vsx35-10-ff668
|
||||
-top top
|
||||
-opt_mode Speed
|
||||
-opt_level 1
|
||||
-power NO
|
||||
-iuc NO
|
||||
-lso top.lso
|
||||
-keep_hierarchy NO
|
||||
-rtlview Yes
|
||||
-glob_opt AllClockNets
|
||||
-read_cores YES
|
||||
-write_timing_constraints NO
|
||||
-cross_clock_analysis NO
|
||||
-hierarchy_separator /
|
||||
-bus_delimiter <>
|
||||
-case maintain
|
||||
-slice_utilization_ratio 100
|
||||
-bram_utilization_ratio 100
|
||||
-dsp_utilization_ratio 100
|
||||
-verilog2001 YES
|
||||
-fsm_extract YES -fsm_encoding Auto
|
||||
-safe_implementation No
|
||||
-fsm_style lut
|
||||
-ram_extract Yes
|
||||
-ram_style Auto
|
||||
-rom_extract Yes
|
||||
-mux_style Auto
|
||||
-decoder_extract YES
|
||||
-priority_extract YES
|
||||
-shreg_extract YES
|
||||
-shift_extract YES
|
||||
-xor_collapse YES
|
||||
-rom_style Auto
|
||||
-auto_bram_packing NO
|
||||
-mux_extract YES
|
||||
-resource_sharing YES
|
||||
-async_to_sync NO
|
||||
-use_dsp48 auto
|
||||
-iobuf YES
|
||||
-max_fanout 500
|
||||
-bufg 32
|
||||
-bufr 24
|
||||
-register_duplication YES
|
||||
-register_balancing No
|
||||
-slice_packing YES
|
||||
-optimize_primitives NO
|
||||
-use_clock_enable Auto
|
||||
-use_sync_set Auto
|
||||
-use_sync_reset Auto
|
||||
-iob auto
|
||||
-equivalent_register_removal YES
|
||||
-slice_utilization_ratio_maxmargin 5
|
||||
@@ -0,0 +1,3 @@
|
||||
vhdl work "W:\vhdl\projects\eval_gray_counter\fifo_ctrl_pkg.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\gray_counter.vhd"
|
||||
vhdl work "W:\vhdl\projects\eval_gray_counter\top.vhd"
|
||||
@@ -0,0 +1 @@
|
||||
vhdl work "d_ff.vhd"
|
||||
Binary file not shown.
@@ -0,0 +1 @@
|
||||
work
|
||||
@@ -0,0 +1,2 @@
|
||||
vhdl work "d_ff.vhd"
|
||||
vhdl work "eval_synch_top.vhd"
|
||||
@@ -0,0 +1,14 @@
|
||||
## NOTE: Do not edit this file.
|
||||
## Autogenerated by ProjNav (creatfdo.tcl) on Sat Oct 08 13:45:11 Westeuropäische Sommerzeit 2005
|
||||
##
|
||||
vlib work
|
||||
vcom -93 -explicit d_ff.vhd
|
||||
vcom -93 -explicit eval_synch_top.vhd
|
||||
vcom -93 -explicit tb_eval_synch.vhd
|
||||
vsim -t 1ps -lib work tb_eval_synch_vhd
|
||||
do {tb_eval_synch_vhd.udo}
|
||||
view wave
|
||||
add wave *
|
||||
view structure
|
||||
view signals
|
||||
run 1000ns
|
||||
@@ -0,0 +1,4 @@
|
||||
-- ProjNav VHDL simulation template: tb_eval_synch_vhd.udo
|
||||
-- You may edit this file after the line that starts with
|
||||
-- '-- START' to customize your simulation
|
||||
-- START user-defined simulation commands
|
||||
@@ -0,0 +1,53 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 13:19:14 10/08/05
|
||||
-- Design Name:
|
||||
-- Module Name: d_ff - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
---- Uncomment the following library declaration if instantiating
|
||||
---- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity d_ff is
|
||||
Generic (
|
||||
tpd : time := 1 ns
|
||||
);
|
||||
Port ( rst : in std_logic;
|
||||
clk : in std_logic;
|
||||
din : in std_logic;
|
||||
dout : out std_logic);
|
||||
end d_ff;
|
||||
|
||||
architecture Behavioral of d_ff is
|
||||
|
||||
begin
|
||||
|
||||
d_ff_proc : process(rst, clk, din)
|
||||
begin
|
||||
if (rst = '1') then
|
||||
dout <= '0' after tpd;
|
||||
elsif rising_edge(clk) then
|
||||
dout <= din after tpd;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
@@ -0,0 +1,71 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 12:33:39 10/08/05
|
||||
-- Design Name:
|
||||
-- Module Name: eval_synch_top - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
---- Uncomment the following library declaration if instantiating
|
||||
---- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity eval_synch_top is
|
||||
Generic (N : integer := 8);
|
||||
Port ( rst : in std_logic;
|
||||
clk : in std_logic;
|
||||
din : in std_logic;
|
||||
dout : out std_logic_vector(0 to N-1));
|
||||
end eval_synch_top;
|
||||
|
||||
architecture Behavioral of eval_synch_top is
|
||||
|
||||
COMPONENT d_ff
|
||||
GENERIC(tpd : time);
|
||||
PORT(
|
||||
rst : IN std_logic;
|
||||
clk : IN std_logic;
|
||||
din : IN std_logic;
|
||||
dout : OUT std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
-------------------------------------------------
|
||||
signal d_i : std_logic_vector(0 to N);
|
||||
|
||||
begin
|
||||
|
||||
d_i(0) <= din;
|
||||
dout <= d_i(1 to N);
|
||||
|
||||
inst_shift_reg : for i in 1 to N generate
|
||||
|
||||
Inst_d_ff: d_ff
|
||||
GENERIC MAP(tpd => 2.5 ns)
|
||||
PORT MAP(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
din => d_i(i-1),
|
||||
dout => d_i(i)
|
||||
);
|
||||
|
||||
end generate;
|
||||
|
||||
end Behavioral;
|
||||
@@ -0,0 +1,106 @@
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 13:42:54 10/08/2005
|
||||
-- Design Name: eval_synch_top
|
||||
-- Module Name: tb_eval_synch.vhd
|
||||
-- Project Name: eval_sync
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- VHDL Test Bench Created by ISE for module: eval_synch_top
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
-- Notes:
|
||||
-- This testbench has been automatically generated using types std_logic and
|
||||
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
|
||||
-- that these types always be used for the top-level I/O of a design in order
|
||||
-- to guarantee that the testbench will bind correctly to the post-implementation
|
||||
-- simulation model.
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.std_logic_unsigned.all;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY tb_eval_synch_vhd IS
|
||||
END tb_eval_synch_vhd;
|
||||
|
||||
ARCHITECTURE behavior OF tb_eval_synch_vhd IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
COMPONENT eval_synch_top
|
||||
PORT(
|
||||
rst : IN std_logic;
|
||||
clk : IN std_logic;
|
||||
din : IN std_logic;
|
||||
dout : OUT std_logic_vector(0 to 7)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--Constants
|
||||
constant PERIOD : time := 10 ns;
|
||||
|
||||
--Inputs
|
||||
SIGNAL rst : std_logic := '1';
|
||||
SIGNAL clk : std_logic := '0';
|
||||
SIGNAL din : std_logic := '0';
|
||||
|
||||
--Outputs
|
||||
SIGNAL dout : std_logic_vector(0 to 7);
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: eval_synch_top PORT MAP(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
din => din,
|
||||
dout => dout
|
||||
);
|
||||
|
||||
tb_clk : PROCESS
|
||||
BEGIN
|
||||
clk <= not clk;
|
||||
wait for PERIOD/2;
|
||||
END PROCESS;
|
||||
|
||||
tb : PROCESS
|
||||
BEGIN
|
||||
|
||||
-- Wait 100 ns for global reset to finish
|
||||
wait for 2*PERIOD;
|
||||
rst <= '0';
|
||||
|
||||
wait for 1.0*PERIOD + 0 ns;
|
||||
din <= '1';
|
||||
|
||||
wait for PERIOD;
|
||||
din <= '0';
|
||||
|
||||
wait for PERIOD;
|
||||
din <= '1';
|
||||
|
||||
wait for PERIOD;
|
||||
din <= '1';
|
||||
|
||||
wait for PERIOD;
|
||||
din <= '0';
|
||||
|
||||
-- Wait 100 ns for global reset to finish
|
||||
wait for 100 ns;
|
||||
|
||||
-- Place stimulus here
|
||||
|
||||
wait; -- will wait forever
|
||||
END PROCESS;
|
||||
|
||||
END;
|
||||
@@ -0,0 +1 @@
|
||||
work
|
||||
@@ -0,0 +1 @@
|
||||
vhdl work main_top.vhdl
|
||||
@@ -0,0 +1,8 @@
|
||||
INST "clki" TNM = "TNM_clk";
|
||||
NET "clki" PERIOD = 20 ns LOW 50 %;
|
||||
|
||||
INST "di" TNM = "testgrp_in";
|
||||
INST "do" TNM = "testgrp_out";
|
||||
TIMEGRP "testgrp_in" OFFSET = IN 10 ns BEFORE "clki" ;
|
||||
TIMEGRP "testgrp_out" OFFSET = OUT 25 ns AFTER "clki" ;
|
||||
#OFFSET = OUT 2 ns BEFORE "clk" TIMEGRP "TNM_clk" ;
|
||||
@@ -0,0 +1,92 @@
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Uncomment the following lines to use the declarations that are
|
||||
-- provided for instantiating Xilinx primitive components.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity main_top is
|
||||
Port ( res : in std_logic;
|
||||
clki : in std_logic;
|
||||
clko : out std_logic;
|
||||
di : in std_logic;
|
||||
do : out std_logic);
|
||||
end main_top;
|
||||
|
||||
architecture Behavioral of main_top is
|
||||
|
||||
type state_type is (idle, active, release);
|
||||
signal state, nextstate : state_type;
|
||||
signal clk : std_logic;
|
||||
shared variable test : std_logic;
|
||||
|
||||
component BUFG
|
||||
port (I: in std_logic; O: out std_logic);
|
||||
end component;
|
||||
|
||||
--**Insert the following after the 'begin' keyword**
|
||||
|
||||
|
||||
begin
|
||||
--U1: BUFG port map (I => clki, O => clk);
|
||||
|
||||
clk <= clki;
|
||||
|
||||
process (res, clk, di, state)
|
||||
begin
|
||||
if (res = '1') then
|
||||
clko <= '0';
|
||||
else
|
||||
clko <= '1';
|
||||
case state is
|
||||
|
||||
when idle =>
|
||||
if (di = '1') then
|
||||
nextstate <= active;
|
||||
else
|
||||
nextstate <= idle;
|
||||
end if;
|
||||
|
||||
when active =>
|
||||
if (di = '1') then
|
||||
nextstate <= active;
|
||||
else
|
||||
nextstate <= idle;
|
||||
end if;
|
||||
|
||||
when release =>
|
||||
nextstate <= idle;
|
||||
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (res, clk, state)
|
||||
begin
|
||||
if (res = '1') then
|
||||
do <= '0';
|
||||
else
|
||||
|
||||
do <= '0';
|
||||
case state is
|
||||
when active =>
|
||||
do <= '1';
|
||||
|
||||
when others =>
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (res, clk)
|
||||
begin
|
||||
if (res = '1') then
|
||||
state <= idle;
|
||||
elsif clk'event and clk = '1' then
|
||||
state <= nextstate;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
@@ -0,0 +1,13 @@
|
||||
## NOTE: Do not edit this file.
|
||||
## Autogenerated by ProjNav (creatfdo.tcl) on Tue Jun 08 23:46:14 Westeuropäische Sommerzeit 2004
|
||||
##
|
||||
vlib work
|
||||
vcom -93 -explicit main_top.vhdl
|
||||
vcom -93 -explicit main_top_tb.vhd
|
||||
vsim -t 1ps -lib work main_top_main_top_tb_vhd_tb
|
||||
do main_top_main_top_tb_vhd_tb.udo
|
||||
view wave
|
||||
add wave *
|
||||
view structure
|
||||
view signals
|
||||
run 1000ns
|
||||
@@ -0,0 +1,15 @@
|
||||
## NOTE: Do not edit this file.
|
||||
## Auto generated by Project Navigator for VHDL Post-PAR Simulation
|
||||
##
|
||||
vlib work
|
||||
## Compile Post-PAR Model for Module main_top
|
||||
vcom -87 -explicit main_top_timesim.vhd
|
||||
vcom -93 -explicit main_top_tb.vhd
|
||||
vsim -t 1ps -sdfmax /UUT=main_top_timesim.sdf -lib work main_top_main_top_tb_vhd_tb
|
||||
do main_top_main_top_tb_vhd_tb.udo
|
||||
view wave
|
||||
add wave *
|
||||
view structure
|
||||
view signals
|
||||
run 1000ns
|
||||
## End
|
||||
@@ -0,0 +1,4 @@
|
||||
-- ProjNav VHDL simulation template: main_top_main_top_tb_vhd_tb.udo
|
||||
-- You may edit this file after the line that starts with
|
||||
-- '-- START' to customize your simulation
|
||||
-- START user-defined simulation commands
|
||||
@@ -0,0 +1,74 @@
|
||||
|
||||
-- VHDL Test Bench Created from source file main_top.vhd -- 22:41:27 06/08/2004
|
||||
--
|
||||
-- Notes:
|
||||
-- This testbench has been automatically generated using types std_logic and
|
||||
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
|
||||
-- that these types always be used for the top-level I/O of a design in order
|
||||
-- to guarantee that the testbench will bind correctly to the post-implementation
|
||||
-- simulation model.
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY main_top_main_top_tb_vhd_tb IS
|
||||
END main_top_main_top_tb_vhd_tb;
|
||||
|
||||
ARCHITECTURE behavior OF main_top_main_top_tb_vhd_tb IS
|
||||
|
||||
COMPONENT main_top
|
||||
PORT(
|
||||
res : IN std_logic;
|
||||
clki : IN std_logic;
|
||||
di : IN std_logic;
|
||||
clko : OUT std_logic;
|
||||
do : OUT std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
constant ClockPeriod : Time := 20 ns;
|
||||
SIGNAL res : std_logic := '1';
|
||||
SIGNAL clki : std_logic;
|
||||
SIGNAL clko : std_logic;
|
||||
SIGNAL di : std_logic := '0';
|
||||
SIGNAL do : std_logic;
|
||||
|
||||
BEGIN
|
||||
|
||||
uut: main_top PORT MAP(
|
||||
res => res,
|
||||
clki => clki,
|
||||
clko => clko,
|
||||
di => di,
|
||||
do => do
|
||||
);
|
||||
|
||||
clkgen: process
|
||||
begin
|
||||
clki <= '1';
|
||||
loop
|
||||
wait for (ClockPeriod / 2);
|
||||
clki <= not clki;
|
||||
end loop;
|
||||
end process;
|
||||
|
||||
-- *** Test Bench - User Defined Section ***
|
||||
tb : PROCESS
|
||||
BEGIN
|
||||
res <= '1';
|
||||
|
||||
wait for 5*ClockPeriod;
|
||||
res <= '0';
|
||||
|
||||
wait for 5*ClockPeriod;
|
||||
di <= '1';
|
||||
|
||||
wait for 14.5*ClockPeriod;
|
||||
di <= '0';
|
||||
|
||||
wait; -- will wait forever
|
||||
END PROCESS;
|
||||
-- *** End Test Bench - User Defined Section ***
|
||||
|
||||
END;
|
||||
@@ -0,0 +1,432 @@
|
||||
-- Xilinx Vhdl netlist produced by netgen application (version G.30)
|
||||
-- Command : -intstyle ise -s 6 -pcf main_top.pcf -ngm main_top.ngm -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim main_top.ncd main_top_timesim.vhd
|
||||
-- Input file : main_top.ncd
|
||||
-- Output file : main_top_timesim.vhd
|
||||
-- Design name : main_top
|
||||
-- # of Entities : 1
|
||||
-- Xilinx : D:/Xilinx
|
||||
-- Device : 2v250cs144-6 (PRODUCTION 1.118 2004-03-12, STEPPING 1)
|
||||
|
||||
-- This vhdl netlist is a simulation model and uses simulation
|
||||
-- primitives which may not represent the true implementation of the
|
||||
-- device, however the netlist is functionally correct and should not
|
||||
-- be modified. This file cannot be synthesized and should only be used
|
||||
-- with supported simulation tools.
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library SIMPRIM;
|
||||
use SIMPRIM.VCOMPONENTS.ALL;
|
||||
use SIMPRIM.VPACKAGE.ALL;
|
||||
|
||||
entity main_top is
|
||||
port (
|
||||
clko : out STD_LOGIC;
|
||||
do : out STD_LOGIC;
|
||||
res : in STD_LOGIC := 'X';
|
||||
clki : in STD_LOGIC := 'X';
|
||||
di : in STD_LOGIC := 'X'
|
||||
);
|
||||
end main_top;
|
||||
|
||||
architecture Structure of main_top is
|
||||
signal di_IBUF : STD_LOGIC;
|
||||
signal do_OBUF : STD_LOGIC;
|
||||
signal clki_IBUFG : STD_LOGIC;
|
||||
signal clko_OBUF : STD_LOGIC;
|
||||
signal res_BUFGP_IBUFG : STD_LOGIC;
|
||||
signal GLOBAL_LOGIC1 : STD_LOGIC;
|
||||
signal res_BUFGP : STD_LOGIC;
|
||||
signal GLOBAL_LOGIC1_0 : STD_LOGIC;
|
||||
signal GSR : STD_LOGIC;
|
||||
signal GTS : STD_LOGIC;
|
||||
signal di_INBUF : STD_LOGIC;
|
||||
signal do_ENABLE : STD_LOGIC;
|
||||
signal do_GTS_OR_T : STD_LOGIC;
|
||||
signal do_O : STD_LOGIC;
|
||||
signal clki_INBUF : STD_LOGIC;
|
||||
signal clko_ENABLE : STD_LOGIC;
|
||||
signal clko_GTS_OR_T : STD_LOGIC;
|
||||
signal clko_O : STD_LOGIC;
|
||||
signal res_INBUF : STD_LOGIC;
|
||||
signal U1_S_INVNOT : STD_LOGIC;
|
||||
signal res_BUFGP_BUFG_S_INVNOT : STD_LOGIC;
|
||||
signal nextstate_1_DXMUX : STD_LOGIC;
|
||||
signal nextstate_1_F : STD_LOGIC;
|
||||
signal nextstate_1_DYMUX : STD_LOGIC;
|
||||
signal nextstate_1_G : STD_LOGIC;
|
||||
signal nextstate_1_CLKINV : STD_LOGIC;
|
||||
signal state_1_DXMUX : STD_LOGIC;
|
||||
signal state_1_DYMUX : STD_LOGIC;
|
||||
signal state_1_SRFFMUX : STD_LOGIC;
|
||||
signal state_1_CLKINV : STD_LOGIC;
|
||||
signal do_OBUF_G : STD_LOGIC;
|
||||
signal nextstate_1_FFY_SET : STD_LOGIC;
|
||||
signal nextstate_1_FFX_RST : STD_LOGIC;
|
||||
signal state_1_FFY_SET : STD_LOGIC;
|
||||
signal state_1_FFX_RST : STD_LOGIC;
|
||||
signal GND : STD_LOGIC;
|
||||
signal VCC : STD_LOGIC;
|
||||
signal NlwInverterSignal_nextstate_0_CLK : STD_LOGIC;
|
||||
signal NlwInverterSignal_nextstate_1_CLK : STD_LOGIC;
|
||||
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal Q_n0003 : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal nextstate : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
begin
|
||||
di_IBUF_0 : X_BUF_PP
|
||||
generic map(
|
||||
PATHPULSE => 605 ps
|
||||
)
|
||||
port map (
|
||||
I => di,
|
||||
O => di_INBUF
|
||||
);
|
||||
do_OBUF_1 : X_TRI_PP
|
||||
generic map(
|
||||
PATHPULSE => 605 ps
|
||||
)
|
||||
port map (
|
||||
I => do_O,
|
||||
CTL => do_ENABLE,
|
||||
O => do
|
||||
);
|
||||
do_ENABLEINV : X_INV
|
||||
port map (
|
||||
I => do_GTS_OR_T,
|
||||
O => do_ENABLE
|
||||
);
|
||||
do_GTS_OR_T_2 : X_BUF_PP
|
||||
generic map(
|
||||
PATHPULSE => 605 ps
|
||||
)
|
||||
port map (
|
||||
I => GTS,
|
||||
O => do_GTS_OR_T
|
||||
);
|
||||
clki_IBUFG_3 : X_BUF_PP
|
||||
generic map(
|
||||
PATHPULSE => 605 ps
|
||||
)
|
||||
port map (
|
||||
I => clki,
|
||||
O => clki_INBUF
|
||||
);
|
||||
clko_OBUF_4 : X_TRI_PP
|
||||
generic map(
|
||||
PATHPULSE => 605 ps
|
||||
)
|
||||
port map (
|
||||
I => clko_O,
|
||||
CTL => clko_ENABLE,
|
||||
O => clko
|
||||
);
|
||||
clko_ENABLEINV : X_INV
|
||||
port map (
|
||||
I => clko_GTS_OR_T,
|
||||
O => clko_ENABLE
|
||||
);
|
||||
clko_GTS_OR_T_5 : X_BUF_PP
|
||||
generic map(
|
||||
PATHPULSE => 605 ps
|
||||
)
|
||||
port map (
|
||||
I => GTS,
|
||||
O => clko_GTS_OR_T
|
||||
);
|
||||
res_BUFGP_IBUFG_6 : X_BUF_PP
|
||||
generic map(
|
||||
PATHPULSE => 605 ps
|
||||
)
|
||||
port map (
|
||||
I => res,
|
||||
O => res_INBUF
|
||||
);
|
||||
U1 : X_BUFGMUX
|
||||
port map (
|
||||
I0 => clki_IBUFG,
|
||||
I1 => GND,
|
||||
S => U1_S_INVNOT,
|
||||
O => clko_OBUF,
|
||||
GSR => GSR
|
||||
);
|
||||
U1_SINV : X_INV
|
||||
port map (
|
||||
I => GLOBAL_LOGIC1,
|
||||
O => U1_S_INVNOT
|
||||
);
|
||||
res_BUFGP_BUFG : X_BUFGMUX
|
||||
port map (
|
||||
I0 => res_BUFGP_IBUFG,
|
||||
I1 => GND,
|
||||
S => res_BUFGP_BUFG_S_INVNOT,
|
||||
O => res_BUFGP,
|
||||
GSR => GSR
|
||||
);
|
||||
res_BUFGP_BUFG_SINV : X_INV
|
||||
port map (
|
||||
I => GLOBAL_LOGIC1_0,
|
||||
O => res_BUFGP_BUFG_S_INVNOT
|
||||
);
|
||||
nextstate_1_DXMUX_7 : X_BUF_PP
|
||||
generic map(
|
||||
PATHPULSE => 605 ps
|
||||
)
|
||||
port map (
|
||||
I => Q_n0003(1),
|
||||
O => nextstate_1_DXMUX
|
||||
);
|
||||
nextstate_1_XUSED : X_BUF_PP
|
||||
generic map(
|
||||
PATHPULSE => 605 ps
|
||||
)
|
||||
port map (
|
||||
I => nextstate_1_F,
|
||||
O => Q_n0003(1)
|
||||
);
|
||||
nextstate_1_DYMUX_8 : X_BUF_PP
|
||||
generic map(
|
||||
PATHPULSE => 605 ps
|
||||
)
|
||||
port map (
|
||||
I => Q_n0003(0),
|
||||
O => nextstate_1_DYMUX
|
||||
);
|
||||
nextstate_1_YUSED : X_BUF_PP
|
||||
generic map(
|
||||
PATHPULSE => 605 ps
|
||||
)
|
||||
port map (
|
||||
I => nextstate_1_G,
|
||||
O => Q_n0003(0)
|
||||
);
|
||||
nextstate_1_CLKINV_9 : X_BUF_PP
|
||||
generic map(
|
||||
PATHPULSE => 605 ps
|
||||
)
|
||||
port map (
|
||||
I => res_BUFGP,
|
||||
O => nextstate_1_CLKINV
|
||||
);
|
||||
state_1_DXMUX_10 : X_BUF_PP
|
||||
generic map(
|
||||
PATHPULSE => 605 ps
|
||||
)
|
||||
port map (
|
||||
I => nextstate(1),
|
||||
O => state_1_DXMUX
|
||||
);
|
||||
state_1_DYMUX_11 : X_BUF_PP
|
||||
generic map(
|
||||
PATHPULSE => 605 ps
|
||||
)
|
||||
port map (
|
||||
I => nextstate(0),
|
||||
O => state_1_DYMUX
|
||||
);
|
||||
state_1_SRFFMUX_12 : X_BUF_PP
|
||||
generic map(
|
||||
PATHPULSE => 605 ps
|
||||
)
|
||||
port map (
|
||||
I => res_BUFGP,
|
||||
O => state_1_SRFFMUX
|
||||
);
|
||||
state_1_CLKINV_13 : X_BUF_PP
|
||||
generic map(
|
||||
PATHPULSE => 605 ps
|
||||
)
|
||||
port map (
|
||||
I => clko_OBUF,
|
||||
O => state_1_CLKINV
|
||||
);
|
||||
do_OBUF_YUSED : X_BUF_PP
|
||||
generic map(
|
||||
PATHPULSE => 605 ps
|
||||
)
|
||||
port map (
|
||||
I => do_OBUF_G,
|
||||
O => do_OBUF
|
||||
);
|
||||
Q_n0003_0_1 : X_LUT4
|
||||
generic map(
|
||||
INIT => X"5544"
|
||||
)
|
||||
port map (
|
||||
ADR0 => di_IBUF,
|
||||
ADR1 => state(1),
|
||||
ADR2 => VCC,
|
||||
ADR3 => state(0),
|
||||
O => nextstate_1_G
|
||||
);
|
||||
nextstate_0 : X_LATCHE
|
||||
generic map(
|
||||
INIT => '1'
|
||||
)
|
||||
port map (
|
||||
I => nextstate_1_DYMUX,
|
||||
GE => VCC,
|
||||
CLK => NlwInverterSignal_nextstate_0_CLK,
|
||||
SET => nextstate_1_FFY_SET,
|
||||
RST => GND,
|
||||
O => nextstate(0)
|
||||
);
|
||||
nextstate_1_FFY_SETOR : X_BUF_PP
|
||||
generic map(
|
||||
PATHPULSE => 605 ps
|
||||
)
|
||||
port map (
|
||||
I => GSR,
|
||||
O => nextstate_1_FFY_SET
|
||||
);
|
||||
Q_n0003_1_1 : X_LUT4
|
||||
generic map(
|
||||
INIT => X"AA88"
|
||||
)
|
||||
port map (
|
||||
ADR0 => di_IBUF,
|
||||
ADR1 => state(1),
|
||||
ADR2 => VCC,
|
||||
ADR3 => state(0),
|
||||
O => nextstate_1_F
|
||||
);
|
||||
nextstate_1 : X_LATCHE
|
||||
generic map(
|
||||
INIT => '0'
|
||||
)
|
||||
port map (
|
||||
I => nextstate_1_DXMUX,
|
||||
GE => VCC,
|
||||
CLK => NlwInverterSignal_nextstate_1_CLK,
|
||||
SET => GND,
|
||||
RST => nextstate_1_FFX_RST,
|
||||
O => nextstate(1)
|
||||
);
|
||||
nextstate_1_FFX_RSTOR : X_BUF_PP
|
||||
generic map(
|
||||
PATHPULSE => 605 ps
|
||||
)
|
||||
port map (
|
||||
I => GSR,
|
||||
O => nextstate_1_FFX_RST
|
||||
);
|
||||
state_0 : X_FF
|
||||
generic map(
|
||||
INIT => '1'
|
||||
)
|
||||
port map (
|
||||
I => state_1_DYMUX,
|
||||
CE => VCC,
|
||||
CLK => state_1_CLKINV,
|
||||
SET => state_1_FFY_SET,
|
||||
RST => GND,
|
||||
O => state(0)
|
||||
);
|
||||
state_1_FFY_SETOR : X_OR2
|
||||
port map (
|
||||
I0 => GSR,
|
||||
I1 => state_1_SRFFMUX,
|
||||
O => state_1_FFY_SET
|
||||
);
|
||||
Q_n00061 : X_LUT4
|
||||
generic map(
|
||||
INIT => X"4444"
|
||||
)
|
||||
port map (
|
||||
ADR0 => res_BUFGP,
|
||||
ADR1 => state(1),
|
||||
ADR2 => VCC,
|
||||
ADR3 => VCC,
|
||||
O => do_OBUF_G
|
||||
);
|
||||
state_1 : X_FF
|
||||
generic map(
|
||||
INIT => '0'
|
||||
)
|
||||
port map (
|
||||
I => state_1_DXMUX,
|
||||
CE => VCC,
|
||||
CLK => state_1_CLKINV,
|
||||
SET => GND,
|
||||
RST => state_1_FFX_RST,
|
||||
O => state(1)
|
||||
);
|
||||
state_1_FFX_RSTOR : X_OR2
|
||||
port map (
|
||||
I0 => state_1_SRFFMUX,
|
||||
I1 => GSR,
|
||||
O => state_1_FFX_RST
|
||||
);
|
||||
PWR_VCC_0_LOGICAL_ONE : X_ONE
|
||||
port map (
|
||||
O => GLOBAL_LOGIC1
|
||||
);
|
||||
PWR_VCC_1_LOGICAL_ONE : X_ONE
|
||||
port map (
|
||||
O => GLOBAL_LOGIC1_0
|
||||
);
|
||||
di_IFF_IMUX : X_BUF_PP
|
||||
generic map(
|
||||
PATHPULSE => 605 ps
|
||||
)
|
||||
port map (
|
||||
I => di_INBUF,
|
||||
O => di_IBUF
|
||||
);
|
||||
do_OUTPUT_OFF_OMUX : X_BUF_PP
|
||||
generic map(
|
||||
PATHPULSE => 605 ps
|
||||
)
|
||||
port map (
|
||||
I => do_OBUF,
|
||||
O => do_O
|
||||
);
|
||||
clki_IFF_IMUX : X_BUF_PP
|
||||
generic map(
|
||||
PATHPULSE => 605 ps
|
||||
)
|
||||
port map (
|
||||
I => clki_INBUF,
|
||||
O => clki_IBUFG
|
||||
);
|
||||
clko_OUTPUT_OFF_OMUX : X_BUF_PP
|
||||
generic map(
|
||||
PATHPULSE => 605 ps
|
||||
)
|
||||
port map (
|
||||
I => clko_OBUF,
|
||||
O => clko_O
|
||||
);
|
||||
res_IFF_IMUX : X_BUF_PP
|
||||
generic map(
|
||||
PATHPULSE => 605 ps
|
||||
)
|
||||
port map (
|
||||
I => res_INBUF,
|
||||
O => res_BUFGP_IBUFG
|
||||
);
|
||||
NlwBlock_main_top_GND : X_ZERO
|
||||
port map (
|
||||
O => GND
|
||||
);
|
||||
NlwBlock_main_top_VCC : X_ONE
|
||||
port map (
|
||||
O => VCC
|
||||
);
|
||||
NlwInverterBlock_nextstate_0_CLK : X_INV
|
||||
port map (
|
||||
I => nextstate_1_CLKINV,
|
||||
O => NlwInverterSignal_nextstate_0_CLK
|
||||
);
|
||||
NlwInverterBlock_nextstate_1_CLK : X_INV
|
||||
port map (
|
||||
I => nextstate_1_CLKINV,
|
||||
O => NlwInverterSignal_nextstate_1_CLK
|
||||
);
|
||||
NlwBlockROC : X_ROC
|
||||
generic map (ROC_WIDTH => 100 ns)
|
||||
port map (O => GSR);
|
||||
NlwBlockTOC : X_TOC
|
||||
port map (O => GTS);
|
||||
|
||||
end Structure;
|
||||
|
||||
@@ -0,0 +1 @@
|
||||
work main_top.vhdl
|
||||
@@ -0,0 +1 @@
|
||||
work main_top.vhdl
|
||||
@@ -0,0 +1 @@
|
||||
work
|
||||
@@ -0,0 +1 @@
|
||||
vhdl work vconfig.vhdl
|
||||
@@ -0,0 +1,13 @@
|
||||
## NOTE: Do not edit this file.
|
||||
## Autogenerated by ProjNav (creatfdo.tcl) on Wed Jun 02 00:12:48 Westeuropäische Sommerzeit 2004
|
||||
##
|
||||
vlib work
|
||||
vcom -93 -explicit vconfig.vhdl
|
||||
vcom -93 -explicit eval2clk_tb.vhd
|
||||
vsim -t 1ps -lib work eval2clk_tb
|
||||
do eval2clk_tb.udo
|
||||
view wave
|
||||
add wave *
|
||||
view structure
|
||||
view signals
|
||||
run 2000ns
|
||||
@@ -0,0 +1,15 @@
|
||||
## NOTE: Do not edit this file.
|
||||
## Auto generated by Project Navigator for VHDL Post-PAR Simulation
|
||||
##
|
||||
vlib work
|
||||
## Compile Post-PAR Model for Module eval2clk
|
||||
vcom -87 -explicit eval2clk_timesim.vhd
|
||||
vcom -93 -explicit eval2clk_tb.vhd
|
||||
vsim -t 1ps -sdfmax /UUT=eval2clk_timesim.sdf -lib work eval2clk_tb
|
||||
do eval2clk_tb.udo
|
||||
view wave
|
||||
add wave *
|
||||
view structure
|
||||
view signals
|
||||
run 2000ns
|
||||
## End
|
||||
@@ -0,0 +1,4 @@
|
||||
-- ProjNav VHDL simulation template: eval2clk_tb.udo
|
||||
-- You may edit this file after the line that starts with
|
||||
-- '-- START' to customize your simulation
|
||||
-- START user-defined simulation commands
|
||||
@@ -0,0 +1,67 @@
|
||||
|
||||
-- VHDL Test Bench Created from source file vconfig.vhd -- 20:20:01 05/01/2004
|
||||
--
|
||||
-- Notes:
|
||||
-- This testbench has been automatically generated using types std_logic and
|
||||
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
|
||||
-- that these types always be used for the top-level I/O of a design in order
|
||||
-- to guarantee that the testbench will bind correctly to the post-implementation
|
||||
-- simulation model.
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY eval2clk_tb IS
|
||||
END eval2clk_tb;
|
||||
|
||||
ARCHITECTURE behavior OF eval2clk_tb IS
|
||||
|
||||
COMPONENT eval2clk
|
||||
PORT(
|
||||
RES : IN std_logic;
|
||||
CLK : IN std_logic;
|
||||
SCLK : INOUT std_logic;
|
||||
dummy_out : INOUT std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
|
||||
SIGNAL RES : std_logic := '1';
|
||||
SIGNAL CLK : std_logic := '0';
|
||||
SIGNAL SCLK : std_logic;
|
||||
SIGNAL dummy_out : std_logic := '0';
|
||||
|
||||
constant ClockPeriod : Time := 16.667 ns;
|
||||
|
||||
BEGIN
|
||||
|
||||
uut: eval2clk PORT MAP(
|
||||
RES => RES,
|
||||
CLK => CLK,
|
||||
SCLK => SCLK,
|
||||
dummy_out => dummy_out
|
||||
);
|
||||
|
||||
busclock: process
|
||||
begin
|
||||
CLK <= '1';
|
||||
loop
|
||||
wait for (ClockPeriod / 2);
|
||||
CLK <= not CLK;
|
||||
end loop;
|
||||
end process;
|
||||
|
||||
-- *** Test Bench - User Defined Section ***
|
||||
tb : PROCESS
|
||||
BEGIN
|
||||
|
||||
wait for 20*ClockPeriod;
|
||||
RES <= '0';
|
||||
|
||||
|
||||
wait; -- will wait forever
|
||||
END PROCESS;
|
||||
-- *** End Test Bench - User Defined Section ***
|
||||
|
||||
END;
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1 @@
|
||||
work vconfig.vhdl
|
||||
@@ -0,0 +1,62 @@
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Uncomment the following lines to use the declarations that are
|
||||
-- provided for instantiating Xilinx primitive components.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity eval2clk is
|
||||
Port ( RES : in std_logic;
|
||||
CLK : in std_logic;
|
||||
SCLK : inout std_logic;
|
||||
dummy_out : inout std_logic);
|
||||
end eval2clk;
|
||||
|
||||
architecture Behavioral of eval2clk is
|
||||
signal count, scount : integer range 0 to 63;
|
||||
signal SCLK1 : std_logic;
|
||||
begin
|
||||
|
||||
process (RES, SCLK1)
|
||||
begin
|
||||
if (RES = '1') then
|
||||
dummy_out <= '1';
|
||||
scount <= 2;
|
||||
|
||||
elsif SCLK1='1' and SCLK1'event then
|
||||
|
||||
if (scount = 0) then
|
||||
scount <= 2;
|
||||
dummy_out <= not dummy_out;
|
||||
|
||||
else
|
||||
scount <= scount - 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (RES, CLK)
|
||||
begin
|
||||
if (RES = '1') then
|
||||
SCLK1 <= '1';
|
||||
COUNT <= 4;
|
||||
|
||||
elsif CLK='1' and CLK'event then
|
||||
|
||||
if (COUNT = 0) then
|
||||
COUNT <= 4;
|
||||
SCLK1 <= not SCLK1;
|
||||
|
||||
else
|
||||
COUNT <= COUNT - 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
SCLK <= RES;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
@@ -0,0 +1,67 @@
|
||||
|
||||
-- VHDL Test Bench Created from source file vconfig.vhd -- 20:20:01 05/01/2004
|
||||
--
|
||||
-- Notes:
|
||||
-- This testbench has been automatically generated using types std_logic and
|
||||
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
|
||||
-- that these types always be used for the top-level I/O of a design in order
|
||||
-- to guarantee that the testbench will bind correctly to the post-implementation
|
||||
-- simulation model.
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY eval2clk_tb IS
|
||||
END eval2clk_tb;
|
||||
|
||||
ARCHITECTURE behavior OF eval2clk_tb IS
|
||||
|
||||
COMPONENT eval2clk
|
||||
PORT(
|
||||
RES : IN std_logic;
|
||||
CLK : IN std_logic;
|
||||
SCLK : INOUT std_logic;
|
||||
dummy_out : OUT std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
|
||||
SIGNAL RES : std_logic := '1';
|
||||
SIGNAL CLK : std_logic := '0';
|
||||
SIGNAL SCLK : std_logic;
|
||||
SIGNAL dummy_out : std_logic := '0';
|
||||
|
||||
constant ClockPeriod : Time := 16.667 ns;
|
||||
|
||||
BEGIN
|
||||
|
||||
uut: eval2clk PORT MAP(
|
||||
RES => RES,
|
||||
CLK => CLK,
|
||||
SCLK => SCLK,
|
||||
dummy_out => dummy_out
|
||||
);
|
||||
|
||||
busclock: process
|
||||
begin
|
||||
CLK <= '1';
|
||||
loop
|
||||
wait for (ClockPeriod / 2);
|
||||
CLK <= not CLK;
|
||||
end loop;
|
||||
end process;
|
||||
|
||||
-- *** Test Bench - User Defined Section ***
|
||||
tb : PROCESS
|
||||
BEGIN
|
||||
|
||||
wait for 20*ClockPeriod;
|
||||
RES <= '0';
|
||||
|
||||
|
||||
wait; -- will wait forever
|
||||
END PROCESS;
|
||||
-- *** End Test Bench - User Defined Section ***
|
||||
|
||||
END;
|
||||
@@ -0,0 +1,34 @@
|
||||
|
||||
-w
|
||||
-g DebugBitstream:No
|
||||
-g Binary:no
|
||||
-g CRC:Enable
|
||||
-g ConfigRate:4
|
||||
-g CclkPin:PullUp
|
||||
-g M0Pin:PullUp
|
||||
-g M1Pin:PullUp
|
||||
-g M2Pin:PullUp
|
||||
-g ProgPin:PullUp
|
||||
-g DonePin:PullUp
|
||||
-g InitPin:Pullup
|
||||
-g CsPin:Pullup
|
||||
-g DinPin:Pullup
|
||||
-g BusyPin:Pullup
|
||||
-g RdWrPin:Pullup
|
||||
-g TckPin:PullUp
|
||||
-g TdiPin:PullUp
|
||||
-g TdoPin:PullUp
|
||||
-g TmsPin:PullUp
|
||||
-g UnusedPin:PullDown
|
||||
-g UserID:0xFFFFFFFF
|
||||
-g DCMShutDown:Disable
|
||||
-g DCIUpdateMode:AsRequired
|
||||
-g StartUpClk:JtagClk
|
||||
-g DONE_cycle:4
|
||||
-g GTS_cycle:5
|
||||
-g GWE_cycle:6
|
||||
-g LCK_cycle:NoWait
|
||||
-g Security:None
|
||||
-g DonePipe:No
|
||||
-g DriveDone:No
|
||||
-g Encrypt:No
|
||||
Binary file not shown.
@@ -0,0 +1 @@
|
||||
work
|
||||
@@ -0,0 +1,2 @@
|
||||
vhdl work "E:/work/XilinxISE/Common/oneshot.vhd"
|
||||
vhdl work "hpi_reg_top.vhd"
|
||||
@@ -0,0 +1,34 @@
|
||||
|
||||
-w
|
||||
-g DebugBitstream:No
|
||||
-g Binary:no
|
||||
-g CRC:Enable
|
||||
-g ConfigRate:4
|
||||
-g CclkPin:PullUp
|
||||
-g M0Pin:PullUp
|
||||
-g M1Pin:PullUp
|
||||
-g M2Pin:PullUp
|
||||
-g ProgPin:PullUp
|
||||
-g DonePin:PullUp
|
||||
-g InitPin:Pullup
|
||||
-g CsPin:Pullup
|
||||
-g DinPin:Pullup
|
||||
-g BusyPin:Pullup
|
||||
-g RdWrPin:Pullup
|
||||
-g TckPin:PullUp
|
||||
-g TdiPin:PullUp
|
||||
-g TdoPin:PullUp
|
||||
-g TmsPin:PullUp
|
||||
-g UnusedPin:PullDown
|
||||
-g UserID:0xFFFFFFFF
|
||||
-g DCMShutDown:Disable
|
||||
-g DCIUpdateMode:AsRequired
|
||||
-g StartUpClk:JtagClk
|
||||
-g DONE_cycle:4
|
||||
-g GTS_cycle:5
|
||||
-g GWE_cycle:6
|
||||
-g LCK_cycle:NoWait
|
||||
-g Security:None
|
||||
-g DonePipe:No
|
||||
-g DriveDone:No
|
||||
-g Encrypt:No
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user