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Disabled TLB and run for 150 us

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jens
2022-09-08 09:07:32 +02:00
parent 518af7c679
commit 609e7bf64d
1 changed files with 2 additions and 2 deletions
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lib/CPUs/MIPS/src/tb_mips_top.vhd
+2 -2
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@@ -42,8 +42,8 @@ ARCHITECTURE behavior OF tb_mips_top IS
constant CLK_PERIOD : time := 10 ns; constant CLK_PERIOD : time := 10 ns;
constant SRAM_ADDR_WIDTH : integer := 17; -- bits constant SRAM_ADDR_WIDTH : integer := 17; -- bits
constant FLASH_ADDR_WIDTH : integer := 17; -- bits constant FLASH_ADDR_WIDTH : integer := 17; -- bits
constant WITH_TLB : boolean := true; constant WITH_TLB : boolean := false;
constant KSEG_01_TRANSLATED : boolean := true; constant KSEG_01_TRANSLATED : boolean := false;
signal debug : chip_debug_t; signal debug : chip_debug_t;
signal tb_fin : STD_LOGIC := '0'; signal tb_fin : STD_LOGIC := '0';