Disabled TLB and run for 150 us

2022-09-08 09:07:32 +02:00
parent 518af7c679
commit 609e7bf64d
1 changed files with 2 additions and 2 deletions
@@ -42,8 +42,8 @@ ARCHITECTURE behavior OF tb_mips_top IS
 	constant CLK_PERIOD 			: time := 10 ns;
 	constant SRAM_ADDR_WIDTH		: integer := 17;		-- bits
 	constant FLASH_ADDR_WIDTH		: integer := 17;		-- bits
-	constant WITH_TLB				: boolean := true;
-	constant KSEG_01_TRANSLATED		: boolean := true;
+	constant WITH_TLB				: boolean := false;
+	constant KSEG_01_TRANSLATED		: boolean := false;
 	signal debug					: chip_debug_t;
 	signal tb_fin					: STD_LOGIC := '0';