jens/vhdl
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jens 609e7bf64d Disabled TLB and run for 150 us
2022-09-08 09:07:32 +02:00
Common
Moved defs.mk
2022-09-08 08:57:26 +02:00
lib
Disabled TLB and run for 150 us
2022-09-08 09:07:32 +02:00
projects
- compile clean with Intel Quartus Prime Lite 21
2022-08-07 14:26:12 +02:00
defs.mk
Moved defs.mk
2022-09-08 08:57:26 +02:00
Makefile
- refactored ISE makefiles
2021-03-29 12:49:42 +00:00
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23 MiB
Languages
VHDL 90.1%
Verilog 4.2%
Tcl 2.5%
SystemVerilog 0.8%
IGOR Pro 0.5%
Other 1.5%