diff --git a/lib/CPUs/MIPS/src/tb_mips_top.vhd b/lib/CPUs/MIPS/src/tb_mips_top.vhd
index bf49e1c..05b6d5d 100644
--- a/lib/CPUs/MIPS/src/tb_mips_top.vhd
+++ b/lib/CPUs/MIPS/src/tb_mips_top.vhd
@@ -42,8 +42,8 @@ ARCHITECTURE behavior OF tb_mips_top IS
 	constant CLK_PERIOD 			: time := 10 ns;
 	constant SRAM_ADDR_WIDTH		: integer := 17;		-- bits
 	constant FLASH_ADDR_WIDTH		: integer := 17;		-- bits
-	constant WITH_TLB				: boolean := true;
-	constant KSEG_01_TRANSLATED		: boolean := true;
+	constant WITH_TLB				: boolean := false;
+	constant KSEG_01_TRANSLATED		: boolean := false;
 	signal debug					: chip_debug_t;
 	signal tb_fin					: STD_LOGIC := '0';