jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

- renamed signals

Browse Source 
git-svn-id: http://moon:8086/svn/vhdl/trunk@1092 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-16 16:53:19 +00:00
parent d282feb11d
commit 02e2f89308
1 changed files with 9 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/CPUs/MIPS/src/core/mips_icache.vhd
+9 -7
View File
@@ -157,14 +157,16 @@ END COMPONENT;
signal data_ram_data_rd : word_t;
signal data_ram_addr_wr : unsigned(lg2(cache_size)-1 downto 0);
signal data_ram_data_wr : word_t;
signal data_ram_we : std_logic;
signal data_ram_we : std_logic;
signal data_ram_re : std_logic;
signal tag_ram_addr_rd : unsigned(cache_index_width-1 downto 0);
signal tag_ram_data_rd : tag_ram_data_t;
signal tag_ram_data_rd_inv : tag_ram_data_t;
signal tag_ram_addr_wr : unsigned(cache_index_width-1 downto 0);
signal tag_ram_data_wr : tag_ram_data_t;
signal tag_ram_we : std_logic;
signal tag_ram_we : std_logic;
signal tag_ram_re : std_logic;
signal fill_count : natural range 0 to 2**word_index_width-1;
signal fill_count_en : std_logic;
@@ -176,7 +178,6 @@ END COMPONENT;
signal request_count : natural range 0 to 2**word_index_width-1;
signal request_count_en : std_logic;
signal request_count_rdy : std_logic;
signal ram_read_en : std_logic;
signal was_miss : std_logic;
signal invalidate_all : std_logic;
signal invalidate_ack : std_logic;
@@ -197,7 +198,6 @@ END COMPONENT;
begin
ram_read_en <= cpu_en or was_miss;
cache_index_inv <= ctrl.inv_addr(cache_index_width+word_index_width+1 downto word_index_width+2);
tag_inv <= ctrl.inv_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
@@ -272,7 +272,7 @@ inst_tag_ram : dpram_2w2r2c_ra
clk_a => CLK_I,
clk_b => CLK_I,
en_a => '1',
en_b => ram_read_en,
en_b => tag_ram_re,
we_a => tag_ram_we,
we_b => '0',
addr_a => tag_ram_addr_wr,
@@ -293,8 +293,8 @@ inst_data_ram : dpram_1w1r2c_ra
(
clk_a => CLK_I,
clk_b => CLK_I,
en_a => '1',
en_b => ram_read_en,
en_a => data_ram_we,
en_b => data_ram_re,
we_a => data_ram_we,
addr_a => data_ram_addr_wr,
addr_b => data_ram_addr_rd,
@@ -335,6 +335,8 @@ cache_state_next:
data_ram_addr_wr <= fill_cache_index & fill_word_index;
data_ram_data_wr <= DAT_I;
data_ram_we <= fill_count_en and ACK_I;
data_ram_re <= (cpu_en or was_miss) and not data_ram_we;
tag_ram_re <= (cpu_en or was_miss) and not data_ram_we;
cache_state:
process(s, cache_req, cache_miss, cache_miss_inv, flush_count_rdy, fill_count_rdy, request_count_rdy, fill_tag, SRDY_I, invalidate_req, invalidate_all)