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git-svn-id: http://moon:8086/svn/vhdl/trunk@1429 cc03376c-175c-47c8-b038-4cd826a8556b
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jens
2021-03-21 12:04:37 +00:00
parent 9edf6a70af
commit 2f7ab91e0d
116 changed files with 50542 additions and 0 deletions
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projects/jtag_test/ise/_impact.cmd
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setPreference -pref StartupClock:AUTO_CORRECTION
setPreference -pref AutoSignature:FALSE
setPreference -pref KeepSVF:FALSE
setPreference -pref ConcurrentMode:FALSE
setPreference -pref UseHighz:FALSE
setPreference -pref ConfigOnFailure:STOP
setPreference -pref UserLevel:NOVICE
setPreference -pref MessageLevel:DETAILED
setPreference -pref svfUseTime:FALSE
setMode -bs
setMode -bs
setCable -port auto
Identify
identifyMPM
assignFile -p 3 -file "H:/work/vhdl/projects/jtag_test/ise/jtag_test.bit"
Program -p 3 -prog -defaultVersion 0
Program -p 3 -prog -defaultVersion 0
Program -p 3 -prog -defaultVersion 0
Program -p 3 -prog -defaultVersion 0
Program -p 3 -prog -defaultVersion 0
Program -p 3 -prog -defaultVersion 0
Program -p 3 -prog -defaultVersion 0
Program -p 3 -prog -defaultVersion 0
Program -p 3 -prog -defaultVersion 0
Program -p 3 -prog -defaultVersion 0
Program -p 3 -prog -defaultVersion 0
saveProjectFile -file "H:/work/vhdl/projects/jtag_test/ise/jtag_test.ipf"
projects/jtag_test/ise/jtag_test.ipf
BIN
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projects/jtag_test/ise/jtag_test.ise
BIN
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projects/jtag_test/ise/jtag_test.lso
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work
projects/jtag_test/ise/jtag_test.prj
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vhdl work "jtag_test.vhd"
projects/jtag_test/ise/jtag_test.ut
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-w
-g DebugBitstream:No
-g Binary:no
-g CRC:Enable
-g ConfigRate:4
-g CclkPin:PullUp
-g M0Pin:PullUp
-g M1Pin:PullUp
-g M2Pin:PullUp
-g ProgPin:PullUp
-g DonePin:PullUp
-g InitPin:Pullup
-g CsPin:Pullup
-g DinPin:Pullup
-g BusyPin:Pullup
-g RdWrPin:Pullup
-g TckPin:PullUp
-g TdiPin:PullUp
-g TdoPin:PullUp
-g TmsPin:PullUp
-g UnusedPin:PullDown
-g UserID:0xFFFFFFFF
-g DCMShutdown:Disable
-g DisableBandgap:No
-g DCIUpdateMode:AsRequired
-g StartUpClk:JtagClk
-g DONE_cycle:4
-g GTS_cycle:5
-g GWE_cycle:6
-g LCK_cycle:NoWait
-g Security:None
-g DonePipe:No
-g DriveDone:No
-g Encrypt:No
projects/jtag_test/ise/jtag_test.vhd
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:44:00 03/07/2007
-- Design Name:
-- Module Name: jtag_test - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity jtag_test is
Port (
sys_rstn_in : in STD_LOGIC;
sys_led : out unsigned(8 downto 0)
);
end jtag_test;
architecture Behavioral of jtag_test is
signal rst, bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
signal user_regi, user_rego : unsigned (7 downto 0);
constant id : unsigned (7 downto 0) := "11010101";
begin
BSCAN_VIRTEX4_inst : BSCAN_VIRTEX4
generic map (
JTAG_CHAIN => 2) -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
port map (
CAPTURE => bs_capture, -- CAPTURE output from TAP controller
DRCK => bs_clk0, -- Data register output for USER functions
RESET => bs_rst, -- Reset output from TAP controller
SEL => bs_sel, -- USER active output
SHIFT => bs_shift, -- SHIFT output from TAP controller
TDI => bs_tdi, -- TDI output from TAP controller
UPDATE => bs_update0, -- UPDATE output from TAP controller
TDO => bs_tdo -- Data input for USER function
);
i00_BUFG : BUFG
port map (
O => bs_clk1,
I => bs_clk0
);
i01_BUFG : BUFG
port map (
O => bs_update1,
I => bs_update0
);
rst <= not sys_rstn_in;
led_out:
process (rst, bs_clk1, bs_update1, user_regi)
begin
if rst = '1' then
sys_led(7 downto 0) <= (others => '0');
elsif rising_edge(bs_update1) then
if bs_sel = '1' then
sys_led(7 downto 0) <= user_regi;
end if;
end if;
end process;
cled_out:
process (rst, bs_clk1, bs_update1, user_regi)
begin
if rst = '1' then
sys_led(8) <= '0';
elsif rising_edge(bs_update1) then
sys_led(8) <= bs_sel;
end if;
end process;
sipo:
process (bs_rst, bs_clk1, bs_tdi, bs_shift)
begin
if bs_rst = '1' then
user_regi <= (others => '0');
elsif rising_edge(bs_clk1) then
if bs_shift = '1' then
user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
end if;
end if;
end process;
piso:
process (rst, bs_clk1, bs_shift, user_rego)
begin
bs_tdo <= user_rego(0);
if rst = '1' then
user_rego <= (others => '0');
elsif rising_edge(bs_clk1) then
if bs_shift = '1' then
user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
else
user_rego <= id;
end if;
end if;
end process;
end Behavioral;
projects/jtag_test/ise/jtag_test.xst
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set -tmpdir ./xst/projnav.tmp
set -xsthdpdir ./xst
run
-ifn jtag_test.prj
-ifmt mixed
-ofn jtag_test
-ofmt NGC
-p xc4vsx35-10-ff668
-top jtag_test
-opt_mode Speed
-opt_level 1
-iuc NO
-lso jtag_test.lso
-keep_hierarchy NO
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case maintain
-slice_utilization_ratio 100
-dsp_utilization_ratio 100
-verilog2001 YES
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style lut
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-mux_style Auto
-decoder_extract YES
-priority_extract YES
-shreg_extract YES
-shift_extract YES
-xor_collapse YES
-rom_style Auto
-mux_extract YES
-resource_sharing YES
-use_dsp48 auto
-iobuf YES
-max_fanout 500
-bufg 32
-bufr 24
-register_duplication YES
-register_balancing No
-slice_packing YES
-optimize_primitives NO
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5
projects/jtag_test/ise/system.ucf
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#
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
# SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
# XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
# AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
# OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
# IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
# AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
# FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
# WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
# IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
# REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
# INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
# FOR A PARTICULAR PURPOSE.
#
# (c) Copyright 2005 Xilinx, Inc.
# All rights reserved.
#
NET "sys_rstn_in" LOC = "D6";
NET sys_rstn_in PULLUP;
NET "sys_rstn_in" TIG;
////////////////////////////////////////////////////////////////////////////
// Buttons, LEDs, and DIP Switches
////////////////////////////////////////////////////////////////////////////
# GPLED 0-3
NET sys_led<0> LOC = G5; #GPLED0
NET sys_led<1> LOC = G6; #GPLED1
NET sys_led<2> LOC = A11; #GPLED2
NET sys_led<3> LOC = A12; #GPLED3
# North-East-South-West-Center LEDs
NET sys_led<4> LOC = F9; # W LED
NET sys_led<5> LOC = A5; # S LED
NET sys_led<6> LOC = E10; # E LED
NET sys_led<7> LOC = E2; # N LED
NET sys_led<8> LOC = "C6"; # C LED
NET "sys_led<*>" TIG;
NET "sys_led<*>" SLEW = SLOW;
NET "sys_led<*>" DRIVE = 2;
projects/jtag_test/v4_test.tcl
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# Source JTAG/TCL frame work
cd $env(CHIPSCOPE)/bin/nt
source $env(CHIPSCOPE)/bin/nt/tcljtag.tcl
# Open JTAG
set handle [jtag_open type=xilinx_platformusb frequency=750000]
jtag_lock $handle
set devlist [jtag_autodetect $handle]
puts $devlist
# Scan chain
set idcode_list [jtag_scanchain $handle]
puts $idcode_list
# Get number of devices in chain
set devcount [jtag_devicecount $handle]
puts "Number of devices in the chain: $devcount"
# Get Device ID
set devtype "Virtex-4SX"
set devid 2
puts "IR Length of device $devid is [jtag_irlength $handle $devid]"
#jtag_navigate $handle TLR
# ---------------------------------------------------------------
# Shift the USER1 Instruction (b1111000010) into the Instruction Register of FPGA
# User 1
puts [jtag_shiftir $handle -buffer "1100001111" -endstate RTI -device $devid]
# DevIDCode
#puts [jtag_shiftir $handle -buffer "1001001111" -endstate RTI -device $devid]
# Write LED <= 0x55
puts [jtag_shiftdr $handle -buffer "10101010" -endstate RTI -device $devid]
# ---------------------------------------------------------------
jtag_unlock $handle
jtag_close $handle
exit