diff --git a/projects/Eval_VConfig/pepExtractor.prj b/projects/Eval_VConfig/pepExtractor.prj new file mode 100644 index 0000000..bae7e2a --- /dev/null +++ b/projects/Eval_VConfig/pepExtractor.prj @@ -0,0 +1 @@ +work vconfig.vhdl diff --git a/projects/Eval_VConfig/sim.do b/projects/Eval_VConfig/sim.do new file mode 100644 index 0000000..5937eb7 --- /dev/null +++ b/projects/Eval_VConfig/sim.do @@ -0,0 +1,5 @@ +do vconfig_tb.fdo +delete wave * +do wave.do +restart -force +run 6000ns -all \ No newline at end of file diff --git a/projects/Eval_VConfig/vconfig.ldo b/projects/Eval_VConfig/vconfig.ldo new file mode 100644 index 0000000..278d0a7 --- /dev/null +++ b/projects/Eval_VConfig/vconfig.ldo @@ -0,0 +1,10 @@ +# Auto generated by Project Navigator for Modelsim +vlib work + +vcom -93 -explicit vconfig.vhdl +## You need to generate your own stimuli +vsim -t 1ps vconfig +view wave +add wave * +view structure +view signals diff --git a/projects/Eval_VConfig/vconfig.lso b/projects/Eval_VConfig/vconfig.lso new file mode 100644 index 0000000..22de730 --- /dev/null +++ b/projects/Eval_VConfig/vconfig.lso @@ -0,0 +1 @@ +work diff --git a/projects/Eval_VConfig/vconfig.prj b/projects/Eval_VConfig/vconfig.prj new file mode 100644 index 0000000..b46a177 --- /dev/null +++ b/projects/Eval_VConfig/vconfig.prj @@ -0,0 +1 @@ +vhdl work vconfig.vhdl diff --git a/projects/Eval_VConfig/vconfig.vhd b/projects/Eval_VConfig/vconfig.vhd new file mode 100644 index 0000000..048cd0b --- /dev/null +++ b/projects/Eval_VConfig/vconfig.vhd @@ -0,0 +1,9236 @@ +-- Xilinx Vhdl netlist produced by netgen application (version G.30) +-- Command : -rpw 100 -ar Structure -xon true -w -ofmt vhdl -sim vconfig.nga vconfig.vhd +-- Input file : vconfig.nga +-- Output file : vconfig.vhd +-- Design name : vconfig.nga +-- # of Entities : 1 +-- Xilinx : D:/Xilinx +-- Device : XC95288XL-6-TQ144 (Speed File: Version 3.0) + +-- This vhdl netlist is a simulation model and uses simulation +-- primitives which may not represent the true implementation of the +-- device, however the netlist is functionally correct and should not +-- be modified. This file cannot be synthesized and should only be used +-- with supported simulation tools. + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library SIMPRIM; +use SIMPRIM.VCOMPONENTS.ALL; +use SIMPRIM.VPACKAGE.ALL; + +entity vconfig is + port ( + nINIT_B : in STD_LOGIC := 'X'; + LOAD : in STD_LOGIC := 'X'; + RES : in STD_LOGIC := 'X'; + DONE : in STD_LOGIC := 'X'; + CLK : in STD_LOGIC := 'X'; + DOUT : out STD_LOGIC; + VCLK : out STD_LOGIC; + DIN : in STD_LOGIC_VECTOR ( 31 downto 0 ); + VCLK_PRESCALE : in STD_LOGIC_VECTOR ( 5 downto 0 ) + ); +end vconfig; + +architecture Structure of vconfig is + signal FOEIO_1 : STD_LOGIC; + signal LOAD_IBUF : STD_LOGIC; + signal DIN_31_IBUF : STD_LOGIC; + signal RES_IBUF : STD_LOGIC; + signal DONE_IBUF : STD_LOGIC; + signal FCLKIO_0 : STD_LOGIC; + signal VCLK_PRESCALE_0_IBUF : STD_LOGIC; + signal VCLK_PRESCALE_4_IBUF : STD_LOGIC; + signal VCLK_PRESCALE_1_IBUF : STD_LOGIC; + signal VCLK_PRESCALE_2_IBUF : STD_LOGIC; + signal VCLK_PRESCALE_3_IBUF : STD_LOGIC; + signal DIN_0_IBUF : STD_LOGIC; + signal DIN_10_IBUF : STD_LOGIC; + signal DIN_11_IBUF : STD_LOGIC; + signal DIN_12_IBUF : STD_LOGIC; + signal DIN_13_IBUF : STD_LOGIC; + signal DIN_14_IBUF : STD_LOGIC; + signal DIN_15_IBUF : STD_LOGIC; + signal DIN_16_IBUF : STD_LOGIC; + signal DIN_17_IBUF : STD_LOGIC; + signal DIN_18_IBUF : STD_LOGIC; + signal DIN_19_IBUF : STD_LOGIC; + signal DIN_1_IBUF : STD_LOGIC; + signal DIN_20_IBUF : STD_LOGIC; + signal DIN_21_IBUF : STD_LOGIC; + signal DIN_22_IBUF : STD_LOGIC; + signal DIN_23_IBUF : STD_LOGIC; + signal DIN_24_IBUF : STD_LOGIC; + signal DIN_25_IBUF : STD_LOGIC; + signal DIN_26_IBUF : STD_LOGIC; + signal DIN_27_IBUF : STD_LOGIC; + signal DIN_28_IBUF : STD_LOGIC; + signal DIN_29_IBUF : STD_LOGIC; + signal DIN_2_IBUF : STD_LOGIC; + signal DIN_30_IBUF : STD_LOGIC; + signal DIN_3_IBUF : STD_LOGIC; + signal DIN_4_IBUF : STD_LOGIC; + signal DIN_5_IBUF : STD_LOGIC; + signal DIN_6_IBUF : STD_LOGIC; + signal DIN_7_IBUF : STD_LOGIC; + signal DIN_8_IBUF : STD_LOGIC; + signal DIN_9_IBUF : STD_LOGIC; + signal VCLK_PRESCALE_5_IBUF : STD_LOGIC; + signal REG_31_Q : STD_LOGIC; + signal REG_31_OE : STD_LOGIC; + signal VCLK_OBUF_Q : STD_LOGIC; + signal REG_31_Q_0 : STD_LOGIC; + signal REG_31_BUFOE_OUT : STD_LOGIC; + signal REG_31_D : STD_LOGIC; + signal REG_31_tsimcreated_xor_Q : STD_LOGIC; + signal REG_31_RSTF : STD_LOGIC; + signal REG_31_SETF : STD_LOGIC; + signal REG_31_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal PRLD : STD_LOGIC; + signal REG_31_tsimcreated_prld_Q : STD_LOGIC; + signal REG_31_CLKF : STD_LOGIC; + signal Vcc : STD_LOGIC; + signal REG_31_D1 : STD_LOGIC; + signal REG_31_D2 : STD_LOGIC; + signal SHIFT_EN : STD_LOGIC; + signal SREG_IS_EMPTY : STD_LOGIC; + signal REG_31_D2_PT_0 : STD_LOGIC; + signal REG_31_D2_PT_1 : STD_LOGIC; + signal SCLK : STD_LOGIC; + signal SHIFT_EN_Q : STD_LOGIC; + signal SHIFT_EN_RSTF : STD_LOGIC; + signal SHIFT_EN_tsimcreated_prld_Q : STD_LOGIC; + signal SHIFT_EN_D : STD_LOGIC; + signal SHIFT_EN_CLKF : STD_LOGIC; + signal Gnd : STD_LOGIC; + signal SHIFT_EN_CE : STD_LOGIC; + signal SHIFT_EN_D1 : STD_LOGIC; + signal SHIFT_EN_D2 : STD_LOGIC; + signal count_0_Q : STD_LOGIC; + signal count_0_RSTF : STD_LOGIC; + signal count_0_SETF : STD_LOGIC; + signal count_0_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal count_0_tsimcreated_prld_Q : STD_LOGIC; + signal count_0_D : STD_LOGIC; + signal count_0_D1 : STD_LOGIC; + signal count_0_D2 : STD_LOGIC; + signal count_0_D2_PT_0 : STD_LOGIC; + signal count_0_D2_PT_1 : STD_LOGIC; + signal count_0_D2_PT_2 : STD_LOGIC; + signal count_4_Q : STD_LOGIC; + signal count_4_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal count_4_EXP : STD_LOGIC; + signal count_4_D : STD_LOGIC; + signal count_4_tsimcreated_xor_Q : STD_LOGIC; + signal count_4_RSTF : STD_LOGIC; + signal count_4_SETF : STD_LOGIC; + signal count_4_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal count_4_tsimcreated_prld_Q : STD_LOGIC; + signal count_4_D1 : STD_LOGIC; + signal count_4_D2 : STD_LOGIC; + signal EXP19_EXP : STD_LOGIC; + signal count_4_D2_PT_0 : STD_LOGIC; + signal count_4_D2_PT_1 : STD_LOGIC; + signal count_4_D2_PT_2 : STD_LOGIC; + signal count_1_Q : STD_LOGIC; + signal count_1_RSTF : STD_LOGIC; + signal count_1_SETF : STD_LOGIC; + signal count_1_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal count_1_tsimcreated_prld_Q : STD_LOGIC; + signal count_1_D : STD_LOGIC; + signal count_1_D1 : STD_LOGIC; + signal count_1_D2 : STD_LOGIC; + signal count_5_EXP : STD_LOGIC; + signal count_1_D2_PT_0 : STD_LOGIC; + signal count_1_D2_PT_1 : STD_LOGIC; + signal count_1_D2_PT_2 : STD_LOGIC; + signal count_1_D2_PT_3 : STD_LOGIC; + signal count_2_Q : STD_LOGIC; + signal count_2_RSTF : STD_LOGIC; + signal count_2_SETF : STD_LOGIC; + signal count_2_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal count_2_tsimcreated_prld_Q : STD_LOGIC; + signal count_2_D : STD_LOGIC; + signal count_2_D1 : STD_LOGIC; + signal count_2_D2 : STD_LOGIC; + signal count_2_D2_PT_0 : STD_LOGIC; + signal count_3_EXP : STD_LOGIC; + signal count_2_D2_PT_1 : STD_LOGIC; + signal count_2_D2_PT_2 : STD_LOGIC; + signal count_2_D2_PT_3 : STD_LOGIC; + signal count_2_D2_PT_4 : STD_LOGIC; + signal count_3_Q : STD_LOGIC; + signal count_3_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal count_3_RSTF : STD_LOGIC; + signal count_3_SETF : STD_LOGIC; + signal count_3_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal count_3_tsimcreated_prld_Q : STD_LOGIC; + signal count_3_D : STD_LOGIC; + signal count_3_D1 : STD_LOGIC; + signal count_3_D2 : STD_LOGIC; + signal EXP20_EXP : STD_LOGIC; + signal count_3_D2_PT_0 : STD_LOGIC; + signal count_3_D2_PT_1 : STD_LOGIC; + signal count_3_D2_PT_2 : STD_LOGIC; + signal REG_0_Q : STD_LOGIC; + signal REG_0_D : STD_LOGIC; + signal REG_0_tsimcreated_xor_Q : STD_LOGIC; + signal REG_0_RSTF : STD_LOGIC; + signal REG_0_SETF : STD_LOGIC; + signal REG_0_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_0_tsimcreated_prld_Q : STD_LOGIC; + signal REG_0_CLKF : STD_LOGIC; + signal REG_0_D1 : STD_LOGIC; + signal REG_0_D2 : STD_LOGIC; + signal REG_10_Q : STD_LOGIC; + signal REG_10_D : STD_LOGIC; + signal REG_10_tsimcreated_xor_Q : STD_LOGIC; + signal REG_10_RSTF : STD_LOGIC; + signal REG_10_SETF : STD_LOGIC; + signal REG_10_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_10_tsimcreated_prld_Q : STD_LOGIC; + signal REG_10_CLKF : STD_LOGIC; + signal REG_10_D1 : STD_LOGIC; + signal REG_10_D2 : STD_LOGIC; + signal REG_10_D2_PT_0 : STD_LOGIC; + signal REG_10_D2_PT_1 : STD_LOGIC; + signal REG_11_Q : STD_LOGIC; + signal REG_11_D : STD_LOGIC; + signal REG_11_tsimcreated_xor_Q : STD_LOGIC; + signal REG_11_RSTF : STD_LOGIC; + signal REG_11_SETF : STD_LOGIC; + signal REG_11_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_11_tsimcreated_prld_Q : STD_LOGIC; + signal REG_11_CLKF : STD_LOGIC; + signal REG_11_D1 : STD_LOGIC; + signal REG_11_D2 : STD_LOGIC; + signal REG_11_D2_PT_0 : STD_LOGIC; + signal REG_11_D2_PT_1 : STD_LOGIC; + signal REG_12_Q : STD_LOGIC; + signal REG_12_D : STD_LOGIC; + signal REG_12_tsimcreated_xor_Q : STD_LOGIC; + signal REG_12_RSTF : STD_LOGIC; + signal REG_12_SETF : STD_LOGIC; + signal REG_12_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_12_tsimcreated_prld_Q : STD_LOGIC; + signal REG_12_CLKF : STD_LOGIC; + signal REG_12_D1 : STD_LOGIC; + signal REG_12_D2 : STD_LOGIC; + signal REG_12_D2_PT_0 : STD_LOGIC; + signal REG_12_D2_PT_1 : STD_LOGIC; + signal REG_13_Q : STD_LOGIC; + signal REG_13_D : STD_LOGIC; + signal REG_13_tsimcreated_xor_Q : STD_LOGIC; + signal REG_13_RSTF : STD_LOGIC; + signal REG_13_SETF : STD_LOGIC; + signal REG_13_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_13_tsimcreated_prld_Q : STD_LOGIC; + signal REG_13_CLKF : STD_LOGIC; + signal REG_13_D1 : STD_LOGIC; + signal REG_13_D2 : STD_LOGIC; + signal REG_13_D2_PT_0 : STD_LOGIC; + signal REG_13_D2_PT_1 : STD_LOGIC; + signal REG_14_Q : STD_LOGIC; + signal REG_14_D : STD_LOGIC; + signal REG_14_tsimcreated_xor_Q : STD_LOGIC; + signal REG_14_RSTF : STD_LOGIC; + signal REG_14_SETF : STD_LOGIC; + signal REG_14_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_14_tsimcreated_prld_Q : STD_LOGIC; + signal REG_14_CLKF : STD_LOGIC; + signal REG_14_D1 : STD_LOGIC; + signal REG_14_D2 : STD_LOGIC; + signal REG_14_D2_PT_0 : STD_LOGIC; + signal REG_14_D2_PT_1 : STD_LOGIC; + signal REG_15_Q : STD_LOGIC; + signal REG_15_D : STD_LOGIC; + signal REG_15_tsimcreated_xor_Q : STD_LOGIC; + signal REG_15_RSTF : STD_LOGIC; + signal REG_15_SETF : STD_LOGIC; + signal REG_15_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_15_tsimcreated_prld_Q : STD_LOGIC; + signal REG_15_CLKF : STD_LOGIC; + signal REG_15_D1 : STD_LOGIC; + signal REG_15_D2 : STD_LOGIC; + signal REG_15_D2_PT_0 : STD_LOGIC; + signal REG_15_D2_PT_1 : STD_LOGIC; + signal REG_16_Q : STD_LOGIC; + signal REG_16_D : STD_LOGIC; + signal REG_16_tsimcreated_xor_Q : STD_LOGIC; + signal REG_16_RSTF : STD_LOGIC; + signal REG_16_SETF : STD_LOGIC; + signal REG_16_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_16_tsimcreated_prld_Q : STD_LOGIC; + signal REG_16_CLKF : STD_LOGIC; + signal REG_16_D1 : STD_LOGIC; + signal REG_16_D2 : STD_LOGIC; + signal REG_16_D2_PT_0 : STD_LOGIC; + signal REG_16_D2_PT_1 : STD_LOGIC; + signal REG_17_Q : STD_LOGIC; + signal REG_17_D : STD_LOGIC; + signal REG_17_tsimcreated_xor_Q : STD_LOGIC; + signal REG_17_RSTF : STD_LOGIC; + signal REG_17_SETF : STD_LOGIC; + signal REG_17_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_17_tsimcreated_prld_Q : STD_LOGIC; + signal REG_17_CLKF : STD_LOGIC; + signal REG_17_D1 : STD_LOGIC; + signal REG_17_D2 : STD_LOGIC; + signal REG_17_D2_PT_0 : STD_LOGIC; + signal REG_17_D2_PT_1 : STD_LOGIC; + signal REG_18_Q : STD_LOGIC; + signal REG_18_D : STD_LOGIC; + signal REG_18_tsimcreated_xor_Q : STD_LOGIC; + signal REG_18_RSTF : STD_LOGIC; + signal REG_18_SETF : STD_LOGIC; + signal REG_18_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_18_tsimcreated_prld_Q : STD_LOGIC; + signal REG_18_CLKF : STD_LOGIC; + signal REG_18_D1 : STD_LOGIC; + signal REG_18_D2 : STD_LOGIC; + signal REG_18_D2_PT_0 : STD_LOGIC; + signal REG_18_D2_PT_1 : STD_LOGIC; + signal REG_19_Q : STD_LOGIC; + signal REG_19_D : STD_LOGIC; + signal REG_19_tsimcreated_xor_Q : STD_LOGIC; + signal REG_19_RSTF : STD_LOGIC; + signal REG_19_SETF : STD_LOGIC; + signal REG_19_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_19_tsimcreated_prld_Q : STD_LOGIC; + signal REG_19_CLKF : STD_LOGIC; + signal REG_19_D1 : STD_LOGIC; + signal REG_19_D2 : STD_LOGIC; + signal REG_19_D2_PT_0 : STD_LOGIC; + signal REG_19_D2_PT_1 : STD_LOGIC; + signal REG_1_Q : STD_LOGIC; + signal REG_1_D : STD_LOGIC; + signal REG_1_tsimcreated_xor_Q : STD_LOGIC; + signal REG_1_RSTF : STD_LOGIC; + signal REG_1_SETF : STD_LOGIC; + signal REG_1_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_1_tsimcreated_prld_Q : STD_LOGIC; + signal REG_1_CLKF : STD_LOGIC; + signal REG_1_D1 : STD_LOGIC; + signal REG_1_D2 : STD_LOGIC; + signal REG_1_D2_PT_0 : STD_LOGIC; + signal REG_1_D2_PT_1 : STD_LOGIC; + signal REG_20_Q : STD_LOGIC; + signal REG_20_D : STD_LOGIC; + signal REG_20_tsimcreated_xor_Q : STD_LOGIC; + signal REG_20_RSTF : STD_LOGIC; + signal REG_20_SETF : STD_LOGIC; + signal REG_20_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_20_tsimcreated_prld_Q : STD_LOGIC; + signal REG_20_CLKF : STD_LOGIC; + signal REG_20_D1 : STD_LOGIC; + signal REG_20_D2 : STD_LOGIC; + signal REG_20_D2_PT_0 : STD_LOGIC; + signal REG_20_D2_PT_1 : STD_LOGIC; + signal REG_21_Q : STD_LOGIC; + signal REG_21_D : STD_LOGIC; + signal REG_21_tsimcreated_xor_Q : STD_LOGIC; + signal REG_21_RSTF : STD_LOGIC; + signal REG_21_SETF : STD_LOGIC; + signal REG_21_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_21_tsimcreated_prld_Q : STD_LOGIC; + signal REG_21_CLKF : STD_LOGIC; + signal REG_21_D1 : STD_LOGIC; + signal REG_21_D2 : STD_LOGIC; + signal REG_21_D2_PT_0 : STD_LOGIC; + signal REG_21_D2_PT_1 : STD_LOGIC; + signal REG_22_Q : STD_LOGIC; + signal REG_22_D : STD_LOGIC; + signal REG_22_tsimcreated_xor_Q : STD_LOGIC; + signal REG_22_RSTF : STD_LOGIC; + signal REG_22_SETF : STD_LOGIC; + signal REG_22_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_22_tsimcreated_prld_Q : STD_LOGIC; + signal REG_22_CLKF : STD_LOGIC; + signal REG_22_D1 : STD_LOGIC; + signal REG_22_D2 : STD_LOGIC; + signal REG_22_D2_PT_0 : STD_LOGIC; + signal REG_22_D2_PT_1 : STD_LOGIC; + signal REG_23_Q : STD_LOGIC; + signal REG_23_D : STD_LOGIC; + signal REG_23_tsimcreated_xor_Q : STD_LOGIC; + signal REG_23_RSTF : STD_LOGIC; + signal REG_23_SETF : STD_LOGIC; + signal REG_23_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_23_tsimcreated_prld_Q : STD_LOGIC; + signal REG_23_CLKF : STD_LOGIC; + signal REG_23_D1 : STD_LOGIC; + signal REG_23_D2 : STD_LOGIC; + signal REG_23_D2_PT_0 : STD_LOGIC; + signal REG_23_D2_PT_1 : STD_LOGIC; + signal REG_24_Q : STD_LOGIC; + signal REG_24_D : STD_LOGIC; + signal REG_24_tsimcreated_xor_Q : STD_LOGIC; + signal REG_24_RSTF : STD_LOGIC; + signal REG_24_SETF : STD_LOGIC; + signal REG_24_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_24_tsimcreated_prld_Q : STD_LOGIC; + signal REG_24_CLKF : STD_LOGIC; + signal REG_24_D1 : STD_LOGIC; + signal REG_24_D2 : STD_LOGIC; + signal REG_24_D2_PT_0 : STD_LOGIC; + signal REG_24_D2_PT_1 : STD_LOGIC; + signal REG_25_Q : STD_LOGIC; + signal REG_25_D : STD_LOGIC; + signal REG_25_tsimcreated_xor_Q : STD_LOGIC; + signal REG_25_RSTF : STD_LOGIC; + signal REG_25_SETF : STD_LOGIC; + signal REG_25_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_25_tsimcreated_prld_Q : STD_LOGIC; + signal REG_25_CLKF : STD_LOGIC; + signal REG_25_D1 : STD_LOGIC; + signal REG_25_D2 : STD_LOGIC; + signal REG_25_D2_PT_0 : STD_LOGIC; + signal REG_25_D2_PT_1 : STD_LOGIC; + signal REG_26_Q : STD_LOGIC; + signal REG_26_D : STD_LOGIC; + signal REG_26_tsimcreated_xor_Q : STD_LOGIC; + signal REG_26_RSTF : STD_LOGIC; + signal REG_26_SETF : STD_LOGIC; + signal REG_26_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_26_tsimcreated_prld_Q : STD_LOGIC; + signal REG_26_CLKF : STD_LOGIC; + signal REG_26_D1 : STD_LOGIC; + signal REG_26_D2 : STD_LOGIC; + signal REG_26_D2_PT_0 : STD_LOGIC; + signal REG_26_D2_PT_1 : STD_LOGIC; + signal REG_27_Q : STD_LOGIC; + signal REG_27_D : STD_LOGIC; + signal REG_27_tsimcreated_xor_Q : STD_LOGIC; + signal REG_27_RSTF : STD_LOGIC; + signal REG_27_SETF : STD_LOGIC; + signal REG_27_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_27_tsimcreated_prld_Q : STD_LOGIC; + signal REG_27_CLKF : STD_LOGIC; + signal REG_27_D1 : STD_LOGIC; + signal REG_27_D2 : STD_LOGIC; + signal REG_27_D2_PT_0 : STD_LOGIC; + signal REG_27_D2_PT_1 : STD_LOGIC; + signal REG_28_Q : STD_LOGIC; + signal REG_28_D : STD_LOGIC; + signal REG_28_tsimcreated_xor_Q : STD_LOGIC; + signal REG_28_RSTF : STD_LOGIC; + signal REG_28_SETF : STD_LOGIC; + signal REG_28_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_28_tsimcreated_prld_Q : STD_LOGIC; + signal REG_28_CLKF : STD_LOGIC; + signal REG_28_D1 : STD_LOGIC; + signal REG_28_D2 : STD_LOGIC; + signal REG_28_D2_PT_0 : STD_LOGIC; + signal REG_28_D2_PT_1 : STD_LOGIC; + signal REG_29_Q : STD_LOGIC; + signal REG_29_D : STD_LOGIC; + signal REG_29_tsimcreated_xor_Q : STD_LOGIC; + signal REG_29_RSTF : STD_LOGIC; + signal REG_29_SETF : STD_LOGIC; + signal REG_29_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_29_tsimcreated_prld_Q : STD_LOGIC; + signal REG_29_CLKF : STD_LOGIC; + signal REG_29_D1 : STD_LOGIC; + signal REG_29_D2 : STD_LOGIC; + signal REG_29_D2_PT_0 : STD_LOGIC; + signal REG_29_D2_PT_1 : STD_LOGIC; + signal REG_2_Q : STD_LOGIC; + signal REG_2_D : STD_LOGIC; + signal REG_2_tsimcreated_xor_Q : STD_LOGIC; + signal REG_2_RSTF : STD_LOGIC; + signal REG_2_SETF : STD_LOGIC; + signal REG_2_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_2_tsimcreated_prld_Q : STD_LOGIC; + signal REG_2_CLKF : STD_LOGIC; + signal REG_2_D1 : STD_LOGIC; + signal REG_2_D2 : STD_LOGIC; + signal REG_2_D2_PT_0 : STD_LOGIC; + signal REG_2_D2_PT_1 : STD_LOGIC; + signal REG_30_Q : STD_LOGIC; + signal REG_30_D : STD_LOGIC; + signal REG_30_tsimcreated_xor_Q : STD_LOGIC; + signal REG_30_RSTF : STD_LOGIC; + signal REG_30_SETF : STD_LOGIC; + signal REG_30_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_30_tsimcreated_prld_Q : STD_LOGIC; + signal REG_30_CLKF : STD_LOGIC; + signal REG_30_D1 : STD_LOGIC; + signal REG_30_D2 : STD_LOGIC; + signal REG_30_D2_PT_0 : STD_LOGIC; + signal REG_30_D2_PT_1 : STD_LOGIC; + signal REG_3_Q : STD_LOGIC; + signal REG_3_D : STD_LOGIC; + signal REG_3_tsimcreated_xor_Q : STD_LOGIC; + signal REG_3_RSTF : STD_LOGIC; + signal REG_3_SETF : STD_LOGIC; + signal REG_3_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_3_tsimcreated_prld_Q : STD_LOGIC; + signal REG_3_CLKF : STD_LOGIC; + signal REG_3_D1 : STD_LOGIC; + signal REG_3_D2 : STD_LOGIC; + signal REG_3_D2_PT_0 : STD_LOGIC; + signal REG_3_D2_PT_1 : STD_LOGIC; + signal REG_4_Q : STD_LOGIC; + signal REG_4_D : STD_LOGIC; + signal REG_4_tsimcreated_xor_Q : STD_LOGIC; + signal REG_4_RSTF : STD_LOGIC; + signal REG_4_SETF : STD_LOGIC; + signal REG_4_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_4_tsimcreated_prld_Q : STD_LOGIC; + signal REG_4_CLKF : STD_LOGIC; + signal REG_4_D1 : STD_LOGIC; + signal REG_4_D2 : STD_LOGIC; + signal REG_4_D2_PT_0 : STD_LOGIC; + signal REG_4_D2_PT_1 : STD_LOGIC; + signal REG_5_Q : STD_LOGIC; + signal REG_5_D : STD_LOGIC; + signal REG_5_tsimcreated_xor_Q : STD_LOGIC; + signal REG_5_RSTF : STD_LOGIC; + signal REG_5_SETF : STD_LOGIC; + signal REG_5_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_5_tsimcreated_prld_Q : STD_LOGIC; + signal REG_5_CLKF : STD_LOGIC; + signal REG_5_D1 : STD_LOGIC; + signal REG_5_D2 : STD_LOGIC; + signal REG_5_D2_PT_0 : STD_LOGIC; + signal REG_5_D2_PT_1 : STD_LOGIC; + signal REG_6_Q : STD_LOGIC; + signal REG_6_D : STD_LOGIC; + signal REG_6_tsimcreated_xor_Q : STD_LOGIC; + signal REG_6_RSTF : STD_LOGIC; + signal REG_6_SETF : STD_LOGIC; + signal REG_6_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_6_tsimcreated_prld_Q : STD_LOGIC; + signal REG_6_CLKF : STD_LOGIC; + signal REG_6_D1 : STD_LOGIC; + signal REG_6_D2 : STD_LOGIC; + signal REG_6_D2_PT_0 : STD_LOGIC; + signal REG_6_D2_PT_1 : STD_LOGIC; + signal REG_7_Q : STD_LOGIC; + signal REG_7_D : STD_LOGIC; + signal REG_7_tsimcreated_xor_Q : STD_LOGIC; + signal REG_7_RSTF : STD_LOGIC; + signal REG_7_SETF : STD_LOGIC; + signal REG_7_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_7_tsimcreated_prld_Q : STD_LOGIC; + signal REG_7_CLKF : STD_LOGIC; + signal REG_7_D1 : STD_LOGIC; + signal REG_7_D2 : STD_LOGIC; + signal REG_7_D2_PT_0 : STD_LOGIC; + signal REG_7_D2_PT_1 : STD_LOGIC; + signal REG_8_Q : STD_LOGIC; + signal REG_8_D : STD_LOGIC; + signal REG_8_tsimcreated_xor_Q : STD_LOGIC; + signal REG_8_RSTF : STD_LOGIC; + signal REG_8_SETF : STD_LOGIC; + signal REG_8_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_8_tsimcreated_prld_Q : STD_LOGIC; + signal REG_8_CLKF : STD_LOGIC; + signal REG_8_D1 : STD_LOGIC; + signal REG_8_D2 : STD_LOGIC; + signal REG_8_D2_PT_0 : STD_LOGIC; + signal REG_8_D2_PT_1 : STD_LOGIC; + signal REG_9_Q : STD_LOGIC; + signal REG_9_D : STD_LOGIC; + signal REG_9_tsimcreated_xor_Q : STD_LOGIC; + signal REG_9_RSTF : STD_LOGIC; + signal REG_9_SETF : STD_LOGIC; + signal REG_9_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_9_tsimcreated_prld_Q : STD_LOGIC; + signal REG_9_CLKF : STD_LOGIC; + signal REG_9_D1 : STD_LOGIC; + signal REG_9_D2 : STD_LOGIC; + signal REG_9_D2_PT_0 : STD_LOGIC; + signal REG_9_D2_PT_1 : STD_LOGIC; + signal count_5_Q : STD_LOGIC; + signal count_5_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal count_5_D : STD_LOGIC; + signal count_5_tsimcreated_xor_Q : STD_LOGIC; + signal count_5_RSTF : STD_LOGIC; + signal count_5_SETF : STD_LOGIC; + signal count_5_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal count_5_tsimcreated_prld_Q : STD_LOGIC; + signal count_5_D1 : STD_LOGIC; + signal count_5_D2 : STD_LOGIC; + signal EXP18_EXP : STD_LOGIC; + signal count_5_D2_PT_0 : STD_LOGIC; + signal count_5_D2_PT_1 : STD_LOGIC; + signal count_5_D2_PT_2 : STD_LOGIC; + signal SREG_IS_EMPTY_Q : STD_LOGIC; + signal SREG_IS_EMPTY_RSTF : STD_LOGIC; + signal SREG_IS_EMPTY_SETF : STD_LOGIC; + signal SREG_IS_EMPTY_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal SREG_IS_EMPTY_tsimcreated_prld_Q : STD_LOGIC; + signal SREG_IS_EMPTY_D : STD_LOGIC; + signal SREG_IS_EMPTY_CLKF : STD_LOGIC; + signal SREG_IS_EMPTY_D1 : STD_LOGIC; + signal SREG_IS_EMPTY_D2 : STD_LOGIC; + signal SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_UIM : STD_LOGIC; + signal SHIFT_CNT_0_Q : STD_LOGIC; + signal SHIFT_CNT_0_RSTF : STD_LOGIC; + signal SHIFT_CNT_0_SETF : STD_LOGIC; + signal SHIFT_CNT_0_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal SHIFT_CNT_0_tsimcreated_prld_Q : STD_LOGIC; + signal SHIFT_CNT_0_D : STD_LOGIC; + signal SHIFT_CNT_0_CLKF : STD_LOGIC; + signal SHIFT_CNT_0_D1 : STD_LOGIC; + signal SHIFT_CNT_0_D2 : STD_LOGIC; + signal SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_UIM : STD_LOGIC; + signal SHIFT_CNT_1_Q : STD_LOGIC; + signal SHIFT_CNT_1_RSTF : STD_LOGIC; + signal SHIFT_CNT_1_SETF : STD_LOGIC; + signal SHIFT_CNT_1_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal SHIFT_CNT_1_tsimcreated_prld_Q : STD_LOGIC; + signal SHIFT_CNT_1_D : STD_LOGIC; + signal SHIFT_CNT_1_CLKF : STD_LOGIC; + signal SHIFT_CNT_1_D1 : STD_LOGIC; + signal SHIFT_CNT_1_D2 : STD_LOGIC; + signal SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_UIM : STD_LOGIC; + signal Msub_n0025_n00002_Msub_n0025_n00002_D2_UIM : STD_LOGIC; + signal Q_OpTx_OpTx_FX_DC_18_INV_124_UIM : STD_LOGIC; + signal SHIFT_CNT_2_Q : STD_LOGIC; + signal SHIFT_CNT_2_RSTF : STD_LOGIC; + signal SHIFT_CNT_2_SETF : STD_LOGIC; + signal SHIFT_CNT_2_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal SHIFT_CNT_2_tsimcreated_prld_Q : STD_LOGIC; + signal SHIFT_CNT_2_D : STD_LOGIC; + signal SHIFT_CNT_2_CLKF : STD_LOGIC; + signal SHIFT_CNT_2_D1 : STD_LOGIC; + signal SHIFT_CNT_2_D2 : STD_LOGIC; + signal SHIFT_CNT_2_SHIFT_CNT_2_RSTF_UIM : STD_LOGIC; + signal Q_OpTx_OpTx_FX_DC_23_INV_125_UIM : STD_LOGIC; + signal SHIFT_CNT_3_Q : STD_LOGIC; + signal SHIFT_CNT_3_RSTF : STD_LOGIC; + signal SHIFT_CNT_3_SETF : STD_LOGIC; + signal SHIFT_CNT_3_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal SHIFT_CNT_3_tsimcreated_prld_Q : STD_LOGIC; + signal SHIFT_CNT_3_D : STD_LOGIC; + signal SHIFT_CNT_3_CLKF : STD_LOGIC; + signal SHIFT_CNT_3_D1 : STD_LOGIC; + signal SHIFT_CNT_3_D2 : STD_LOGIC; + signal SHIFT_CNT_3_SHIFT_CNT_3_RSTF_UIM : STD_LOGIC; + signal Msub_n0025_n00022_Msub_n0025_n00022_D2_UIM : STD_LOGIC; + signal Q_OpTx_FX_DC_20_UIM : STD_LOGIC; + signal SHIFT_CNT_4_Q : STD_LOGIC; + signal SHIFT_CNT_4_RSTF : STD_LOGIC; + signal SHIFT_CNT_4_SETF : STD_LOGIC; + signal SHIFT_CNT_4_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal SHIFT_CNT_4_tsimcreated_prld_Q : STD_LOGIC; + signal SHIFT_CNT_4_D : STD_LOGIC; + signal SHIFT_CNT_4_CLKF : STD_LOGIC; + signal SHIFT_CNT_4_D1 : STD_LOGIC; + signal SHIFT_CNT_4_D2 : STD_LOGIC; + signal SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_UIM : STD_LOGIC; + signal Q_OpTx_FX_DC_21_UIM : STD_LOGIC; + signal Q_OpTx_OpTx_FX_SC_22_INV_126_UIM : STD_LOGIC; + signal VCLK_OBUF_Q_1 : STD_LOGIC; + signal VCLK_OBUF_D : STD_LOGIC; + signal VCLK_OBUF_tsimcreated_xor_Q : STD_LOGIC; + signal VCLK_OBUF_RSTF : STD_LOGIC; + signal VCLK_OBUF_CE : STD_LOGIC; + signal VCLK_OBUF_D1 : STD_LOGIC; + signal VCLK_OBUF_D2 : STD_LOGIC; + signal SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_Q : STD_LOGIC; + signal SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D : STD_LOGIC; + signal SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D1 : STD_LOGIC; + signal SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2 : STD_LOGIC; + signal SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_0 : STD_LOGIC; + signal SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1 : STD_LOGIC; + signal SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_Q : STD_LOGIC; + signal SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D : STD_LOGIC; + signal SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D1 : STD_LOGIC; + signal SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2 : STD_LOGIC; + signal SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_0 : STD_LOGIC; + signal SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_1 : STD_LOGIC; + signal SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_2 : STD_LOGIC; + signal SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3 : STD_LOGIC; + signal SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_Q : STD_LOGIC; + signal SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D : STD_LOGIC; + signal SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D1 : STD_LOGIC; + signal SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2 : STD_LOGIC; + signal SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_0 : STD_LOGIC; + signal SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_1 : STD_LOGIC; + signal SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_2 : STD_LOGIC; + signal SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_3 : STD_LOGIC; + signal SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4 : STD_LOGIC; + signal Msub_n0025_n00002_Msub_n0025_n00002_D2_Q : STD_LOGIC; + signal Msub_n0025_n00002_Msub_n0025_n00002_D2_D : STD_LOGIC; + signal Msub_n0025_n00002_Msub_n0025_n00002_D2_D1 : STD_LOGIC; + signal Msub_n0025_n00002_Msub_n0025_n00002_D2_D2 : STD_LOGIC; + signal Q_OpTx_OpTx_FX_DC_18_INV_124_Q : STD_LOGIC; + signal Q_OpTx_OpTx_FX_DC_18_INV_124_D : STD_LOGIC; + signal Q_OpTx_OpTx_FX_DC_18_INV_124_D1 : STD_LOGIC; + signal Q_OpTx_OpTx_FX_DC_18_INV_124_D2 : STD_LOGIC; + signal SHIFT_CNT_2_SHIFT_CNT_2_RSTF_Q : STD_LOGIC; + signal SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D : STD_LOGIC; + signal SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D1 : STD_LOGIC; + signal SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2 : STD_LOGIC; + signal SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_0 : STD_LOGIC; + signal SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_1 : STD_LOGIC; + signal SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_2 : STD_LOGIC; + signal Q_OpTx_OpTx_FX_DC_23_INV_125_Q : STD_LOGIC; + signal Q_OpTx_OpTx_FX_DC_23_INV_125_D : STD_LOGIC; + signal Q_OpTx_OpTx_FX_DC_23_INV_125_D1 : STD_LOGIC; + signal Q_OpTx_OpTx_FX_DC_23_INV_125_D2 : STD_LOGIC; + signal Q_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_0 : STD_LOGIC; + signal Q_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_1 : STD_LOGIC; + signal Q_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2 : STD_LOGIC; + signal SHIFT_CNT_3_SHIFT_CNT_3_RSTF_Q : STD_LOGIC; + signal SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D : STD_LOGIC; + signal SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D1 : STD_LOGIC; + signal SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2 : STD_LOGIC; + signal SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_0 : STD_LOGIC; + signal SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_1 : STD_LOGIC; + signal SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_2 : STD_LOGIC; + signal SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3 : STD_LOGIC; + signal Msub_n0025_n00022_Msub_n0025_n00022_D2_Q : STD_LOGIC; + signal Msub_n0025_n00022_Msub_n0025_n00022_D2_D : STD_LOGIC; + signal Msub_n0025_n00022_Msub_n0025_n00022_D2_D1 : STD_LOGIC; + signal Msub_n0025_n00022_Msub_n0025_n00022_D2_D2 : STD_LOGIC; + signal Q_OpTx_FX_DC_20_Q : STD_LOGIC; + signal Q_OpTx_FX_DC_20_D : STD_LOGIC; + signal Q_OpTx_FX_DC_20_D1 : STD_LOGIC; + signal Q_OpTx_FX_DC_20_D2 : STD_LOGIC; + signal Q_OpTx_FX_DC_20_D2_PT_0 : STD_LOGIC; + signal Q_OpTx_FX_DC_20_D2_PT_1 : STD_LOGIC; + signal SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_Q : STD_LOGIC; + signal SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D : STD_LOGIC; + signal SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D1 : STD_LOGIC; + signal SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2 : STD_LOGIC; + signal SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_0 : STD_LOGIC; + signal SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_1 : STD_LOGIC; + signal SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_2 : STD_LOGIC; + signal SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3 : STD_LOGIC; + signal Q_OpTx_FX_DC_21_Q : STD_LOGIC; + signal Q_OpTx_FX_DC_21_D : STD_LOGIC; + signal Q_OpTx_FX_DC_21_D1 : STD_LOGIC; + signal Q_OpTx_FX_DC_21_D2 : STD_LOGIC; + signal Q_OpTx_FX_DC_21_D2_PT_0 : STD_LOGIC; + signal Q_OpTx_FX_DC_21_D2_PT_1 : STD_LOGIC; + signal Q_OpTx_OpTx_FX_SC_22_INV_126_Q : STD_LOGIC; + signal Q_OpTx_OpTx_FX_SC_22_INV_126_D : STD_LOGIC; + signal Q_OpTx_OpTx_FX_SC_22_INV_126_D1 : STD_LOGIC; + signal Q_OpTx_OpTx_FX_SC_22_INV_126_D2 : STD_LOGIC; + signal Q_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_0 : STD_LOGIC; + signal Q_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_1 : STD_LOGIC; + signal Q_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_2 : STD_LOGIC; + signal Q_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3 : STD_LOGIC; + signal EXP18_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP18_EXP_PT_0 : STD_LOGIC; + signal EXP18_EXP_PT_1 : STD_LOGIC; + signal EXP19_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP19_EXP_PT_0 : STD_LOGIC; + signal EXP19_EXP_PT_1 : STD_LOGIC; + signal EXP19_EXP_PT_2 : STD_LOGIC; + signal EXP20_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP20_EXP_PT_0 : STD_LOGIC; + signal EXP20_EXP_PT_1 : STD_LOGIC; + signal EXP20_EXP_PT_2 : STD_LOGIC; + signal EXP20_EXP_PT_3 : STD_LOGIC; + signal NlwInverterSignal_REG_31_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_31_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_31_D2_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_31_D2_PT_0_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_31_D2_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_31_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_31_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_31_D2_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_31_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_31_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_31_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_31_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_EN_D2_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_EN_D2_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_EN_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_EN_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_EN_CE_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_EN_CE_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_0_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_0_D_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_0_D2_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_0_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_0_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_0_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_0_D2_PT_2_IN2 : STD_LOGIC; + signal NlwInverterSignal_count_0_D2_PT_2_IN3 : STD_LOGIC; + signal NlwInverterSignal_count_0_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_count_0_D2_PT_2_IN5 : STD_LOGIC; + signal NlwInverterSignal_count_0_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_4_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_4_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_4_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_4_D2_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_count_4_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_count_4_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_count_4_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_4_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_4_D2_PT_2_IN2 : STD_LOGIC; + signal NlwInverterSignal_count_4_D2_PT_2_IN3 : STD_LOGIC; + signal NlwInverterSignal_count_4_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_count_4_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_4_EXP_tsimrenamed_net_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_4_EXP_tsimrenamed_net_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_4_EXP_tsimrenamed_net_IN2 : STD_LOGIC; + signal NlwInverterSignal_count_1_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_1_D_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_1_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_1_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_1_D2_PT_2_IN2 : STD_LOGIC; + signal NlwInverterSignal_count_1_D2_PT_3_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_1_D2_PT_3_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_1_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_2_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_2_D_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_2_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_2_D2_PT_3_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_2_D2_PT_3_IN2 : STD_LOGIC; + signal NlwInverterSignal_count_2_D2_PT_4_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_2_D2_PT_4_IN2 : STD_LOGIC; + signal NlwInverterSignal_count_2_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_3_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_3_D_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_3_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_3_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_3_D2_PT_2_IN2 : STD_LOGIC; + signal NlwInverterSignal_count_3_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_3_EXP_tsimrenamed_net_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_3_EXP_tsimrenamed_net_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_3_EXP_tsimrenamed_net_IN2 : STD_LOGIC; + signal NlwInverterSignal_count_3_EXP_tsimrenamed_net_IN3 : STD_LOGIC; + signal NlwInverterSignal_count_3_EXP_tsimrenamed_net_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_0_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_D2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_D2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_D2_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_10_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_10_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_10_D2_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_10_D2_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_10_D2_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_10_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_10_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_10_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_10_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_10_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_10_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_10_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_11_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_11_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_11_D2_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_11_D2_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_11_D2_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_11_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_11_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_11_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_11_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_11_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_11_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_11_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_12_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_12_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_12_D2_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_12_D2_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_12_D2_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_12_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_12_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_12_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_12_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_12_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_12_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_12_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_13_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_13_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_13_D2_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_13_D2_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_13_D2_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_13_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_13_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_13_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_13_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_13_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_13_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_13_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_14_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_14_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_14_D2_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_14_D2_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_14_D2_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_14_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_14_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_14_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_14_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_14_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_14_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_14_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_15_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_15_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_15_D2_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_15_D2_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_15_D2_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_15_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_15_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_15_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_15_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_15_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_15_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_15_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_16_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_16_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_16_D2_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_16_D2_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_16_D2_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_16_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_16_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_16_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_16_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_16_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_16_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_16_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_17_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_17_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_17_D2_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_17_D2_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_17_D2_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_17_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_17_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_17_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_17_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_17_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_17_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_17_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_18_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_18_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_18_D2_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_18_D2_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_18_D2_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_18_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_18_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_18_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_18_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_18_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_18_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_18_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_19_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_19_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_19_D2_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_19_D2_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_19_D2_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_19_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_19_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_19_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_19_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_19_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_19_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_19_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_1_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_D2_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_D2_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_1_D2_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_1_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_1_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_1_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_20_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_20_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_20_D2_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_20_D2_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_20_D2_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_20_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_20_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_20_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_20_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_20_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_20_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_20_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_21_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_21_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_21_D2_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_21_D2_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_21_D2_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_21_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_21_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_21_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_21_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_21_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_21_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_21_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_22_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_22_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_22_D2_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_22_D2_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_22_D2_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_22_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_22_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_22_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_22_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_22_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_22_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_22_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_23_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_23_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_23_D2_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_23_D2_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_23_D2_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_23_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_23_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_23_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_23_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_23_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_23_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_23_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_24_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_24_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_24_D2_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_24_D2_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_24_D2_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_24_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_24_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_24_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_24_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_24_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_24_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_24_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_25_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_25_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_25_D2_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_25_D2_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_25_D2_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_25_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_25_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_25_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_25_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_25_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_25_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_25_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_26_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_26_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_26_D2_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_26_D2_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_26_D2_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_26_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_26_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_26_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_26_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_26_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_26_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_26_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_27_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_27_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_27_D2_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_27_D2_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_27_D2_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_27_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_27_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_27_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_27_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_27_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_27_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_27_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_28_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_28_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_28_D2_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_28_D2_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_28_D2_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_28_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_28_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_28_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_28_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_28_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_28_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_28_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_29_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_29_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_29_D2_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_29_D2_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_29_D2_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_29_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_29_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_29_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_29_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_29_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_29_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_29_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_2_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_2_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_2_D2_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_2_D2_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_2_D2_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_2_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_2_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_2_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_2_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_2_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_2_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_2_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_30_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_30_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_30_D2_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_30_D2_PT_0_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_30_D2_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_30_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_30_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_30_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_30_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_30_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_30_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_30_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_3_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_3_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_3_D2_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_3_D2_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_3_D2_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_3_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_3_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_3_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_3_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_3_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_3_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_3_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_4_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_4_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_4_D2_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_4_D2_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_4_D2_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_4_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_4_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_4_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_4_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_4_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_4_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_4_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_5_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_5_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_5_D2_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_5_D2_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_5_D2_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_5_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_5_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_5_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_5_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_5_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_5_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_5_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_6_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_6_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_6_D2_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_6_D2_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_6_D2_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_6_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_6_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_6_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_6_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_6_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_6_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_6_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_7_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_7_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_7_D2_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_7_D2_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_7_D2_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_7_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_7_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_7_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_7_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_7_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_7_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_7_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_8_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_8_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_8_D2_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_8_D2_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_8_D2_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_8_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_8_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_8_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_8_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_8_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_8_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_8_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_9_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_9_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_9_D2_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_9_D2_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_9_D2_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_9_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_9_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_9_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_9_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_9_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_9_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_9_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_count_5_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_5_D2_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_count_5_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_5_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_5_EXP_tsimrenamed_net_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_5_EXP_tsimrenamed_net_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_5_EXP_tsimrenamed_net_IN2 : STD_LOGIC; + signal NlwInverterSignal_count_5_EXP_tsimrenamed_net_IN3 : STD_LOGIC; + signal NlwInverterSignal_count_5_EXP_tsimrenamed_net_IN4 : STD_LOGIC; + signal NlwInverterSignal_count_5_EXP_tsimrenamed_net_IN5 : STD_LOGIC; + signal NlwInverterSignal_SREG_IS_EMPTY_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_SREG_IS_EMPTY_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_0_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_0_SETF_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_0_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_0_RSTF_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_0_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_1_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_1_SETF_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_1_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_1_RSTF_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_1_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_1_RSTF_IN3 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_1_RSTF_IN4 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_2_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_2_SETF_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_2_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_3_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_3_SETF_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_3_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_3_RSTF_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_3_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_3_RSTF_IN3 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_4_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_4_SETF_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_4_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_4_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_VCLK_OBUF_CE_IN0 : STD_LOGIC; + signal NlwInverterSignal_VCLK_OBUF_CE_IN1 : STD_LOGIC; + signal NlwInverterSignal_VCLK_OBUF_CE_IN2 : STD_LOGIC; + signal NlwInverterSignal_VCLK_OBUF_CE_IN3 : STD_LOGIC; + signal NlwInverterSignal_VCLK_OBUF_CE_IN4 : STD_LOGIC; + signal NlwInverterSignal_VCLK_OBUF_CE_IN5 : STD_LOGIC; + signal NlwInverterSignal_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN6 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_0_IN2 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN2 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN3 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN4 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN5 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_0_IN2 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_2_IN3 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_3_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_3_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_3_IN2 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN2 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN3 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN4 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN5 : STD_LOGIC; + signal NlwInverterSignal_Msub_n0025_n00002_Msub_n0025_n00002_D2_D2_IN0 : STD_LOGIC; + signal NlwInverterSignal_Msub_n0025_n00002_Msub_n0025_n00002_D2_D2_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_0_IN4 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_2_IN3 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_0_IN2 : STD_LOGIC; + signal NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN2 : STD_LOGIC; + signal NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN3 : STD_LOGIC; + signal NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN5 : STD_LOGIC; + signal NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN6 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_0_IN4 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3_IN3 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3_IN4 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3_IN5 : STD_LOGIC; + signal NlwInverterSignal_Msub_n0025_n00022_Msub_n0025_n00022_D2_D2_IN0 : STD_LOGIC; + signal NlwInverterSignal_Msub_n0025_n00022_Msub_n0025_n00022_D2_D2_IN1 : STD_LOGIC; + signal NlwInverterSignal_Msub_n0025_n00022_Msub_n0025_n00022_D2_D2_IN2 : STD_LOGIC; + signal NlwInverterSignal_Msub_n0025_n00022_Msub_n0025_n00022_D2_D2_IN3 : STD_LOGIC; + signal NlwInverterSignal_OpTx_FX_DC_20_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_OpTx_FX_DC_20_D2_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_OpTx_FX_DC_20_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_OpTx_FX_DC_20_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_OpTx_FX_DC_20_D2_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_0_IN2 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_2_IN2 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN2 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN3 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN4 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN5 : STD_LOGIC; + signal NlwInverterSignal_OpTx_FX_DC_21_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_OpTx_FX_DC_21_D2_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_OpTx_FX_DC_21_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_OpTx_FX_DC_21_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_OpTx_FX_DC_21_D2_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_OpTx_FX_DC_21_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3_IN0 : STD_LOGIC; + signal NlwInverterSignal_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3_IN1 : STD_LOGIC; + signal NlwInverterSignal_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3_IN2 : STD_LOGIC; + signal NlwInverterSignal_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3_IN3 : STD_LOGIC; + signal NlwInverterSignal_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP18_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP18_EXP_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_EXP18_EXP_PT_0_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP18_EXP_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_EXP18_EXP_PT_0_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP18_EXP_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP18_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP18_EXP_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_EXP18_EXP_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP18_EXP_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_EXP18_EXP_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP18_EXP_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP19_EXP_PT_0_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP19_EXP_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_EXP19_EXP_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP19_EXP_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_EXP19_EXP_PT_2_IN3 : STD_LOGIC; + signal NlwInverterSignal_EXP19_EXP_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP19_EXP_PT_2_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP20_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP20_EXP_PT_0_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP20_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP20_EXP_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP20_EXP_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP20_EXP_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_EXP20_EXP_PT_2_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP20_EXP_PT_2_IN3 : STD_LOGIC; + signal NlwInverterSignal_EXP20_EXP_PT_3_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP20_EXP_PT_3_IN1 : STD_LOGIC; + signal NlwInverterSignal_EXP20_EXP_PT_3_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP20_EXP_PT_3_IN3 : STD_LOGIC; + signal REG : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal count : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal SHIFT_CNT : STD_LOGIC_VECTOR ( 4 downto 0 ); +begin + FOEIO_1_2 : X_BUF + port map ( + I => nINIT_B, + O => FOEIO_1 + ); + LOAD_IBUF_3 : X_BUF + port map ( + I => LOAD, + O => LOAD_IBUF + ); + DIN_31_IBUF_4 : X_BUF + port map ( + I => DIN(31), + O => DIN_31_IBUF + ); + RES_IBUF_5 : X_BUF + port map ( + I => RES, + O => RES_IBUF + ); + DONE_IBUF_6 : X_BUF + port map ( + I => DONE, + O => DONE_IBUF + ); + FCLKIO_0_7 : X_BUF + port map ( + I => CLK, + O => FCLKIO_0 + ); + VCLK_PRESCALE_0_IBUF_8 : X_BUF + port map ( + I => VCLK_PRESCALE(0), + O => VCLK_PRESCALE_0_IBUF + ); + VCLK_PRESCALE_4_IBUF_9 : X_BUF + port map ( + I => VCLK_PRESCALE(4), + O => VCLK_PRESCALE_4_IBUF + ); + VCLK_PRESCALE_1_IBUF_10 : X_BUF + port map ( + I => VCLK_PRESCALE(1), + O => VCLK_PRESCALE_1_IBUF + ); + VCLK_PRESCALE_2_IBUF_11 : X_BUF + port map ( + I => VCLK_PRESCALE(2), + O => VCLK_PRESCALE_2_IBUF + ); + VCLK_PRESCALE_3_IBUF_12 : X_BUF + port map ( + I => VCLK_PRESCALE(3), + O => VCLK_PRESCALE_3_IBUF + ); + DIN_0_IBUF_13 : X_BUF + port map ( + I => DIN(0), + O => DIN_0_IBUF + ); + DIN_10_IBUF_14 : X_BUF + port map ( + I => DIN(10), + O => DIN_10_IBUF + ); + DIN_11_IBUF_15 : X_BUF + port map ( + I => DIN(11), + O => DIN_11_IBUF + ); + DIN_12_IBUF_16 : X_BUF + port map ( + I => DIN(12), + O => DIN_12_IBUF + ); + DIN_13_IBUF_17 : X_BUF + port map ( + I => DIN(13), + O => DIN_13_IBUF + ); + DIN_14_IBUF_18 : X_BUF + port map ( + I => DIN(14), + O => DIN_14_IBUF + ); + DIN_15_IBUF_19 : X_BUF + port map ( + I => DIN(15), + O => DIN_15_IBUF + ); + DIN_16_IBUF_20 : X_BUF + port map ( + I => DIN(16), + O => DIN_16_IBUF + ); + DIN_17_IBUF_21 : X_BUF + port map ( + I => DIN(17), + O => DIN_17_IBUF + ); + DIN_18_IBUF_22 : X_BUF + port map ( + I => DIN(18), + O => DIN_18_IBUF + ); + DIN_19_IBUF_23 : X_BUF + port map ( + I => DIN(19), + O => DIN_19_IBUF + ); + DIN_1_IBUF_24 : X_BUF + port map ( + I => DIN(1), + O => DIN_1_IBUF + ); + DIN_20_IBUF_25 : X_BUF + port map ( + I => DIN(20), + O => DIN_20_IBUF + ); + DIN_21_IBUF_26 : X_BUF + port map ( + I => DIN(21), + O => DIN_21_IBUF + ); + DIN_22_IBUF_27 : X_BUF + port map ( + I => DIN(22), + O => DIN_22_IBUF + ); + DIN_23_IBUF_28 : X_BUF + port map ( + I => DIN(23), + O => DIN_23_IBUF + ); + DIN_24_IBUF_29 : X_BUF + port map ( + I => DIN(24), + O => DIN_24_IBUF + ); + DIN_25_IBUF_30 : X_BUF + port map ( + I => DIN(25), + O => DIN_25_IBUF + ); + DIN_26_IBUF_31 : X_BUF + port map ( + I => DIN(26), + O => DIN_26_IBUF + ); + DIN_27_IBUF_32 : X_BUF + port map ( + I => DIN(27), + O => DIN_27_IBUF + ); + DIN_28_IBUF_33 : X_BUF + port map ( + I => DIN(28), + O => DIN_28_IBUF + ); + DIN_29_IBUF_34 : X_BUF + port map ( + I => DIN(29), + O => DIN_29_IBUF + ); + DIN_2_IBUF_35 : X_BUF + port map ( + I => DIN(2), + O => DIN_2_IBUF + ); + DIN_30_IBUF_36 : X_BUF + port map ( + I => DIN(30), + O => DIN_30_IBUF + ); + DIN_3_IBUF_37 : X_BUF + port map ( + I => DIN(3), + O => DIN_3_IBUF + ); + DIN_4_IBUF_38 : X_BUF + port map ( + I => DIN(4), + O => DIN_4_IBUF + ); + DIN_5_IBUF_39 : X_BUF + port map ( + I => DIN(5), + O => DIN_5_IBUF + ); + DIN_6_IBUF_40 : X_BUF + port map ( + I => DIN(6), + O => DIN_6_IBUF + ); + DIN_7_IBUF_41 : X_BUF + port map ( + I => DIN(7), + O => DIN_7_IBUF + ); + DIN_8_IBUF_42 : X_BUF + port map ( + I => DIN(8), + O => DIN_8_IBUF + ); + DIN_9_IBUF_43 : X_BUF + port map ( + I => DIN(9), + O => DIN_9_IBUF + ); + VCLK_PRESCALE_5_IBUF_44 : X_BUF + port map ( + I => VCLK_PRESCALE(5), + O => VCLK_PRESCALE_5_IBUF + ); + DOUT_45 : X_TRI + port map ( + I => REG_31_Q, + CTL => REG_31_OE, + O => DOUT + ); + VCLK_46 : X_BUF + port map ( + I => VCLK_OBUF_Q, + O => VCLK + ); + REG_31_Q_47 : X_BUF + port map ( + I => REG_31_Q_0, + O => REG_31_Q + ); + REG_31_Q_48 : X_BUF + port map ( + I => REG_31_Q_0, + O => REG(31) + ); + REG_31_OE_49 : X_BUF + port map ( + I => REG_31_BUFOE_OUT, + O => REG_31_OE + ); + REG_31_BUFOE_OUT_50 : X_BUF + port map ( + I => FOEIO_1, + O => REG_31_BUFOE_OUT + ); + REG_31_tsimcreated_xor_Q_51 : X_XOR2 + port map ( + I0 => REG_31_D, + I1 => REG_31_Q_0, + O => REG_31_tsimcreated_xor_Q + ); + REG_31_tsimcreated_set_and_noreset_Q_52 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_31_tsimcreated_set_and_noreset_IN0, + I1 => REG_31_SETF, + O => REG_31_tsimcreated_set_and_noreset_Q + ); + REG_31_tsimcreated_prld_Q_53 : X_OR2 + port map ( + I0 => REG_31_RSTF, + I1 => PRLD, + O => REG_31_tsimcreated_prld_Q + ); + REG_31_REG : X_FF + port map ( + I => REG_31_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_31_CLKF, + SET => REG_31_tsimcreated_set_and_noreset_Q, + RST => REG_31_tsimcreated_prld_Q, + O => REG_31_Q_0 + ); + Vcc_54 : X_ONE + port map ( + O => Vcc + ); + REG_31_D_55 : X_XOR2 + port map ( + I0 => REG_31_D1, + I1 => REG_31_D2, + O => REG_31_D + ); + REG_31_D1_56 : X_ZERO + port map ( + O => REG_31_D1 + ); + REG_31_D2_PT_0_57 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_31_D2_PT_0_IN0, + I1 => NlwInverterSignal_REG_31_D2_PT_0_IN1, + I2 => REG(31), + I3 => SHIFT_EN, + I4 => NlwInverterSignal_REG_31_D2_PT_0_IN4, + I5 => NlwInverterSignal_REG_31_D2_PT_0_IN5, + O => REG_31_D2_PT_0 + ); + REG_31_D2_PT_1_58 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_31_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_31_D2_PT_1_IN1, + I2 => NlwInverterSignal_REG_31_D2_PT_1_IN2, + I3 => SHIFT_EN, + I4 => REG(30), + I5 => NlwInverterSignal_REG_31_D2_PT_1_IN5, + O => REG_31_D2_PT_1 + ); + REG_31_D2_59 : X_OR2 + port map ( + I0 => REG_31_D2_PT_0, + I1 => REG_31_D2_PT_1, + O => REG_31_D2 + ); + REG_31_CLKF_60 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_31_CLKF_IN0, + I1 => NlwInverterSignal_REG_31_CLKF_IN1, + O => REG_31_CLKF + ); + REG_31_SETF_61 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => DIN_31_IBUF, + I2 => SREG_IS_EMPTY, + O => REG_31_SETF + ); + REG_31_RSTF_62 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => NlwInverterSignal_REG_31_RSTF_IN1, + I2 => SREG_IS_EMPTY, + O => REG_31_RSTF + ); + SHIFT_EN_63 : X_BUF + port map ( + I => SHIFT_EN_Q, + O => SHIFT_EN + ); + SHIFT_EN_tsimcreated_prld_Q_64 : X_OR2 + port map ( + I0 => SHIFT_EN_RSTF, + I1 => PRLD, + O => SHIFT_EN_tsimcreated_prld_Q + ); + SHIFT_EN_REG : X_FF + port map ( + I => SHIFT_EN_D, + CE => SHIFT_EN_CE, + CLK => SHIFT_EN_CLKF, + SET => Gnd, + RST => SHIFT_EN_tsimcreated_prld_Q, + O => SHIFT_EN_Q + ); + Gnd_65 : X_ZERO + port map ( + O => Gnd + ); + SHIFT_EN_D_66 : X_XOR2 + port map ( + I0 => SHIFT_EN_D1, + I1 => SHIFT_EN_D2, + O => SHIFT_EN_D + ); + SHIFT_EN_D1_67 : X_ZERO + port map ( + O => SHIFT_EN_D1 + ); + SHIFT_EN_D2_68 : X_AND2 + port map ( + I0 => NlwInverterSignal_SHIFT_EN_D2_IN0, + I1 => NlwInverterSignal_SHIFT_EN_D2_IN1, + O => SHIFT_EN_D2 + ); + SHIFT_EN_CLKF_69 : X_AND2 + port map ( + I0 => NlwInverterSignal_SHIFT_EN_CLKF_IN0, + I1 => NlwInverterSignal_SHIFT_EN_CLKF_IN1, + O => SHIFT_EN_CLKF + ); + SHIFT_EN_RSTF_70 : X_AND2 + port map ( + I0 => RES_IBUF, + I1 => RES_IBUF, + O => SHIFT_EN_RSTF + ); + SHIFT_EN_CE_71 : X_AND2 + port map ( + I0 => NlwInverterSignal_SHIFT_EN_CE_IN0, + I1 => NlwInverterSignal_SHIFT_EN_CE_IN1, + O => SHIFT_EN_CE + ); + count_0_Q_72 : X_BUF + port map ( + I => count_0_Q, + O => count(0) + ); + count_0_tsimcreated_set_and_noreset_Q_73 : X_AND2 + port map ( + I0 => NlwInverterSignal_count_0_tsimcreated_set_and_noreset_IN0, + I1 => count_0_SETF, + O => count_0_tsimcreated_set_and_noreset_Q + ); + count_0_tsimcreated_prld_Q_74 : X_OR2 + port map ( + I0 => count_0_RSTF, + I1 => PRLD, + O => count_0_tsimcreated_prld_Q + ); + count_0_REG : X_FF + port map ( + I => count_0_D, + CE => Vcc, + CLK => FCLKIO_0, + SET => count_0_tsimcreated_set_and_noreset_Q, + RST => count_0_tsimcreated_prld_Q, + O => count_0_Q + ); + count_0_D_75 : X_XOR2 + port map ( + I0 => NlwInverterSignal_count_0_D_IN0, + I1 => count_0_D2, + O => count_0_D + ); + count_0_D1_76 : X_ZERO + port map ( + O => count_0_D1 + ); + count_0_D2_PT_0_77 : X_AND2 + port map ( + I0 => RES_IBUF, + I1 => NlwInverterSignal_count_0_D2_PT_0_IN1, + O => count_0_D2_PT_0 + ); + count_0_D2_PT_1_78 : X_AND2 + port map ( + I0 => NlwInverterSignal_count_0_D2_PT_1_IN0, + I1 => count(0), + O => count_0_D2_PT_1 + ); + count_0_D2_PT_2_79 : X_AND6 + port map ( + I0 => NlwInverterSignal_count_0_D2_PT_2_IN0, + I1 => NlwInverterSignal_count_0_D2_PT_2_IN1, + I2 => NlwInverterSignal_count_0_D2_PT_2_IN2, + I3 => NlwInverterSignal_count_0_D2_PT_2_IN3, + I4 => NlwInverterSignal_count_0_D2_PT_2_IN4, + I5 => NlwInverterSignal_count_0_D2_PT_2_IN5, + O => count_0_D2_PT_2 + ); + count_0_D2_80 : X_OR3 + port map ( + I0 => count_0_D2_PT_0, + I1 => count_0_D2_PT_1, + I2 => count_0_D2_PT_2, + O => count_0_D2 + ); + count_0_SETF_81 : X_AND2 + port map ( + I0 => RES_IBUF, + I1 => VCLK_PRESCALE_0_IBUF, + O => count_0_SETF + ); + count_0_RSTF_82 : X_AND2 + port map ( + I0 => RES_IBUF, + I1 => NlwInverterSignal_count_0_RSTF_IN1, + O => count_0_RSTF + ); + count_4_Q_83 : X_BUF + port map ( + I => count_4_Q, + O => count(4) + ); + count_4_EXP_84 : X_BUF + port map ( + I => count_4_EXP_tsimrenamed_net_Q, + O => count_4_EXP + ); + count_4_tsimcreated_xor_Q_85 : X_XOR2 + port map ( + I0 => count_4_D, + I1 => count_4_Q, + O => count_4_tsimcreated_xor_Q + ); + count_4_tsimcreated_set_and_noreset_Q_86 : X_AND2 + port map ( + I0 => NlwInverterSignal_count_4_tsimcreated_set_and_noreset_IN0, + I1 => count_4_SETF, + O => count_4_tsimcreated_set_and_noreset_Q + ); + count_4_tsimcreated_prld_Q_87 : X_OR2 + port map ( + I0 => count_4_RSTF, + I1 => PRLD, + O => count_4_tsimcreated_prld_Q + ); + count_4_REG : X_FF + port map ( + I => count_4_tsimcreated_xor_Q, + CE => Vcc, + CLK => FCLKIO_0, + SET => count_4_tsimcreated_set_and_noreset_Q, + RST => count_4_tsimcreated_prld_Q, + O => count_4_Q + ); + count_4_D_88 : X_XOR2 + port map ( + I0 => count_4_D1, + I1 => count_4_D2, + O => count_4_D + ); + count_4_D1_89 : X_ZERO + port map ( + O => count_4_D1 + ); + count_4_D2_PT_0_90 : X_AND2 + port map ( + I0 => EXP19_EXP, + I1 => EXP19_EXP, + O => count_4_D2_PT_0 + ); + count_4_D2_PT_1_91 : X_AND6 + port map ( + I0 => NlwInverterSignal_count_4_D2_PT_1_IN0, + I1 => NlwInverterSignal_count_4_D2_PT_1_IN1, + I2 => NlwInverterSignal_count_4_D2_PT_1_IN2, + I3 => NlwInverterSignal_count_4_D2_PT_1_IN3, + I4 => NlwInverterSignal_count_4_D2_PT_1_IN4, + I5 => count(5), + O => count_4_D2_PT_1 + ); + count_4_D2_PT_2_92 : X_AND6 + port map ( + I0 => NlwInverterSignal_count_4_D2_PT_2_IN0, + I1 => NlwInverterSignal_count_4_D2_PT_2_IN1, + I2 => NlwInverterSignal_count_4_D2_PT_2_IN2, + I3 => NlwInverterSignal_count_4_D2_PT_2_IN3, + I4 => NlwInverterSignal_count_4_D2_PT_2_IN4, + I5 => VCLK_PRESCALE_4_IBUF, + O => count_4_D2_PT_2 + ); + count_4_D2_93 : X_OR3 + port map ( + I0 => count_4_D2_PT_0, + I1 => count_4_D2_PT_1, + I2 => count_4_D2_PT_2, + O => count_4_D2 + ); + count_4_SETF_94 : X_AND2 + port map ( + I0 => RES_IBUF, + I1 => VCLK_PRESCALE_4_IBUF, + O => count_4_SETF + ); + count_4_RSTF_95 : X_AND2 + port map ( + I0 => RES_IBUF, + I1 => NlwInverterSignal_count_4_RSTF_IN1, + O => count_4_RSTF + ); + count_4_EXP_tsimrenamed_net_Q_96 : X_AND4 + port map ( + I0 => NlwInverterSignal_count_4_EXP_tsimrenamed_net_IN0, + I1 => NlwInverterSignal_count_4_EXP_tsimrenamed_net_IN1, + I2 => NlwInverterSignal_count_4_EXP_tsimrenamed_net_IN2, + I3 => count(2), + O => count_4_EXP_tsimrenamed_net_Q + ); + count_1_Q_97 : X_BUF + port map ( + I => count_1_Q, + O => count(1) + ); + count_1_tsimcreated_set_and_noreset_Q_98 : X_AND2 + port map ( + I0 => NlwInverterSignal_count_1_tsimcreated_set_and_noreset_IN0, + I1 => count_1_SETF, + O => count_1_tsimcreated_set_and_noreset_Q + ); + count_1_tsimcreated_prld_Q_99 : X_OR2 + port map ( + I0 => count_1_RSTF, + I1 => PRLD, + O => count_1_tsimcreated_prld_Q + ); + count_1_REG : X_FF + port map ( + I => count_1_D, + CE => Vcc, + CLK => FCLKIO_0, + SET => count_1_tsimcreated_set_and_noreset_Q, + RST => count_1_tsimcreated_prld_Q, + O => count_1_Q + ); + count_1_D_100 : X_XOR2 + port map ( + I0 => NlwInverterSignal_count_1_D_IN0, + I1 => count_1_D2, + O => count_1_D + ); + count_1_D1_101 : X_ZERO + port map ( + O => count_1_D1 + ); + count_1_D2_PT_0_102 : X_AND2 + port map ( + I0 => count_5_EXP, + I1 => count_5_EXP, + O => count_1_D2_PT_0 + ); + count_1_D2_PT_1_103 : X_AND2 + port map ( + I0 => RES_IBUF, + I1 => NlwInverterSignal_count_1_D2_PT_1_IN1, + O => count_1_D2_PT_1 + ); + count_1_D2_PT_2_104 : X_AND3 + port map ( + I0 => NlwInverterSignal_count_1_D2_PT_2_IN0, + I1 => count(0), + I2 => NlwInverterSignal_count_1_D2_PT_2_IN2, + O => count_1_D2_PT_2 + ); + count_1_D2_PT_3_105 : X_AND3 + port map ( + I0 => NlwInverterSignal_count_1_D2_PT_3_IN0, + I1 => NlwInverterSignal_count_1_D2_PT_3_IN1, + I2 => count(1), + O => count_1_D2_PT_3 + ); + count_1_D2_106 : X_OR4 + port map ( + I0 => count_1_D2_PT_0, + I1 => count_1_D2_PT_1, + I2 => count_1_D2_PT_2, + I3 => count_1_D2_PT_3, + O => count_1_D2 + ); + count_1_SETF_107 : X_AND2 + port map ( + I0 => RES_IBUF, + I1 => VCLK_PRESCALE_1_IBUF, + O => count_1_SETF + ); + count_1_RSTF_108 : X_AND2 + port map ( + I0 => RES_IBUF, + I1 => NlwInverterSignal_count_1_RSTF_IN1, + O => count_1_RSTF + ); + count_2_Q_109 : X_BUF + port map ( + I => count_2_Q, + O => count(2) + ); + count_2_tsimcreated_set_and_noreset_Q_110 : X_AND2 + port map ( + I0 => NlwInverterSignal_count_2_tsimcreated_set_and_noreset_IN0, + I1 => count_2_SETF, + O => count_2_tsimcreated_set_and_noreset_Q + ); + count_2_tsimcreated_prld_Q_111 : X_OR2 + port map ( + I0 => count_2_RSTF, + I1 => PRLD, + O => count_2_tsimcreated_prld_Q + ); + count_2_REG : X_FF + port map ( + I => count_2_D, + CE => Vcc, + CLK => FCLKIO_0, + SET => count_2_tsimcreated_set_and_noreset_Q, + RST => count_2_tsimcreated_prld_Q, + O => count_2_Q + ); + count_2_D_112 : X_XOR2 + port map ( + I0 => NlwInverterSignal_count_2_D_IN0, + I1 => count_2_D2, + O => count_2_D + ); + count_2_D1_113 : X_ZERO + port map ( + O => count_2_D1 + ); + count_2_D2_PT_0_114 : X_AND2 + port map ( + I0 => count_4_EXP, + I1 => count_4_EXP, + O => count_2_D2_PT_0 + ); + count_2_D2_PT_1_115 : X_AND2 + port map ( + I0 => count_3_EXP, + I1 => count_3_EXP, + O => count_2_D2_PT_1 + ); + count_2_D2_PT_2_116 : X_AND2 + port map ( + I0 => RES_IBUF, + I1 => NlwInverterSignal_count_2_D2_PT_2_IN1, + O => count_2_D2_PT_2 + ); + count_2_D2_PT_3_117 : X_AND3 + port map ( + I0 => NlwInverterSignal_count_2_D2_PT_3_IN0, + I1 => count(0), + I2 => NlwInverterSignal_count_2_D2_PT_3_IN2, + O => count_2_D2_PT_3 + ); + count_2_D2_PT_4_118 : X_AND3 + port map ( + I0 => NlwInverterSignal_count_2_D2_PT_4_IN0, + I1 => count(1), + I2 => NlwInverterSignal_count_2_D2_PT_4_IN2, + O => count_2_D2_PT_4 + ); + count_2_D2_119 : X_OR5 + port map ( + I0 => count_2_D2_PT_0, + I1 => count_2_D2_PT_1, + I2 => count_2_D2_PT_2, + I3 => count_2_D2_PT_3, + I4 => count_2_D2_PT_4, + O => count_2_D2 + ); + count_2_SETF_120 : X_AND2 + port map ( + I0 => RES_IBUF, + I1 => VCLK_PRESCALE_2_IBUF, + O => count_2_SETF + ); + count_2_RSTF_121 : X_AND2 + port map ( + I0 => RES_IBUF, + I1 => NlwInverterSignal_count_2_RSTF_IN1, + O => count_2_RSTF + ); + count_3_Q_122 : X_BUF + port map ( + I => count_3_Q, + O => count(3) + ); + count_3_EXP_123 : X_BUF + port map ( + I => count_3_EXP_tsimrenamed_net_Q, + O => count_3_EXP + ); + count_3_tsimcreated_set_and_noreset_Q_124 : X_AND2 + port map ( + I0 => NlwInverterSignal_count_3_tsimcreated_set_and_noreset_IN0, + I1 => count_3_SETF, + O => count_3_tsimcreated_set_and_noreset_Q + ); + count_3_tsimcreated_prld_Q_125 : X_OR2 + port map ( + I0 => count_3_RSTF, + I1 => PRLD, + O => count_3_tsimcreated_prld_Q + ); + count_3_REG : X_FF + port map ( + I => count_3_D, + CE => Vcc, + CLK => FCLKIO_0, + SET => count_3_tsimcreated_set_and_noreset_Q, + RST => count_3_tsimcreated_prld_Q, + O => count_3_Q + ); + count_3_D_126 : X_XOR2 + port map ( + I0 => NlwInverterSignal_count_3_D_IN0, + I1 => count_3_D2, + O => count_3_D + ); + count_3_D1_127 : X_ZERO + port map ( + O => count_3_D1 + ); + count_3_D2_PT_0_128 : X_AND2 + port map ( + I0 => EXP20_EXP, + I1 => EXP20_EXP, + O => count_3_D2_PT_0 + ); + count_3_D2_PT_1_129 : X_AND2 + port map ( + I0 => RES_IBUF, + I1 => NlwInverterSignal_count_3_D2_PT_1_IN1, + O => count_3_D2_PT_1 + ); + count_3_D2_PT_2_130 : X_AND3 + port map ( + I0 => NlwInverterSignal_count_3_D2_PT_2_IN0, + I1 => count(0), + I2 => NlwInverterSignal_count_3_D2_PT_2_IN2, + O => count_3_D2_PT_2 + ); + count_3_D2_131 : X_OR3 + port map ( + I0 => count_3_D2_PT_0, + I1 => count_3_D2_PT_1, + I2 => count_3_D2_PT_2, + O => count_3_D2 + ); + count_3_SETF_132 : X_AND2 + port map ( + I0 => RES_IBUF, + I1 => VCLK_PRESCALE_3_IBUF, + O => count_3_SETF + ); + count_3_RSTF_133 : X_AND2 + port map ( + I0 => RES_IBUF, + I1 => NlwInverterSignal_count_3_RSTF_IN1, + O => count_3_RSTF + ); + count_3_EXP_tsimrenamed_net_Q_134 : X_AND5 + port map ( + I0 => NlwInverterSignal_count_3_EXP_tsimrenamed_net_IN0, + I1 => NlwInverterSignal_count_3_EXP_tsimrenamed_net_IN1, + I2 => NlwInverterSignal_count_3_EXP_tsimrenamed_net_IN2, + I3 => NlwInverterSignal_count_3_EXP_tsimrenamed_net_IN3, + I4 => NlwInverterSignal_count_3_EXP_tsimrenamed_net_IN4, + O => count_3_EXP_tsimrenamed_net_Q + ); + REG_0_Q_135 : X_BUF + port map ( + I => REG_0_Q, + O => REG(0) + ); + REG_0_tsimcreated_xor_Q_136 : X_XOR2 + port map ( + I0 => REG_0_D, + I1 => REG_0_Q, + O => REG_0_tsimcreated_xor_Q + ); + REG_0_tsimcreated_set_and_noreset_Q_137 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_tsimcreated_set_and_noreset_IN0, + I1 => REG_0_SETF, + O => REG_0_tsimcreated_set_and_noreset_Q + ); + REG_0_tsimcreated_prld_Q_138 : X_OR2 + port map ( + I0 => REG_0_RSTF, + I1 => PRLD, + O => REG_0_tsimcreated_prld_Q + ); + REG_0_REG : X_FF + port map ( + I => REG_0_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_0_CLKF, + SET => REG_0_tsimcreated_set_and_noreset_Q, + RST => REG_0_tsimcreated_prld_Q, + O => REG_0_Q + ); + REG_0_D_139 : X_XOR2 + port map ( + I0 => REG_0_D1, + I1 => REG_0_D2, + O => REG_0_D + ); + REG_0_D1_140 : X_ZERO + port map ( + O => REG_0_D1 + ); + REG_0_D2_141 : X_AND5 + port map ( + I0 => NlwInverterSignal_REG_0_D2_IN0, + I1 => NlwInverterSignal_REG_0_D2_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_D2_IN3, + I4 => REG(0), + O => REG_0_D2 + ); + REG_0_CLKF_142 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_CLKF_IN0, + I1 => NlwInverterSignal_REG_0_CLKF_IN1, + O => REG_0_CLKF + ); + REG_0_SETF_143 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => DIN_0_IBUF, + O => REG_0_SETF + ); + REG_0_RSTF_144 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => NlwInverterSignal_REG_0_RSTF_IN2, + O => REG_0_RSTF + ); + REG_10_Q_145 : X_BUF + port map ( + I => REG_10_Q, + O => REG(10) + ); + REG_10_tsimcreated_xor_Q_146 : X_XOR2 + port map ( + I0 => REG_10_D, + I1 => REG_10_Q, + O => REG_10_tsimcreated_xor_Q + ); + REG_10_tsimcreated_set_and_noreset_Q_147 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_10_tsimcreated_set_and_noreset_IN0, + I1 => REG_10_SETF, + O => REG_10_tsimcreated_set_and_noreset_Q + ); + REG_10_tsimcreated_prld_Q_148 : X_OR2 + port map ( + I0 => REG_10_RSTF, + I1 => PRLD, + O => REG_10_tsimcreated_prld_Q + ); + REG_10_REG : X_FF + port map ( + I => REG_10_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_10_CLKF, + SET => REG_10_tsimcreated_set_and_noreset_Q, + RST => REG_10_tsimcreated_prld_Q, + O => REG_10_Q + ); + REG_10_D_149 : X_XOR2 + port map ( + I0 => REG_10_D1, + I1 => REG_10_D2, + O => REG_10_D + ); + REG_10_D1_150 : X_ZERO + port map ( + O => REG_10_D1 + ); + REG_10_D2_PT_0_151 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_10_D2_PT_0_IN0, + I1 => NlwInverterSignal_REG_10_D2_PT_0_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_10_D2_PT_0_IN3, + I4 => REG(10), + I5 => NlwInverterSignal_REG_10_D2_PT_0_IN5, + O => REG_10_D2_PT_0 + ); + REG_10_D2_PT_1_152 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_10_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_10_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_10_D2_PT_1_IN3, + I4 => NlwInverterSignal_REG_10_D2_PT_1_IN4, + I5 => REG(9), + O => REG_10_D2_PT_1 + ); + REG_10_D2_153 : X_OR2 + port map ( + I0 => REG_10_D2_PT_0, + I1 => REG_10_D2_PT_1, + O => REG_10_D2 + ); + REG_10_CLKF_154 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_10_CLKF_IN0, + I1 => NlwInverterSignal_REG_10_CLKF_IN1, + O => REG_10_CLKF + ); + REG_10_SETF_155 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => DIN_10_IBUF, + O => REG_10_SETF + ); + REG_10_RSTF_156 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => NlwInverterSignal_REG_10_RSTF_IN2, + O => REG_10_RSTF + ); + REG_11_Q_157 : X_BUF + port map ( + I => REG_11_Q, + O => REG(11) + ); + REG_11_tsimcreated_xor_Q_158 : X_XOR2 + port map ( + I0 => REG_11_D, + I1 => REG_11_Q, + O => REG_11_tsimcreated_xor_Q + ); + REG_11_tsimcreated_set_and_noreset_Q_159 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_11_tsimcreated_set_and_noreset_IN0, + I1 => REG_11_SETF, + O => REG_11_tsimcreated_set_and_noreset_Q + ); + REG_11_tsimcreated_prld_Q_160 : X_OR2 + port map ( + I0 => REG_11_RSTF, + I1 => PRLD, + O => REG_11_tsimcreated_prld_Q + ); + REG_11_REG : X_FF + port map ( + I => REG_11_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_11_CLKF, + SET => REG_11_tsimcreated_set_and_noreset_Q, + RST => REG_11_tsimcreated_prld_Q, + O => REG_11_Q + ); + REG_11_D_161 : X_XOR2 + port map ( + I0 => REG_11_D1, + I1 => REG_11_D2, + O => REG_11_D + ); + REG_11_D1_162 : X_ZERO + port map ( + O => REG_11_D1 + ); + REG_11_D2_PT_0_163 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_11_D2_PT_0_IN0, + I1 => NlwInverterSignal_REG_11_D2_PT_0_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_11_D2_PT_0_IN3, + I4 => REG(10), + I5 => NlwInverterSignal_REG_11_D2_PT_0_IN5, + O => REG_11_D2_PT_0 + ); + REG_11_D2_PT_1_164 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_11_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_11_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_11_D2_PT_1_IN3, + I4 => NlwInverterSignal_REG_11_D2_PT_1_IN4, + I5 => REG(11), + O => REG_11_D2_PT_1 + ); + REG_11_D2_165 : X_OR2 + port map ( + I0 => REG_11_D2_PT_0, + I1 => REG_11_D2_PT_1, + O => REG_11_D2 + ); + REG_11_CLKF_166 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_11_CLKF_IN0, + I1 => NlwInverterSignal_REG_11_CLKF_IN1, + O => REG_11_CLKF + ); + REG_11_SETF_167 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => DIN_11_IBUF, + O => REG_11_SETF + ); + REG_11_RSTF_168 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => NlwInverterSignal_REG_11_RSTF_IN2, + O => REG_11_RSTF + ); + REG_12_Q_169 : X_BUF + port map ( + I => REG_12_Q, + O => REG(12) + ); + REG_12_tsimcreated_xor_Q_170 : X_XOR2 + port map ( + I0 => REG_12_D, + I1 => REG_12_Q, + O => REG_12_tsimcreated_xor_Q + ); + REG_12_tsimcreated_set_and_noreset_Q_171 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_12_tsimcreated_set_and_noreset_IN0, + I1 => REG_12_SETF, + O => REG_12_tsimcreated_set_and_noreset_Q + ); + REG_12_tsimcreated_prld_Q_172 : X_OR2 + port map ( + I0 => REG_12_RSTF, + I1 => PRLD, + O => REG_12_tsimcreated_prld_Q + ); + REG_12_REG : X_FF + port map ( + I => REG_12_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_12_CLKF, + SET => REG_12_tsimcreated_set_and_noreset_Q, + RST => REG_12_tsimcreated_prld_Q, + O => REG_12_Q + ); + REG_12_D_173 : X_XOR2 + port map ( + I0 => REG_12_D1, + I1 => REG_12_D2, + O => REG_12_D + ); + REG_12_D1_174 : X_ZERO + port map ( + O => REG_12_D1 + ); + REG_12_D2_PT_0_175 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_12_D2_PT_0_IN0, + I1 => NlwInverterSignal_REG_12_D2_PT_0_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_12_D2_PT_0_IN3, + I4 => REG(11), + I5 => NlwInverterSignal_REG_12_D2_PT_0_IN5, + O => REG_12_D2_PT_0 + ); + REG_12_D2_PT_1_176 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_12_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_12_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_12_D2_PT_1_IN3, + I4 => NlwInverterSignal_REG_12_D2_PT_1_IN4, + I5 => REG(12), + O => REG_12_D2_PT_1 + ); + REG_12_D2_177 : X_OR2 + port map ( + I0 => REG_12_D2_PT_0, + I1 => REG_12_D2_PT_1, + O => REG_12_D2 + ); + REG_12_CLKF_178 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_12_CLKF_IN0, + I1 => NlwInverterSignal_REG_12_CLKF_IN1, + O => REG_12_CLKF + ); + REG_12_SETF_179 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => DIN_12_IBUF, + O => REG_12_SETF + ); + REG_12_RSTF_180 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => NlwInverterSignal_REG_12_RSTF_IN2, + O => REG_12_RSTF + ); + REG_13_Q_181 : X_BUF + port map ( + I => REG_13_Q, + O => REG(13) + ); + REG_13_tsimcreated_xor_Q_182 : X_XOR2 + port map ( + I0 => REG_13_D, + I1 => REG_13_Q, + O => REG_13_tsimcreated_xor_Q + ); + REG_13_tsimcreated_set_and_noreset_Q_183 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_13_tsimcreated_set_and_noreset_IN0, + I1 => REG_13_SETF, + O => REG_13_tsimcreated_set_and_noreset_Q + ); + REG_13_tsimcreated_prld_Q_184 : X_OR2 + port map ( + I0 => REG_13_RSTF, + I1 => PRLD, + O => REG_13_tsimcreated_prld_Q + ); + REG_13_REG : X_FF + port map ( + I => REG_13_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_13_CLKF, + SET => REG_13_tsimcreated_set_and_noreset_Q, + RST => REG_13_tsimcreated_prld_Q, + O => REG_13_Q + ); + REG_13_D_185 : X_XOR2 + port map ( + I0 => REG_13_D1, + I1 => REG_13_D2, + O => REG_13_D + ); + REG_13_D1_186 : X_ZERO + port map ( + O => REG_13_D1 + ); + REG_13_D2_PT_0_187 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_13_D2_PT_0_IN0, + I1 => NlwInverterSignal_REG_13_D2_PT_0_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_13_D2_PT_0_IN3, + I4 => REG(12), + I5 => NlwInverterSignal_REG_13_D2_PT_0_IN5, + O => REG_13_D2_PT_0 + ); + REG_13_D2_PT_1_188 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_13_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_13_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_13_D2_PT_1_IN3, + I4 => NlwInverterSignal_REG_13_D2_PT_1_IN4, + I5 => REG(13), + O => REG_13_D2_PT_1 + ); + REG_13_D2_189 : X_OR2 + port map ( + I0 => REG_13_D2_PT_0, + I1 => REG_13_D2_PT_1, + O => REG_13_D2 + ); + REG_13_CLKF_190 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_13_CLKF_IN0, + I1 => NlwInverterSignal_REG_13_CLKF_IN1, + O => REG_13_CLKF + ); + REG_13_SETF_191 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => DIN_13_IBUF, + O => REG_13_SETF + ); + REG_13_RSTF_192 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => NlwInverterSignal_REG_13_RSTF_IN2, + O => REG_13_RSTF + ); + REG_14_Q_193 : X_BUF + port map ( + I => REG_14_Q, + O => REG(14) + ); + REG_14_tsimcreated_xor_Q_194 : X_XOR2 + port map ( + I0 => REG_14_D, + I1 => REG_14_Q, + O => REG_14_tsimcreated_xor_Q + ); + REG_14_tsimcreated_set_and_noreset_Q_195 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_14_tsimcreated_set_and_noreset_IN0, + I1 => REG_14_SETF, + O => REG_14_tsimcreated_set_and_noreset_Q + ); + REG_14_tsimcreated_prld_Q_196 : X_OR2 + port map ( + I0 => REG_14_RSTF, + I1 => PRLD, + O => REG_14_tsimcreated_prld_Q + ); + REG_14_REG : X_FF + port map ( + I => REG_14_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_14_CLKF, + SET => REG_14_tsimcreated_set_and_noreset_Q, + RST => REG_14_tsimcreated_prld_Q, + O => REG_14_Q + ); + REG_14_D_197 : X_XOR2 + port map ( + I0 => REG_14_D1, + I1 => REG_14_D2, + O => REG_14_D + ); + REG_14_D1_198 : X_ZERO + port map ( + O => REG_14_D1 + ); + REG_14_D2_PT_0_199 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_14_D2_PT_0_IN0, + I1 => NlwInverterSignal_REG_14_D2_PT_0_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_14_D2_PT_0_IN3, + I4 => REG(13), + I5 => NlwInverterSignal_REG_14_D2_PT_0_IN5, + O => REG_14_D2_PT_0 + ); + REG_14_D2_PT_1_200 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_14_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_14_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_14_D2_PT_1_IN3, + I4 => NlwInverterSignal_REG_14_D2_PT_1_IN4, + I5 => REG(14), + O => REG_14_D2_PT_1 + ); + REG_14_D2_201 : X_OR2 + port map ( + I0 => REG_14_D2_PT_0, + I1 => REG_14_D2_PT_1, + O => REG_14_D2 + ); + REG_14_CLKF_202 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_14_CLKF_IN0, + I1 => NlwInverterSignal_REG_14_CLKF_IN1, + O => REG_14_CLKF + ); + REG_14_SETF_203 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => DIN_14_IBUF, + O => REG_14_SETF + ); + REG_14_RSTF_204 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => NlwInverterSignal_REG_14_RSTF_IN2, + O => REG_14_RSTF + ); + REG_15_Q_205 : X_BUF + port map ( + I => REG_15_Q, + O => REG(15) + ); + REG_15_tsimcreated_xor_Q_206 : X_XOR2 + port map ( + I0 => REG_15_D, + I1 => REG_15_Q, + O => REG_15_tsimcreated_xor_Q + ); + REG_15_tsimcreated_set_and_noreset_Q_207 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_15_tsimcreated_set_and_noreset_IN0, + I1 => REG_15_SETF, + O => REG_15_tsimcreated_set_and_noreset_Q + ); + REG_15_tsimcreated_prld_Q_208 : X_OR2 + port map ( + I0 => REG_15_RSTF, + I1 => PRLD, + O => REG_15_tsimcreated_prld_Q + ); + REG_15_REG : X_FF + port map ( + I => REG_15_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_15_CLKF, + SET => REG_15_tsimcreated_set_and_noreset_Q, + RST => REG_15_tsimcreated_prld_Q, + O => REG_15_Q + ); + REG_15_D_209 : X_XOR2 + port map ( + I0 => REG_15_D1, + I1 => REG_15_D2, + O => REG_15_D + ); + REG_15_D1_210 : X_ZERO + port map ( + O => REG_15_D1 + ); + REG_15_D2_PT_0_211 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_15_D2_PT_0_IN0, + I1 => NlwInverterSignal_REG_15_D2_PT_0_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_15_D2_PT_0_IN3, + I4 => REG(14), + I5 => NlwInverterSignal_REG_15_D2_PT_0_IN5, + O => REG_15_D2_PT_0 + ); + REG_15_D2_PT_1_212 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_15_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_15_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_15_D2_PT_1_IN3, + I4 => NlwInverterSignal_REG_15_D2_PT_1_IN4, + I5 => REG(15), + O => REG_15_D2_PT_1 + ); + REG_15_D2_213 : X_OR2 + port map ( + I0 => REG_15_D2_PT_0, + I1 => REG_15_D2_PT_1, + O => REG_15_D2 + ); + REG_15_CLKF_214 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_15_CLKF_IN0, + I1 => NlwInverterSignal_REG_15_CLKF_IN1, + O => REG_15_CLKF + ); + REG_15_SETF_215 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => DIN_15_IBUF, + O => REG_15_SETF + ); + REG_15_RSTF_216 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => NlwInverterSignal_REG_15_RSTF_IN2, + O => REG_15_RSTF + ); + REG_16_Q_217 : X_BUF + port map ( + I => REG_16_Q, + O => REG(16) + ); + REG_16_tsimcreated_xor_Q_218 : X_XOR2 + port map ( + I0 => REG_16_D, + I1 => REG_16_Q, + O => REG_16_tsimcreated_xor_Q + ); + REG_16_tsimcreated_set_and_noreset_Q_219 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_16_tsimcreated_set_and_noreset_IN0, + I1 => REG_16_SETF, + O => REG_16_tsimcreated_set_and_noreset_Q + ); + REG_16_tsimcreated_prld_Q_220 : X_OR2 + port map ( + I0 => REG_16_RSTF, + I1 => PRLD, + O => REG_16_tsimcreated_prld_Q + ); + REG_16_REG : X_FF + port map ( + I => REG_16_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_16_CLKF, + SET => REG_16_tsimcreated_set_and_noreset_Q, + RST => REG_16_tsimcreated_prld_Q, + O => REG_16_Q + ); + REG_16_D_221 : X_XOR2 + port map ( + I0 => REG_16_D1, + I1 => REG_16_D2, + O => REG_16_D + ); + REG_16_D1_222 : X_ZERO + port map ( + O => REG_16_D1 + ); + REG_16_D2_PT_0_223 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_16_D2_PT_0_IN0, + I1 => NlwInverterSignal_REG_16_D2_PT_0_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_16_D2_PT_0_IN3, + I4 => REG(15), + I5 => NlwInverterSignal_REG_16_D2_PT_0_IN5, + O => REG_16_D2_PT_0 + ); + REG_16_D2_PT_1_224 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_16_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_16_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_16_D2_PT_1_IN3, + I4 => NlwInverterSignal_REG_16_D2_PT_1_IN4, + I5 => REG(16), + O => REG_16_D2_PT_1 + ); + REG_16_D2_225 : X_OR2 + port map ( + I0 => REG_16_D2_PT_0, + I1 => REG_16_D2_PT_1, + O => REG_16_D2 + ); + REG_16_CLKF_226 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_16_CLKF_IN0, + I1 => NlwInverterSignal_REG_16_CLKF_IN1, + O => REG_16_CLKF + ); + REG_16_SETF_227 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => DIN_16_IBUF, + O => REG_16_SETF + ); + REG_16_RSTF_228 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => NlwInverterSignal_REG_16_RSTF_IN2, + O => REG_16_RSTF + ); + REG_17_Q_229 : X_BUF + port map ( + I => REG_17_Q, + O => REG(17) + ); + REG_17_tsimcreated_xor_Q_230 : X_XOR2 + port map ( + I0 => REG_17_D, + I1 => REG_17_Q, + O => REG_17_tsimcreated_xor_Q + ); + REG_17_tsimcreated_set_and_noreset_Q_231 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_17_tsimcreated_set_and_noreset_IN0, + I1 => REG_17_SETF, + O => REG_17_tsimcreated_set_and_noreset_Q + ); + REG_17_tsimcreated_prld_Q_232 : X_OR2 + port map ( + I0 => REG_17_RSTF, + I1 => PRLD, + O => REG_17_tsimcreated_prld_Q + ); + REG_17_REG : X_FF + port map ( + I => REG_17_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_17_CLKF, + SET => REG_17_tsimcreated_set_and_noreset_Q, + RST => REG_17_tsimcreated_prld_Q, + O => REG_17_Q + ); + REG_17_D_233 : X_XOR2 + port map ( + I0 => REG_17_D1, + I1 => REG_17_D2, + O => REG_17_D + ); + REG_17_D1_234 : X_ZERO + port map ( + O => REG_17_D1 + ); + REG_17_D2_PT_0_235 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_17_D2_PT_0_IN0, + I1 => NlwInverterSignal_REG_17_D2_PT_0_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_17_D2_PT_0_IN3, + I4 => REG(16), + I5 => NlwInverterSignal_REG_17_D2_PT_0_IN5, + O => REG_17_D2_PT_0 + ); + REG_17_D2_PT_1_236 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_17_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_17_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_17_D2_PT_1_IN3, + I4 => NlwInverterSignal_REG_17_D2_PT_1_IN4, + I5 => REG(17), + O => REG_17_D2_PT_1 + ); + REG_17_D2_237 : X_OR2 + port map ( + I0 => REG_17_D2_PT_0, + I1 => REG_17_D2_PT_1, + O => REG_17_D2 + ); + REG_17_CLKF_238 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_17_CLKF_IN0, + I1 => NlwInverterSignal_REG_17_CLKF_IN1, + O => REG_17_CLKF + ); + REG_17_SETF_239 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => DIN_17_IBUF, + O => REG_17_SETF + ); + REG_17_RSTF_240 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => NlwInverterSignal_REG_17_RSTF_IN2, + O => REG_17_RSTF + ); + REG_18_Q_241 : X_BUF + port map ( + I => REG_18_Q, + O => REG(18) + ); + REG_18_tsimcreated_xor_Q_242 : X_XOR2 + port map ( + I0 => REG_18_D, + I1 => REG_18_Q, + O => REG_18_tsimcreated_xor_Q + ); + REG_18_tsimcreated_set_and_noreset_Q_243 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_18_tsimcreated_set_and_noreset_IN0, + I1 => REG_18_SETF, + O => REG_18_tsimcreated_set_and_noreset_Q + ); + REG_18_tsimcreated_prld_Q_244 : X_OR2 + port map ( + I0 => REG_18_RSTF, + I1 => PRLD, + O => REG_18_tsimcreated_prld_Q + ); + REG_18_REG : X_FF + port map ( + I => REG_18_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_18_CLKF, + SET => REG_18_tsimcreated_set_and_noreset_Q, + RST => REG_18_tsimcreated_prld_Q, + O => REG_18_Q + ); + REG_18_D_245 : X_XOR2 + port map ( + I0 => REG_18_D1, + I1 => REG_18_D2, + O => REG_18_D + ); + REG_18_D1_246 : X_ZERO + port map ( + O => REG_18_D1 + ); + REG_18_D2_PT_0_247 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_18_D2_PT_0_IN0, + I1 => NlwInverterSignal_REG_18_D2_PT_0_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_18_D2_PT_0_IN3, + I4 => REG(17), + I5 => NlwInverterSignal_REG_18_D2_PT_0_IN5, + O => REG_18_D2_PT_0 + ); + REG_18_D2_PT_1_248 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_18_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_18_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_18_D2_PT_1_IN3, + I4 => NlwInverterSignal_REG_18_D2_PT_1_IN4, + I5 => REG(18), + O => REG_18_D2_PT_1 + ); + REG_18_D2_249 : X_OR2 + port map ( + I0 => REG_18_D2_PT_0, + I1 => REG_18_D2_PT_1, + O => REG_18_D2 + ); + REG_18_CLKF_250 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_18_CLKF_IN0, + I1 => NlwInverterSignal_REG_18_CLKF_IN1, + O => REG_18_CLKF + ); + REG_18_SETF_251 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => DIN_18_IBUF, + O => REG_18_SETF + ); + REG_18_RSTF_252 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => NlwInverterSignal_REG_18_RSTF_IN2, + O => REG_18_RSTF + ); + REG_19_Q_253 : X_BUF + port map ( + I => REG_19_Q, + O => REG(19) + ); + REG_19_tsimcreated_xor_Q_254 : X_XOR2 + port map ( + I0 => REG_19_D, + I1 => REG_19_Q, + O => REG_19_tsimcreated_xor_Q + ); + REG_19_tsimcreated_set_and_noreset_Q_255 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_19_tsimcreated_set_and_noreset_IN0, + I1 => REG_19_SETF, + O => REG_19_tsimcreated_set_and_noreset_Q + ); + REG_19_tsimcreated_prld_Q_256 : X_OR2 + port map ( + I0 => REG_19_RSTF, + I1 => PRLD, + O => REG_19_tsimcreated_prld_Q + ); + REG_19_REG : X_FF + port map ( + I => REG_19_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_19_CLKF, + SET => REG_19_tsimcreated_set_and_noreset_Q, + RST => REG_19_tsimcreated_prld_Q, + O => REG_19_Q + ); + REG_19_D_257 : X_XOR2 + port map ( + I0 => REG_19_D1, + I1 => REG_19_D2, + O => REG_19_D + ); + REG_19_D1_258 : X_ZERO + port map ( + O => REG_19_D1 + ); + REG_19_D2_PT_0_259 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_19_D2_PT_0_IN0, + I1 => NlwInverterSignal_REG_19_D2_PT_0_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_19_D2_PT_0_IN3, + I4 => REG(18), + I5 => NlwInverterSignal_REG_19_D2_PT_0_IN5, + O => REG_19_D2_PT_0 + ); + REG_19_D2_PT_1_260 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_19_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_19_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_19_D2_PT_1_IN3, + I4 => NlwInverterSignal_REG_19_D2_PT_1_IN4, + I5 => REG(19), + O => REG_19_D2_PT_1 + ); + REG_19_D2_261 : X_OR2 + port map ( + I0 => REG_19_D2_PT_0, + I1 => REG_19_D2_PT_1, + O => REG_19_D2 + ); + REG_19_CLKF_262 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_19_CLKF_IN0, + I1 => NlwInverterSignal_REG_19_CLKF_IN1, + O => REG_19_CLKF + ); + REG_19_SETF_263 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => DIN_19_IBUF, + O => REG_19_SETF + ); + REG_19_RSTF_264 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => NlwInverterSignal_REG_19_RSTF_IN2, + O => REG_19_RSTF + ); + REG_1_Q_265 : X_BUF + port map ( + I => REG_1_Q, + O => REG(1) + ); + REG_1_tsimcreated_xor_Q_266 : X_XOR2 + port map ( + I0 => REG_1_D, + I1 => REG_1_Q, + O => REG_1_tsimcreated_xor_Q + ); + REG_1_tsimcreated_set_and_noreset_Q_267 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_tsimcreated_set_and_noreset_IN0, + I1 => REG_1_SETF, + O => REG_1_tsimcreated_set_and_noreset_Q + ); + REG_1_tsimcreated_prld_Q_268 : X_OR2 + port map ( + I0 => REG_1_RSTF, + I1 => PRLD, + O => REG_1_tsimcreated_prld_Q + ); + REG_1_REG : X_FF + port map ( + I => REG_1_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_1_CLKF, + SET => REG_1_tsimcreated_set_and_noreset_Q, + RST => REG_1_tsimcreated_prld_Q, + O => REG_1_Q + ); + REG_1_D_269 : X_XOR2 + port map ( + I0 => REG_1_D1, + I1 => REG_1_D2, + O => REG_1_D + ); + REG_1_D1_270 : X_ZERO + port map ( + O => REG_1_D1 + ); + REG_1_D2_PT_0_271 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_D2_PT_0_IN0, + I1 => NlwInverterSignal_REG_1_D2_PT_0_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_1_D2_PT_0_IN3, + I4 => REG(0), + I5 => NlwInverterSignal_REG_1_D2_PT_0_IN5, + O => REG_1_D2_PT_0 + ); + REG_1_D2_PT_1_272 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_1_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_1_D2_PT_1_IN3, + I4 => NlwInverterSignal_REG_1_D2_PT_1_IN4, + I5 => REG(1), + O => REG_1_D2_PT_1 + ); + REG_1_D2_273 : X_OR2 + port map ( + I0 => REG_1_D2_PT_0, + I1 => REG_1_D2_PT_1, + O => REG_1_D2 + ); + REG_1_CLKF_274 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_CLKF_IN0, + I1 => NlwInverterSignal_REG_1_CLKF_IN1, + O => REG_1_CLKF + ); + REG_1_SETF_275 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => DIN_1_IBUF, + O => REG_1_SETF + ); + REG_1_RSTF_276 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => NlwInverterSignal_REG_1_RSTF_IN2, + O => REG_1_RSTF + ); + REG_20_Q_277 : X_BUF + port map ( + I => REG_20_Q, + O => REG(20) + ); + REG_20_tsimcreated_xor_Q_278 : X_XOR2 + port map ( + I0 => REG_20_D, + I1 => REG_20_Q, + O => REG_20_tsimcreated_xor_Q + ); + REG_20_tsimcreated_set_and_noreset_Q_279 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_20_tsimcreated_set_and_noreset_IN0, + I1 => REG_20_SETF, + O => REG_20_tsimcreated_set_and_noreset_Q + ); + REG_20_tsimcreated_prld_Q_280 : X_OR2 + port map ( + I0 => REG_20_RSTF, + I1 => PRLD, + O => REG_20_tsimcreated_prld_Q + ); + REG_20_REG : X_FF + port map ( + I => REG_20_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_20_CLKF, + SET => REG_20_tsimcreated_set_and_noreset_Q, + RST => REG_20_tsimcreated_prld_Q, + O => REG_20_Q + ); + REG_20_D_281 : X_XOR2 + port map ( + I0 => REG_20_D1, + I1 => REG_20_D2, + O => REG_20_D + ); + REG_20_D1_282 : X_ZERO + port map ( + O => REG_20_D1 + ); + REG_20_D2_PT_0_283 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_20_D2_PT_0_IN0, + I1 => NlwInverterSignal_REG_20_D2_PT_0_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_20_D2_PT_0_IN3, + I4 => REG(19), + I5 => NlwInverterSignal_REG_20_D2_PT_0_IN5, + O => REG_20_D2_PT_0 + ); + REG_20_D2_PT_1_284 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_20_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_20_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_20_D2_PT_1_IN3, + I4 => NlwInverterSignal_REG_20_D2_PT_1_IN4, + I5 => REG(20), + O => REG_20_D2_PT_1 + ); + REG_20_D2_285 : X_OR2 + port map ( + I0 => REG_20_D2_PT_0, + I1 => REG_20_D2_PT_1, + O => REG_20_D2 + ); + REG_20_CLKF_286 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_20_CLKF_IN0, + I1 => NlwInverterSignal_REG_20_CLKF_IN1, + O => REG_20_CLKF + ); + REG_20_SETF_287 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => DIN_20_IBUF, + O => REG_20_SETF + ); + REG_20_RSTF_288 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => NlwInverterSignal_REG_20_RSTF_IN2, + O => REG_20_RSTF + ); + REG_21_Q_289 : X_BUF + port map ( + I => REG_21_Q, + O => REG(21) + ); + REG_21_tsimcreated_xor_Q_290 : X_XOR2 + port map ( + I0 => REG_21_D, + I1 => REG_21_Q, + O => REG_21_tsimcreated_xor_Q + ); + REG_21_tsimcreated_set_and_noreset_Q_291 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_21_tsimcreated_set_and_noreset_IN0, + I1 => REG_21_SETF, + O => REG_21_tsimcreated_set_and_noreset_Q + ); + REG_21_tsimcreated_prld_Q_292 : X_OR2 + port map ( + I0 => REG_21_RSTF, + I1 => PRLD, + O => REG_21_tsimcreated_prld_Q + ); + REG_21_REG : X_FF + port map ( + I => REG_21_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_21_CLKF, + SET => REG_21_tsimcreated_set_and_noreset_Q, + RST => REG_21_tsimcreated_prld_Q, + O => REG_21_Q + ); + REG_21_D_293 : X_XOR2 + port map ( + I0 => REG_21_D1, + I1 => REG_21_D2, + O => REG_21_D + ); + REG_21_D1_294 : X_ZERO + port map ( + O => REG_21_D1 + ); + REG_21_D2_PT_0_295 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_21_D2_PT_0_IN0, + I1 => NlwInverterSignal_REG_21_D2_PT_0_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_21_D2_PT_0_IN3, + I4 => REG(20), + I5 => NlwInverterSignal_REG_21_D2_PT_0_IN5, + O => REG_21_D2_PT_0 + ); + REG_21_D2_PT_1_296 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_21_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_21_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_21_D2_PT_1_IN3, + I4 => NlwInverterSignal_REG_21_D2_PT_1_IN4, + I5 => REG(21), + O => REG_21_D2_PT_1 + ); + REG_21_D2_297 : X_OR2 + port map ( + I0 => REG_21_D2_PT_0, + I1 => REG_21_D2_PT_1, + O => REG_21_D2 + ); + REG_21_CLKF_298 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_21_CLKF_IN0, + I1 => NlwInverterSignal_REG_21_CLKF_IN1, + O => REG_21_CLKF + ); + REG_21_SETF_299 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => DIN_21_IBUF, + O => REG_21_SETF + ); + REG_21_RSTF_300 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => NlwInverterSignal_REG_21_RSTF_IN2, + O => REG_21_RSTF + ); + REG_22_Q_301 : X_BUF + port map ( + I => REG_22_Q, + O => REG(22) + ); + REG_22_tsimcreated_xor_Q_302 : X_XOR2 + port map ( + I0 => REG_22_D, + I1 => REG_22_Q, + O => REG_22_tsimcreated_xor_Q + ); + REG_22_tsimcreated_set_and_noreset_Q_303 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_22_tsimcreated_set_and_noreset_IN0, + I1 => REG_22_SETF, + O => REG_22_tsimcreated_set_and_noreset_Q + ); + REG_22_tsimcreated_prld_Q_304 : X_OR2 + port map ( + I0 => REG_22_RSTF, + I1 => PRLD, + O => REG_22_tsimcreated_prld_Q + ); + REG_22_REG : X_FF + port map ( + I => REG_22_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_22_CLKF, + SET => REG_22_tsimcreated_set_and_noreset_Q, + RST => REG_22_tsimcreated_prld_Q, + O => REG_22_Q + ); + REG_22_D_305 : X_XOR2 + port map ( + I0 => REG_22_D1, + I1 => REG_22_D2, + O => REG_22_D + ); + REG_22_D1_306 : X_ZERO + port map ( + O => REG_22_D1 + ); + REG_22_D2_PT_0_307 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_22_D2_PT_0_IN0, + I1 => NlwInverterSignal_REG_22_D2_PT_0_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_22_D2_PT_0_IN3, + I4 => REG(21), + I5 => NlwInverterSignal_REG_22_D2_PT_0_IN5, + O => REG_22_D2_PT_0 + ); + REG_22_D2_PT_1_308 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_22_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_22_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_22_D2_PT_1_IN3, + I4 => NlwInverterSignal_REG_22_D2_PT_1_IN4, + I5 => REG(22), + O => REG_22_D2_PT_1 + ); + REG_22_D2_309 : X_OR2 + port map ( + I0 => REG_22_D2_PT_0, + I1 => REG_22_D2_PT_1, + O => REG_22_D2 + ); + REG_22_CLKF_310 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_22_CLKF_IN0, + I1 => NlwInverterSignal_REG_22_CLKF_IN1, + O => REG_22_CLKF + ); + REG_22_SETF_311 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => DIN_22_IBUF, + O => REG_22_SETF + ); + REG_22_RSTF_312 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => NlwInverterSignal_REG_22_RSTF_IN2, + O => REG_22_RSTF + ); + REG_23_Q_313 : X_BUF + port map ( + I => REG_23_Q, + O => REG(23) + ); + REG_23_tsimcreated_xor_Q_314 : X_XOR2 + port map ( + I0 => REG_23_D, + I1 => REG_23_Q, + O => REG_23_tsimcreated_xor_Q + ); + REG_23_tsimcreated_set_and_noreset_Q_315 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_23_tsimcreated_set_and_noreset_IN0, + I1 => REG_23_SETF, + O => REG_23_tsimcreated_set_and_noreset_Q + ); + REG_23_tsimcreated_prld_Q_316 : X_OR2 + port map ( + I0 => REG_23_RSTF, + I1 => PRLD, + O => REG_23_tsimcreated_prld_Q + ); + REG_23_REG : X_FF + port map ( + I => REG_23_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_23_CLKF, + SET => REG_23_tsimcreated_set_and_noreset_Q, + RST => REG_23_tsimcreated_prld_Q, + O => REG_23_Q + ); + REG_23_D_317 : X_XOR2 + port map ( + I0 => REG_23_D1, + I1 => REG_23_D2, + O => REG_23_D + ); + REG_23_D1_318 : X_ZERO + port map ( + O => REG_23_D1 + ); + REG_23_D2_PT_0_319 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_23_D2_PT_0_IN0, + I1 => NlwInverterSignal_REG_23_D2_PT_0_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_23_D2_PT_0_IN3, + I4 => REG(22), + I5 => NlwInverterSignal_REG_23_D2_PT_0_IN5, + O => REG_23_D2_PT_0 + ); + REG_23_D2_PT_1_320 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_23_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_23_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_23_D2_PT_1_IN3, + I4 => NlwInverterSignal_REG_23_D2_PT_1_IN4, + I5 => REG(23), + O => REG_23_D2_PT_1 + ); + REG_23_D2_321 : X_OR2 + port map ( + I0 => REG_23_D2_PT_0, + I1 => REG_23_D2_PT_1, + O => REG_23_D2 + ); + REG_23_CLKF_322 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_23_CLKF_IN0, + I1 => NlwInverterSignal_REG_23_CLKF_IN1, + O => REG_23_CLKF + ); + REG_23_SETF_323 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => DIN_23_IBUF, + O => REG_23_SETF + ); + REG_23_RSTF_324 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => NlwInverterSignal_REG_23_RSTF_IN2, + O => REG_23_RSTF + ); + REG_24_Q_325 : X_BUF + port map ( + I => REG_24_Q, + O => REG(24) + ); + REG_24_tsimcreated_xor_Q_326 : X_XOR2 + port map ( + I0 => REG_24_D, + I1 => REG_24_Q, + O => REG_24_tsimcreated_xor_Q + ); + REG_24_tsimcreated_set_and_noreset_Q_327 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_24_tsimcreated_set_and_noreset_IN0, + I1 => REG_24_SETF, + O => REG_24_tsimcreated_set_and_noreset_Q + ); + REG_24_tsimcreated_prld_Q_328 : X_OR2 + port map ( + I0 => REG_24_RSTF, + I1 => PRLD, + O => REG_24_tsimcreated_prld_Q + ); + REG_24_REG : X_FF + port map ( + I => REG_24_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_24_CLKF, + SET => REG_24_tsimcreated_set_and_noreset_Q, + RST => REG_24_tsimcreated_prld_Q, + O => REG_24_Q + ); + REG_24_D_329 : X_XOR2 + port map ( + I0 => REG_24_D1, + I1 => REG_24_D2, + O => REG_24_D + ); + REG_24_D1_330 : X_ZERO + port map ( + O => REG_24_D1 + ); + REG_24_D2_PT_0_331 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_24_D2_PT_0_IN0, + I1 => NlwInverterSignal_REG_24_D2_PT_0_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_24_D2_PT_0_IN3, + I4 => REG(23), + I5 => NlwInverterSignal_REG_24_D2_PT_0_IN5, + O => REG_24_D2_PT_0 + ); + REG_24_D2_PT_1_332 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_24_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_24_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_24_D2_PT_1_IN3, + I4 => NlwInverterSignal_REG_24_D2_PT_1_IN4, + I5 => REG(24), + O => REG_24_D2_PT_1 + ); + REG_24_D2_333 : X_OR2 + port map ( + I0 => REG_24_D2_PT_0, + I1 => REG_24_D2_PT_1, + O => REG_24_D2 + ); + REG_24_CLKF_334 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_24_CLKF_IN0, + I1 => NlwInverterSignal_REG_24_CLKF_IN1, + O => REG_24_CLKF + ); + REG_24_SETF_335 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => DIN_24_IBUF, + O => REG_24_SETF + ); + REG_24_RSTF_336 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => NlwInverterSignal_REG_24_RSTF_IN2, + O => REG_24_RSTF + ); + REG_25_Q_337 : X_BUF + port map ( + I => REG_25_Q, + O => REG(25) + ); + REG_25_tsimcreated_xor_Q_338 : X_XOR2 + port map ( + I0 => REG_25_D, + I1 => REG_25_Q, + O => REG_25_tsimcreated_xor_Q + ); + REG_25_tsimcreated_set_and_noreset_Q_339 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_25_tsimcreated_set_and_noreset_IN0, + I1 => REG_25_SETF, + O => REG_25_tsimcreated_set_and_noreset_Q + ); + REG_25_tsimcreated_prld_Q_340 : X_OR2 + port map ( + I0 => REG_25_RSTF, + I1 => PRLD, + O => REG_25_tsimcreated_prld_Q + ); + REG_25_REG : X_FF + port map ( + I => REG_25_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_25_CLKF, + SET => REG_25_tsimcreated_set_and_noreset_Q, + RST => REG_25_tsimcreated_prld_Q, + O => REG_25_Q + ); + REG_25_D_341 : X_XOR2 + port map ( + I0 => REG_25_D1, + I1 => REG_25_D2, + O => REG_25_D + ); + REG_25_D1_342 : X_ZERO + port map ( + O => REG_25_D1 + ); + REG_25_D2_PT_0_343 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_25_D2_PT_0_IN0, + I1 => NlwInverterSignal_REG_25_D2_PT_0_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_25_D2_PT_0_IN3, + I4 => REG(24), + I5 => NlwInverterSignal_REG_25_D2_PT_0_IN5, + O => REG_25_D2_PT_0 + ); + REG_25_D2_PT_1_344 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_25_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_25_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_25_D2_PT_1_IN3, + I4 => NlwInverterSignal_REG_25_D2_PT_1_IN4, + I5 => REG(25), + O => REG_25_D2_PT_1 + ); + REG_25_D2_345 : X_OR2 + port map ( + I0 => REG_25_D2_PT_0, + I1 => REG_25_D2_PT_1, + O => REG_25_D2 + ); + REG_25_CLKF_346 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_25_CLKF_IN0, + I1 => NlwInverterSignal_REG_25_CLKF_IN1, + O => REG_25_CLKF + ); + REG_25_SETF_347 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => DIN_25_IBUF, + O => REG_25_SETF + ); + REG_25_RSTF_348 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => NlwInverterSignal_REG_25_RSTF_IN2, + O => REG_25_RSTF + ); + REG_26_Q_349 : X_BUF + port map ( + I => REG_26_Q, + O => REG(26) + ); + REG_26_tsimcreated_xor_Q_350 : X_XOR2 + port map ( + I0 => REG_26_D, + I1 => REG_26_Q, + O => REG_26_tsimcreated_xor_Q + ); + REG_26_tsimcreated_set_and_noreset_Q_351 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_26_tsimcreated_set_and_noreset_IN0, + I1 => REG_26_SETF, + O => REG_26_tsimcreated_set_and_noreset_Q + ); + REG_26_tsimcreated_prld_Q_352 : X_OR2 + port map ( + I0 => REG_26_RSTF, + I1 => PRLD, + O => REG_26_tsimcreated_prld_Q + ); + REG_26_REG : X_FF + port map ( + I => REG_26_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_26_CLKF, + SET => REG_26_tsimcreated_set_and_noreset_Q, + RST => REG_26_tsimcreated_prld_Q, + O => REG_26_Q + ); + REG_26_D_353 : X_XOR2 + port map ( + I0 => REG_26_D1, + I1 => REG_26_D2, + O => REG_26_D + ); + REG_26_D1_354 : X_ZERO + port map ( + O => REG_26_D1 + ); + REG_26_D2_PT_0_355 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_26_D2_PT_0_IN0, + I1 => NlwInverterSignal_REG_26_D2_PT_0_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_26_D2_PT_0_IN3, + I4 => REG(25), + I5 => NlwInverterSignal_REG_26_D2_PT_0_IN5, + O => REG_26_D2_PT_0 + ); + REG_26_D2_PT_1_356 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_26_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_26_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_26_D2_PT_1_IN3, + I4 => NlwInverterSignal_REG_26_D2_PT_1_IN4, + I5 => REG(26), + O => REG_26_D2_PT_1 + ); + REG_26_D2_357 : X_OR2 + port map ( + I0 => REG_26_D2_PT_0, + I1 => REG_26_D2_PT_1, + O => REG_26_D2 + ); + REG_26_CLKF_358 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_26_CLKF_IN0, + I1 => NlwInverterSignal_REG_26_CLKF_IN1, + O => REG_26_CLKF + ); + REG_26_SETF_359 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => DIN_26_IBUF, + O => REG_26_SETF + ); + REG_26_RSTF_360 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => NlwInverterSignal_REG_26_RSTF_IN2, + O => REG_26_RSTF + ); + REG_27_Q_361 : X_BUF + port map ( + I => REG_27_Q, + O => REG(27) + ); + REG_27_tsimcreated_xor_Q_362 : X_XOR2 + port map ( + I0 => REG_27_D, + I1 => REG_27_Q, + O => REG_27_tsimcreated_xor_Q + ); + REG_27_tsimcreated_set_and_noreset_Q_363 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_27_tsimcreated_set_and_noreset_IN0, + I1 => REG_27_SETF, + O => REG_27_tsimcreated_set_and_noreset_Q + ); + REG_27_tsimcreated_prld_Q_364 : X_OR2 + port map ( + I0 => REG_27_RSTF, + I1 => PRLD, + O => REG_27_tsimcreated_prld_Q + ); + REG_27_REG : X_FF + port map ( + I => REG_27_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_27_CLKF, + SET => REG_27_tsimcreated_set_and_noreset_Q, + RST => REG_27_tsimcreated_prld_Q, + O => REG_27_Q + ); + REG_27_D_365 : X_XOR2 + port map ( + I0 => REG_27_D1, + I1 => REG_27_D2, + O => REG_27_D + ); + REG_27_D1_366 : X_ZERO + port map ( + O => REG_27_D1 + ); + REG_27_D2_PT_0_367 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_27_D2_PT_0_IN0, + I1 => NlwInverterSignal_REG_27_D2_PT_0_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_27_D2_PT_0_IN3, + I4 => REG(26), + I5 => NlwInverterSignal_REG_27_D2_PT_0_IN5, + O => REG_27_D2_PT_0 + ); + REG_27_D2_PT_1_368 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_27_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_27_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_27_D2_PT_1_IN3, + I4 => NlwInverterSignal_REG_27_D2_PT_1_IN4, + I5 => REG(27), + O => REG_27_D2_PT_1 + ); + REG_27_D2_369 : X_OR2 + port map ( + I0 => REG_27_D2_PT_0, + I1 => REG_27_D2_PT_1, + O => REG_27_D2 + ); + REG_27_CLKF_370 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_27_CLKF_IN0, + I1 => NlwInverterSignal_REG_27_CLKF_IN1, + O => REG_27_CLKF + ); + REG_27_SETF_371 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => DIN_27_IBUF, + O => REG_27_SETF + ); + REG_27_RSTF_372 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => NlwInverterSignal_REG_27_RSTF_IN2, + O => REG_27_RSTF + ); + REG_28_Q_373 : X_BUF + port map ( + I => REG_28_Q, + O => REG(28) + ); + REG_28_tsimcreated_xor_Q_374 : X_XOR2 + port map ( + I0 => REG_28_D, + I1 => REG_28_Q, + O => REG_28_tsimcreated_xor_Q + ); + REG_28_tsimcreated_set_and_noreset_Q_375 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_28_tsimcreated_set_and_noreset_IN0, + I1 => REG_28_SETF, + O => REG_28_tsimcreated_set_and_noreset_Q + ); + REG_28_tsimcreated_prld_Q_376 : X_OR2 + port map ( + I0 => REG_28_RSTF, + I1 => PRLD, + O => REG_28_tsimcreated_prld_Q + ); + REG_28_REG : X_FF + port map ( + I => REG_28_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_28_CLKF, + SET => REG_28_tsimcreated_set_and_noreset_Q, + RST => REG_28_tsimcreated_prld_Q, + O => REG_28_Q + ); + REG_28_D_377 : X_XOR2 + port map ( + I0 => REG_28_D1, + I1 => REG_28_D2, + O => REG_28_D + ); + REG_28_D1_378 : X_ZERO + port map ( + O => REG_28_D1 + ); + REG_28_D2_PT_0_379 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_28_D2_PT_0_IN0, + I1 => NlwInverterSignal_REG_28_D2_PT_0_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_28_D2_PT_0_IN3, + I4 => REG(27), + I5 => NlwInverterSignal_REG_28_D2_PT_0_IN5, + O => REG_28_D2_PT_0 + ); + REG_28_D2_PT_1_380 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_28_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_28_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_28_D2_PT_1_IN3, + I4 => NlwInverterSignal_REG_28_D2_PT_1_IN4, + I5 => REG(28), + O => REG_28_D2_PT_1 + ); + REG_28_D2_381 : X_OR2 + port map ( + I0 => REG_28_D2_PT_0, + I1 => REG_28_D2_PT_1, + O => REG_28_D2 + ); + REG_28_CLKF_382 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_28_CLKF_IN0, + I1 => NlwInverterSignal_REG_28_CLKF_IN1, + O => REG_28_CLKF + ); + REG_28_SETF_383 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => DIN_28_IBUF, + O => REG_28_SETF + ); + REG_28_RSTF_384 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => NlwInverterSignal_REG_28_RSTF_IN2, + O => REG_28_RSTF + ); + REG_29_Q_385 : X_BUF + port map ( + I => REG_29_Q, + O => REG(29) + ); + REG_29_tsimcreated_xor_Q_386 : X_XOR2 + port map ( + I0 => REG_29_D, + I1 => REG_29_Q, + O => REG_29_tsimcreated_xor_Q + ); + REG_29_tsimcreated_set_and_noreset_Q_387 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_29_tsimcreated_set_and_noreset_IN0, + I1 => REG_29_SETF, + O => REG_29_tsimcreated_set_and_noreset_Q + ); + REG_29_tsimcreated_prld_Q_388 : X_OR2 + port map ( + I0 => REG_29_RSTF, + I1 => PRLD, + O => REG_29_tsimcreated_prld_Q + ); + REG_29_REG : X_FF + port map ( + I => REG_29_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_29_CLKF, + SET => REG_29_tsimcreated_set_and_noreset_Q, + RST => REG_29_tsimcreated_prld_Q, + O => REG_29_Q + ); + REG_29_D_389 : X_XOR2 + port map ( + I0 => REG_29_D1, + I1 => REG_29_D2, + O => REG_29_D + ); + REG_29_D1_390 : X_ZERO + port map ( + O => REG_29_D1 + ); + REG_29_D2_PT_0_391 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_29_D2_PT_0_IN0, + I1 => NlwInverterSignal_REG_29_D2_PT_0_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_29_D2_PT_0_IN3, + I4 => REG(28), + I5 => NlwInverterSignal_REG_29_D2_PT_0_IN5, + O => REG_29_D2_PT_0 + ); + REG_29_D2_PT_1_392 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_29_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_29_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_29_D2_PT_1_IN3, + I4 => NlwInverterSignal_REG_29_D2_PT_1_IN4, + I5 => REG(29), + O => REG_29_D2_PT_1 + ); + REG_29_D2_393 : X_OR2 + port map ( + I0 => REG_29_D2_PT_0, + I1 => REG_29_D2_PT_1, + O => REG_29_D2 + ); + REG_29_CLKF_394 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_29_CLKF_IN0, + I1 => NlwInverterSignal_REG_29_CLKF_IN1, + O => REG_29_CLKF + ); + REG_29_SETF_395 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => DIN_29_IBUF, + O => REG_29_SETF + ); + REG_29_RSTF_396 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => NlwInverterSignal_REG_29_RSTF_IN2, + O => REG_29_RSTF + ); + REG_2_Q_397 : X_BUF + port map ( + I => REG_2_Q, + O => REG(2) + ); + REG_2_tsimcreated_xor_Q_398 : X_XOR2 + port map ( + I0 => REG_2_D, + I1 => REG_2_Q, + O => REG_2_tsimcreated_xor_Q + ); + REG_2_tsimcreated_set_and_noreset_Q_399 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_2_tsimcreated_set_and_noreset_IN0, + I1 => REG_2_SETF, + O => REG_2_tsimcreated_set_and_noreset_Q + ); + REG_2_tsimcreated_prld_Q_400 : X_OR2 + port map ( + I0 => REG_2_RSTF, + I1 => PRLD, + O => REG_2_tsimcreated_prld_Q + ); + REG_2_REG : X_FF + port map ( + I => REG_2_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_2_CLKF, + SET => REG_2_tsimcreated_set_and_noreset_Q, + RST => REG_2_tsimcreated_prld_Q, + O => REG_2_Q + ); + REG_2_D_401 : X_XOR2 + port map ( + I0 => REG_2_D1, + I1 => REG_2_D2, + O => REG_2_D + ); + REG_2_D1_402 : X_ZERO + port map ( + O => REG_2_D1 + ); + REG_2_D2_PT_0_403 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_2_D2_PT_0_IN0, + I1 => NlwInverterSignal_REG_2_D2_PT_0_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_2_D2_PT_0_IN3, + I4 => REG(1), + I5 => NlwInverterSignal_REG_2_D2_PT_0_IN5, + O => REG_2_D2_PT_0 + ); + REG_2_D2_PT_1_404 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_2_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_2_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_2_D2_PT_1_IN3, + I4 => NlwInverterSignal_REG_2_D2_PT_1_IN4, + I5 => REG(2), + O => REG_2_D2_PT_1 + ); + REG_2_D2_405 : X_OR2 + port map ( + I0 => REG_2_D2_PT_0, + I1 => REG_2_D2_PT_1, + O => REG_2_D2 + ); + REG_2_CLKF_406 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_2_CLKF_IN0, + I1 => NlwInverterSignal_REG_2_CLKF_IN1, + O => REG_2_CLKF + ); + REG_2_SETF_407 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => DIN_2_IBUF, + O => REG_2_SETF + ); + REG_2_RSTF_408 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => NlwInverterSignal_REG_2_RSTF_IN2, + O => REG_2_RSTF + ); + REG_30_Q_409 : X_BUF + port map ( + I => REG_30_Q, + O => REG(30) + ); + REG_30_tsimcreated_xor_Q_410 : X_XOR2 + port map ( + I0 => REG_30_D, + I1 => REG_30_Q, + O => REG_30_tsimcreated_xor_Q + ); + REG_30_tsimcreated_set_and_noreset_Q_411 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_30_tsimcreated_set_and_noreset_IN0, + I1 => REG_30_SETF, + O => REG_30_tsimcreated_set_and_noreset_Q + ); + REG_30_tsimcreated_prld_Q_412 : X_OR2 + port map ( + I0 => REG_30_RSTF, + I1 => PRLD, + O => REG_30_tsimcreated_prld_Q + ); + REG_30_REG : X_FF + port map ( + I => REG_30_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_30_CLKF, + SET => REG_30_tsimcreated_set_and_noreset_Q, + RST => REG_30_tsimcreated_prld_Q, + O => REG_30_Q + ); + REG_30_D_413 : X_XOR2 + port map ( + I0 => REG_30_D1, + I1 => REG_30_D2, + O => REG_30_D + ); + REG_30_D1_414 : X_ZERO + port map ( + O => REG_30_D1 + ); + REG_30_D2_PT_0_415 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_30_D2_PT_0_IN0, + I1 => NlwInverterSignal_REG_30_D2_PT_0_IN1, + I2 => SHIFT_EN, + I3 => REG(30), + I4 => NlwInverterSignal_REG_30_D2_PT_0_IN4, + I5 => NlwInverterSignal_REG_30_D2_PT_0_IN5, + O => REG_30_D2_PT_0 + ); + REG_30_D2_PT_1_416 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_30_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_30_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_30_D2_PT_1_IN3, + I4 => NlwInverterSignal_REG_30_D2_PT_1_IN4, + I5 => REG(29), + O => REG_30_D2_PT_1 + ); + REG_30_D2_417 : X_OR2 + port map ( + I0 => REG_30_D2_PT_0, + I1 => REG_30_D2_PT_1, + O => REG_30_D2 + ); + REG_30_CLKF_418 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_30_CLKF_IN0, + I1 => NlwInverterSignal_REG_30_CLKF_IN1, + O => REG_30_CLKF + ); + REG_30_SETF_419 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => DIN_30_IBUF, + O => REG_30_SETF + ); + REG_30_RSTF_420 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => NlwInverterSignal_REG_30_RSTF_IN2, + O => REG_30_RSTF + ); + REG_3_Q_421 : X_BUF + port map ( + I => REG_3_Q, + O => REG(3) + ); + REG_3_tsimcreated_xor_Q_422 : X_XOR2 + port map ( + I0 => REG_3_D, + I1 => REG_3_Q, + O => REG_3_tsimcreated_xor_Q + ); + REG_3_tsimcreated_set_and_noreset_Q_423 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_3_tsimcreated_set_and_noreset_IN0, + I1 => REG_3_SETF, + O => REG_3_tsimcreated_set_and_noreset_Q + ); + REG_3_tsimcreated_prld_Q_424 : X_OR2 + port map ( + I0 => REG_3_RSTF, + I1 => PRLD, + O => REG_3_tsimcreated_prld_Q + ); + REG_3_REG : X_FF + port map ( + I => REG_3_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_3_CLKF, + SET => REG_3_tsimcreated_set_and_noreset_Q, + RST => REG_3_tsimcreated_prld_Q, + O => REG_3_Q + ); + REG_3_D_425 : X_XOR2 + port map ( + I0 => REG_3_D1, + I1 => REG_3_D2, + O => REG_3_D + ); + REG_3_D1_426 : X_ZERO + port map ( + O => REG_3_D1 + ); + REG_3_D2_PT_0_427 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_3_D2_PT_0_IN0, + I1 => NlwInverterSignal_REG_3_D2_PT_0_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_3_D2_PT_0_IN3, + I4 => REG(2), + I5 => NlwInverterSignal_REG_3_D2_PT_0_IN5, + O => REG_3_D2_PT_0 + ); + REG_3_D2_PT_1_428 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_3_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_3_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_3_D2_PT_1_IN3, + I4 => NlwInverterSignal_REG_3_D2_PT_1_IN4, + I5 => REG(3), + O => REG_3_D2_PT_1 + ); + REG_3_D2_429 : X_OR2 + port map ( + I0 => REG_3_D2_PT_0, + I1 => REG_3_D2_PT_1, + O => REG_3_D2 + ); + REG_3_CLKF_430 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_3_CLKF_IN0, + I1 => NlwInverterSignal_REG_3_CLKF_IN1, + O => REG_3_CLKF + ); + REG_3_SETF_431 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => DIN_3_IBUF, + O => REG_3_SETF + ); + REG_3_RSTF_432 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => NlwInverterSignal_REG_3_RSTF_IN2, + O => REG_3_RSTF + ); + REG_4_Q_433 : X_BUF + port map ( + I => REG_4_Q, + O => REG(4) + ); + REG_4_tsimcreated_xor_Q_434 : X_XOR2 + port map ( + I0 => REG_4_D, + I1 => REG_4_Q, + O => REG_4_tsimcreated_xor_Q + ); + REG_4_tsimcreated_set_and_noreset_Q_435 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_4_tsimcreated_set_and_noreset_IN0, + I1 => REG_4_SETF, + O => REG_4_tsimcreated_set_and_noreset_Q + ); + REG_4_tsimcreated_prld_Q_436 : X_OR2 + port map ( + I0 => REG_4_RSTF, + I1 => PRLD, + O => REG_4_tsimcreated_prld_Q + ); + REG_4_REG : X_FF + port map ( + I => REG_4_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_4_CLKF, + SET => REG_4_tsimcreated_set_and_noreset_Q, + RST => REG_4_tsimcreated_prld_Q, + O => REG_4_Q + ); + REG_4_D_437 : X_XOR2 + port map ( + I0 => REG_4_D1, + I1 => REG_4_D2, + O => REG_4_D + ); + REG_4_D1_438 : X_ZERO + port map ( + O => REG_4_D1 + ); + REG_4_D2_PT_0_439 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_4_D2_PT_0_IN0, + I1 => NlwInverterSignal_REG_4_D2_PT_0_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_4_D2_PT_0_IN3, + I4 => REG(3), + I5 => NlwInverterSignal_REG_4_D2_PT_0_IN5, + O => REG_4_D2_PT_0 + ); + REG_4_D2_PT_1_440 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_4_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_4_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_4_D2_PT_1_IN3, + I4 => NlwInverterSignal_REG_4_D2_PT_1_IN4, + I5 => REG(4), + O => REG_4_D2_PT_1 + ); + REG_4_D2_441 : X_OR2 + port map ( + I0 => REG_4_D2_PT_0, + I1 => REG_4_D2_PT_1, + O => REG_4_D2 + ); + REG_4_CLKF_442 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_4_CLKF_IN0, + I1 => NlwInverterSignal_REG_4_CLKF_IN1, + O => REG_4_CLKF + ); + REG_4_SETF_443 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => DIN_4_IBUF, + O => REG_4_SETF + ); + REG_4_RSTF_444 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => NlwInverterSignal_REG_4_RSTF_IN2, + O => REG_4_RSTF + ); + REG_5_Q_445 : X_BUF + port map ( + I => REG_5_Q, + O => REG(5) + ); + REG_5_tsimcreated_xor_Q_446 : X_XOR2 + port map ( + I0 => REG_5_D, + I1 => REG_5_Q, + O => REG_5_tsimcreated_xor_Q + ); + REG_5_tsimcreated_set_and_noreset_Q_447 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_5_tsimcreated_set_and_noreset_IN0, + I1 => REG_5_SETF, + O => REG_5_tsimcreated_set_and_noreset_Q + ); + REG_5_tsimcreated_prld_Q_448 : X_OR2 + port map ( + I0 => REG_5_RSTF, + I1 => PRLD, + O => REG_5_tsimcreated_prld_Q + ); + REG_5_REG : X_FF + port map ( + I => REG_5_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_5_CLKF, + SET => REG_5_tsimcreated_set_and_noreset_Q, + RST => REG_5_tsimcreated_prld_Q, + O => REG_5_Q + ); + REG_5_D_449 : X_XOR2 + port map ( + I0 => REG_5_D1, + I1 => REG_5_D2, + O => REG_5_D + ); + REG_5_D1_450 : X_ZERO + port map ( + O => REG_5_D1 + ); + REG_5_D2_PT_0_451 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_5_D2_PT_0_IN0, + I1 => NlwInverterSignal_REG_5_D2_PT_0_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_5_D2_PT_0_IN3, + I4 => REG(4), + I5 => NlwInverterSignal_REG_5_D2_PT_0_IN5, + O => REG_5_D2_PT_0 + ); + REG_5_D2_PT_1_452 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_5_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_5_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_5_D2_PT_1_IN3, + I4 => NlwInverterSignal_REG_5_D2_PT_1_IN4, + I5 => REG(5), + O => REG_5_D2_PT_1 + ); + REG_5_D2_453 : X_OR2 + port map ( + I0 => REG_5_D2_PT_0, + I1 => REG_5_D2_PT_1, + O => REG_5_D2 + ); + REG_5_CLKF_454 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_5_CLKF_IN0, + I1 => NlwInverterSignal_REG_5_CLKF_IN1, + O => REG_5_CLKF + ); + REG_5_SETF_455 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => DIN_5_IBUF, + O => REG_5_SETF + ); + REG_5_RSTF_456 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => NlwInverterSignal_REG_5_RSTF_IN2, + O => REG_5_RSTF + ); + REG_6_Q_457 : X_BUF + port map ( + I => REG_6_Q, + O => REG(6) + ); + REG_6_tsimcreated_xor_Q_458 : X_XOR2 + port map ( + I0 => REG_6_D, + I1 => REG_6_Q, + O => REG_6_tsimcreated_xor_Q + ); + REG_6_tsimcreated_set_and_noreset_Q_459 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_6_tsimcreated_set_and_noreset_IN0, + I1 => REG_6_SETF, + O => REG_6_tsimcreated_set_and_noreset_Q + ); + REG_6_tsimcreated_prld_Q_460 : X_OR2 + port map ( + I0 => REG_6_RSTF, + I1 => PRLD, + O => REG_6_tsimcreated_prld_Q + ); + REG_6_REG : X_FF + port map ( + I => REG_6_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_6_CLKF, + SET => REG_6_tsimcreated_set_and_noreset_Q, + RST => REG_6_tsimcreated_prld_Q, + O => REG_6_Q + ); + REG_6_D_461 : X_XOR2 + port map ( + I0 => REG_6_D1, + I1 => REG_6_D2, + O => REG_6_D + ); + REG_6_D1_462 : X_ZERO + port map ( + O => REG_6_D1 + ); + REG_6_D2_PT_0_463 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_6_D2_PT_0_IN0, + I1 => NlwInverterSignal_REG_6_D2_PT_0_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_6_D2_PT_0_IN3, + I4 => REG(5), + I5 => NlwInverterSignal_REG_6_D2_PT_0_IN5, + O => REG_6_D2_PT_0 + ); + REG_6_D2_PT_1_464 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_6_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_6_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_6_D2_PT_1_IN3, + I4 => NlwInverterSignal_REG_6_D2_PT_1_IN4, + I5 => REG(6), + O => REG_6_D2_PT_1 + ); + REG_6_D2_465 : X_OR2 + port map ( + I0 => REG_6_D2_PT_0, + I1 => REG_6_D2_PT_1, + O => REG_6_D2 + ); + REG_6_CLKF_466 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_6_CLKF_IN0, + I1 => NlwInverterSignal_REG_6_CLKF_IN1, + O => REG_6_CLKF + ); + REG_6_SETF_467 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => DIN_6_IBUF, + O => REG_6_SETF + ); + REG_6_RSTF_468 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => NlwInverterSignal_REG_6_RSTF_IN2, + O => REG_6_RSTF + ); + REG_7_Q_469 : X_BUF + port map ( + I => REG_7_Q, + O => REG(7) + ); + REG_7_tsimcreated_xor_Q_470 : X_XOR2 + port map ( + I0 => REG_7_D, + I1 => REG_7_Q, + O => REG_7_tsimcreated_xor_Q + ); + REG_7_tsimcreated_set_and_noreset_Q_471 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_7_tsimcreated_set_and_noreset_IN0, + I1 => REG_7_SETF, + O => REG_7_tsimcreated_set_and_noreset_Q + ); + REG_7_tsimcreated_prld_Q_472 : X_OR2 + port map ( + I0 => REG_7_RSTF, + I1 => PRLD, + O => REG_7_tsimcreated_prld_Q + ); + REG_7_REG : X_FF + port map ( + I => REG_7_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_7_CLKF, + SET => REG_7_tsimcreated_set_and_noreset_Q, + RST => REG_7_tsimcreated_prld_Q, + O => REG_7_Q + ); + REG_7_D_473 : X_XOR2 + port map ( + I0 => REG_7_D1, + I1 => REG_7_D2, + O => REG_7_D + ); + REG_7_D1_474 : X_ZERO + port map ( + O => REG_7_D1 + ); + REG_7_D2_PT_0_475 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_7_D2_PT_0_IN0, + I1 => NlwInverterSignal_REG_7_D2_PT_0_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_7_D2_PT_0_IN3, + I4 => REG(6), + I5 => NlwInverterSignal_REG_7_D2_PT_0_IN5, + O => REG_7_D2_PT_0 + ); + REG_7_D2_PT_1_476 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_7_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_7_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_7_D2_PT_1_IN3, + I4 => NlwInverterSignal_REG_7_D2_PT_1_IN4, + I5 => REG(7), + O => REG_7_D2_PT_1 + ); + REG_7_D2_477 : X_OR2 + port map ( + I0 => REG_7_D2_PT_0, + I1 => REG_7_D2_PT_1, + O => REG_7_D2 + ); + REG_7_CLKF_478 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_7_CLKF_IN0, + I1 => NlwInverterSignal_REG_7_CLKF_IN1, + O => REG_7_CLKF + ); + REG_7_SETF_479 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => DIN_7_IBUF, + O => REG_7_SETF + ); + REG_7_RSTF_480 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => NlwInverterSignal_REG_7_RSTF_IN2, + O => REG_7_RSTF + ); + REG_8_Q_481 : X_BUF + port map ( + I => REG_8_Q, + O => REG(8) + ); + REG_8_tsimcreated_xor_Q_482 : X_XOR2 + port map ( + I0 => REG_8_D, + I1 => REG_8_Q, + O => REG_8_tsimcreated_xor_Q + ); + REG_8_tsimcreated_set_and_noreset_Q_483 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_8_tsimcreated_set_and_noreset_IN0, + I1 => REG_8_SETF, + O => REG_8_tsimcreated_set_and_noreset_Q + ); + REG_8_tsimcreated_prld_Q_484 : X_OR2 + port map ( + I0 => REG_8_RSTF, + I1 => PRLD, + O => REG_8_tsimcreated_prld_Q + ); + REG_8_REG : X_FF + port map ( + I => REG_8_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_8_CLKF, + SET => REG_8_tsimcreated_set_and_noreset_Q, + RST => REG_8_tsimcreated_prld_Q, + O => REG_8_Q + ); + REG_8_D_485 : X_XOR2 + port map ( + I0 => REG_8_D1, + I1 => REG_8_D2, + O => REG_8_D + ); + REG_8_D1_486 : X_ZERO + port map ( + O => REG_8_D1 + ); + REG_8_D2_PT_0_487 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_8_D2_PT_0_IN0, + I1 => NlwInverterSignal_REG_8_D2_PT_0_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_8_D2_PT_0_IN3, + I4 => REG(7), + I5 => NlwInverterSignal_REG_8_D2_PT_0_IN5, + O => REG_8_D2_PT_0 + ); + REG_8_D2_PT_1_488 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_8_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_8_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_8_D2_PT_1_IN3, + I4 => NlwInverterSignal_REG_8_D2_PT_1_IN4, + I5 => REG(8), + O => REG_8_D2_PT_1 + ); + REG_8_D2_489 : X_OR2 + port map ( + I0 => REG_8_D2_PT_0, + I1 => REG_8_D2_PT_1, + O => REG_8_D2 + ); + REG_8_CLKF_490 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_8_CLKF_IN0, + I1 => NlwInverterSignal_REG_8_CLKF_IN1, + O => REG_8_CLKF + ); + REG_8_SETF_491 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => DIN_8_IBUF, + O => REG_8_SETF + ); + REG_8_RSTF_492 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => NlwInverterSignal_REG_8_RSTF_IN2, + O => REG_8_RSTF + ); + REG_9_Q_493 : X_BUF + port map ( + I => REG_9_Q, + O => REG(9) + ); + REG_9_tsimcreated_xor_Q_494 : X_XOR2 + port map ( + I0 => REG_9_D, + I1 => REG_9_Q, + O => REG_9_tsimcreated_xor_Q + ); + REG_9_tsimcreated_set_and_noreset_Q_495 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_9_tsimcreated_set_and_noreset_IN0, + I1 => REG_9_SETF, + O => REG_9_tsimcreated_set_and_noreset_Q + ); + REG_9_tsimcreated_prld_Q_496 : X_OR2 + port map ( + I0 => REG_9_RSTF, + I1 => PRLD, + O => REG_9_tsimcreated_prld_Q + ); + REG_9_REG : X_FF + port map ( + I => REG_9_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_9_CLKF, + SET => REG_9_tsimcreated_set_and_noreset_Q, + RST => REG_9_tsimcreated_prld_Q, + O => REG_9_Q + ); + REG_9_D_497 : X_XOR2 + port map ( + I0 => REG_9_D1, + I1 => REG_9_D2, + O => REG_9_D + ); + REG_9_D1_498 : X_ZERO + port map ( + O => REG_9_D1 + ); + REG_9_D2_PT_0_499 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_9_D2_PT_0_IN0, + I1 => NlwInverterSignal_REG_9_D2_PT_0_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_9_D2_PT_0_IN3, + I4 => REG(9), + I5 => NlwInverterSignal_REG_9_D2_PT_0_IN5, + O => REG_9_D2_PT_0 + ); + REG_9_D2_PT_1_500 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_9_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_9_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_9_D2_PT_1_IN3, + I4 => NlwInverterSignal_REG_9_D2_PT_1_IN4, + I5 => REG(8), + O => REG_9_D2_PT_1 + ); + REG_9_D2_501 : X_OR2 + port map ( + I0 => REG_9_D2_PT_0, + I1 => REG_9_D2_PT_1, + O => REG_9_D2 + ); + REG_9_CLKF_502 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_9_CLKF_IN0, + I1 => NlwInverterSignal_REG_9_CLKF_IN1, + O => REG_9_CLKF + ); + REG_9_SETF_503 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => DIN_9_IBUF, + O => REG_9_SETF + ); + REG_9_RSTF_504 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => SREG_IS_EMPTY, + I2 => NlwInverterSignal_REG_9_RSTF_IN2, + O => REG_9_RSTF + ); + count_5_Q_505 : X_BUF + port map ( + I => count_5_Q, + O => count(5) + ); + count_5_EXP_506 : X_BUF + port map ( + I => count_5_EXP_tsimrenamed_net_Q, + O => count_5_EXP + ); + count_5_tsimcreated_xor_Q_507 : X_XOR2 + port map ( + I0 => count_5_D, + I1 => count_5_Q, + O => count_5_tsimcreated_xor_Q + ); + count_5_tsimcreated_set_and_noreset_Q_508 : X_AND2 + port map ( + I0 => NlwInverterSignal_count_5_tsimcreated_set_and_noreset_IN0, + I1 => count_5_SETF, + O => count_5_tsimcreated_set_and_noreset_Q + ); + count_5_tsimcreated_prld_Q_509 : X_OR2 + port map ( + I0 => count_5_RSTF, + I1 => PRLD, + O => count_5_tsimcreated_prld_Q + ); + count_5_REG : X_FF + port map ( + I => count_5_tsimcreated_xor_Q, + CE => Vcc, + CLK => FCLKIO_0, + SET => count_5_tsimcreated_set_and_noreset_Q, + RST => count_5_tsimcreated_prld_Q, + O => count_5_Q + ); + count_5_D_510 : X_XOR2 + port map ( + I0 => count_5_D1, + I1 => count_5_D2, + O => count_5_D + ); + count_5_D1_511 : X_ZERO + port map ( + O => count_5_D1 + ); + count_5_D2_PT_0_512 : X_AND2 + port map ( + I0 => EXP18_EXP, + I1 => EXP18_EXP, + O => count_5_D2_PT_0 + ); + count_5_D2_PT_1_513 : X_AND3 + port map ( + I0 => RES_IBUF, + I1 => count(5), + I2 => NlwInverterSignal_count_5_D2_PT_1_IN2, + O => count_5_D2_PT_1 + ); + count_5_D2_PT_2_514 : X_AND3 + port map ( + I0 => RES_IBUF, + I1 => NlwInverterSignal_count_5_D2_PT_2_IN1, + I2 => VCLK_PRESCALE_5_IBUF, + O => count_5_D2_PT_2 + ); + count_5_D2_515 : X_OR3 + port map ( + I0 => count_5_D2_PT_0, + I1 => count_5_D2_PT_1, + I2 => count_5_D2_PT_2, + O => count_5_D2 + ); + count_5_SETF_516 : X_AND2 + port map ( + I0 => RES_IBUF, + I1 => VCLK_PRESCALE_5_IBUF, + O => count_5_SETF + ); + count_5_RSTF_517 : X_AND2 + port map ( + I0 => RES_IBUF, + I1 => NlwInverterSignal_count_5_RSTF_IN1, + O => count_5_RSTF + ); + count_5_EXP_tsimrenamed_net_Q_518 : X_AND6 + port map ( + I0 => NlwInverterSignal_count_5_EXP_tsimrenamed_net_IN0, + I1 => NlwInverterSignal_count_5_EXP_tsimrenamed_net_IN1, + I2 => NlwInverterSignal_count_5_EXP_tsimrenamed_net_IN2, + I3 => NlwInverterSignal_count_5_EXP_tsimrenamed_net_IN3, + I4 => NlwInverterSignal_count_5_EXP_tsimrenamed_net_IN4, + I5 => NlwInverterSignal_count_5_EXP_tsimrenamed_net_IN5, + O => count_5_EXP_tsimrenamed_net_Q + ); + SREG_IS_EMPTY_519 : X_BUF + port map ( + I => SREG_IS_EMPTY_Q, + O => SREG_IS_EMPTY + ); + SREG_IS_EMPTY_tsimcreated_set_and_noreset_Q_520 : X_AND2 + port map ( + I0 => NlwInverterSignal_SREG_IS_EMPTY_tsimcreated_set_and_noreset_IN0, + I1 => SREG_IS_EMPTY_SETF, + O => SREG_IS_EMPTY_tsimcreated_set_and_noreset_Q + ); + SREG_IS_EMPTY_tsimcreated_prld_Q_521 : X_OR2 + port map ( + I0 => SREG_IS_EMPTY_RSTF, + I1 => PRLD, + O => SREG_IS_EMPTY_tsimcreated_prld_Q + ); + SREG_IS_EMPTY_REG : X_FF + port map ( + I => SREG_IS_EMPTY_D, + CE => Vcc, + CLK => SREG_IS_EMPTY_CLKF, + SET => SREG_IS_EMPTY_tsimcreated_set_and_noreset_Q, + RST => SREG_IS_EMPTY_tsimcreated_prld_Q, + O => SREG_IS_EMPTY_Q + ); + SREG_IS_EMPTY_D_522 : X_XOR2 + port map ( + I0 => SREG_IS_EMPTY_D1, + I1 => SREG_IS_EMPTY_D2, + O => SREG_IS_EMPTY_D + ); + SREG_IS_EMPTY_D1_523 : X_ZERO + port map ( + O => SREG_IS_EMPTY_D1 + ); + SREG_IS_EMPTY_D2_524 : X_ZERO + port map ( + O => SREG_IS_EMPTY_D2 + ); + SREG_IS_EMPTY_CLKF_525 : X_ZERO + port map ( + O => SREG_IS_EMPTY_CLKF + ); + SREG_IS_EMPTY_SETF_526 : X_AND2 + port map ( + I0 => SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_UIM, + I1 => SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_UIM, + O => SREG_IS_EMPTY_SETF + ); + SREG_IS_EMPTY_RSTF_527 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => NlwInverterSignal_SREG_IS_EMPTY_RSTF_IN1, + I2 => SREG_IS_EMPTY, + O => SREG_IS_EMPTY_RSTF + ); + SHIFT_CNT_0_Q_528 : X_BUF + port map ( + I => SHIFT_CNT_0_Q, + O => SHIFT_CNT(0) + ); + SHIFT_CNT_0_tsimcreated_set_and_noreset_Q_529 : X_AND2 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_0_tsimcreated_set_and_noreset_IN0, + I1 => SHIFT_CNT_0_SETF, + O => SHIFT_CNT_0_tsimcreated_set_and_noreset_Q + ); + SHIFT_CNT_0_tsimcreated_prld_Q_530 : X_OR2 + port map ( + I0 => SHIFT_CNT_0_RSTF, + I1 => PRLD, + O => SHIFT_CNT_0_tsimcreated_prld_Q + ); + SHIFT_CNT_0_REG : X_FF + port map ( + I => SHIFT_CNT_0_D, + CE => Vcc, + CLK => SHIFT_CNT_0_CLKF, + SET => SHIFT_CNT_0_tsimcreated_set_and_noreset_Q, + RST => SHIFT_CNT_0_tsimcreated_prld_Q, + O => SHIFT_CNT_0_Q + ); + SHIFT_CNT_0_D_531 : X_XOR2 + port map ( + I0 => SHIFT_CNT_0_D1, + I1 => SHIFT_CNT_0_D2, + O => SHIFT_CNT_0_D + ); + SHIFT_CNT_0_D1_532 : X_ZERO + port map ( + O => SHIFT_CNT_0_D1 + ); + SHIFT_CNT_0_D2_533 : X_ZERO + port map ( + O => SHIFT_CNT_0_D2 + ); + SHIFT_CNT_0_CLKF_534 : X_ZERO + port map ( + O => SHIFT_CNT_0_CLKF + ); + SHIFT_CNT_0_SETF_535 : X_AND2 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_0_SETF_IN0, + I1 => NlwInverterSignal_SHIFT_CNT_0_SETF_IN1, + O => SHIFT_CNT_0_SETF + ); + SHIFT_CNT_0_RSTF_536 : X_AND4 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_0_RSTF_IN0, + I1 => NlwInverterSignal_SHIFT_CNT_0_RSTF_IN1, + I2 => SHIFT_EN, + I3 => SHIFT_CNT(0), + O => SHIFT_CNT_0_RSTF + ); + SHIFT_CNT_1_Q_537 : X_BUF + port map ( + I => SHIFT_CNT_1_Q, + O => SHIFT_CNT(1) + ); + SHIFT_CNT_1_tsimcreated_set_and_noreset_Q_538 : X_AND2 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_1_tsimcreated_set_and_noreset_IN0, + I1 => SHIFT_CNT_1_SETF, + O => SHIFT_CNT_1_tsimcreated_set_and_noreset_Q + ); + SHIFT_CNT_1_tsimcreated_prld_Q_539 : X_OR2 + port map ( + I0 => SHIFT_CNT_1_RSTF, + I1 => PRLD, + O => SHIFT_CNT_1_tsimcreated_prld_Q + ); + SHIFT_CNT_1_REG : X_FF + port map ( + I => SHIFT_CNT_1_D, + CE => Vcc, + CLK => SHIFT_CNT_1_CLKF, + SET => SHIFT_CNT_1_tsimcreated_set_and_noreset_Q, + RST => SHIFT_CNT_1_tsimcreated_prld_Q, + O => SHIFT_CNT_1_Q + ); + SHIFT_CNT_1_D_540 : X_XOR2 + port map ( + I0 => SHIFT_CNT_1_D1, + I1 => SHIFT_CNT_1_D2, + O => SHIFT_CNT_1_D + ); + SHIFT_CNT_1_D1_541 : X_ZERO + port map ( + O => SHIFT_CNT_1_D1 + ); + SHIFT_CNT_1_D2_542 : X_ZERO + port map ( + O => SHIFT_CNT_1_D2 + ); + SHIFT_CNT_1_CLKF_543 : X_ZERO + port map ( + O => SHIFT_CNT_1_CLKF + ); + SHIFT_CNT_1_SETF_544 : X_AND2 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_1_SETF_IN0, + I1 => NlwInverterSignal_SHIFT_CNT_1_SETF_IN1, + O => SHIFT_CNT_1_SETF + ); + SHIFT_CNT_1_RSTF_545 : X_AND5 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_1_RSTF_IN0, + I1 => NlwInverterSignal_SHIFT_CNT_1_RSTF_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_SHIFT_CNT_1_RSTF_IN3, + I4 => NlwInverterSignal_SHIFT_CNT_1_RSTF_IN4, + O => SHIFT_CNT_1_RSTF + ); + SHIFT_CNT_2_Q_546 : X_BUF + port map ( + I => SHIFT_CNT_2_Q, + O => SHIFT_CNT(2) + ); + SHIFT_CNT_2_tsimcreated_set_and_noreset_Q_547 : X_AND2 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_2_tsimcreated_set_and_noreset_IN0, + I1 => SHIFT_CNT_2_SETF, + O => SHIFT_CNT_2_tsimcreated_set_and_noreset_Q + ); + SHIFT_CNT_2_tsimcreated_prld_Q_548 : X_OR2 + port map ( + I0 => SHIFT_CNT_2_RSTF, + I1 => PRLD, + O => SHIFT_CNT_2_tsimcreated_prld_Q + ); + SHIFT_CNT_2_REG : X_FF + port map ( + I => SHIFT_CNT_2_D, + CE => Vcc, + CLK => SHIFT_CNT_2_CLKF, + SET => SHIFT_CNT_2_tsimcreated_set_and_noreset_Q, + RST => SHIFT_CNT_2_tsimcreated_prld_Q, + O => SHIFT_CNT_2_Q + ); + SHIFT_CNT_2_D_549 : X_XOR2 + port map ( + I0 => SHIFT_CNT_2_D1, + I1 => SHIFT_CNT_2_D2, + O => SHIFT_CNT_2_D + ); + SHIFT_CNT_2_D1_550 : X_ZERO + port map ( + O => SHIFT_CNT_2_D1 + ); + SHIFT_CNT_2_D2_551 : X_ZERO + port map ( + O => SHIFT_CNT_2_D2 + ); + SHIFT_CNT_2_CLKF_552 : X_ZERO + port map ( + O => SHIFT_CNT_2_CLKF + ); + SHIFT_CNT_2_SETF_553 : X_AND2 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_2_SETF_IN0, + I1 => NlwInverterSignal_SHIFT_CNT_2_SETF_IN1, + O => SHIFT_CNT_2_SETF + ); + SHIFT_CNT_2_RSTF_554 : X_AND2 + port map ( + I0 => SHIFT_CNT_2_SHIFT_CNT_2_RSTF_UIM, + I1 => SHIFT_CNT_2_SHIFT_CNT_2_RSTF_UIM, + O => SHIFT_CNT_2_RSTF + ); + SHIFT_CNT_3_Q_555 : X_BUF + port map ( + I => SHIFT_CNT_3_Q, + O => SHIFT_CNT(3) + ); + SHIFT_CNT_3_tsimcreated_set_and_noreset_Q_556 : X_AND2 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_3_tsimcreated_set_and_noreset_IN0, + I1 => SHIFT_CNT_3_SETF, + O => SHIFT_CNT_3_tsimcreated_set_and_noreset_Q + ); + SHIFT_CNT_3_tsimcreated_prld_Q_557 : X_OR2 + port map ( + I0 => SHIFT_CNT_3_RSTF, + I1 => PRLD, + O => SHIFT_CNT_3_tsimcreated_prld_Q + ); + SHIFT_CNT_3_REG : X_FF + port map ( + I => SHIFT_CNT_3_D, + CE => Vcc, + CLK => SHIFT_CNT_3_CLKF, + SET => SHIFT_CNT_3_tsimcreated_set_and_noreset_Q, + RST => SHIFT_CNT_3_tsimcreated_prld_Q, + O => SHIFT_CNT_3_Q + ); + SHIFT_CNT_3_D_558 : X_XOR2 + port map ( + I0 => SHIFT_CNT_3_D1, + I1 => SHIFT_CNT_3_D2, + O => SHIFT_CNT_3_D + ); + SHIFT_CNT_3_D1_559 : X_ZERO + port map ( + O => SHIFT_CNT_3_D1 + ); + SHIFT_CNT_3_D2_560 : X_ZERO + port map ( + O => SHIFT_CNT_3_D2 + ); + SHIFT_CNT_3_CLKF_561 : X_ZERO + port map ( + O => SHIFT_CNT_3_CLKF + ); + SHIFT_CNT_3_SETF_562 : X_AND2 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_3_SETF_IN0, + I1 => NlwInverterSignal_SHIFT_CNT_3_SETF_IN1, + O => SHIFT_CNT_3_SETF + ); + SHIFT_CNT_3_RSTF_563 : X_AND5 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_3_RSTF_IN0, + I1 => NlwInverterSignal_SHIFT_CNT_3_RSTF_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_SHIFT_CNT_3_RSTF_IN3, + I4 => Q_OpTx_FX_DC_20_UIM, + O => SHIFT_CNT_3_RSTF + ); + SHIFT_CNT_4_Q_564 : X_BUF + port map ( + I => SHIFT_CNT_4_Q, + O => SHIFT_CNT(4) + ); + SHIFT_CNT_4_tsimcreated_set_and_noreset_Q_565 : X_AND2 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_4_tsimcreated_set_and_noreset_IN0, + I1 => SHIFT_CNT_4_SETF, + O => SHIFT_CNT_4_tsimcreated_set_and_noreset_Q + ); + SHIFT_CNT_4_tsimcreated_prld_Q_566 : X_OR2 + port map ( + I0 => SHIFT_CNT_4_RSTF, + I1 => PRLD, + O => SHIFT_CNT_4_tsimcreated_prld_Q + ); + SHIFT_CNT_4_REG : X_FF + port map ( + I => SHIFT_CNT_4_D, + CE => Vcc, + CLK => SHIFT_CNT_4_CLKF, + SET => SHIFT_CNT_4_tsimcreated_set_and_noreset_Q, + RST => SHIFT_CNT_4_tsimcreated_prld_Q, + O => SHIFT_CNT_4_Q + ); + SHIFT_CNT_4_D_567 : X_XOR2 + port map ( + I0 => SHIFT_CNT_4_D1, + I1 => SHIFT_CNT_4_D2, + O => SHIFT_CNT_4_D + ); + SHIFT_CNT_4_D1_568 : X_ZERO + port map ( + O => SHIFT_CNT_4_D1 + ); + SHIFT_CNT_4_D2_569 : X_ZERO + port map ( + O => SHIFT_CNT_4_D2 + ); + SHIFT_CNT_4_CLKF_570 : X_ZERO + port map ( + O => SHIFT_CNT_4_CLKF + ); + SHIFT_CNT_4_SETF_571 : X_AND2 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_4_SETF_IN0, + I1 => NlwInverterSignal_SHIFT_CNT_4_SETF_IN1, + O => SHIFT_CNT_4_SETF + ); + SHIFT_CNT_4_RSTF_572 : X_AND2 + port map ( + I0 => Q_OpTx_FX_DC_21_UIM, + I1 => NlwInverterSignal_SHIFT_CNT_4_RSTF_IN1, + O => SHIFT_CNT_4_RSTF + ); + VCLK_OBUF_Q_573 : X_BUF + port map ( + I => VCLK_OBUF_Q_1, + O => VCLK_OBUF_Q + ); + SCLK_574 : X_BUF + port map ( + I => VCLK_OBUF_Q_1, + O => SCLK + ); + VCLK_OBUF_tsimcreated_xor_Q_575 : X_XOR2 + port map ( + I0 => VCLK_OBUF_D, + I1 => VCLK_OBUF_Q_1, + O => VCLK_OBUF_tsimcreated_xor_Q + ); + VCLK_OBUF_REG : X_FF + port map ( + I => VCLK_OBUF_tsimcreated_xor_Q, + CE => VCLK_OBUF_CE, + CLK => FCLKIO_0, + SET => PRLD, + RST => VCLK_OBUF_RSTF, + O => VCLK_OBUF_Q_1 + ); + VCLK_OBUF_D_576 : X_XOR2 + port map ( + I0 => VCLK_OBUF_D1, + I1 => VCLK_OBUF_D2, + O => VCLK_OBUF_D + ); + VCLK_OBUF_D1_577 : X_ZERO + port map ( + O => VCLK_OBUF_D1 + ); + VCLK_OBUF_D2_578 : X_ONE + port map ( + O => VCLK_OBUF_D2 + ); + VCLK_OBUF_RSTF_579 : X_AND2 + port map ( + I0 => RES_IBUF, + I1 => RES_IBUF, + O => VCLK_OBUF_RSTF + ); + VCLK_OBUF_CE_580 : X_AND6 + port map ( + I0 => NlwInverterSignal_VCLK_OBUF_CE_IN0, + I1 => NlwInverterSignal_VCLK_OBUF_CE_IN1, + I2 => NlwInverterSignal_VCLK_OBUF_CE_IN2, + I3 => NlwInverterSignal_VCLK_OBUF_CE_IN3, + I4 => NlwInverterSignal_VCLK_OBUF_CE_IN4, + I5 => NlwInverterSignal_VCLK_OBUF_CE_IN5, + O => VCLK_OBUF_CE + ); + SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_UIM_581 : X_BUF + port map ( + I => SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_Q, + O => SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_UIM + ); + SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_Q_582 : X_BUF + port map ( + I => SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D, + O => SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_Q + ); + SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D_583 : X_XOR2 + port map ( + I0 => SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D1, + I1 => SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2, + O => SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D + ); + SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D1_584 : X_ZERO + port map ( + O => SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D1 + ); + SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_0_585 : X_AND2 + port map ( + I0 => RES_IBUF, + I1 => RES_IBUF, + O => SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_0 + ); + SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_586 : X_AND7 + port map ( + I0 => NlwInverterSignal_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN0, + I1 => SHIFT_EN, + I2 => NlwInverterSignal_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN2, + I3 => NlwInverterSignal_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN3, + I4 => NlwInverterSignal_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN4, + I5 => NlwInverterSignal_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN5, + I6 => NlwInverterSignal_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN6, + O => SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1 + ); + SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_587 : X_OR2 + port map ( + I0 => SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_0, + I1 => SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1, + O => SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2 + ); + SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_UIM_588 : X_BUF + port map ( + I => SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_Q, + O => SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_UIM + ); + SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_Q_589 : X_BUF + port map ( + I => SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D, + O => SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_Q + ); + SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D_590 : X_XOR2 + port map ( + I0 => SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D1, + I1 => SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2, + O => SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D + ); + SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D1_591 : X_ZERO + port map ( + O => SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D1 + ); + SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_0_592 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_0_IN1, + I2 => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_0_IN2, + O => SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_0 + ); + SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_1_593 : X_AND3 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_1_IN0, + I1 => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_1_IN1, + I2 => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_1_IN2, + O => SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_1 + ); + SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_2_594 : X_AND3 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_2_IN0, + I1 => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_2_IN1, + I2 => SHIFT_CNT(0), + O => SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_2 + ); + SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_595 : X_AND6 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN0, + I1 => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN1, + I2 => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN2, + I3 => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN3, + I4 => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN4, + I5 => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN5, + O => SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3 + ); + SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_596 : X_OR4 + port map ( + I0 => SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_0, + I1 => SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_1, + I2 => SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_2, + I3 => SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3, + O => SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2 + ); + SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_UIM_597 : X_BUF + port map ( + I => SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_Q, + O => SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_UIM + ); + SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_Q_598 : X_BUF + port map ( + I => SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D, + O => SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_Q + ); + SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D_599 : X_XOR2 + port map ( + I0 => SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D1, + I1 => SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2, + O => SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D + ); + SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D1_600 : X_ZERO + port map ( + O => SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D1 + ); + SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_0_601 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_0_IN1, + I2 => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_0_IN2, + O => SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_0 + ); + SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_1_602 : X_AND3 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_1_IN0, + I1 => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_1_IN1, + I2 => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_1_IN2, + O => SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_1 + ); + SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_2_603 : X_AND4 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_2_IN0, + I1 => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_2_IN1, + I2 => SHIFT_CNT(0), + I3 => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_2_IN3, + O => SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_2 + ); + SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_3_604 : X_AND4 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_3_IN0, + I1 => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_3_IN1, + I2 => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_3_IN2, + I3 => SHIFT_CNT(1), + O => SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_3 + ); + SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_605 : X_AND6 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN0, + I1 => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN1, + I2 => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN2, + I3 => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN3, + I4 => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN4, + I5 => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN5, + O => SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4 + ); + SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_606 : X_OR5 + port map ( + I0 => SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_0, + I1 => SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_1, + I2 => SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_2, + I3 => SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_3, + I4 => SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4, + O => SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2 + ); + Msub_n0025_n00002_Msub_n0025_n00002_D2_UIM_607 : X_BUF + port map ( + I => Msub_n0025_n00002_Msub_n0025_n00002_D2_Q, + O => Msub_n0025_n00002_Msub_n0025_n00002_D2_UIM + ); + Msub_n0025_n00002_Msub_n0025_n00002_D2_Q_608 : X_BUF + port map ( + I => Msub_n0025_n00002_Msub_n0025_n00002_D2_D, + O => Msub_n0025_n00002_Msub_n0025_n00002_D2_Q + ); + Msub_n0025_n00002_Msub_n0025_n00002_D2_D_609 : X_XOR2 + port map ( + I0 => Msub_n0025_n00002_Msub_n0025_n00002_D2_D1, + I1 => Msub_n0025_n00002_Msub_n0025_n00002_D2_D2, + O => Msub_n0025_n00002_Msub_n0025_n00002_D2_D + ); + Msub_n0025_n00002_Msub_n0025_n00002_D2_D1_610 : X_ZERO + port map ( + O => Msub_n0025_n00002_Msub_n0025_n00002_D2_D1 + ); + Msub_n0025_n00002_Msub_n0025_n00002_D2_D2_611 : X_AND2 + port map ( + I0 => NlwInverterSignal_Msub_n0025_n00002_Msub_n0025_n00002_D2_D2_IN0, + I1 => NlwInverterSignal_Msub_n0025_n00002_Msub_n0025_n00002_D2_D2_IN1, + O => Msub_n0025_n00002_Msub_n0025_n00002_D2_D2 + ); + Q_OpTx_OpTx_FX_DC_18_INV_124_UIM_612 : X_BUF + port map ( + I => Q_OpTx_OpTx_FX_DC_18_INV_124_Q, + O => Q_OpTx_OpTx_FX_DC_18_INV_124_UIM + ); + Q_OpTx_OpTx_FX_DC_18_INV_124_Q_613 : X_BUF + port map ( + I => Q_OpTx_OpTx_FX_DC_18_INV_124_D, + O => Q_OpTx_OpTx_FX_DC_18_INV_124_Q + ); + Q_OpTx_OpTx_FX_DC_18_INV_124_D_614 : X_XOR2 + port map ( + I0 => Q_OpTx_OpTx_FX_DC_18_INV_124_D1, + I1 => Q_OpTx_OpTx_FX_DC_18_INV_124_D2, + O => Q_OpTx_OpTx_FX_DC_18_INV_124_D + ); + Q_OpTx_OpTx_FX_DC_18_INV_124_D1_615 : X_ZERO + port map ( + O => Q_OpTx_OpTx_FX_DC_18_INV_124_D1 + ); + Q_OpTx_OpTx_FX_DC_18_INV_124_D2_616 : X_AND2 + port map ( + I0 => SHIFT_CNT(0), + I1 => SHIFT_CNT(1), + O => Q_OpTx_OpTx_FX_DC_18_INV_124_D2 + ); + SHIFT_CNT_2_SHIFT_CNT_2_RSTF_UIM_617 : X_BUF + port map ( + I => SHIFT_CNT_2_SHIFT_CNT_2_RSTF_Q, + O => SHIFT_CNT_2_SHIFT_CNT_2_RSTF_UIM + ); + SHIFT_CNT_2_SHIFT_CNT_2_RSTF_Q_618 : X_BUF + port map ( + I => SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D, + O => SHIFT_CNT_2_SHIFT_CNT_2_RSTF_Q + ); + SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D_619 : X_XOR2 + port map ( + I0 => SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D1, + I1 => SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2, + O => SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D + ); + SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D1_620 : X_ZERO + port map ( + O => SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D1 + ); + SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_0_621 : X_AND5 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_0_IN0, + I1 => NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_0_IN1, + I2 => SHIFT_EN, + I3 => SHIFT_CNT(0), + I4 => NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_0_IN4, + O => SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_0 + ); + SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_1_622 : X_AND5 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_1_IN0, + I1 => NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => SHIFT_CNT(1), + I4 => NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_1_IN4, + O => SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_1 + ); + SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_2_623 : X_AND6 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_2_IN0, + I1 => NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_2_IN3, + I4 => NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_2_IN4, + I5 => SHIFT_CNT(2), + O => SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_2 + ); + SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_624 : X_OR3 + port map ( + I0 => SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_0, + I1 => SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_1, + I2 => SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_2, + O => SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2 + ); + Q_OpTx_OpTx_FX_DC_23_INV_125_UIM_625 : X_BUF + port map ( + I => Q_OpTx_OpTx_FX_DC_23_INV_125_Q, + O => Q_OpTx_OpTx_FX_DC_23_INV_125_UIM + ); + Q_OpTx_OpTx_FX_DC_23_INV_125_Q_626 : X_BUF + port map ( + I => Q_OpTx_OpTx_FX_DC_23_INV_125_D, + O => Q_OpTx_OpTx_FX_DC_23_INV_125_Q + ); + Q_OpTx_OpTx_FX_DC_23_INV_125_D_627 : X_XOR2 + port map ( + I0 => Q_OpTx_OpTx_FX_DC_23_INV_125_D1, + I1 => Q_OpTx_OpTx_FX_DC_23_INV_125_D2, + O => Q_OpTx_OpTx_FX_DC_23_INV_125_D + ); + Q_OpTx_OpTx_FX_DC_23_INV_125_D1_628 : X_ZERO + port map ( + O => Q_OpTx_OpTx_FX_DC_23_INV_125_D1 + ); + Q_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_0_629 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_0_IN1, + I2 => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_0_IN2, + O => Q_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_0 + ); + Q_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_1_630 : X_AND3 + port map ( + I0 => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_1_IN0, + I1 => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_1_IN1, + I2 => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_1_IN2, + O => Q_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_1 + ); + Q_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_631 : X_AND7 + port map ( + I0 => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN0, + I1 => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN1, + I2 => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN2, + I3 => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN3, + I4 => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN4, + I5 => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN5, + I6 => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN6, + O => Q_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2 + ); + Q_OpTx_OpTx_FX_DC_23_INV_125_D2_632 : X_OR3 + port map ( + I0 => Q_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_0, + I1 => Q_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_1, + I2 => Q_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2, + O => Q_OpTx_OpTx_FX_DC_23_INV_125_D2 + ); + SHIFT_CNT_3_SHIFT_CNT_3_RSTF_UIM_633 : X_BUF + port map ( + I => SHIFT_CNT_3_SHIFT_CNT_3_RSTF_Q, + O => SHIFT_CNT_3_SHIFT_CNT_3_RSTF_UIM + ); + SHIFT_CNT_3_SHIFT_CNT_3_RSTF_Q_634 : X_BUF + port map ( + I => SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D, + O => SHIFT_CNT_3_SHIFT_CNT_3_RSTF_Q + ); + SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D_635 : X_XOR2 + port map ( + I0 => SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D1, + I1 => SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2, + O => SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D + ); + SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D1_636 : X_ZERO + port map ( + O => SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D1 + ); + SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_0_637 : X_AND5 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_0_IN0, + I1 => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_0_IN1, + I2 => SHIFT_EN, + I3 => SHIFT_CNT(0), + I4 => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_0_IN4, + O => SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_0 + ); + SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_1_638 : X_AND5 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_1_IN0, + I1 => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => SHIFT_CNT(1), + I4 => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_1_IN4, + O => SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_1 + ); + SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_2_639 : X_AND5 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_2_IN0, + I1 => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => SHIFT_CNT(2), + I4 => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_2_IN4, + O => SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_2 + ); + SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3_640 : X_AND7 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3_IN0, + I1 => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3_IN3, + I4 => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3_IN4, + I5 => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3_IN5, + I6 => SHIFT_CNT(3), + O => SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3 + ); + SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_641 : X_OR4 + port map ( + I0 => SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_0, + I1 => SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_1, + I2 => SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_2, + I3 => SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3, + O => SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2 + ); + Msub_n0025_n00022_Msub_n0025_n00022_D2_UIM_642 : X_BUF + port map ( + I => Msub_n0025_n00022_Msub_n0025_n00022_D2_Q, + O => Msub_n0025_n00022_Msub_n0025_n00022_D2_UIM + ); + Msub_n0025_n00022_Msub_n0025_n00022_D2_Q_643 : X_BUF + port map ( + I => Msub_n0025_n00022_Msub_n0025_n00022_D2_D, + O => Msub_n0025_n00022_Msub_n0025_n00022_D2_Q + ); + Msub_n0025_n00022_Msub_n0025_n00022_D2_D_644 : X_XOR2 + port map ( + I0 => Msub_n0025_n00022_Msub_n0025_n00022_D2_D1, + I1 => Msub_n0025_n00022_Msub_n0025_n00022_D2_D2, + O => Msub_n0025_n00022_Msub_n0025_n00022_D2_D + ); + Msub_n0025_n00022_Msub_n0025_n00022_D2_D1_645 : X_ZERO + port map ( + O => Msub_n0025_n00022_Msub_n0025_n00022_D2_D1 + ); + Msub_n0025_n00022_Msub_n0025_n00022_D2_D2_646 : X_AND4 + port map ( + I0 => NlwInverterSignal_Msub_n0025_n00022_Msub_n0025_n00022_D2_D2_IN0, + I1 => NlwInverterSignal_Msub_n0025_n00022_Msub_n0025_n00022_D2_D2_IN1, + I2 => NlwInverterSignal_Msub_n0025_n00022_Msub_n0025_n00022_D2_D2_IN2, + I3 => NlwInverterSignal_Msub_n0025_n00022_Msub_n0025_n00022_D2_D2_IN3, + O => Msub_n0025_n00022_Msub_n0025_n00022_D2_D2 + ); + Q_OpTx_FX_DC_20_UIM_647 : X_BUF + port map ( + I => Q_OpTx_FX_DC_20_Q, + O => Q_OpTx_FX_DC_20_UIM + ); + Q_OpTx_FX_DC_20_Q_648 : X_BUF + port map ( + I => Q_OpTx_FX_DC_20_D, + O => Q_OpTx_FX_DC_20_Q + ); + Q_OpTx_FX_DC_20_D_649 : X_XOR2 + port map ( + I0 => Q_OpTx_FX_DC_20_D1, + I1 => Q_OpTx_FX_DC_20_D2, + O => Q_OpTx_FX_DC_20_D + ); + Q_OpTx_FX_DC_20_D1_650 : X_ZERO + port map ( + O => Q_OpTx_FX_DC_20_D1 + ); + Q_OpTx_FX_DC_20_D2_PT_0_651 : X_AND2 + port map ( + I0 => NlwInverterSignal_OpTx_FX_DC_20_D2_PT_0_IN0, + I1 => NlwInverterSignal_OpTx_FX_DC_20_D2_PT_0_IN1, + O => Q_OpTx_FX_DC_20_D2_PT_0 + ); + Q_OpTx_FX_DC_20_D2_PT_1_652 : X_AND3 + port map ( + I0 => NlwInverterSignal_OpTx_FX_DC_20_D2_PT_1_IN0, + I1 => NlwInverterSignal_OpTx_FX_DC_20_D2_PT_1_IN1, + I2 => NlwInverterSignal_OpTx_FX_DC_20_D2_PT_1_IN2, + O => Q_OpTx_FX_DC_20_D2_PT_1 + ); + Q_OpTx_FX_DC_20_D2_653 : X_OR2 + port map ( + I0 => Q_OpTx_FX_DC_20_D2_PT_0, + I1 => Q_OpTx_FX_DC_20_D2_PT_1, + O => Q_OpTx_FX_DC_20_D2 + ); + SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_UIM_654 : X_BUF + port map ( + I => SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_Q, + O => SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_UIM + ); + SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_Q_655 : X_BUF + port map ( + I => SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D, + O => SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_Q + ); + SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D_656 : X_XOR2 + port map ( + I0 => SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D1, + I1 => SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2, + O => SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D + ); + SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D1_657 : X_ZERO + port map ( + O => SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D1 + ); + SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_0_658 : X_AND3 + port map ( + I0 => LOAD_IBUF, + I1 => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_0_IN1, + I2 => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_0_IN2, + O => SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_0 + ); + SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_1_659 : X_AND3 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_1_IN0, + I1 => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_1_IN1, + I2 => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_1_IN2, + O => SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_1 + ); + SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_2_660 : X_AND3 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_2_IN0, + I1 => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_2_IN1, + I2 => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_2_IN2, + O => SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_2 + ); + SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_661 : X_AND6 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN0, + I1 => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN1, + I2 => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN2, + I3 => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN3, + I4 => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN4, + I5 => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN5, + O => SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3 + ); + SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_662 : X_OR4 + port map ( + I0 => SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_0, + I1 => SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_1, + I2 => SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_2, + I3 => SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3, + O => SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2 + ); + Q_OpTx_FX_DC_21_UIM_663 : X_BUF + port map ( + I => Q_OpTx_FX_DC_21_Q, + O => Q_OpTx_FX_DC_21_UIM + ); + Q_OpTx_FX_DC_21_Q_664 : X_BUF + port map ( + I => Q_OpTx_FX_DC_21_D, + O => Q_OpTx_FX_DC_21_Q + ); + Q_OpTx_FX_DC_21_D_665 : X_XOR2 + port map ( + I0 => Q_OpTx_FX_DC_21_D1, + I1 => Q_OpTx_FX_DC_21_D2, + O => Q_OpTx_FX_DC_21_D + ); + Q_OpTx_FX_DC_21_D1_666 : X_ZERO + port map ( + O => Q_OpTx_FX_DC_21_D1 + ); + Q_OpTx_FX_DC_21_D2_PT_0_667 : X_AND2 + port map ( + I0 => NlwInverterSignal_OpTx_FX_DC_21_D2_PT_0_IN0, + I1 => NlwInverterSignal_OpTx_FX_DC_21_D2_PT_0_IN1, + O => Q_OpTx_FX_DC_21_D2_PT_0 + ); + Q_OpTx_FX_DC_21_D2_PT_1_668 : X_AND4 + port map ( + I0 => NlwInverterSignal_OpTx_FX_DC_21_D2_PT_1_IN0, + I1 => NlwInverterSignal_OpTx_FX_DC_21_D2_PT_1_IN1, + I2 => NlwInverterSignal_OpTx_FX_DC_21_D2_PT_1_IN2, + I3 => NlwInverterSignal_OpTx_FX_DC_21_D2_PT_1_IN3, + O => Q_OpTx_FX_DC_21_D2_PT_1 + ); + Q_OpTx_FX_DC_21_D2_669 : X_OR2 + port map ( + I0 => Q_OpTx_FX_DC_21_D2_PT_0, + I1 => Q_OpTx_FX_DC_21_D2_PT_1, + O => Q_OpTx_FX_DC_21_D2 + ); + Q_OpTx_OpTx_FX_SC_22_INV_126_UIM_670 : X_BUF + port map ( + I => Q_OpTx_OpTx_FX_SC_22_INV_126_Q, + O => Q_OpTx_OpTx_FX_SC_22_INV_126_UIM + ); + Q_OpTx_OpTx_FX_SC_22_INV_126_Q_671 : X_BUF + port map ( + I => Q_OpTx_OpTx_FX_SC_22_INV_126_D, + O => Q_OpTx_OpTx_FX_SC_22_INV_126_Q + ); + Q_OpTx_OpTx_FX_SC_22_INV_126_D_672 : X_XOR2 + port map ( + I0 => Q_OpTx_OpTx_FX_SC_22_INV_126_D1, + I1 => Q_OpTx_OpTx_FX_SC_22_INV_126_D2, + O => Q_OpTx_OpTx_FX_SC_22_INV_126_D + ); + Q_OpTx_OpTx_FX_SC_22_INV_126_D1_673 : X_ZERO + port map ( + O => Q_OpTx_OpTx_FX_SC_22_INV_126_D1 + ); + Q_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_0_674 : X_AND2 + port map ( + I0 => LOAD_IBUF, + I1 => LOAD_IBUF, + O => Q_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_0 + ); + Q_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_1_675 : X_AND2 + port map ( + I0 => RES_IBUF, + I1 => RES_IBUF, + O => Q_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_1 + ); + Q_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_2_676 : X_AND2 + port map ( + I0 => NlwInverterSignal_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_2_IN0, + I1 => NlwInverterSignal_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_2_IN1, + O => Q_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_2 + ); + Q_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3_677 : X_AND5 + port map ( + I0 => NlwInverterSignal_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3_IN0, + I1 => NlwInverterSignal_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3_IN1, + I2 => NlwInverterSignal_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3_IN2, + I3 => NlwInverterSignal_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3_IN3, + I4 => NlwInverterSignal_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3_IN4, + O => Q_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3 + ); + Q_OpTx_OpTx_FX_SC_22_INV_126_D2_678 : X_OR4 + port map ( + I0 => Q_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_0, + I1 => Q_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_1, + I2 => Q_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_2, + I3 => Q_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3, + O => Q_OpTx_OpTx_FX_SC_22_INV_126_D2 + ); + EXP18_EXP_679 : X_BUF + port map ( + I => EXP18_EXP_tsimrenamed_net_Q, + O => EXP18_EXP + ); + EXP18_EXP_PT_0_680 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP18_EXP_PT_0_IN0, + I1 => NlwInverterSignal_EXP18_EXP_PT_0_IN1, + I2 => NlwInverterSignal_EXP18_EXP_PT_0_IN2, + I3 => NlwInverterSignal_EXP18_EXP_PT_0_IN3, + I4 => NlwInverterSignal_EXP18_EXP_PT_0_IN4, + I5 => NlwInverterSignal_EXP18_EXP_PT_0_IN5, + I6 => count(5), + O => EXP18_EXP_PT_0 + ); + EXP18_EXP_PT_1_681 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP18_EXP_PT_1_IN0, + I1 => NlwInverterSignal_EXP18_EXP_PT_1_IN1, + I2 => NlwInverterSignal_EXP18_EXP_PT_1_IN2, + I3 => NlwInverterSignal_EXP18_EXP_PT_1_IN3, + I4 => NlwInverterSignal_EXP18_EXP_PT_1_IN4, + I5 => NlwInverterSignal_EXP18_EXP_PT_1_IN5, + I6 => VCLK_PRESCALE_5_IBUF, + O => EXP18_EXP_PT_1 + ); + EXP18_EXP_tsimrenamed_net_Q_682 : X_OR2 + port map ( + I0 => EXP18_EXP_PT_0, + I1 => EXP18_EXP_PT_1, + O => EXP18_EXP_tsimrenamed_net_Q + ); + EXP19_EXP_683 : X_BUF + port map ( + I => EXP19_EXP_tsimrenamed_net_Q, + O => EXP19_EXP + ); + EXP19_EXP_PT_0_684 : X_AND3 + port map ( + I0 => RES_IBUF, + I1 => count(4), + I2 => NlwInverterSignal_EXP19_EXP_PT_0_IN2, + O => EXP19_EXP_PT_0 + ); + EXP19_EXP_PT_1_685 : X_AND3 + port map ( + I0 => RES_IBUF, + I1 => NlwInverterSignal_EXP19_EXP_PT_1_IN1, + I2 => VCLK_PRESCALE_4_IBUF, + O => EXP19_EXP_PT_1 + ); + EXP19_EXP_PT_2_686 : X_AND6 + port map ( + I0 => NlwInverterSignal_EXP19_EXP_PT_2_IN0, + I1 => NlwInverterSignal_EXP19_EXP_PT_2_IN1, + I2 => count(4), + I3 => NlwInverterSignal_EXP19_EXP_PT_2_IN3, + I4 => NlwInverterSignal_EXP19_EXP_PT_2_IN4, + I5 => NlwInverterSignal_EXP19_EXP_PT_2_IN5, + O => EXP19_EXP_PT_2 + ); + EXP19_EXP_tsimrenamed_net_Q_687 : X_OR3 + port map ( + I0 => EXP19_EXP_PT_0, + I1 => EXP19_EXP_PT_1, + I2 => EXP19_EXP_PT_2, + O => EXP19_EXP_tsimrenamed_net_Q + ); + EXP20_EXP_688 : X_BUF + port map ( + I => EXP20_EXP_tsimrenamed_net_Q, + O => EXP20_EXP + ); + EXP20_EXP_PT_0_689 : X_AND3 + port map ( + I0 => NlwInverterSignal_EXP20_EXP_PT_0_IN0, + I1 => count(1), + I2 => NlwInverterSignal_EXP20_EXP_PT_0_IN2, + O => EXP20_EXP_PT_0 + ); + EXP20_EXP_PT_1_690 : X_AND3 + port map ( + I0 => NlwInverterSignal_EXP20_EXP_PT_1_IN0, + I1 => count(2), + I2 => NlwInverterSignal_EXP20_EXP_PT_1_IN2, + O => EXP20_EXP_PT_1 + ); + EXP20_EXP_PT_2_691 : X_AND4 + port map ( + I0 => NlwInverterSignal_EXP20_EXP_PT_2_IN0, + I1 => NlwInverterSignal_EXP20_EXP_PT_2_IN1, + I2 => NlwInverterSignal_EXP20_EXP_PT_2_IN2, + I3 => NlwInverterSignal_EXP20_EXP_PT_2_IN3, + O => EXP20_EXP_PT_2 + ); + EXP20_EXP_PT_3_692 : X_AND5 + port map ( + I0 => NlwInverterSignal_EXP20_EXP_PT_3_IN0, + I1 => NlwInverterSignal_EXP20_EXP_PT_3_IN1, + I2 => NlwInverterSignal_EXP20_EXP_PT_3_IN2, + I3 => NlwInverterSignal_EXP20_EXP_PT_3_IN3, + I4 => count(3), + O => EXP20_EXP_PT_3 + ); + EXP20_EXP_tsimrenamed_net_Q_693 : X_OR4 + port map ( + I0 => EXP20_EXP_PT_0, + I1 => EXP20_EXP_PT_1, + I2 => EXP20_EXP_PT_2, + I3 => EXP20_EXP_PT_3, + O => EXP20_EXP_tsimrenamed_net_Q + ); + NlwInverterBlock_REG_31_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_31_RSTF, + O => NlwInverterSignal_REG_31_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_31_D2_PT_0_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_31_D2_PT_0_IN0 + ); + NlwInverterBlock_REG_31_D2_PT_0_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_31_D2_PT_0_IN1 + ); + NlwInverterBlock_REG_31_D2_PT_0_IN4 : X_INV + port map ( + I => REG(30), + O => NlwInverterSignal_REG_31_D2_PT_0_IN4 + ); + NlwInverterBlock_REG_31_D2_PT_0_IN5 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_31_D2_PT_0_IN5 + ); + NlwInverterBlock_REG_31_D2_PT_1_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_31_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_31_D2_PT_1_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_31_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_31_D2_PT_1_IN2 : X_INV + port map ( + I => REG(31), + O => NlwInverterSignal_REG_31_D2_PT_1_IN2 + ); + NlwInverterBlock_REG_31_D2_PT_1_IN5 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_31_D2_PT_1_IN5 + ); + NlwInverterBlock_REG_31_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_31_CLKF_IN0 + ); + NlwInverterBlock_REG_31_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_31_CLKF_IN1 + ); + NlwInverterBlock_REG_31_RSTF_IN1 : X_INV + port map ( + I => DIN_31_IBUF, + O => NlwInverterSignal_REG_31_RSTF_IN1 + ); + NlwInverterBlock_SHIFT_EN_D2_IN0 : X_INV + port map ( + I => DONE_IBUF, + O => NlwInverterSignal_SHIFT_EN_D2_IN0 + ); + NlwInverterBlock_SHIFT_EN_D2_IN1 : X_INV + port map ( + I => DONE_IBUF, + O => NlwInverterSignal_SHIFT_EN_D2_IN1 + ); + NlwInverterBlock_SHIFT_EN_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_SHIFT_EN_CLKF_IN0 + ); + NlwInverterBlock_SHIFT_EN_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_SHIFT_EN_CLKF_IN1 + ); + NlwInverterBlock_SHIFT_EN_CE_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_SHIFT_EN_CE_IN0 + ); + NlwInverterBlock_SHIFT_EN_CE_IN1 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_SHIFT_EN_CE_IN1 + ); + NlwInverterBlock_count_0_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => count_0_RSTF, + O => NlwInverterSignal_count_0_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_count_0_D_IN0 : X_INV + port map ( + I => count_0_D1, + O => NlwInverterSignal_count_0_D_IN0 + ); + NlwInverterBlock_count_0_D2_PT_0_IN1 : X_INV + port map ( + I => VCLK_PRESCALE_0_IBUF, + O => NlwInverterSignal_count_0_D2_PT_0_IN1 + ); + NlwInverterBlock_count_0_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_count_0_D2_PT_1_IN0 + ); + NlwInverterBlock_count_0_D2_PT_2_IN0 : X_INV + port map ( + I => VCLK_PRESCALE_0_IBUF, + O => NlwInverterSignal_count_0_D2_PT_2_IN0 + ); + NlwInverterBlock_count_0_D2_PT_2_IN1 : X_INV + port map ( + I => count(4), + O => NlwInverterSignal_count_0_D2_PT_2_IN1 + ); + NlwInverterBlock_count_0_D2_PT_2_IN2 : X_INV + port map ( + I => count(1), + O => NlwInverterSignal_count_0_D2_PT_2_IN2 + ); + NlwInverterBlock_count_0_D2_PT_2_IN3 : X_INV + port map ( + I => count(2), + O => NlwInverterSignal_count_0_D2_PT_2_IN3 + ); + NlwInverterBlock_count_0_D2_PT_2_IN4 : X_INV + port map ( + I => count(3), + O => NlwInverterSignal_count_0_D2_PT_2_IN4 + ); + NlwInverterBlock_count_0_D2_PT_2_IN5 : X_INV + port map ( + I => count(5), + O => NlwInverterSignal_count_0_D2_PT_2_IN5 + ); + NlwInverterBlock_count_0_RSTF_IN1 : X_INV + port map ( + I => VCLK_PRESCALE_0_IBUF, + O => NlwInverterSignal_count_0_RSTF_IN1 + ); + NlwInverterBlock_count_4_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => count_4_RSTF, + O => NlwInverterSignal_count_4_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_count_4_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_count_4_D2_PT_1_IN0 + ); + NlwInverterBlock_count_4_D2_PT_1_IN1 : X_INV + port map ( + I => count(0), + O => NlwInverterSignal_count_4_D2_PT_1_IN1 + ); + NlwInverterBlock_count_4_D2_PT_1_IN2 : X_INV + port map ( + I => count(1), + O => NlwInverterSignal_count_4_D2_PT_1_IN2 + ); + NlwInverterBlock_count_4_D2_PT_1_IN3 : X_INV + port map ( + I => count(2), + O => NlwInverterSignal_count_4_D2_PT_1_IN3 + ); + NlwInverterBlock_count_4_D2_PT_1_IN4 : X_INV + port map ( + I => count(3), + O => NlwInverterSignal_count_4_D2_PT_1_IN4 + ); + NlwInverterBlock_count_4_D2_PT_2_IN0 : X_INV + port map ( + I => count(0), + O => NlwInverterSignal_count_4_D2_PT_2_IN0 + ); + NlwInverterBlock_count_4_D2_PT_2_IN1 : X_INV + port map ( + I => count(4), + O => NlwInverterSignal_count_4_D2_PT_2_IN1 + ); + NlwInverterBlock_count_4_D2_PT_2_IN2 : X_INV + port map ( + I => count(1), + O => NlwInverterSignal_count_4_D2_PT_2_IN2 + ); + NlwInverterBlock_count_4_D2_PT_2_IN3 : X_INV + port map ( + I => count(2), + O => NlwInverterSignal_count_4_D2_PT_2_IN3 + ); + NlwInverterBlock_count_4_D2_PT_2_IN4 : X_INV + port map ( + I => count(3), + O => NlwInverterSignal_count_4_D2_PT_2_IN4 + ); + NlwInverterBlock_count_4_RSTF_IN1 : X_INV + port map ( + I => VCLK_PRESCALE_4_IBUF, + O => NlwInverterSignal_count_4_RSTF_IN1 + ); + NlwInverterBlock_count_4_EXP_tsimrenamed_net_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_count_4_EXP_tsimrenamed_net_IN0 + ); + NlwInverterBlock_count_4_EXP_tsimrenamed_net_IN1 : X_INV + port map ( + I => count(0), + O => NlwInverterSignal_count_4_EXP_tsimrenamed_net_IN1 + ); + NlwInverterBlock_count_4_EXP_tsimrenamed_net_IN2 : X_INV + port map ( + I => count(1), + O => NlwInverterSignal_count_4_EXP_tsimrenamed_net_IN2 + ); + NlwInverterBlock_count_1_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => count_1_RSTF, + O => NlwInverterSignal_count_1_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_count_1_D_IN0 : X_INV + port map ( + I => count_1_D1, + O => NlwInverterSignal_count_1_D_IN0 + ); + NlwInverterBlock_count_1_D2_PT_1_IN1 : X_INV + port map ( + I => VCLK_PRESCALE_1_IBUF, + O => NlwInverterSignal_count_1_D2_PT_1_IN1 + ); + NlwInverterBlock_count_1_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_count_1_D2_PT_2_IN0 + ); + NlwInverterBlock_count_1_D2_PT_2_IN2 : X_INV + port map ( + I => count(1), + O => NlwInverterSignal_count_1_D2_PT_2_IN2 + ); + NlwInverterBlock_count_1_D2_PT_3_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_count_1_D2_PT_3_IN0 + ); + NlwInverterBlock_count_1_D2_PT_3_IN1 : X_INV + port map ( + I => count(0), + O => NlwInverterSignal_count_1_D2_PT_3_IN1 + ); + NlwInverterBlock_count_1_RSTF_IN1 : X_INV + port map ( + I => VCLK_PRESCALE_1_IBUF, + O => NlwInverterSignal_count_1_RSTF_IN1 + ); + NlwInverterBlock_count_2_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => count_2_RSTF, + O => NlwInverterSignal_count_2_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_count_2_D_IN0 : X_INV + port map ( + I => count_2_D1, + O => NlwInverterSignal_count_2_D_IN0 + ); + NlwInverterBlock_count_2_D2_PT_2_IN1 : X_INV + port map ( + I => VCLK_PRESCALE_2_IBUF, + O => NlwInverterSignal_count_2_D2_PT_2_IN1 + ); + NlwInverterBlock_count_2_D2_PT_3_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_count_2_D2_PT_3_IN0 + ); + NlwInverterBlock_count_2_D2_PT_3_IN2 : X_INV + port map ( + I => count(2), + O => NlwInverterSignal_count_2_D2_PT_3_IN2 + ); + NlwInverterBlock_count_2_D2_PT_4_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_count_2_D2_PT_4_IN0 + ); + NlwInverterBlock_count_2_D2_PT_4_IN2 : X_INV + port map ( + I => count(2), + O => NlwInverterSignal_count_2_D2_PT_4_IN2 + ); + NlwInverterBlock_count_2_RSTF_IN1 : X_INV + port map ( + I => VCLK_PRESCALE_2_IBUF, + O => NlwInverterSignal_count_2_RSTF_IN1 + ); + NlwInverterBlock_count_3_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => count_3_RSTF, + O => NlwInverterSignal_count_3_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_count_3_D_IN0 : X_INV + port map ( + I => count_3_D1, + O => NlwInverterSignal_count_3_D_IN0 + ); + NlwInverterBlock_count_3_D2_PT_1_IN1 : X_INV + port map ( + I => VCLK_PRESCALE_3_IBUF, + O => NlwInverterSignal_count_3_D2_PT_1_IN1 + ); + NlwInverterBlock_count_3_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_count_3_D2_PT_2_IN0 + ); + NlwInverterBlock_count_3_D2_PT_2_IN2 : X_INV + port map ( + I => count(3), + O => NlwInverterSignal_count_3_D2_PT_2_IN2 + ); + NlwInverterBlock_count_3_RSTF_IN1 : X_INV + port map ( + I => VCLK_PRESCALE_3_IBUF, + O => NlwInverterSignal_count_3_RSTF_IN1 + ); + NlwInverterBlock_count_3_EXP_tsimrenamed_net_IN0 : X_INV + port map ( + I => count(4), + O => NlwInverterSignal_count_3_EXP_tsimrenamed_net_IN0 + ); + NlwInverterBlock_count_3_EXP_tsimrenamed_net_IN1 : X_INV + port map ( + I => count(2), + O => NlwInverterSignal_count_3_EXP_tsimrenamed_net_IN1 + ); + NlwInverterBlock_count_3_EXP_tsimrenamed_net_IN2 : X_INV + port map ( + I => count(3), + O => NlwInverterSignal_count_3_EXP_tsimrenamed_net_IN2 + ); + NlwInverterBlock_count_3_EXP_tsimrenamed_net_IN3 : X_INV + port map ( + I => count(5), + O => NlwInverterSignal_count_3_EXP_tsimrenamed_net_IN3 + ); + NlwInverterBlock_count_3_EXP_tsimrenamed_net_IN4 : X_INV + port map ( + I => VCLK_PRESCALE_2_IBUF, + O => NlwInverterSignal_count_3_EXP_tsimrenamed_net_IN4 + ); + NlwInverterBlock_REG_0_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_0_RSTF, + O => NlwInverterSignal_REG_0_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_0_D2_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_0_D2_IN0 + ); + NlwInverterBlock_REG_0_D2_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_D2_IN1 + ); + NlwInverterBlock_REG_0_D2_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_0_D2_IN3 + ); + NlwInverterBlock_REG_0_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_CLKF_IN0 + ); + NlwInverterBlock_REG_0_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_CLKF_IN1 + ); + NlwInverterBlock_REG_0_RSTF_IN2 : X_INV + port map ( + I => DIN_0_IBUF, + O => NlwInverterSignal_REG_0_RSTF_IN2 + ); + NlwInverterBlock_REG_10_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_10_RSTF, + O => NlwInverterSignal_REG_10_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_10_D2_PT_0_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_10_D2_PT_0_IN0 + ); + NlwInverterBlock_REG_10_D2_PT_0_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_10_D2_PT_0_IN1 + ); + NlwInverterBlock_REG_10_D2_PT_0_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_10_D2_PT_0_IN3 + ); + NlwInverterBlock_REG_10_D2_PT_0_IN5 : X_INV + port map ( + I => REG(9), + O => NlwInverterSignal_REG_10_D2_PT_0_IN5 + ); + NlwInverterBlock_REG_10_D2_PT_1_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_10_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_10_D2_PT_1_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_10_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_10_D2_PT_1_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_10_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_10_D2_PT_1_IN4 : X_INV + port map ( + I => REG(10), + O => NlwInverterSignal_REG_10_D2_PT_1_IN4 + ); + NlwInverterBlock_REG_10_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_10_CLKF_IN0 + ); + NlwInverterBlock_REG_10_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_10_CLKF_IN1 + ); + NlwInverterBlock_REG_10_RSTF_IN2 : X_INV + port map ( + I => DIN_10_IBUF, + O => NlwInverterSignal_REG_10_RSTF_IN2 + ); + NlwInverterBlock_REG_11_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_11_RSTF, + O => NlwInverterSignal_REG_11_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_11_D2_PT_0_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_11_D2_PT_0_IN0 + ); + NlwInverterBlock_REG_11_D2_PT_0_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_11_D2_PT_0_IN1 + ); + NlwInverterBlock_REG_11_D2_PT_0_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_11_D2_PT_0_IN3 + ); + NlwInverterBlock_REG_11_D2_PT_0_IN5 : X_INV + port map ( + I => REG(11), + O => NlwInverterSignal_REG_11_D2_PT_0_IN5 + ); + NlwInverterBlock_REG_11_D2_PT_1_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_11_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_11_D2_PT_1_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_11_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_11_D2_PT_1_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_11_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_11_D2_PT_1_IN4 : X_INV + port map ( + I => REG(10), + O => NlwInverterSignal_REG_11_D2_PT_1_IN4 + ); + NlwInverterBlock_REG_11_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_11_CLKF_IN0 + ); + NlwInverterBlock_REG_11_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_11_CLKF_IN1 + ); + NlwInverterBlock_REG_11_RSTF_IN2 : X_INV + port map ( + I => DIN_11_IBUF, + O => NlwInverterSignal_REG_11_RSTF_IN2 + ); + NlwInverterBlock_REG_12_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_12_RSTF, + O => NlwInverterSignal_REG_12_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_12_D2_PT_0_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_12_D2_PT_0_IN0 + ); + NlwInverterBlock_REG_12_D2_PT_0_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_12_D2_PT_0_IN1 + ); + NlwInverterBlock_REG_12_D2_PT_0_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_12_D2_PT_0_IN3 + ); + NlwInverterBlock_REG_12_D2_PT_0_IN5 : X_INV + port map ( + I => REG(12), + O => NlwInverterSignal_REG_12_D2_PT_0_IN5 + ); + NlwInverterBlock_REG_12_D2_PT_1_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_12_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_12_D2_PT_1_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_12_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_12_D2_PT_1_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_12_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_12_D2_PT_1_IN4 : X_INV + port map ( + I => REG(11), + O => NlwInverterSignal_REG_12_D2_PT_1_IN4 + ); + NlwInverterBlock_REG_12_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_12_CLKF_IN0 + ); + NlwInverterBlock_REG_12_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_12_CLKF_IN1 + ); + NlwInverterBlock_REG_12_RSTF_IN2 : X_INV + port map ( + I => DIN_12_IBUF, + O => NlwInverterSignal_REG_12_RSTF_IN2 + ); + NlwInverterBlock_REG_13_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_13_RSTF, + O => NlwInverterSignal_REG_13_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_13_D2_PT_0_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_13_D2_PT_0_IN0 + ); + NlwInverterBlock_REG_13_D2_PT_0_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_13_D2_PT_0_IN1 + ); + NlwInverterBlock_REG_13_D2_PT_0_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_13_D2_PT_0_IN3 + ); + NlwInverterBlock_REG_13_D2_PT_0_IN5 : X_INV + port map ( + I => REG(13), + O => NlwInverterSignal_REG_13_D2_PT_0_IN5 + ); + NlwInverterBlock_REG_13_D2_PT_1_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_13_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_13_D2_PT_1_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_13_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_13_D2_PT_1_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_13_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_13_D2_PT_1_IN4 : X_INV + port map ( + I => REG(12), + O => NlwInverterSignal_REG_13_D2_PT_1_IN4 + ); + NlwInverterBlock_REG_13_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_13_CLKF_IN0 + ); + NlwInverterBlock_REG_13_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_13_CLKF_IN1 + ); + NlwInverterBlock_REG_13_RSTF_IN2 : X_INV + port map ( + I => DIN_13_IBUF, + O => NlwInverterSignal_REG_13_RSTF_IN2 + ); + NlwInverterBlock_REG_14_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_14_RSTF, + O => NlwInverterSignal_REG_14_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_14_D2_PT_0_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_14_D2_PT_0_IN0 + ); + NlwInverterBlock_REG_14_D2_PT_0_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_14_D2_PT_0_IN1 + ); + NlwInverterBlock_REG_14_D2_PT_0_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_14_D2_PT_0_IN3 + ); + NlwInverterBlock_REG_14_D2_PT_0_IN5 : X_INV + port map ( + I => REG(14), + O => NlwInverterSignal_REG_14_D2_PT_0_IN5 + ); + NlwInverterBlock_REG_14_D2_PT_1_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_14_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_14_D2_PT_1_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_14_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_14_D2_PT_1_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_14_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_14_D2_PT_1_IN4 : X_INV + port map ( + I => REG(13), + O => NlwInverterSignal_REG_14_D2_PT_1_IN4 + ); + NlwInverterBlock_REG_14_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_14_CLKF_IN0 + ); + NlwInverterBlock_REG_14_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_14_CLKF_IN1 + ); + NlwInverterBlock_REG_14_RSTF_IN2 : X_INV + port map ( + I => DIN_14_IBUF, + O => NlwInverterSignal_REG_14_RSTF_IN2 + ); + NlwInverterBlock_REG_15_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_15_RSTF, + O => NlwInverterSignal_REG_15_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_15_D2_PT_0_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_15_D2_PT_0_IN0 + ); + NlwInverterBlock_REG_15_D2_PT_0_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_15_D2_PT_0_IN1 + ); + NlwInverterBlock_REG_15_D2_PT_0_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_15_D2_PT_0_IN3 + ); + NlwInverterBlock_REG_15_D2_PT_0_IN5 : X_INV + port map ( + I => REG(15), + O => NlwInverterSignal_REG_15_D2_PT_0_IN5 + ); + NlwInverterBlock_REG_15_D2_PT_1_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_15_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_15_D2_PT_1_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_15_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_15_D2_PT_1_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_15_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_15_D2_PT_1_IN4 : X_INV + port map ( + I => REG(14), + O => NlwInverterSignal_REG_15_D2_PT_1_IN4 + ); + NlwInverterBlock_REG_15_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_15_CLKF_IN0 + ); + NlwInverterBlock_REG_15_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_15_CLKF_IN1 + ); + NlwInverterBlock_REG_15_RSTF_IN2 : X_INV + port map ( + I => DIN_15_IBUF, + O => NlwInverterSignal_REG_15_RSTF_IN2 + ); + NlwInverterBlock_REG_16_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_16_RSTF, + O => NlwInverterSignal_REG_16_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_16_D2_PT_0_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_16_D2_PT_0_IN0 + ); + NlwInverterBlock_REG_16_D2_PT_0_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_16_D2_PT_0_IN1 + ); + NlwInverterBlock_REG_16_D2_PT_0_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_16_D2_PT_0_IN3 + ); + NlwInverterBlock_REG_16_D2_PT_0_IN5 : X_INV + port map ( + I => REG(16), + O => NlwInverterSignal_REG_16_D2_PT_0_IN5 + ); + NlwInverterBlock_REG_16_D2_PT_1_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_16_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_16_D2_PT_1_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_16_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_16_D2_PT_1_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_16_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_16_D2_PT_1_IN4 : X_INV + port map ( + I => REG(15), + O => NlwInverterSignal_REG_16_D2_PT_1_IN4 + ); + NlwInverterBlock_REG_16_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_16_CLKF_IN0 + ); + NlwInverterBlock_REG_16_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_16_CLKF_IN1 + ); + NlwInverterBlock_REG_16_RSTF_IN2 : X_INV + port map ( + I => DIN_16_IBUF, + O => NlwInverterSignal_REG_16_RSTF_IN2 + ); + NlwInverterBlock_REG_17_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_17_RSTF, + O => NlwInverterSignal_REG_17_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_17_D2_PT_0_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_17_D2_PT_0_IN0 + ); + NlwInverterBlock_REG_17_D2_PT_0_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_17_D2_PT_0_IN1 + ); + NlwInverterBlock_REG_17_D2_PT_0_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_17_D2_PT_0_IN3 + ); + NlwInverterBlock_REG_17_D2_PT_0_IN5 : X_INV + port map ( + I => REG(17), + O => NlwInverterSignal_REG_17_D2_PT_0_IN5 + ); + NlwInverterBlock_REG_17_D2_PT_1_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_17_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_17_D2_PT_1_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_17_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_17_D2_PT_1_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_17_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_17_D2_PT_1_IN4 : X_INV + port map ( + I => REG(16), + O => NlwInverterSignal_REG_17_D2_PT_1_IN4 + ); + NlwInverterBlock_REG_17_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_17_CLKF_IN0 + ); + NlwInverterBlock_REG_17_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_17_CLKF_IN1 + ); + NlwInverterBlock_REG_17_RSTF_IN2 : X_INV + port map ( + I => DIN_17_IBUF, + O => NlwInverterSignal_REG_17_RSTF_IN2 + ); + NlwInverterBlock_REG_18_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_18_RSTF, + O => NlwInverterSignal_REG_18_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_18_D2_PT_0_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_18_D2_PT_0_IN0 + ); + NlwInverterBlock_REG_18_D2_PT_0_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_18_D2_PT_0_IN1 + ); + NlwInverterBlock_REG_18_D2_PT_0_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_18_D2_PT_0_IN3 + ); + NlwInverterBlock_REG_18_D2_PT_0_IN5 : X_INV + port map ( + I => REG(18), + O => NlwInverterSignal_REG_18_D2_PT_0_IN5 + ); + NlwInverterBlock_REG_18_D2_PT_1_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_18_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_18_D2_PT_1_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_18_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_18_D2_PT_1_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_18_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_18_D2_PT_1_IN4 : X_INV + port map ( + I => REG(17), + O => NlwInverterSignal_REG_18_D2_PT_1_IN4 + ); + NlwInverterBlock_REG_18_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_18_CLKF_IN0 + ); + NlwInverterBlock_REG_18_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_18_CLKF_IN1 + ); + NlwInverterBlock_REG_18_RSTF_IN2 : X_INV + port map ( + I => DIN_18_IBUF, + O => NlwInverterSignal_REG_18_RSTF_IN2 + ); + NlwInverterBlock_REG_19_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_19_RSTF, + O => NlwInverterSignal_REG_19_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_19_D2_PT_0_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_19_D2_PT_0_IN0 + ); + NlwInverterBlock_REG_19_D2_PT_0_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_19_D2_PT_0_IN1 + ); + NlwInverterBlock_REG_19_D2_PT_0_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_19_D2_PT_0_IN3 + ); + NlwInverterBlock_REG_19_D2_PT_0_IN5 : X_INV + port map ( + I => REG(19), + O => NlwInverterSignal_REG_19_D2_PT_0_IN5 + ); + NlwInverterBlock_REG_19_D2_PT_1_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_19_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_19_D2_PT_1_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_19_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_19_D2_PT_1_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_19_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_19_D2_PT_1_IN4 : X_INV + port map ( + I => REG(18), + O => NlwInverterSignal_REG_19_D2_PT_1_IN4 + ); + NlwInverterBlock_REG_19_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_19_CLKF_IN0 + ); + NlwInverterBlock_REG_19_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_19_CLKF_IN1 + ); + NlwInverterBlock_REG_19_RSTF_IN2 : X_INV + port map ( + I => DIN_19_IBUF, + O => NlwInverterSignal_REG_19_RSTF_IN2 + ); + NlwInverterBlock_REG_1_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_1_RSTF, + O => NlwInverterSignal_REG_1_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_1_D2_PT_0_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_1_D2_PT_0_IN0 + ); + NlwInverterBlock_REG_1_D2_PT_0_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_D2_PT_0_IN1 + ); + NlwInverterBlock_REG_1_D2_PT_0_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_1_D2_PT_0_IN3 + ); + NlwInverterBlock_REG_1_D2_PT_0_IN5 : X_INV + port map ( + I => REG(1), + O => NlwInverterSignal_REG_1_D2_PT_0_IN5 + ); + NlwInverterBlock_REG_1_D2_PT_1_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_1_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_1_D2_PT_1_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_1_D2_PT_1_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_1_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_1_D2_PT_1_IN4 : X_INV + port map ( + I => REG(0), + O => NlwInverterSignal_REG_1_D2_PT_1_IN4 + ); + NlwInverterBlock_REG_1_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_CLKF_IN0 + ); + NlwInverterBlock_REG_1_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_CLKF_IN1 + ); + NlwInverterBlock_REG_1_RSTF_IN2 : X_INV + port map ( + I => DIN_1_IBUF, + O => NlwInverterSignal_REG_1_RSTF_IN2 + ); + NlwInverterBlock_REG_20_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_20_RSTF, + O => NlwInverterSignal_REG_20_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_20_D2_PT_0_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_20_D2_PT_0_IN0 + ); + NlwInverterBlock_REG_20_D2_PT_0_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_20_D2_PT_0_IN1 + ); + NlwInverterBlock_REG_20_D2_PT_0_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_20_D2_PT_0_IN3 + ); + NlwInverterBlock_REG_20_D2_PT_0_IN5 : X_INV + port map ( + I => REG(20), + O => NlwInverterSignal_REG_20_D2_PT_0_IN5 + ); + NlwInverterBlock_REG_20_D2_PT_1_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_20_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_20_D2_PT_1_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_20_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_20_D2_PT_1_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_20_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_20_D2_PT_1_IN4 : X_INV + port map ( + I => REG(19), + O => NlwInverterSignal_REG_20_D2_PT_1_IN4 + ); + NlwInverterBlock_REG_20_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_20_CLKF_IN0 + ); + NlwInverterBlock_REG_20_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_20_CLKF_IN1 + ); + NlwInverterBlock_REG_20_RSTF_IN2 : X_INV + port map ( + I => DIN_20_IBUF, + O => NlwInverterSignal_REG_20_RSTF_IN2 + ); + NlwInverterBlock_REG_21_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_21_RSTF, + O => NlwInverterSignal_REG_21_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_21_D2_PT_0_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_21_D2_PT_0_IN0 + ); + NlwInverterBlock_REG_21_D2_PT_0_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_21_D2_PT_0_IN1 + ); + NlwInverterBlock_REG_21_D2_PT_0_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_21_D2_PT_0_IN3 + ); + NlwInverterBlock_REG_21_D2_PT_0_IN5 : X_INV + port map ( + I => REG(21), + O => NlwInverterSignal_REG_21_D2_PT_0_IN5 + ); + NlwInverterBlock_REG_21_D2_PT_1_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_21_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_21_D2_PT_1_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_21_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_21_D2_PT_1_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_21_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_21_D2_PT_1_IN4 : X_INV + port map ( + I => REG(20), + O => NlwInverterSignal_REG_21_D2_PT_1_IN4 + ); + NlwInverterBlock_REG_21_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_21_CLKF_IN0 + ); + NlwInverterBlock_REG_21_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_21_CLKF_IN1 + ); + NlwInverterBlock_REG_21_RSTF_IN2 : X_INV + port map ( + I => DIN_21_IBUF, + O => NlwInverterSignal_REG_21_RSTF_IN2 + ); + NlwInverterBlock_REG_22_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_22_RSTF, + O => NlwInverterSignal_REG_22_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_22_D2_PT_0_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_22_D2_PT_0_IN0 + ); + NlwInverterBlock_REG_22_D2_PT_0_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_22_D2_PT_0_IN1 + ); + NlwInverterBlock_REG_22_D2_PT_0_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_22_D2_PT_0_IN3 + ); + NlwInverterBlock_REG_22_D2_PT_0_IN5 : X_INV + port map ( + I => REG(22), + O => NlwInverterSignal_REG_22_D2_PT_0_IN5 + ); + NlwInverterBlock_REG_22_D2_PT_1_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_22_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_22_D2_PT_1_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_22_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_22_D2_PT_1_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_22_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_22_D2_PT_1_IN4 : X_INV + port map ( + I => REG(21), + O => NlwInverterSignal_REG_22_D2_PT_1_IN4 + ); + NlwInverterBlock_REG_22_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_22_CLKF_IN0 + ); + NlwInverterBlock_REG_22_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_22_CLKF_IN1 + ); + NlwInverterBlock_REG_22_RSTF_IN2 : X_INV + port map ( + I => DIN_22_IBUF, + O => NlwInverterSignal_REG_22_RSTF_IN2 + ); + NlwInverterBlock_REG_23_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_23_RSTF, + O => NlwInverterSignal_REG_23_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_23_D2_PT_0_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_23_D2_PT_0_IN0 + ); + NlwInverterBlock_REG_23_D2_PT_0_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_23_D2_PT_0_IN1 + ); + NlwInverterBlock_REG_23_D2_PT_0_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_23_D2_PT_0_IN3 + ); + NlwInverterBlock_REG_23_D2_PT_0_IN5 : X_INV + port map ( + I => REG(23), + O => NlwInverterSignal_REG_23_D2_PT_0_IN5 + ); + NlwInverterBlock_REG_23_D2_PT_1_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_23_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_23_D2_PT_1_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_23_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_23_D2_PT_1_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_23_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_23_D2_PT_1_IN4 : X_INV + port map ( + I => REG(22), + O => NlwInverterSignal_REG_23_D2_PT_1_IN4 + ); + NlwInverterBlock_REG_23_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_23_CLKF_IN0 + ); + NlwInverterBlock_REG_23_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_23_CLKF_IN1 + ); + NlwInverterBlock_REG_23_RSTF_IN2 : X_INV + port map ( + I => DIN_23_IBUF, + O => NlwInverterSignal_REG_23_RSTF_IN2 + ); + NlwInverterBlock_REG_24_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_24_RSTF, + O => NlwInverterSignal_REG_24_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_24_D2_PT_0_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_24_D2_PT_0_IN0 + ); + NlwInverterBlock_REG_24_D2_PT_0_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_24_D2_PT_0_IN1 + ); + NlwInverterBlock_REG_24_D2_PT_0_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_24_D2_PT_0_IN3 + ); + NlwInverterBlock_REG_24_D2_PT_0_IN5 : X_INV + port map ( + I => REG(24), + O => NlwInverterSignal_REG_24_D2_PT_0_IN5 + ); + NlwInverterBlock_REG_24_D2_PT_1_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_24_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_24_D2_PT_1_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_24_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_24_D2_PT_1_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_24_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_24_D2_PT_1_IN4 : X_INV + port map ( + I => REG(23), + O => NlwInverterSignal_REG_24_D2_PT_1_IN4 + ); + NlwInverterBlock_REG_24_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_24_CLKF_IN0 + ); + NlwInverterBlock_REG_24_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_24_CLKF_IN1 + ); + NlwInverterBlock_REG_24_RSTF_IN2 : X_INV + port map ( + I => DIN_24_IBUF, + O => NlwInverterSignal_REG_24_RSTF_IN2 + ); + NlwInverterBlock_REG_25_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_25_RSTF, + O => NlwInverterSignal_REG_25_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_25_D2_PT_0_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_25_D2_PT_0_IN0 + ); + NlwInverterBlock_REG_25_D2_PT_0_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_25_D2_PT_0_IN1 + ); + NlwInverterBlock_REG_25_D2_PT_0_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_25_D2_PT_0_IN3 + ); + NlwInverterBlock_REG_25_D2_PT_0_IN5 : X_INV + port map ( + I => REG(25), + O => NlwInverterSignal_REG_25_D2_PT_0_IN5 + ); + NlwInverterBlock_REG_25_D2_PT_1_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_25_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_25_D2_PT_1_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_25_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_25_D2_PT_1_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_25_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_25_D2_PT_1_IN4 : X_INV + port map ( + I => REG(24), + O => NlwInverterSignal_REG_25_D2_PT_1_IN4 + ); + NlwInverterBlock_REG_25_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_25_CLKF_IN0 + ); + NlwInverterBlock_REG_25_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_25_CLKF_IN1 + ); + NlwInverterBlock_REG_25_RSTF_IN2 : X_INV + port map ( + I => DIN_25_IBUF, + O => NlwInverterSignal_REG_25_RSTF_IN2 + ); + NlwInverterBlock_REG_26_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_26_RSTF, + O => NlwInverterSignal_REG_26_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_26_D2_PT_0_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_26_D2_PT_0_IN0 + ); + NlwInverterBlock_REG_26_D2_PT_0_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_26_D2_PT_0_IN1 + ); + NlwInverterBlock_REG_26_D2_PT_0_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_26_D2_PT_0_IN3 + ); + NlwInverterBlock_REG_26_D2_PT_0_IN5 : X_INV + port map ( + I => REG(26), + O => NlwInverterSignal_REG_26_D2_PT_0_IN5 + ); + NlwInverterBlock_REG_26_D2_PT_1_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_26_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_26_D2_PT_1_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_26_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_26_D2_PT_1_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_26_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_26_D2_PT_1_IN4 : X_INV + port map ( + I => REG(25), + O => NlwInverterSignal_REG_26_D2_PT_1_IN4 + ); + NlwInverterBlock_REG_26_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_26_CLKF_IN0 + ); + NlwInverterBlock_REG_26_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_26_CLKF_IN1 + ); + NlwInverterBlock_REG_26_RSTF_IN2 : X_INV + port map ( + I => DIN_26_IBUF, + O => NlwInverterSignal_REG_26_RSTF_IN2 + ); + NlwInverterBlock_REG_27_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_27_RSTF, + O => NlwInverterSignal_REG_27_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_27_D2_PT_0_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_27_D2_PT_0_IN0 + ); + NlwInverterBlock_REG_27_D2_PT_0_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_27_D2_PT_0_IN1 + ); + NlwInverterBlock_REG_27_D2_PT_0_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_27_D2_PT_0_IN3 + ); + NlwInverterBlock_REG_27_D2_PT_0_IN5 : X_INV + port map ( + I => REG(27), + O => NlwInverterSignal_REG_27_D2_PT_0_IN5 + ); + NlwInverterBlock_REG_27_D2_PT_1_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_27_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_27_D2_PT_1_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_27_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_27_D2_PT_1_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_27_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_27_D2_PT_1_IN4 : X_INV + port map ( + I => REG(26), + O => NlwInverterSignal_REG_27_D2_PT_1_IN4 + ); + NlwInverterBlock_REG_27_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_27_CLKF_IN0 + ); + NlwInverterBlock_REG_27_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_27_CLKF_IN1 + ); + NlwInverterBlock_REG_27_RSTF_IN2 : X_INV + port map ( + I => DIN_27_IBUF, + O => NlwInverterSignal_REG_27_RSTF_IN2 + ); + NlwInverterBlock_REG_28_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_28_RSTF, + O => NlwInverterSignal_REG_28_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_28_D2_PT_0_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_28_D2_PT_0_IN0 + ); + NlwInverterBlock_REG_28_D2_PT_0_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_28_D2_PT_0_IN1 + ); + NlwInverterBlock_REG_28_D2_PT_0_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_28_D2_PT_0_IN3 + ); + NlwInverterBlock_REG_28_D2_PT_0_IN5 : X_INV + port map ( + I => REG(28), + O => NlwInverterSignal_REG_28_D2_PT_0_IN5 + ); + NlwInverterBlock_REG_28_D2_PT_1_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_28_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_28_D2_PT_1_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_28_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_28_D2_PT_1_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_28_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_28_D2_PT_1_IN4 : X_INV + port map ( + I => REG(27), + O => NlwInverterSignal_REG_28_D2_PT_1_IN4 + ); + NlwInverterBlock_REG_28_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_28_CLKF_IN0 + ); + NlwInverterBlock_REG_28_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_28_CLKF_IN1 + ); + NlwInverterBlock_REG_28_RSTF_IN2 : X_INV + port map ( + I => DIN_28_IBUF, + O => NlwInverterSignal_REG_28_RSTF_IN2 + ); + NlwInverterBlock_REG_29_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_29_RSTF, + O => NlwInverterSignal_REG_29_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_29_D2_PT_0_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_29_D2_PT_0_IN0 + ); + NlwInverterBlock_REG_29_D2_PT_0_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_29_D2_PT_0_IN1 + ); + NlwInverterBlock_REG_29_D2_PT_0_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_29_D2_PT_0_IN3 + ); + NlwInverterBlock_REG_29_D2_PT_0_IN5 : X_INV + port map ( + I => REG(29), + O => NlwInverterSignal_REG_29_D2_PT_0_IN5 + ); + NlwInverterBlock_REG_29_D2_PT_1_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_29_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_29_D2_PT_1_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_29_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_29_D2_PT_1_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_29_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_29_D2_PT_1_IN4 : X_INV + port map ( + I => REG(28), + O => NlwInverterSignal_REG_29_D2_PT_1_IN4 + ); + NlwInverterBlock_REG_29_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_29_CLKF_IN0 + ); + NlwInverterBlock_REG_29_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_29_CLKF_IN1 + ); + NlwInverterBlock_REG_29_RSTF_IN2 : X_INV + port map ( + I => DIN_29_IBUF, + O => NlwInverterSignal_REG_29_RSTF_IN2 + ); + NlwInverterBlock_REG_2_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_2_RSTF, + O => NlwInverterSignal_REG_2_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_2_D2_PT_0_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_2_D2_PT_0_IN0 + ); + NlwInverterBlock_REG_2_D2_PT_0_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_2_D2_PT_0_IN1 + ); + NlwInverterBlock_REG_2_D2_PT_0_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_2_D2_PT_0_IN3 + ); + NlwInverterBlock_REG_2_D2_PT_0_IN5 : X_INV + port map ( + I => REG(2), + O => NlwInverterSignal_REG_2_D2_PT_0_IN5 + ); + NlwInverterBlock_REG_2_D2_PT_1_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_2_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_2_D2_PT_1_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_2_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_2_D2_PT_1_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_2_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_2_D2_PT_1_IN4 : X_INV + port map ( + I => REG(1), + O => NlwInverterSignal_REG_2_D2_PT_1_IN4 + ); + NlwInverterBlock_REG_2_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_2_CLKF_IN0 + ); + NlwInverterBlock_REG_2_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_2_CLKF_IN1 + ); + NlwInverterBlock_REG_2_RSTF_IN2 : X_INV + port map ( + I => DIN_2_IBUF, + O => NlwInverterSignal_REG_2_RSTF_IN2 + ); + NlwInverterBlock_REG_30_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_30_RSTF, + O => NlwInverterSignal_REG_30_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_30_D2_PT_0_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_30_D2_PT_0_IN0 + ); + NlwInverterBlock_REG_30_D2_PT_0_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_30_D2_PT_0_IN1 + ); + NlwInverterBlock_REG_30_D2_PT_0_IN4 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_30_D2_PT_0_IN4 + ); + NlwInverterBlock_REG_30_D2_PT_0_IN5 : X_INV + port map ( + I => REG(29), + O => NlwInverterSignal_REG_30_D2_PT_0_IN5 + ); + NlwInverterBlock_REG_30_D2_PT_1_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_30_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_30_D2_PT_1_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_30_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_30_D2_PT_1_IN3 : X_INV + port map ( + I => REG(30), + O => NlwInverterSignal_REG_30_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_30_D2_PT_1_IN4 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_30_D2_PT_1_IN4 + ); + NlwInverterBlock_REG_30_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_30_CLKF_IN0 + ); + NlwInverterBlock_REG_30_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_30_CLKF_IN1 + ); + NlwInverterBlock_REG_30_RSTF_IN2 : X_INV + port map ( + I => DIN_30_IBUF, + O => NlwInverterSignal_REG_30_RSTF_IN2 + ); + NlwInverterBlock_REG_3_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_3_RSTF, + O => NlwInverterSignal_REG_3_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_3_D2_PT_0_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_3_D2_PT_0_IN0 + ); + NlwInverterBlock_REG_3_D2_PT_0_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_3_D2_PT_0_IN1 + ); + NlwInverterBlock_REG_3_D2_PT_0_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_3_D2_PT_0_IN3 + ); + NlwInverterBlock_REG_3_D2_PT_0_IN5 : X_INV + port map ( + I => REG(3), + O => NlwInverterSignal_REG_3_D2_PT_0_IN5 + ); + NlwInverterBlock_REG_3_D2_PT_1_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_3_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_3_D2_PT_1_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_3_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_3_D2_PT_1_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_3_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_3_D2_PT_1_IN4 : X_INV + port map ( + I => REG(2), + O => NlwInverterSignal_REG_3_D2_PT_1_IN4 + ); + NlwInverterBlock_REG_3_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_3_CLKF_IN0 + ); + NlwInverterBlock_REG_3_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_3_CLKF_IN1 + ); + NlwInverterBlock_REG_3_RSTF_IN2 : X_INV + port map ( + I => DIN_3_IBUF, + O => NlwInverterSignal_REG_3_RSTF_IN2 + ); + NlwInverterBlock_REG_4_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_4_RSTF, + O => NlwInverterSignal_REG_4_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_4_D2_PT_0_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_4_D2_PT_0_IN0 + ); + NlwInverterBlock_REG_4_D2_PT_0_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_4_D2_PT_0_IN1 + ); + NlwInverterBlock_REG_4_D2_PT_0_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_4_D2_PT_0_IN3 + ); + NlwInverterBlock_REG_4_D2_PT_0_IN5 : X_INV + port map ( + I => REG(4), + O => NlwInverterSignal_REG_4_D2_PT_0_IN5 + ); + NlwInverterBlock_REG_4_D2_PT_1_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_4_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_4_D2_PT_1_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_4_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_4_D2_PT_1_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_4_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_4_D2_PT_1_IN4 : X_INV + port map ( + I => REG(3), + O => NlwInverterSignal_REG_4_D2_PT_1_IN4 + ); + NlwInverterBlock_REG_4_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_4_CLKF_IN0 + ); + NlwInverterBlock_REG_4_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_4_CLKF_IN1 + ); + NlwInverterBlock_REG_4_RSTF_IN2 : X_INV + port map ( + I => DIN_4_IBUF, + O => NlwInverterSignal_REG_4_RSTF_IN2 + ); + NlwInverterBlock_REG_5_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_5_RSTF, + O => NlwInverterSignal_REG_5_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_5_D2_PT_0_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_5_D2_PT_0_IN0 + ); + NlwInverterBlock_REG_5_D2_PT_0_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_5_D2_PT_0_IN1 + ); + NlwInverterBlock_REG_5_D2_PT_0_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_5_D2_PT_0_IN3 + ); + NlwInverterBlock_REG_5_D2_PT_0_IN5 : X_INV + port map ( + I => REG(5), + O => NlwInverterSignal_REG_5_D2_PT_0_IN5 + ); + NlwInverterBlock_REG_5_D2_PT_1_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_5_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_5_D2_PT_1_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_5_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_5_D2_PT_1_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_5_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_5_D2_PT_1_IN4 : X_INV + port map ( + I => REG(4), + O => NlwInverterSignal_REG_5_D2_PT_1_IN4 + ); + NlwInverterBlock_REG_5_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_5_CLKF_IN0 + ); + NlwInverterBlock_REG_5_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_5_CLKF_IN1 + ); + NlwInverterBlock_REG_5_RSTF_IN2 : X_INV + port map ( + I => DIN_5_IBUF, + O => NlwInverterSignal_REG_5_RSTF_IN2 + ); + NlwInverterBlock_REG_6_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_6_RSTF, + O => NlwInverterSignal_REG_6_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_6_D2_PT_0_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_6_D2_PT_0_IN0 + ); + NlwInverterBlock_REG_6_D2_PT_0_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_6_D2_PT_0_IN1 + ); + NlwInverterBlock_REG_6_D2_PT_0_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_6_D2_PT_0_IN3 + ); + NlwInverterBlock_REG_6_D2_PT_0_IN5 : X_INV + port map ( + I => REG(6), + O => NlwInverterSignal_REG_6_D2_PT_0_IN5 + ); + NlwInverterBlock_REG_6_D2_PT_1_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_6_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_6_D2_PT_1_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_6_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_6_D2_PT_1_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_6_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_6_D2_PT_1_IN4 : X_INV + port map ( + I => REG(5), + O => NlwInverterSignal_REG_6_D2_PT_1_IN4 + ); + NlwInverterBlock_REG_6_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_6_CLKF_IN0 + ); + NlwInverterBlock_REG_6_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_6_CLKF_IN1 + ); + NlwInverterBlock_REG_6_RSTF_IN2 : X_INV + port map ( + I => DIN_6_IBUF, + O => NlwInverterSignal_REG_6_RSTF_IN2 + ); + NlwInverterBlock_REG_7_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_7_RSTF, + O => NlwInverterSignal_REG_7_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_7_D2_PT_0_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_7_D2_PT_0_IN0 + ); + NlwInverterBlock_REG_7_D2_PT_0_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_7_D2_PT_0_IN1 + ); + NlwInverterBlock_REG_7_D2_PT_0_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_7_D2_PT_0_IN3 + ); + NlwInverterBlock_REG_7_D2_PT_0_IN5 : X_INV + port map ( + I => REG(7), + O => NlwInverterSignal_REG_7_D2_PT_0_IN5 + ); + NlwInverterBlock_REG_7_D2_PT_1_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_7_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_7_D2_PT_1_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_7_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_7_D2_PT_1_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_7_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_7_D2_PT_1_IN4 : X_INV + port map ( + I => REG(6), + O => NlwInverterSignal_REG_7_D2_PT_1_IN4 + ); + NlwInverterBlock_REG_7_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_7_CLKF_IN0 + ); + NlwInverterBlock_REG_7_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_7_CLKF_IN1 + ); + NlwInverterBlock_REG_7_RSTF_IN2 : X_INV + port map ( + I => DIN_7_IBUF, + O => NlwInverterSignal_REG_7_RSTF_IN2 + ); + NlwInverterBlock_REG_8_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_8_RSTF, + O => NlwInverterSignal_REG_8_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_8_D2_PT_0_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_8_D2_PT_0_IN0 + ); + NlwInverterBlock_REG_8_D2_PT_0_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_8_D2_PT_0_IN1 + ); + NlwInverterBlock_REG_8_D2_PT_0_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_8_D2_PT_0_IN3 + ); + NlwInverterBlock_REG_8_D2_PT_0_IN5 : X_INV + port map ( + I => REG(8), + O => NlwInverterSignal_REG_8_D2_PT_0_IN5 + ); + NlwInverterBlock_REG_8_D2_PT_1_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_8_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_8_D2_PT_1_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_8_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_8_D2_PT_1_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_8_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_8_D2_PT_1_IN4 : X_INV + port map ( + I => REG(7), + O => NlwInverterSignal_REG_8_D2_PT_1_IN4 + ); + NlwInverterBlock_REG_8_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_8_CLKF_IN0 + ); + NlwInverterBlock_REG_8_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_8_CLKF_IN1 + ); + NlwInverterBlock_REG_8_RSTF_IN2 : X_INV + port map ( + I => DIN_8_IBUF, + O => NlwInverterSignal_REG_8_RSTF_IN2 + ); + NlwInverterBlock_REG_9_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_9_RSTF, + O => NlwInverterSignal_REG_9_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_9_D2_PT_0_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_9_D2_PT_0_IN0 + ); + NlwInverterBlock_REG_9_D2_PT_0_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_9_D2_PT_0_IN1 + ); + NlwInverterBlock_REG_9_D2_PT_0_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_9_D2_PT_0_IN3 + ); + NlwInverterBlock_REG_9_D2_PT_0_IN5 : X_INV + port map ( + I => REG(8), + O => NlwInverterSignal_REG_9_D2_PT_0_IN5 + ); + NlwInverterBlock_REG_9_D2_PT_1_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_REG_9_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_9_D2_PT_1_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_9_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_9_D2_PT_1_IN3 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_REG_9_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_9_D2_PT_1_IN4 : X_INV + port map ( + I => REG(9), + O => NlwInverterSignal_REG_9_D2_PT_1_IN4 + ); + NlwInverterBlock_REG_9_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_9_CLKF_IN0 + ); + NlwInverterBlock_REG_9_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_9_CLKF_IN1 + ); + NlwInverterBlock_REG_9_RSTF_IN2 : X_INV + port map ( + I => DIN_9_IBUF, + O => NlwInverterSignal_REG_9_RSTF_IN2 + ); + NlwInverterBlock_count_5_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => count_5_RSTF, + O => NlwInverterSignal_count_5_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_count_5_D2_PT_1_IN2 : X_INV + port map ( + I => VCLK_PRESCALE_5_IBUF, + O => NlwInverterSignal_count_5_D2_PT_1_IN2 + ); + NlwInverterBlock_count_5_D2_PT_2_IN1 : X_INV + port map ( + I => count(5), + O => NlwInverterSignal_count_5_D2_PT_2_IN1 + ); + NlwInverterBlock_count_5_RSTF_IN1 : X_INV + port map ( + I => VCLK_PRESCALE_5_IBUF, + O => NlwInverterSignal_count_5_RSTF_IN1 + ); + NlwInverterBlock_count_5_EXP_tsimrenamed_net_IN0 : X_INV + port map ( + I => count(0), + O => NlwInverterSignal_count_5_EXP_tsimrenamed_net_IN0 + ); + NlwInverterBlock_count_5_EXP_tsimrenamed_net_IN1 : X_INV + port map ( + I => count(4), + O => NlwInverterSignal_count_5_EXP_tsimrenamed_net_IN1 + ); + NlwInverterBlock_count_5_EXP_tsimrenamed_net_IN2 : X_INV + port map ( + I => count(2), + O => NlwInverterSignal_count_5_EXP_tsimrenamed_net_IN2 + ); + NlwInverterBlock_count_5_EXP_tsimrenamed_net_IN3 : X_INV + port map ( + I => count(3), + O => NlwInverterSignal_count_5_EXP_tsimrenamed_net_IN3 + ); + NlwInverterBlock_count_5_EXP_tsimrenamed_net_IN4 : X_INV + port map ( + I => count(5), + O => NlwInverterSignal_count_5_EXP_tsimrenamed_net_IN4 + ); + NlwInverterBlock_count_5_EXP_tsimrenamed_net_IN5 : X_INV + port map ( + I => VCLK_PRESCALE_1_IBUF, + O => NlwInverterSignal_count_5_EXP_tsimrenamed_net_IN5 + ); + NlwInverterBlock_SREG_IS_EMPTY_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => SREG_IS_EMPTY_RSTF, + O => NlwInverterSignal_SREG_IS_EMPTY_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_SREG_IS_EMPTY_RSTF_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_SREG_IS_EMPTY_RSTF_IN1 + ); + NlwInverterBlock_SHIFT_CNT_0_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => SHIFT_CNT_0_RSTF, + O => NlwInverterSignal_SHIFT_CNT_0_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_SHIFT_CNT_0_SETF_IN0 : X_INV + port map ( + I => SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_UIM, + O => NlwInverterSignal_SHIFT_CNT_0_SETF_IN0 + ); + NlwInverterBlock_SHIFT_CNT_0_SETF_IN1 : X_INV + port map ( + I => SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_UIM, + O => NlwInverterSignal_SHIFT_CNT_0_SETF_IN1 + ); + NlwInverterBlock_SHIFT_CNT_0_RSTF_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_SHIFT_CNT_0_RSTF_IN0 + ); + NlwInverterBlock_SHIFT_CNT_0_RSTF_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_SHIFT_CNT_0_RSTF_IN1 + ); + NlwInverterBlock_SHIFT_CNT_1_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => SHIFT_CNT_1_RSTF, + O => NlwInverterSignal_SHIFT_CNT_1_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_SHIFT_CNT_1_SETF_IN0 : X_INV + port map ( + I => SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_UIM, + O => NlwInverterSignal_SHIFT_CNT_1_SETF_IN0 + ); + NlwInverterBlock_SHIFT_CNT_1_SETF_IN1 : X_INV + port map ( + I => SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_UIM, + O => NlwInverterSignal_SHIFT_CNT_1_SETF_IN1 + ); + NlwInverterBlock_SHIFT_CNT_1_RSTF_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_SHIFT_CNT_1_RSTF_IN0 + ); + NlwInverterBlock_SHIFT_CNT_1_RSTF_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_SHIFT_CNT_1_RSTF_IN1 + ); + NlwInverterBlock_SHIFT_CNT_1_RSTF_IN3 : X_INV + port map ( + I => Msub_n0025_n00002_Msub_n0025_n00002_D2_UIM, + O => NlwInverterSignal_SHIFT_CNT_1_RSTF_IN3 + ); + NlwInverterBlock_SHIFT_CNT_1_RSTF_IN4 : X_INV + port map ( + I => Q_OpTx_OpTx_FX_DC_18_INV_124_UIM, + O => NlwInverterSignal_SHIFT_CNT_1_RSTF_IN4 + ); + NlwInverterBlock_SHIFT_CNT_2_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => SHIFT_CNT_2_RSTF, + O => NlwInverterSignal_SHIFT_CNT_2_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_SHIFT_CNT_2_SETF_IN0 : X_INV + port map ( + I => SHIFT_CNT_2_SHIFT_CNT_2_RSTF_UIM, + O => NlwInverterSignal_SHIFT_CNT_2_SETF_IN0 + ); + NlwInverterBlock_SHIFT_CNT_2_SETF_IN1 : X_INV + port map ( + I => Q_OpTx_OpTx_FX_DC_23_INV_125_UIM, + O => NlwInverterSignal_SHIFT_CNT_2_SETF_IN1 + ); + NlwInverterBlock_SHIFT_CNT_3_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => SHIFT_CNT_3_RSTF, + O => NlwInverterSignal_SHIFT_CNT_3_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_SHIFT_CNT_3_SETF_IN0 : X_INV + port map ( + I => Q_OpTx_OpTx_FX_DC_23_INV_125_UIM, + O => NlwInverterSignal_SHIFT_CNT_3_SETF_IN0 + ); + NlwInverterBlock_SHIFT_CNT_3_SETF_IN1 : X_INV + port map ( + I => SHIFT_CNT_3_SHIFT_CNT_3_RSTF_UIM, + O => NlwInverterSignal_SHIFT_CNT_3_SETF_IN1 + ); + NlwInverterBlock_SHIFT_CNT_3_RSTF_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_SHIFT_CNT_3_RSTF_IN0 + ); + NlwInverterBlock_SHIFT_CNT_3_RSTF_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_SHIFT_CNT_3_RSTF_IN1 + ); + NlwInverterBlock_SHIFT_CNT_3_RSTF_IN3 : X_INV + port map ( + I => Msub_n0025_n00022_Msub_n0025_n00022_D2_UIM, + O => NlwInverterSignal_SHIFT_CNT_3_RSTF_IN3 + ); + NlwInverterBlock_SHIFT_CNT_4_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => SHIFT_CNT_4_RSTF, + O => NlwInverterSignal_SHIFT_CNT_4_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_SHIFT_CNT_4_SETF_IN0 : X_INV + port map ( + I => SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_UIM, + O => NlwInverterSignal_SHIFT_CNT_4_SETF_IN0 + ); + NlwInverterBlock_SHIFT_CNT_4_SETF_IN1 : X_INV + port map ( + I => SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_UIM, + O => NlwInverterSignal_SHIFT_CNT_4_SETF_IN1 + ); + NlwInverterBlock_SHIFT_CNT_4_RSTF_IN1 : X_INV + port map ( + I => Q_OpTx_OpTx_FX_SC_22_INV_126_UIM, + O => NlwInverterSignal_SHIFT_CNT_4_RSTF_IN1 + ); + NlwInverterBlock_VCLK_OBUF_CE_IN0 : X_INV + port map ( + I => count(0), + O => NlwInverterSignal_VCLK_OBUF_CE_IN0 + ); + NlwInverterBlock_VCLK_OBUF_CE_IN1 : X_INV + port map ( + I => count(4), + O => NlwInverterSignal_VCLK_OBUF_CE_IN1 + ); + NlwInverterBlock_VCLK_OBUF_CE_IN2 : X_INV + port map ( + I => count(1), + O => NlwInverterSignal_VCLK_OBUF_CE_IN2 + ); + NlwInverterBlock_VCLK_OBUF_CE_IN3 : X_INV + port map ( + I => count(2), + O => NlwInverterSignal_VCLK_OBUF_CE_IN3 + ); + NlwInverterBlock_VCLK_OBUF_CE_IN4 : X_INV + port map ( + I => count(3), + O => NlwInverterSignal_VCLK_OBUF_CE_IN4 + ); + NlwInverterBlock_VCLK_OBUF_CE_IN5 : X_INV + port map ( + I => count(5), + O => NlwInverterSignal_VCLK_OBUF_CE_IN5 + ); + NlwInverterBlock_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN0 + ); + NlwInverterBlock_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN2 : X_INV + port map ( + I => SHIFT_CNT(0), + O => NlwInverterSignal_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN2 + ); + NlwInverterBlock_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN3 : X_INV + port map ( + I => SHIFT_CNT(1), + O => NlwInverterSignal_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN3 + ); + NlwInverterBlock_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN4 : X_INV + port map ( + I => SHIFT_CNT(2), + O => NlwInverterSignal_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN4 + ); + NlwInverterBlock_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN5 : X_INV + port map ( + I => SHIFT_CNT(3), + O => NlwInverterSignal_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN5 + ); + NlwInverterBlock_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN6 : X_INV + port map ( + I => SHIFT_CNT(4), + O => NlwInverterSignal_SREG_IS_EMPTY_SREG_IS_EMPTY_SETF_D2_PT_1_IN6 + ); + NlwInverterBlock_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_0_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_0_IN1 + ); + NlwInverterBlock_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_0_IN2 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_0_IN2 + ); + NlwInverterBlock_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_1_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_1_IN0 + ); + NlwInverterBlock_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_1_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_1_IN1 + ); + NlwInverterBlock_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_1_IN2 : X_INV + port map ( + I => SHIFT_EN, + O => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_1_IN2 + ); + NlwInverterBlock_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_2_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_2_IN0 + ); + NlwInverterBlock_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_2_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_2_IN1 + ); + NlwInverterBlock_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN0 + ); + NlwInverterBlock_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN1 + ); + NlwInverterBlock_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN2 : X_INV + port map ( + I => SHIFT_CNT(1), + O => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN2 + ); + NlwInverterBlock_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN3 : X_INV + port map ( + I => SHIFT_CNT(2), + O => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN3 + ); + NlwInverterBlock_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN4 : X_INV + port map ( + I => SHIFT_CNT(3), + O => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN4 + ); + NlwInverterBlock_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN5 : X_INV + port map ( + I => SHIFT_CNT(4), + O => NlwInverterSignal_SHIFT_CNT_0_SHIFT_CNT_0_SETF_INT_D2_PT_3_IN5 + ); + NlwInverterBlock_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_0_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_0_IN1 + ); + NlwInverterBlock_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_0_IN2 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_0_IN2 + ); + NlwInverterBlock_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_1_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_1_IN0 + ); + NlwInverterBlock_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_1_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_1_IN1 + ); + NlwInverterBlock_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_1_IN2 : X_INV + port map ( + I => SHIFT_EN, + O => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_1_IN2 + ); + NlwInverterBlock_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_2_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_2_IN0 + ); + NlwInverterBlock_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_2_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_2_IN1 + ); + NlwInverterBlock_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_2_IN3 : X_INV + port map ( + I => SHIFT_CNT(1), + O => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_2_IN3 + ); + NlwInverterBlock_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_3_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_3_IN0 + ); + NlwInverterBlock_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_3_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_3_IN1 + ); + NlwInverterBlock_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_3_IN2 : X_INV + port map ( + I => SHIFT_CNT(0), + O => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_3_IN2 + ); + NlwInverterBlock_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN0 + ); + NlwInverterBlock_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN1 + ); + NlwInverterBlock_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN2 : X_INV + port map ( + I => SHIFT_CNT(1), + O => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN2 + ); + NlwInverterBlock_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN3 : X_INV + port map ( + I => SHIFT_CNT(2), + O => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN3 + ); + NlwInverterBlock_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN4 : X_INV + port map ( + I => SHIFT_CNT(3), + O => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN4 + ); + NlwInverterBlock_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN5 : X_INV + port map ( + I => SHIFT_CNT(4), + O => NlwInverterSignal_SHIFT_CNT_1_SHIFT_CNT_1_SETF_INT_D2_PT_4_IN5 + ); + NlwInverterBlock_Msub_n0025_n00002_Msub_n0025_n00002_D2_D2_IN0 : X_INV + port map ( + I => SHIFT_CNT(0), + O => NlwInverterSignal_Msub_n0025_n00002_Msub_n0025_n00002_D2_D2_IN0 + ); + NlwInverterBlock_Msub_n0025_n00002_Msub_n0025_n00002_D2_D2_IN1 : X_INV + port map ( + I => SHIFT_CNT(1), + O => NlwInverterSignal_Msub_n0025_n00002_Msub_n0025_n00002_D2_D2_IN1 + ); + NlwInverterBlock_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_0_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_0_IN0 + ); + NlwInverterBlock_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_0_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_0_IN1 + ); + NlwInverterBlock_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_0_IN4 : X_INV + port map ( + I => SHIFT_CNT(2), + O => NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_0_IN4 + ); + NlwInverterBlock_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_1_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_1_IN0 + ); + NlwInverterBlock_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_1_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_1_IN1 + ); + NlwInverterBlock_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_1_IN4 : X_INV + port map ( + I => SHIFT_CNT(2), + O => NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_1_IN4 + ); + NlwInverterBlock_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_2_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_2_IN0 + ); + NlwInverterBlock_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_2_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_2_IN1 + ); + NlwInverterBlock_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_2_IN3 : X_INV + port map ( + I => SHIFT_CNT(0), + O => NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_2_IN3 + ); + NlwInverterBlock_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_2_IN4 : X_INV + port map ( + I => SHIFT_CNT(1), + O => NlwInverterSignal_SHIFT_CNT_2_SHIFT_CNT_2_RSTF_D2_PT_2_IN4 + ); + NlwInverterBlock_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_0_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_0_IN1 + ); + NlwInverterBlock_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_0_IN2 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_0_IN2 + ); + NlwInverterBlock_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_1_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_1_IN0 + ); + NlwInverterBlock_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_1_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_1_IN1 + ); + NlwInverterBlock_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_1_IN2 : X_INV + port map ( + I => SHIFT_EN, + O => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_1_IN2 + ); + NlwInverterBlock_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN0 + ); + NlwInverterBlock_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN1 + ); + NlwInverterBlock_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN2 : X_INV + port map ( + I => SHIFT_CNT(0), + O => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN2 + ); + NlwInverterBlock_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN3 : X_INV + port map ( + I => SHIFT_CNT(1), + O => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN3 + ); + NlwInverterBlock_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN4 : X_INV + port map ( + I => SHIFT_CNT(2), + O => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN4 + ); + NlwInverterBlock_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN5 : X_INV + port map ( + I => SHIFT_CNT(3), + O => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN5 + ); + NlwInverterBlock_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN6 : X_INV + port map ( + I => SHIFT_CNT(4), + O => NlwInverterSignal_OpTx_OpTx_FX_DC_23_INV_125_D2_PT_2_IN6 + ); + NlwInverterBlock_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_0_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_0_IN0 + ); + NlwInverterBlock_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_0_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_0_IN1 + ); + NlwInverterBlock_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_0_IN4 : X_INV + port map ( + I => SHIFT_CNT(3), + O => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_0_IN4 + ); + NlwInverterBlock_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_1_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_1_IN0 + ); + NlwInverterBlock_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_1_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_1_IN1 + ); + NlwInverterBlock_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_1_IN4 : X_INV + port map ( + I => SHIFT_CNT(3), + O => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_1_IN4 + ); + NlwInverterBlock_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_2_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_2_IN0 + ); + NlwInverterBlock_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_2_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_2_IN1 + ); + NlwInverterBlock_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_2_IN4 : X_INV + port map ( + I => SHIFT_CNT(3), + O => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_2_IN4 + ); + NlwInverterBlock_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3_IN0 + ); + NlwInverterBlock_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3_IN1 + ); + NlwInverterBlock_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3_IN3 : X_INV + port map ( + I => SHIFT_CNT(0), + O => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3_IN3 + ); + NlwInverterBlock_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3_IN4 : X_INV + port map ( + I => SHIFT_CNT(1), + O => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3_IN4 + ); + NlwInverterBlock_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3_IN5 : X_INV + port map ( + I => SHIFT_CNT(2), + O => NlwInverterSignal_SHIFT_CNT_3_SHIFT_CNT_3_RSTF_D2_PT_3_IN5 + ); + NlwInverterBlock_Msub_n0025_n00022_Msub_n0025_n00022_D2_D2_IN0 : X_INV + port map ( + I => SHIFT_CNT(0), + O => NlwInverterSignal_Msub_n0025_n00022_Msub_n0025_n00022_D2_D2_IN0 + ); + NlwInverterBlock_Msub_n0025_n00022_Msub_n0025_n00022_D2_D2_IN1 : X_INV + port map ( + I => SHIFT_CNT(1), + O => NlwInverterSignal_Msub_n0025_n00022_Msub_n0025_n00022_D2_D2_IN1 + ); + NlwInverterBlock_Msub_n0025_n00022_Msub_n0025_n00022_D2_D2_IN2 : X_INV + port map ( + I => SHIFT_CNT(2), + O => NlwInverterSignal_Msub_n0025_n00022_Msub_n0025_n00022_D2_D2_IN2 + ); + NlwInverterBlock_Msub_n0025_n00022_Msub_n0025_n00022_D2_D2_IN3 : X_INV + port map ( + I => SHIFT_CNT(3), + O => NlwInverterSignal_Msub_n0025_n00022_Msub_n0025_n00022_D2_D2_IN3 + ); + NlwInverterBlock_OpTx_FX_DC_20_D2_PT_0_IN0 : X_INV + port map ( + I => SHIFT_CNT(3), + O => NlwInverterSignal_OpTx_FX_DC_20_D2_PT_0_IN0 + ); + NlwInverterBlock_OpTx_FX_DC_20_D2_PT_0_IN1 : X_INV + port map ( + I => SHIFT_CNT(3), + O => NlwInverterSignal_OpTx_FX_DC_20_D2_PT_0_IN1 + ); + NlwInverterBlock_OpTx_FX_DC_20_D2_PT_1_IN0 : X_INV + port map ( + I => SHIFT_CNT(0), + O => NlwInverterSignal_OpTx_FX_DC_20_D2_PT_1_IN0 + ); + NlwInverterBlock_OpTx_FX_DC_20_D2_PT_1_IN1 : X_INV + port map ( + I => SHIFT_CNT(1), + O => NlwInverterSignal_OpTx_FX_DC_20_D2_PT_1_IN1 + ); + NlwInverterBlock_OpTx_FX_DC_20_D2_PT_1_IN2 : X_INV + port map ( + I => SHIFT_CNT(2), + O => NlwInverterSignal_OpTx_FX_DC_20_D2_PT_1_IN2 + ); + NlwInverterBlock_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_0_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_0_IN1 + ); + NlwInverterBlock_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_0_IN2 : X_INV + port map ( + I => SREG_IS_EMPTY, + O => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_0_IN2 + ); + NlwInverterBlock_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_1_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_1_IN0 + ); + NlwInverterBlock_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_1_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_1_IN1 + ); + NlwInverterBlock_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_1_IN2 : X_INV + port map ( + I => SHIFT_EN, + O => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_1_IN2 + ); + NlwInverterBlock_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_2_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_2_IN0 + ); + NlwInverterBlock_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_2_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_2_IN1 + ); + NlwInverterBlock_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_2_IN2 : X_INV + port map ( + I => SHIFT_CNT(4), + O => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_2_IN2 + ); + NlwInverterBlock_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN0 : X_INV + port map ( + I => LOAD_IBUF, + O => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN0 + ); + NlwInverterBlock_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN1 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN1 + ); + NlwInverterBlock_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN2 : X_INV + port map ( + I => SHIFT_CNT(0), + O => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN2 + ); + NlwInverterBlock_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN3 : X_INV + port map ( + I => SHIFT_CNT(1), + O => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN3 + ); + NlwInverterBlock_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN4 : X_INV + port map ( + I => SHIFT_CNT(2), + O => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN4 + ); + NlwInverterBlock_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN5 : X_INV + port map ( + I => SHIFT_CNT(3), + O => NlwInverterSignal_SHIFT_CNT_4_SHIFT_CNT_4_SETF_INT_D2_PT_3_IN5 + ); + NlwInverterBlock_OpTx_FX_DC_21_D2_PT_0_IN0 : X_INV + port map ( + I => SHIFT_CNT(4), + O => NlwInverterSignal_OpTx_FX_DC_21_D2_PT_0_IN0 + ); + NlwInverterBlock_OpTx_FX_DC_21_D2_PT_0_IN1 : X_INV + port map ( + I => SHIFT_CNT(4), + O => NlwInverterSignal_OpTx_FX_DC_21_D2_PT_0_IN1 + ); + NlwInverterBlock_OpTx_FX_DC_21_D2_PT_1_IN0 : X_INV + port map ( + I => SHIFT_CNT(0), + O => NlwInverterSignal_OpTx_FX_DC_21_D2_PT_1_IN0 + ); + NlwInverterBlock_OpTx_FX_DC_21_D2_PT_1_IN1 : X_INV + port map ( + I => SHIFT_CNT(1), + O => NlwInverterSignal_OpTx_FX_DC_21_D2_PT_1_IN1 + ); + NlwInverterBlock_OpTx_FX_DC_21_D2_PT_1_IN2 : X_INV + port map ( + I => SHIFT_CNT(2), + O => NlwInverterSignal_OpTx_FX_DC_21_D2_PT_1_IN2 + ); + NlwInverterBlock_OpTx_FX_DC_21_D2_PT_1_IN3 : X_INV + port map ( + I => SHIFT_CNT(3), + O => NlwInverterSignal_OpTx_FX_DC_21_D2_PT_1_IN3 + ); + NlwInverterBlock_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_2_IN0 : X_INV + port map ( + I => SHIFT_EN, + O => NlwInverterSignal_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_2_IN0 + ); + NlwInverterBlock_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_2_IN1 : X_INV + port map ( + I => SHIFT_EN, + O => NlwInverterSignal_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_2_IN1 + ); + NlwInverterBlock_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3_IN0 : X_INV + port map ( + I => SHIFT_CNT(0), + O => NlwInverterSignal_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3_IN0 + ); + NlwInverterBlock_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3_IN1 : X_INV + port map ( + I => SHIFT_CNT(1), + O => NlwInverterSignal_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3_IN1 + ); + NlwInverterBlock_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3_IN2 : X_INV + port map ( + I => SHIFT_CNT(2), + O => NlwInverterSignal_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3_IN2 + ); + NlwInverterBlock_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3_IN3 : X_INV + port map ( + I => SHIFT_CNT(3), + O => NlwInverterSignal_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3_IN3 + ); + NlwInverterBlock_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3_IN4 : X_INV + port map ( + I => SHIFT_CNT(4), + O => NlwInverterSignal_OpTx_OpTx_FX_SC_22_INV_126_D2_PT_3_IN4 + ); + NlwInverterBlock_EXP18_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP18_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP18_EXP_PT_0_IN1 : X_INV + port map ( + I => count(0), + O => NlwInverterSignal_EXP18_EXP_PT_0_IN1 + ); + NlwInverterBlock_EXP18_EXP_PT_0_IN2 : X_INV + port map ( + I => count(4), + O => NlwInverterSignal_EXP18_EXP_PT_0_IN2 + ); + NlwInverterBlock_EXP18_EXP_PT_0_IN3 : X_INV + port map ( + I => count(1), + O => NlwInverterSignal_EXP18_EXP_PT_0_IN3 + ); + NlwInverterBlock_EXP18_EXP_PT_0_IN4 : X_INV + port map ( + I => count(2), + O => NlwInverterSignal_EXP18_EXP_PT_0_IN4 + ); + NlwInverterBlock_EXP18_EXP_PT_0_IN5 : X_INV + port map ( + I => count(3), + O => NlwInverterSignal_EXP18_EXP_PT_0_IN5 + ); + NlwInverterBlock_EXP18_EXP_PT_1_IN0 : X_INV + port map ( + I => count(0), + O => NlwInverterSignal_EXP18_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP18_EXP_PT_1_IN1 : X_INV + port map ( + I => count(4), + O => NlwInverterSignal_EXP18_EXP_PT_1_IN1 + ); + NlwInverterBlock_EXP18_EXP_PT_1_IN2 : X_INV + port map ( + I => count(1), + O => NlwInverterSignal_EXP18_EXP_PT_1_IN2 + ); + NlwInverterBlock_EXP18_EXP_PT_1_IN3 : X_INV + port map ( + I => count(2), + O => NlwInverterSignal_EXP18_EXP_PT_1_IN3 + ); + NlwInverterBlock_EXP18_EXP_PT_1_IN4 : X_INV + port map ( + I => count(3), + O => NlwInverterSignal_EXP18_EXP_PT_1_IN4 + ); + NlwInverterBlock_EXP18_EXP_PT_1_IN5 : X_INV + port map ( + I => count(5), + O => NlwInverterSignal_EXP18_EXP_PT_1_IN5 + ); + NlwInverterBlock_EXP19_EXP_PT_0_IN2 : X_INV + port map ( + I => VCLK_PRESCALE_4_IBUF, + O => NlwInverterSignal_EXP19_EXP_PT_0_IN2 + ); + NlwInverterBlock_EXP19_EXP_PT_1_IN1 : X_INV + port map ( + I => count(4), + O => NlwInverterSignal_EXP19_EXP_PT_1_IN1 + ); + NlwInverterBlock_EXP19_EXP_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP19_EXP_PT_2_IN0 + ); + NlwInverterBlock_EXP19_EXP_PT_2_IN1 : X_INV + port map ( + I => count(0), + O => NlwInverterSignal_EXP19_EXP_PT_2_IN1 + ); + NlwInverterBlock_EXP19_EXP_PT_2_IN3 : X_INV + port map ( + I => count(1), + O => NlwInverterSignal_EXP19_EXP_PT_2_IN3 + ); + NlwInverterBlock_EXP19_EXP_PT_2_IN4 : X_INV + port map ( + I => count(2), + O => NlwInverterSignal_EXP19_EXP_PT_2_IN4 + ); + NlwInverterBlock_EXP19_EXP_PT_2_IN5 : X_INV + port map ( + I => count(3), + O => NlwInverterSignal_EXP19_EXP_PT_2_IN5 + ); + NlwInverterBlock_EXP20_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP20_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP20_EXP_PT_0_IN2 : X_INV + port map ( + I => count(3), + O => NlwInverterSignal_EXP20_EXP_PT_0_IN2 + ); + NlwInverterBlock_EXP20_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP20_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP20_EXP_PT_1_IN2 : X_INV + port map ( + I => count(3), + O => NlwInverterSignal_EXP20_EXP_PT_1_IN2 + ); + NlwInverterBlock_EXP20_EXP_PT_2_IN0 : X_INV + port map ( + I => count(4), + O => NlwInverterSignal_EXP20_EXP_PT_2_IN0 + ); + NlwInverterBlock_EXP20_EXP_PT_2_IN1 : X_INV + port map ( + I => count(3), + O => NlwInverterSignal_EXP20_EXP_PT_2_IN1 + ); + NlwInverterBlock_EXP20_EXP_PT_2_IN2 : X_INV + port map ( + I => count(5), + O => NlwInverterSignal_EXP20_EXP_PT_2_IN2 + ); + NlwInverterBlock_EXP20_EXP_PT_2_IN3 : X_INV + port map ( + I => VCLK_PRESCALE_3_IBUF, + O => NlwInverterSignal_EXP20_EXP_PT_2_IN3 + ); + NlwInverterBlock_EXP20_EXP_PT_3_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP20_EXP_PT_3_IN0 + ); + NlwInverterBlock_EXP20_EXP_PT_3_IN1 : X_INV + port map ( + I => count(0), + O => NlwInverterSignal_EXP20_EXP_PT_3_IN1 + ); + NlwInverterBlock_EXP20_EXP_PT_3_IN2 : X_INV + port map ( + I => count(1), + O => NlwInverterSignal_EXP20_EXP_PT_3_IN2 + ); + NlwInverterBlock_EXP20_EXP_PT_3_IN3 : X_INV + port map ( + I => count(2), + O => NlwInverterSignal_EXP20_EXP_PT_3_IN3 + ); + NlwBlockROC : X_ROC + generic map (ROC_WIDTH => 100 ns) + port map (O => PRLD); + +end Structure; + diff --git a/projects/Eval_VConfig/vconfig.vhdl b/projects/Eval_VConfig/vconfig.vhdl new file mode 100644 index 0000000..be44c3b --- /dev/null +++ b/projects/Eval_VConfig/vconfig.vhdl @@ -0,0 +1,183 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following lines to use the declarations that are +-- provided for instantiating Xilinx primitive components. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity vconfig is + Port ( RES : in std_logic; + nINIT_B : in std_logic; + CLK : in std_logic; + DONE : in std_logic; + CCLK : out std_logic; + CCLK_PRESCALER : in std_logic_vector(5 downto 0); + LOAD_PRESCALER : in std_logic; + DIN : in std_logic_vector(31 downto 0); + DOUT : out std_logic; + LOAD_SREG : in std_logic; + BUF_IS_EMPTY : inout std_logic); +end vconfig; + +architecture Behavioral of vconfig is + +constant nbits : integer := 32; +constant nBufs : integer := 2; + +type t_config_state is (CFG_STOP, CFG_INIT, CFG_RUN); +type t_buf is array (0 to nBufs-1) of std_logic_vector (nBits-1 downto 0); + +signal REG: t_buf; +signal count, CLK_SCALE: integer range 0 to 63; +signal SHIFT_CNT: integer range 0 to nbits-1; +signal state, next_state : t_config_state; +signal SCLK, SHIFT_EN : STD_LOGIC; +signal buf_depth: integer range 0 to 2; +signal tempID, readBufId, writeBufId : integer range 0 to nBufs-1; + + +begin + +-- 4-bit loadable serial-in and serial-out shift register +-- CLK: in STD_LOGIC; +-- DIN: in STD_LOGIC; +-- LOAD: in STD_LOGIC; +-- LOAD_DATA: in STD_LOGIC_VECTOR(3 downto 0); +-- DOUT: out STD_LOGIC; + + +process (RES, SCLK, state, nINIT_B, DONE, REG, BUF_IS_EMPTY) +begin + if (RES = '1') then + CCLK <= '1'; + SHIFT_EN <= '0'; + DOUT <= 'Z'; + + else + case state is + when CFG_STOP => + SHIFT_EN <= '0'; + CCLK <= '1'; + if (DONE = '0' and BUF_IS_EMPTY = '0') then + next_state <= CFG_INIT; + else + next_state <= CFG_STOP; + end if; + + when CFG_INIT => + CCLK <= SCLK; + next_state <= CFG_RUN; + + when CFG_RUN => + SHIFT_EN <= '1'; + CCLK <= SCLK; + if (DONE = '1' or nINIT_B = '0' or BUF_IS_EMPTY = '1') then + next_state <= CFG_STOP; + else + next_state <= CFG_RUN; + end if; + end case; + if (nINIT_B = '1') then + DOUT <= STD_LOGIC(REG(readBufId)(nbits-1)); + else + DOUT <= 'Z'; + end if; + end if; + +end process; + +sreg: + process(RES, SCLK, REG, DIN, LOAD_SREG, SHIFT_EN, SHIFT_CNT) + begin + if (RES = '1') then + BUF_IS_EMPTY <= '1'; + SHIFT_CNT <= 0; + writeBufId <= 0; + readBufId <= 0; + buf_depth <= 0; + + elsif (LOAD_SREG = '1') then + REG(writeBufId) <= DIN; + + if (SHIFT_EN = '0') then + SHIFT_CNT <= nbits-1; + end if; + + if (buf_depth = nbufs) then + buf_depth <= buf_depth ; + else + buf_depth <= buf_depth + 1; + end if; + + else + if SCLK='0' and SCLK'event then + if SHIFT_EN = '1' then + REG(readBufId)(nbits-1 downto 0) <= REG(readBufId)(nbits-2 downto 0) & '0'; + if (SHIFT_CNT = 0) then + if (buf_depth = 0) then + writeBufId <= 0; + readBufId <= 0; + else + SHIFT_CNT <= nbits-1; + tempID <= readBufID; + readBufID <= writeBufId; + writeBufId <= tempID; + buf_depth <= buf_depth - 1; + end if; + else + SHIFT_CNT <= SHIFT_CNT - 1; + end if; + end if; + end if; + end if; + if (SHIFT_CNT = 0 and buf_depth = 1) then + BUF_IS_EMPTY <= '1'; + else + BUF_IS_EMPTY <= '0'; + end if; + end process; + +-- 4-bit synchronous counter with count enable, +-- asynchronous reset +-- CLK: in STD_LOGIC; +-- RESET: in STD_LOGIC; +-- CE, LOAD, DIR: in STD_LOGIC; +-- DIN: in STD_LOGIC_VECTOR(3 downto 0); +-- COUNT: inout STD_LOGIC_VECTOR(3 downto 0); +cfg_state_gen: + process(RES, SCLK, next_state) + begin + if (RES = '1') then + state <= CFG_STOP; + elsif SCLK='1' and SCLK'event then + state <= next_state; + end if; + end process; + + +clk_prescaler: +process (RES, CLK, CCLK_PRESCALER, LOAD_PRESCALER) +begin + if (RES = '1') then + SCLK <= '1'; + CLK_SCALE <= 1; + COUNT <= CLK_SCALE; + + elsif (LOAD_PRESCALER = '1') then + CLK_SCALE <= CONV_INTEGER(CCLK_PRESCALER); + + elsif CLK='1' and CLK'event then + if (COUNT = 1) then + SCLK <= not SCLK; + + COUNT <= CLK_SCALE; + else + COUNT <= COUNT - 1; + end if; + end if; +end process; + +end Behavioral; diff --git a/projects/Eval_VConfig/vconfig_locked.ucf b/projects/Eval_VConfig/vconfig_locked.ucf new file mode 100644 index 0000000..31e62e0 --- /dev/null +++ b/projects/Eval_VConfig/vconfig_locked.ucf @@ -0,0 +1,54 @@ + +#PINLOCK_BEGIN + +#Sun May 02 01:57:09 2004 + +NET "CLK" LOC = "S:PIN30"; +NET "DIN<0>" LOC = "S:PIN94"; +NET "DIN<10>" LOC = "S:PIN132"; +NET "DIN<11>" LOC = "S:PIN12"; +NET "DIN<12>" LOC = "S:PIN124"; +NET "DIN<13>" LOC = "S:PIN85"; +NET "DIN<14>" LOC = "S:PIN118"; +NET "DIN<15>" LOC = "S:PIN82"; +NET "DIN<16>" LOC = "S:PIN139"; +NET "DIN<17>" LOC = "S:PIN40"; +NET "DIN<18>" LOC = "S:PIN6"; +NET "DIN<19>" LOC = "S:PIN115"; +NET "DIN<1>" LOC = "S:PIN35"; +NET "DIN<20>" LOC = "S:PIN134"; +NET "DIN<21>" LOC = "S:PIN76"; +NET "DIN<22>" LOC = "S:PIN136"; +NET "DIN<23>" LOC = "S:PIN13"; +NET "DIN<24>" LOC = "S:PIN103"; +NET "DIN<25>" LOC = "S:PIN112"; +NET "DIN<26>" LOC = "S:PIN59"; +NET "DIN<27>" LOC = "S:PIN88"; +NET "DIN<28>" LOC = "S:PIN101"; +NET "DIN<29>" LOC = "S:PIN25"; +NET "DIN<2>" LOC = "S:PIN93"; +NET "DIN<30>" LOC = "S:PIN38"; +NET "DIN<31>" LOC = "S:PIN91"; +NET "DIN<3>" LOC = "S:PIN21"; +NET "DIN<4>" LOC = "S:PIN143"; +NET "DIN<5>" LOC = "S:PIN28"; +NET "DIN<6>" LOC = "S:PIN24"; +NET "DIN<7>" LOC = "S:PIN44"; +NET "DIN<8>" LOC = "S:PIN104"; +NET "DIN<9>" LOC = "S:PIN140"; +NET "DONE" LOC = "S:PIN48"; +NET "LOAD_PRESCALER" LOC = "S:PIN74"; +NET "LOAD_SREG" LOC = "S:PIN64"; +NET "RES" LOC = "S:PIN98"; +NET "VCLK_PRESCALER<0>" LOC = "S:PIN11"; +NET "VCLK_PRESCALER<1>" LOC = "S:PIN97"; +NET "VCLK_PRESCALER<2>" LOC = "S:PIN133"; +NET "VCLK_PRESCALER<3>" LOC = "S:PIN7"; +NET "VCLK_PRESCALER<4>" LOC = "S:PIN138"; +NET "VCLK_PRESCALER<5>" LOC = "S:PIN142"; +NET "nINIT_B" LOC = "S:PIN10"; +NET "DOUT" LOC = "S:PIN79"; +NET "SCLK" LOC = "S:PIN9"; +NET "VCLK" LOC = "S:PIN50"; +NET "dummy_out" LOC = "S:PIN117"; +#PINLOCK_END diff --git a/projects/Eval_VConfig/vconfig_tb.fdo b/projects/Eval_VConfig/vconfig_tb.fdo new file mode 100644 index 0000000..cfe2a04 --- /dev/null +++ b/projects/Eval_VConfig/vconfig_tb.fdo @@ -0,0 +1,13 @@ +## NOTE: Do not edit this file. +## Autogenerated by ProjNav (creatfdo.tcl) on Wed May 05 21:50:05 Westeuropäische Sommerzeit 2004 +## +vlib work +vcom -93 -explicit vconfig.vhdl +vcom -93 -explicit vconfig_tb.vhd +vsim -t 1ps -lib work vconfig_tb +do vconfig_tb.udo +view wave +add wave * +view structure +view signals +run 6000ns diff --git a/projects/Eval_VConfig/vconfig_tb.tdo b/projects/Eval_VConfig/vconfig_tb.tdo new file mode 100644 index 0000000..b97c007 --- /dev/null +++ b/projects/Eval_VConfig/vconfig_tb.tdo @@ -0,0 +1,15 @@ +## NOTE: Do not edit this file. +## Auto generated by Project Navigator for VHDL Post-PAR Simulation +## +vlib work +## Compile Post-PAR Model for Module vconfig +vcom -87 -explicit vconfig_timesim.vhd +vcom -93 -explicit vconfig_tb.vhd +vsim -t 1ps -sdfmax /UUT=vconfig_timesim.sdf -lib work vconfig_tb +do vconfig_tb.udo +view wave +add wave * +view structure +view signals +run 6000ns +## End diff --git a/projects/Eval_VConfig/vconfig_tb.udo b/projects/Eval_VConfig/vconfig_tb.udo new file mode 100644 index 0000000..71e50c2 --- /dev/null +++ b/projects/Eval_VConfig/vconfig_tb.udo @@ -0,0 +1,4 @@ +-- ProjNav VHDL simulation template: vconfig_tb.udo +-- You may edit this file after the line that starts with +-- '-- START' to customize your simulation +-- START user-defined simulation commands diff --git a/projects/Eval_VConfig/vconfig_tb.vhd b/projects/Eval_VConfig/vconfig_tb.vhd new file mode 100644 index 0000000..cedcf69 --- /dev/null +++ b/projects/Eval_VConfig/vconfig_tb.vhd @@ -0,0 +1,129 @@ + +-- VHDL Test Bench Created from source file vconfig.vhd -- 20:20:01 05/01/2004 +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-- +LIBRARY ieee; +USE ieee.numeric_std.ALL; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +ENTITY vconfig_tb IS +END vconfig_tb; + +ARCHITECTURE behavior OF vconfig_tb IS + + COMPONENT vconfig + PORT( + RES : IN std_logic; + nINIT_B : IN std_logic; + CLK : IN std_logic; + DONE : IN std_logic; + CCLK : OUT std_logic; + CCLK_PRESCALER : IN std_logic_vector(5 downto 0); + LOAD_PRESCALER : in std_logic; + DIN : IN std_logic_vector(31 downto 0); + DOUT : OUT std_logic; + BUF_IS_EMPTY : inout std_logic; + LOAD_SREG : IN std_logic + ); + END COMPONENT; + + SIGNAL RES : std_logic := '1'; + SIGNAL nINIT_B : std_logic := '0'; + SIGNAL CLK : std_logic := '0'; + SIGNAL DONE : std_logic := '1'; + SIGNAL CCLK : std_logic; + SIGNAL CCLK_PRESCALER : std_logic_vector(5 downto 0); + SIGNAL LOAD_PRESCALER : std_logic := '0'; + SIGNAL DOUT : std_logic; + SIGNAL DIN : std_logic_vector(31 downto 0); + SIGNAL LOAD_SREG : std_logic := '0'; + SIGNAL BUF_IS_EMPTY : std_logic; + + constant ClockPeriod : Time := 16.667 ns; + constant CFG_PRESCALE: integer range 0 to 63 := 2; + +BEGIN + + uut: vconfig PORT MAP( + RES => RES, + nINIT_B => nINIT_B, + CLK => CLK, + DONE => DONE, + CCLK => CCLK, + CCLK_PRESCALER => CCLK_PRESCALER, + LOAD_PRESCALER => LOAD_PRESCALER, + DOUT => DOUT, + DIN => DIN, + BUF_IS_EMPTY => BUF_IS_EMPTY, + LOAD_SREG => LOAD_SREG + ); + + busclock: process + begin + CLK <= '1'; + loop + wait for (ClockPeriod / 2); + CLK <= not CLK; + end loop; + end process; + +-- *** Test Bench - User Defined Section *** + tb : PROCESS + BEGIN + + wait for 5*ClockPeriod; + RES <= '0'; + + wait for 5*ClockPeriod; + CCLK_PRESCALER <= CONV_STD_LOGIC_VECTOR(CFG_PRESCALE,6); + + wait for 1.5*ClockPeriod; + LOAD_PRESCALER <= '1'; + + wait for 1*ClockPeriod; + LOAD_PRESCALER <= '0'; + + wait for 1*ClockPeriod; + DIN <= X"BAA34569"; + + wait for 1.5*ClockPeriod; + LOAD_SREG <= '1'; + + wait for 1.0*ClockPeriod; + LOAD_SREG <= '0'; + + wait for 5*ClockPeriod; + DONE <= '0'; + + wait for 2*ClockPeriod; + nINIT_B <= '1'; + + wait for 30.0*real(CFG_PRESCALE)*ClockPeriod*2; + + DIN <= X"8654F41B"; + + wait for 1.5*ClockPeriod; + LOAD_SREG <= '1'; + + wait for 2.0*ClockPeriod; + LOAD_SREG <= '0'; + + wait for 29.0*real(CFG_PRESCALE)*ClockPeriod*2; + DONE <= '1'; + + wait for 10.0*ClockPeriod; + nINIT_B <= '0'; + + wait; -- will wait forever + END PROCESS; +-- *** End Test Bench - User Defined Section *** + +END; diff --git a/projects/Eval_VConfig/vconfig_timesim.vhd b/projects/Eval_VConfig/vconfig_timesim.vhd new file mode 100644 index 0000000..7deb6c4 --- /dev/null +++ b/projects/Eval_VConfig/vconfig_timesim.vhd @@ -0,0 +1,21777 @@ +-- Xilinx Vhdl netlist produced by netgen application (version G.30) +-- Command : -rpw 100 -ar Structure -xon true -w -ofmt vhdl -sim vconfig.nga vconfig_timesim.vhd +-- Input file : vconfig.nga +-- Output file : vconfig_timesim.vhd +-- Design name : vconfig.nga +-- # of Entities : 1 +-- Xilinx : D:/Xilinx +-- Device : XC95288XL-6-TQ144 (Speed File: Version 3.0) + +-- This vhdl netlist is a simulation model and uses simulation +-- primitives which may not represent the true implementation of the +-- device, however the netlist is functionally correct and should not +-- be modified. This file cannot be synthesized and should only be used +-- with supported simulation tools. + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library SIMPRIM; +use SIMPRIM.VCOMPONENTS.ALL; +use SIMPRIM.VPACKAGE.ALL; + +entity vconfig is + port ( + CLK : in STD_LOGIC := 'X'; + RES : in STD_LOGIC := 'X'; + LOAD_PRESCALER : in STD_LOGIC := 'X'; + LOAD_SREG : in STD_LOGIC := 'X'; + DONE : in STD_LOGIC := 'X'; + nINIT_B : in STD_LOGIC := 'X'; + DOUT : out STD_LOGIC; + BUF_IS_EMPTY : out STD_LOGIC; + CCLK : out STD_LOGIC; + CCLK_PRESCALER : in STD_LOGIC_VECTOR ( 5 downto 0 ); + DIN : in STD_LOGIC_VECTOR ( 31 downto 0 ) + ); +end vconfig; + +architecture Structure of vconfig is + signal FCLKIO_0 : STD_LOGIC; + signal RES_IBUF : STD_LOGIC; + signal LOAD_PRESCALER_IBUF : STD_LOGIC; + signal LOAD_SREG_IBUF : STD_LOGIC; + signal CCLK_PRESCALER_0_IBUF : STD_LOGIC; + signal DIN_0_IBUF : STD_LOGIC; + signal DIN_1_IBUF : STD_LOGIC; + signal DIN_10_IBUF : STD_LOGIC; + signal DIN_11_IBUF : STD_LOGIC; + signal DIN_12_IBUF : STD_LOGIC; + signal DIN_13_IBUF : STD_LOGIC; + signal DIN_14_IBUF : STD_LOGIC; + signal DIN_15_IBUF : STD_LOGIC; + signal DIN_16_IBUF : STD_LOGIC; + signal DIN_17_IBUF : STD_LOGIC; + signal DIN_18_IBUF : STD_LOGIC; + signal DIN_19_IBUF : STD_LOGIC; + signal DIN_2_IBUF : STD_LOGIC; + signal DIN_20_IBUF : STD_LOGIC; + signal DIN_21_IBUF : STD_LOGIC; + signal DIN_22_IBUF : STD_LOGIC; + signal DIN_23_IBUF : STD_LOGIC; + signal DIN_24_IBUF : STD_LOGIC; + signal DIN_25_IBUF : STD_LOGIC; + signal DIN_26_IBUF : STD_LOGIC; + signal DIN_27_IBUF : STD_LOGIC; + signal DIN_28_IBUF : STD_LOGIC; + signal DIN_29_IBUF : STD_LOGIC; + signal DIN_3_IBUF : STD_LOGIC; + signal DIN_30_IBUF : STD_LOGIC; + signal DIN_31_IBUF : STD_LOGIC; + signal DIN_4_IBUF : STD_LOGIC; + signal DIN_5_IBUF : STD_LOGIC; + signal DIN_6_IBUF : STD_LOGIC; + signal DIN_7_IBUF : STD_LOGIC; + signal DIN_8_IBUF : STD_LOGIC; + signal DIN_9_IBUF : STD_LOGIC; + signal DONE_IBUF : STD_LOGIC; + signal nINIT_B_IBUF : STD_LOGIC; + signal CCLK_PRESCALER_1_IBUF : STD_LOGIC; + signal CCLK_PRESCALER_2_IBUF : STD_LOGIC; + signal CCLK_PRESCALER_3_IBUF : STD_LOGIC; + signal CCLK_PRESCALER_4_IBUF : STD_LOGIC; + signal CCLK_PRESCALER_5_IBUF : STD_LOGIC; + signal DOUT_OBUFE : STD_LOGIC; + signal DOUT_OBUFE_OE : STD_LOGIC; + signal BUF_IS_EMPTY_OBUF_Q : STD_LOGIC; + signal CCLK_OBUF : STD_LOGIC; + signal SCLK_Q : STD_LOGIC; + signal SCLK : STD_LOGIC; + signal SCLK_D : STD_LOGIC; + signal SCLK_tsimcreated_xor_Q : STD_LOGIC; + signal SCLK_SETF : STD_LOGIC; + signal PRLD : STD_LOGIC; + signal SCLK_CE : STD_LOGIC; + signal SCLK_D1 : STD_LOGIC; + signal SCLK_D2 : STD_LOGIC; + signal readBufId_0_Q : STD_LOGIC; + signal readBufId_0_RSTF : STD_LOGIC; + signal readBufId_0_tsimcreated_prld_Q : STD_LOGIC; + signal readBufId_0_D : STD_LOGIC; + signal readBufId_0_CLKF : STD_LOGIC; + signal Gnd : STD_LOGIC; + signal readBufId_0_CE : STD_LOGIC; + signal readBufId_0_D1 : STD_LOGIC; + signal readBufId_0_D2 : STD_LOGIC; + signal readBufId_0_D2_PT_0 : STD_LOGIC; + signal readBufId_0_D2_PT_1 : STD_LOGIC; + signal SHIFT_EN : STD_LOGIC; + signal buf_depth_0_Q : STD_LOGIC; + signal buf_depth_0_D : STD_LOGIC; + signal buf_depth_0_tsimcreated_xor_Q : STD_LOGIC; + signal buf_depth_0_RSTF : STD_LOGIC; + signal buf_depth_0_SETF : STD_LOGIC; + signal buf_depth_0_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal buf_depth_0_tsimcreated_prld_Q : STD_LOGIC; + signal buf_depth_0_CLKF : STD_LOGIC; + signal Vcc : STD_LOGIC; + signal buf_depth_0_D1 : STD_LOGIC; + signal buf_depth_0_D2 : STD_LOGIC; + signal buf_depth_0_D2_PT_0 : STD_LOGIC; + signal buf_depth_0_D2_PT_1 : STD_LOGIC; + signal buf_depth_0_buf_depth_0_RSTF_UIM : STD_LOGIC; + signal buf_depth_1_Q : STD_LOGIC; + signal buf_depth_1_D : STD_LOGIC; + signal buf_depth_1_tsimcreated_xor_Q : STD_LOGIC; + signal buf_depth_1_RSTF : STD_LOGIC; + signal buf_depth_1_SETF : STD_LOGIC; + signal buf_depth_1_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal buf_depth_1_tsimcreated_prld_Q : STD_LOGIC; + signal buf_depth_1_CLKF : STD_LOGIC; + signal buf_depth_1_D1 : STD_LOGIC; + signal buf_depth_1_D2 : STD_LOGIC; + signal buf_depth_1_D2_PT_0 : STD_LOGIC; + signal buf_depth_1_D2_PT_1 : STD_LOGIC; + signal buf_depth_1_buf_depth_1_RSTF_UIM : STD_LOGIC; + signal SHIFT_CNT_0_Q : STD_LOGIC; + signal SHIFT_CNT_0_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal SHIFT_CNT_0_EXP : STD_LOGIC; + signal SHIFT_CNT_0_D : STD_LOGIC; + signal SHIFT_CNT_0_tsimcreated_xor_Q : STD_LOGIC; + signal SHIFT_CNT_0_RSTF : STD_LOGIC; + signal SHIFT_CNT_0_SETF : STD_LOGIC; + signal SHIFT_CNT_0_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal SHIFT_CNT_0_tsimcreated_prld_Q : STD_LOGIC; + signal SHIFT_CNT_0_CLKF : STD_LOGIC; + signal SHIFT_CNT_0_D1 : STD_LOGIC; + signal SHIFT_CNT_0_D2 : STD_LOGIC; + signal SHIFT_CNT_0_D2_PT_0 : STD_LOGIC; + signal EXP69_EXP : STD_LOGIC; + signal SHIFT_CNT_0_D2_PT_1 : STD_LOGIC; + signal count_0_Q : STD_LOGIC; + signal count_0_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal count_0_EXP : STD_LOGIC; + signal count_0_RSTF : STD_LOGIC; + signal count_0_SETF : STD_LOGIC; + signal count_0_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal count_0_tsimcreated_prld_Q : STD_LOGIC; + signal count_0_D : STD_LOGIC; + signal count_0_D1 : STD_LOGIC; + signal count_0_D2 : STD_LOGIC; + signal EXP67_EXP : STD_LOGIC; + signal count_0_D2_PT_0 : STD_LOGIC; + signal count_0_D2_PT_1 : STD_LOGIC; + signal count_0_D2_PT_2 : STD_LOGIC; + signal count_4_Q : STD_LOGIC; + signal count_4_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal count_4_EXP : STD_LOGIC; + signal count_4_D : STD_LOGIC; + signal count_4_tsimcreated_xor_Q : STD_LOGIC; + signal count_4_RSTF : STD_LOGIC; + signal count_4_SETF : STD_LOGIC; + signal count_4_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal count_4_tsimcreated_prld_Q : STD_LOGIC; + signal count_4_D1 : STD_LOGIC; + signal count_4_D2 : STD_LOGIC; + signal CLK_SCALE_0_EXP : STD_LOGIC; + signal count_4_D2_PT_0 : STD_LOGIC; + signal count_4_D2_PT_1 : STD_LOGIC; + signal count_4_D2_PT_2 : STD_LOGIC; + signal SHIFT_CNT_1_Q : STD_LOGIC; + signal SHIFT_CNT_1_D : STD_LOGIC; + signal SHIFT_CNT_1_tsimcreated_xor_Q : STD_LOGIC; + signal SHIFT_CNT_1_RSTF : STD_LOGIC; + signal SHIFT_CNT_1_SETF : STD_LOGIC; + signal SHIFT_CNT_1_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal SHIFT_CNT_1_tsimcreated_prld_Q : STD_LOGIC; + signal SHIFT_CNT_1_CLKF : STD_LOGIC; + signal SHIFT_CNT_1_D1 : STD_LOGIC; + signal SHIFT_CNT_1_D2 : STD_LOGIC; + signal SHIFT_CNT_1_D2_PT_0 : STD_LOGIC; + signal SHIFT_CNT_1_D2_PT_1 : STD_LOGIC; + signal SHIFT_CNT_2_EXP : STD_LOGIC; + signal SHIFT_CNT_1_D2_PT_2 : STD_LOGIC; + signal SHIFT_CNT_3_EXP : STD_LOGIC; + signal SHIFT_CNT_1_D2_PT_3 : STD_LOGIC; + signal SHIFT_CNT_2_Q : STD_LOGIC; + signal SHIFT_CNT_2_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal SHIFT_CNT_2_D : STD_LOGIC; + signal SHIFT_CNT_2_tsimcreated_xor_Q : STD_LOGIC; + signal SHIFT_CNT_2_RSTF : STD_LOGIC; + signal SHIFT_CNT_2_SETF : STD_LOGIC; + signal SHIFT_CNT_2_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal SHIFT_CNT_2_tsimcreated_prld_Q : STD_LOGIC; + signal SHIFT_CNT_2_CLKF : STD_LOGIC; + signal SHIFT_CNT_2_D1 : STD_LOGIC; + signal SHIFT_CNT_2_D2 : STD_LOGIC; + signal SHIFT_CNT_2_D2_PT_0 : STD_LOGIC; + signal BUF_IS_EMPTY_OBUF_EXP : STD_LOGIC; + signal SHIFT_CNT_2_D2_PT_1 : STD_LOGIC; + signal SHIFT_CNT_3_Q : STD_LOGIC; + signal SHIFT_CNT_3_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal SHIFT_CNT_3_D : STD_LOGIC; + signal SHIFT_CNT_3_tsimcreated_xor_Q : STD_LOGIC; + signal SHIFT_CNT_3_RSTF : STD_LOGIC; + signal SHIFT_CNT_3_SETF : STD_LOGIC; + signal SHIFT_CNT_3_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal SHIFT_CNT_3_tsimcreated_prld_Q : STD_LOGIC; + signal SHIFT_CNT_3_CLKF : STD_LOGIC; + signal SHIFT_CNT_3_D1 : STD_LOGIC; + signal SHIFT_CNT_3_D2 : STD_LOGIC; + signal buf_depth_0_buf_depth_0_RSTF_EXP : STD_LOGIC; + signal SHIFT_CNT_3_D2_PT_0 : STD_LOGIC; + signal SHIFT_CNT_3_D2_PT_1 : STD_LOGIC; + signal count_1_Q : STD_LOGIC; + signal count_1_D : STD_LOGIC; + signal count_1_tsimcreated_xor_Q : STD_LOGIC; + signal count_1_RSTF : STD_LOGIC; + signal count_1_SETF : STD_LOGIC; + signal count_1_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal count_1_tsimcreated_prld_Q : STD_LOGIC; + signal count_1_D1 : STD_LOGIC; + signal count_1_D2 : STD_LOGIC; + signal CLK_SCALE_1_EXP : STD_LOGIC; + signal count_1_D2_PT_0 : STD_LOGIC; + signal count_1_D2_PT_1 : STD_LOGIC; + signal count_1_D2_PT_2 : STD_LOGIC; + signal count_1_D2_PT_3 : STD_LOGIC; + signal count_2_Q : STD_LOGIC; + signal count_2_D : STD_LOGIC; + signal count_2_tsimcreated_xor_Q : STD_LOGIC; + signal count_2_RSTF : STD_LOGIC; + signal count_2_SETF : STD_LOGIC; + signal count_2_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal count_2_tsimcreated_prld_Q : STD_LOGIC; + signal count_2_D1 : STD_LOGIC; + signal count_2_D2 : STD_LOGIC; + signal count_2_D2_PT_0 : STD_LOGIC; + signal count_2_D2_PT_1 : STD_LOGIC; + signal count_2_D2_PT_2 : STD_LOGIC; + signal count_2_D2_PT_3 : STD_LOGIC; + signal count_3_Q : STD_LOGIC; + signal count_3_D : STD_LOGIC; + signal count_3_tsimcreated_xor_Q : STD_LOGIC; + signal count_3_RSTF : STD_LOGIC; + signal count_3_SETF : STD_LOGIC; + signal count_3_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal count_3_tsimcreated_prld_Q : STD_LOGIC; + signal count_3_D1 : STD_LOGIC; + signal count_3_D2 : STD_LOGIC; + signal count_3_D2_PT_0 : STD_LOGIC; + signal count_3_D2_PT_1 : STD_LOGIC; + signal count_3_D2_PT_2 : STD_LOGIC; + signal count_3_D2_PT_3 : STD_LOGIC; + signal SHIFT_CNT_4_Q : STD_LOGIC; + signal SHIFT_CNT_4_D : STD_LOGIC; + signal SHIFT_CNT_4_tsimcreated_xor_Q : STD_LOGIC; + signal SHIFT_CNT_4_RSTF : STD_LOGIC; + signal SHIFT_CNT_4_SETF : STD_LOGIC; + signal SHIFT_CNT_4_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal SHIFT_CNT_4_tsimcreated_prld_Q : STD_LOGIC; + signal SHIFT_CNT_4_CLKF : STD_LOGIC; + signal SHIFT_CNT_4_D1 : STD_LOGIC; + signal SHIFT_CNT_4_D2 : STD_LOGIC; + signal SHIFT_CNT_4_D2_PT_0 : STD_LOGIC; + signal SHIFT_CNT_4_D2_PT_1 : STD_LOGIC; + signal SHIFT_CNT_4_D2_PT_2 : STD_LOGIC; + signal count_5_Q : STD_LOGIC; + signal count_5_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal count_5_EXP : STD_LOGIC; + signal count_5_D : STD_LOGIC; + signal count_5_tsimcreated_xor_Q : STD_LOGIC; + signal count_5_RSTF : STD_LOGIC; + signal count_5_SETF : STD_LOGIC; + signal count_5_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal count_5_tsimcreated_prld_Q : STD_LOGIC; + signal count_5_D1 : STD_LOGIC; + signal count_5_D2 : STD_LOGIC; + signal CLK_SCALE_2_EXP : STD_LOGIC; + signal count_5_D2_PT_0 : STD_LOGIC; + signal count_5_D2_PT_1 : STD_LOGIC; + signal count_5_D2_PT_2 : STD_LOGIC; + signal writeBufId_0_Q : STD_LOGIC; + signal writeBufId_0_RSTF : STD_LOGIC; + signal writeBufId_0_tsimcreated_prld_Q : STD_LOGIC; + signal writeBufId_0_D : STD_LOGIC; + signal writeBufId_0_CLKF : STD_LOGIC; + signal writeBufId_0_CE : STD_LOGIC; + signal writeBufId_0_D1 : STD_LOGIC; + signal writeBufId_0_D2 : STD_LOGIC; + signal writeBufId_0_D2_PT_0 : STD_LOGIC; + signal writeBufId_0_D2_PT_1 : STD_LOGIC; + signal CLK_SCALE_0_Q : STD_LOGIC; + signal CLK_SCALE_0_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal CLK_SCALE_0_D : STD_LOGIC; + signal CLK_SCALE_0_D1 : STD_LOGIC; + signal CLK_SCALE_0_D2 : STD_LOGIC; + signal CLK_SCALE_0_D2_PT_0 : STD_LOGIC; + signal CLK_SCALE_0_D2_PT_1 : STD_LOGIC; + signal CLK_SCALE_0_D2_PT_2 : STD_LOGIC; + signal CLK_SCALE_0_D2_PT_3 : STD_LOGIC; + signal CLK_SCALE_0_EXP_PT_0 : STD_LOGIC; + signal CLK_SCALE_0_EXP_PT_1 : STD_LOGIC; + signal REG_0_0_Q : STD_LOGIC; + signal REG_0_0 : STD_LOGIC; + signal REG_0_0_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal REG_0_0_EXP : STD_LOGIC; + signal REG_0_0_D : STD_LOGIC; + signal REG_0_0_tsimcreated_xor_Q : STD_LOGIC; + signal REG_0_0_RSTF : STD_LOGIC; + signal REG_0_0_SETF : STD_LOGIC; + signal REG_0_0_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_0_0_tsimcreated_prld_Q : STD_LOGIC; + signal REG_0_0_CLKF : STD_LOGIC; + signal REG_0_0_D1 : STD_LOGIC; + signal REG_0_0_D2 : STD_LOGIC; + signal EXP22_EXP : STD_LOGIC; + signal REG_0_4 : STD_LOGIC; + signal REG_0_0_EXP_PT_0 : STD_LOGIC; + signal REG_0_0_EXP_PT_1 : STD_LOGIC; + signal REG_0_1_Q : STD_LOGIC; + signal REG_0_1 : STD_LOGIC; + signal REG_0_1_D : STD_LOGIC; + signal REG_0_1_tsimcreated_xor_Q : STD_LOGIC; + signal REG_0_1_RSTF : STD_LOGIC; + signal REG_0_1_SETF : STD_LOGIC; + signal REG_0_1_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_0_1_tsimcreated_prld_Q : STD_LOGIC; + signal REG_0_1_CLKF : STD_LOGIC; + signal REG_0_1_D1 : STD_LOGIC; + signal REG_0_1_D2 : STD_LOGIC; + signal EXP18_EXP : STD_LOGIC; + signal REG_0_1_D2_PT_0 : STD_LOGIC; + signal REG_0_1_D2_PT_1 : STD_LOGIC; + signal REG_0_1_D2_PT_2 : STD_LOGIC; + signal REG_0_10_Q : STD_LOGIC; + signal REG_0_10 : STD_LOGIC; + signal REG_0_10_D : STD_LOGIC; + signal REG_0_10_tsimcreated_xor_Q : STD_LOGIC; + signal REG_0_10_RSTF : STD_LOGIC; + signal REG_0_10_SETF : STD_LOGIC; + signal REG_0_10_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_0_10_tsimcreated_prld_Q : STD_LOGIC; + signal REG_0_10_CLKF : STD_LOGIC; + signal REG_0_10_D1 : STD_LOGIC; + signal REG_0_10_D2 : STD_LOGIC; + signal EXP65_EXP : STD_LOGIC; + signal REG_0_10_D2_PT_0 : STD_LOGIC; + signal REG_0_9 : STD_LOGIC; + signal REG_0_10_D2_PT_1 : STD_LOGIC; + signal REG_0_10_D2_PT_2 : STD_LOGIC; + signal REG_0_11_Q : STD_LOGIC; + signal REG_0_11 : STD_LOGIC; + signal REG_0_11_D : STD_LOGIC; + signal REG_0_11_tsimcreated_xor_Q : STD_LOGIC; + signal REG_0_11_RSTF : STD_LOGIC; + signal REG_0_11_SETF : STD_LOGIC; + signal REG_0_11_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_0_11_tsimcreated_prld_Q : STD_LOGIC; + signal REG_0_11_CLKF : STD_LOGIC; + signal REG_0_11_D1 : STD_LOGIC; + signal REG_0_11_D2 : STD_LOGIC; + signal SHIFT_EN_EXP : STD_LOGIC; + signal REG_0_11_D2_PT_0 : STD_LOGIC; + signal REG_0_11_D2_PT_1 : STD_LOGIC; + signal REG_0_11_D2_PT_2 : STD_LOGIC; + signal REG_0_12_Q : STD_LOGIC; + signal REG_0_12 : STD_LOGIC; + signal REG_0_12_D : STD_LOGIC; + signal REG_0_12_tsimcreated_xor_Q : STD_LOGIC; + signal REG_0_12_RSTF : STD_LOGIC; + signal REG_0_12_SETF : STD_LOGIC; + signal REG_0_12_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_0_12_tsimcreated_prld_Q : STD_LOGIC; + signal REG_0_12_CLKF : STD_LOGIC; + signal REG_0_12_D1 : STD_LOGIC; + signal REG_0_12_D2 : STD_LOGIC; + signal REG_0_13_EXP : STD_LOGIC; + signal REG_0_12_D2_PT_0 : STD_LOGIC; + signal REG_0_12_D2_PT_1 : STD_LOGIC; + signal REG_0_12_D2_PT_2 : STD_LOGIC; + signal REG_0_13_Q : STD_LOGIC; + signal REG_0_13 : STD_LOGIC; + signal REG_0_13_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal REG_0_13_D : STD_LOGIC; + signal REG_0_13_tsimcreated_xor_Q : STD_LOGIC; + signal REG_0_13_RSTF : STD_LOGIC; + signal REG_0_13_SETF : STD_LOGIC; + signal REG_0_13_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_0_13_tsimcreated_prld_Q : STD_LOGIC; + signal REG_0_13_CLKF : STD_LOGIC; + signal REG_0_13_D1 : STD_LOGIC; + signal REG_0_13_D2 : STD_LOGIC; + signal CCLK_OBUF_EXP : STD_LOGIC; + signal REG_0_13_EXP_PT_0 : STD_LOGIC; + signal REG_0_13_EXP_PT_1 : STD_LOGIC; + signal REG_0_14_Q : STD_LOGIC; + signal REG_0_14 : STD_LOGIC; + signal REG_0_14_D : STD_LOGIC; + signal REG_0_14_tsimcreated_xor_Q : STD_LOGIC; + signal REG_0_14_RSTF : STD_LOGIC; + signal REG_0_14_SETF : STD_LOGIC; + signal REG_0_14_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_0_14_tsimcreated_prld_Q : STD_LOGIC; + signal REG_0_14_CLKF : STD_LOGIC; + signal REG_0_14_D1 : STD_LOGIC; + signal REG_0_14_D2 : STD_LOGIC; + signal EXP66_EXP : STD_LOGIC; + signal REG_0_14_D2_PT_0 : STD_LOGIC; + signal REG_0_14_D2_PT_1 : STD_LOGIC; + signal REG_0_14_D2_PT_2 : STD_LOGIC; + signal REG_0_15_Q : STD_LOGIC; + signal REG_0_15 : STD_LOGIC; + signal REG_0_15_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal REG_0_15_EXP : STD_LOGIC; + signal REG_0_15_D : STD_LOGIC; + signal REG_0_15_tsimcreated_xor_Q : STD_LOGIC; + signal REG_0_15_RSTF : STD_LOGIC; + signal REG_0_15_SETF : STD_LOGIC; + signal REG_0_15_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_0_15_tsimcreated_prld_Q : STD_LOGIC; + signal REG_0_15_CLKF : STD_LOGIC; + signal REG_0_15_D1 : STD_LOGIC; + signal REG_0_15_D2 : STD_LOGIC; + signal EXP30_EXP : STD_LOGIC; + signal REG_0_15_D2_PT_0 : STD_LOGIC; + signal REG_0_15_D2_PT_1 : STD_LOGIC; + signal REG_0_16 : STD_LOGIC; + signal REG_0_16_Q : STD_LOGIC; + signal REG_0_16_D : STD_LOGIC; + signal REG_0_16_tsimcreated_xor_Q : STD_LOGIC; + signal REG_0_16_RSTF : STD_LOGIC; + signal REG_0_16_SETF : STD_LOGIC; + signal REG_0_16_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_0_16_tsimcreated_prld_Q : STD_LOGIC; + signal REG_0_16_CLKF : STD_LOGIC; + signal REG_0_16_D1 : STD_LOGIC; + signal REG_0_16_D2 : STD_LOGIC; + signal REG_0_16_D2_PT_0 : STD_LOGIC; + signal REG_0_17_EXP : STD_LOGIC; + signal REG_0_16_D2_PT_1 : STD_LOGIC; + signal REG_0_16_D2_PT_2 : STD_LOGIC; + signal REG_0_16_D2_PT_3 : STD_LOGIC; + signal REG_0_17_Q : STD_LOGIC; + signal REG_0_17 : STD_LOGIC; + signal REG_0_17_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal REG_0_17_D : STD_LOGIC; + signal REG_0_17_tsimcreated_xor_Q : STD_LOGIC; + signal REG_0_17_RSTF : STD_LOGIC; + signal REG_0_17_SETF : STD_LOGIC; + signal REG_0_17_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_0_17_tsimcreated_prld_Q : STD_LOGIC; + signal REG_0_17_CLKF : STD_LOGIC; + signal REG_0_17_D1 : STD_LOGIC; + signal REG_0_17_D2 : STD_LOGIC; + signal EXP29_EXP : STD_LOGIC; + signal REG_0_17_D2_PT_0 : STD_LOGIC; + signal REG_0_17_D2_PT_1 : STD_LOGIC; + signal REG_0_18_Q : STD_LOGIC; + signal REG_0_18 : STD_LOGIC; + signal REG_0_18_D : STD_LOGIC; + signal REG_0_18_tsimcreated_xor_Q : STD_LOGIC; + signal REG_0_18_RSTF : STD_LOGIC; + signal REG_0_18_SETF : STD_LOGIC; + signal REG_0_18_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_0_18_tsimcreated_prld_Q : STD_LOGIC; + signal REG_0_18_CLKF : STD_LOGIC; + signal REG_0_18_D1 : STD_LOGIC; + signal REG_0_18_D2 : STD_LOGIC; + signal EXP32_EXP : STD_LOGIC; + signal REG_0_18_D2_PT_0 : STD_LOGIC; + signal REG_0_18_D2_PT_1 : STD_LOGIC; + signal REG_0_18_D2_PT_2 : STD_LOGIC; + signal REG_0_19_Q : STD_LOGIC; + signal REG_0_19 : STD_LOGIC; + signal REG_0_19_D : STD_LOGIC; + signal REG_0_19_tsimcreated_xor_Q : STD_LOGIC; + signal REG_0_19_RSTF : STD_LOGIC; + signal REG_0_19_SETF : STD_LOGIC; + signal REG_0_19_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_0_19_tsimcreated_prld_Q : STD_LOGIC; + signal REG_0_19_CLKF : STD_LOGIC; + signal REG_0_19_D1 : STD_LOGIC; + signal REG_0_19_D2 : STD_LOGIC; + signal state_0_EXP : STD_LOGIC; + signal REG_0_19_D2_PT_0 : STD_LOGIC; + signal REG_0_19_D2_PT_1 : STD_LOGIC; + signal REG_0_19_D2_PT_2 : STD_LOGIC; + signal REG_0_2_Q : STD_LOGIC; + signal REG_0_2 : STD_LOGIC; + signal REG_0_2_D : STD_LOGIC; + signal REG_0_2_tsimcreated_xor_Q : STD_LOGIC; + signal REG_0_2_RSTF : STD_LOGIC; + signal REG_0_2_SETF : STD_LOGIC; + signal REG_0_2_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_0_2_tsimcreated_prld_Q : STD_LOGIC; + signal REG_0_2_CLKF : STD_LOGIC; + signal REG_0_2_D1 : STD_LOGIC; + signal REG_0_2_D2 : STD_LOGIC; + signal REG_0_3_EXP : STD_LOGIC; + signal REG_0_2_D2_PT_0 : STD_LOGIC; + signal REG_0_2_D2_PT_1 : STD_LOGIC; + signal REG_0_2_D2_PT_2 : STD_LOGIC; + signal REG_0_20_Q : STD_LOGIC; + signal REG_0_20 : STD_LOGIC; + signal REG_0_20_D : STD_LOGIC; + signal REG_0_20_tsimcreated_xor_Q : STD_LOGIC; + signal REG_0_20_RSTF : STD_LOGIC; + signal REG_0_20_SETF : STD_LOGIC; + signal REG_0_20_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_0_20_tsimcreated_prld_Q : STD_LOGIC; + signal REG_0_20_CLKF : STD_LOGIC; + signal REG_0_20_D1 : STD_LOGIC; + signal REG_0_20_D2 : STD_LOGIC; + signal EXP31_EXP : STD_LOGIC; + signal REG_0_20_D2_PT_0 : STD_LOGIC; + signal REG_0_20_D2_PT_1 : STD_LOGIC; + signal REG_0_20_D2_PT_2 : STD_LOGIC; + signal REG_0_21_Q : STD_LOGIC; + signal REG_0_21 : STD_LOGIC; + signal REG_0_21_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal REG_0_21_EXP : STD_LOGIC; + signal REG_0_21_D : STD_LOGIC; + signal REG_0_21_tsimcreated_xor_Q : STD_LOGIC; + signal REG_0_21_RSTF : STD_LOGIC; + signal REG_0_21_SETF : STD_LOGIC; + signal REG_0_21_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_0_21_tsimcreated_prld_Q : STD_LOGIC; + signal REG_0_21_CLKF : STD_LOGIC; + signal REG_0_21_D1 : STD_LOGIC; + signal REG_0_21_D2 : STD_LOGIC; + signal EXP34_EXP : STD_LOGIC; + signal REG_0_21_D2_PT_0 : STD_LOGIC; + signal REG_0_21_D2_PT_1 : STD_LOGIC; + signal REG_0_22 : STD_LOGIC; + signal REG_0_22_Q : STD_LOGIC; + signal REG_0_22_D : STD_LOGIC; + signal REG_0_22_tsimcreated_xor_Q : STD_LOGIC; + signal REG_0_22_RSTF : STD_LOGIC; + signal REG_0_22_SETF : STD_LOGIC; + signal REG_0_22_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_0_22_tsimcreated_prld_Q : STD_LOGIC; + signal REG_0_22_CLKF : STD_LOGIC; + signal REG_0_22_D1 : STD_LOGIC; + signal REG_0_22_D2 : STD_LOGIC; + signal REG_0_22_D2_PT_0 : STD_LOGIC; + signal REG_0_23_EXP : STD_LOGIC; + signal REG_0_22_D2_PT_1 : STD_LOGIC; + signal REG_0_22_D2_PT_2 : STD_LOGIC; + signal REG_0_22_D2_PT_3 : STD_LOGIC; + signal REG_0_23_Q : STD_LOGIC; + signal REG_0_23 : STD_LOGIC; + signal REG_0_23_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal REG_0_23_D : STD_LOGIC; + signal REG_0_23_tsimcreated_xor_Q : STD_LOGIC; + signal REG_0_23_RSTF : STD_LOGIC; + signal REG_0_23_SETF : STD_LOGIC; + signal REG_0_23_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_0_23_tsimcreated_prld_Q : STD_LOGIC; + signal REG_0_23_CLKF : STD_LOGIC; + signal REG_0_23_D1 : STD_LOGIC; + signal REG_0_23_D2 : STD_LOGIC; + signal EXP33_EXP : STD_LOGIC; + signal REG_0_23_D2_PT_0 : STD_LOGIC; + signal REG_0_23_D2_PT_1 : STD_LOGIC; + signal REG_0_24_Q : STD_LOGIC; + signal REG_0_24 : STD_LOGIC; + signal REG_0_24_D : STD_LOGIC; + signal REG_0_24_tsimcreated_xor_Q : STD_LOGIC; + signal REG_0_24_RSTF : STD_LOGIC; + signal REG_0_24_SETF : STD_LOGIC; + signal REG_0_24_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_0_24_tsimcreated_prld_Q : STD_LOGIC; + signal REG_0_24_CLKF : STD_LOGIC; + signal REG_0_24_D1 : STD_LOGIC; + signal REG_0_24_D2 : STD_LOGIC; + signal EXP36_EXP : STD_LOGIC; + signal REG_0_24_D2_PT_0 : STD_LOGIC; + signal REG_0_24_D2_PT_1 : STD_LOGIC; + signal REG_0_24_D2_PT_2 : STD_LOGIC; + signal REG_0_25_Q : STD_LOGIC; + signal REG_0_25 : STD_LOGIC; + signal REG_0_25_D : STD_LOGIC; + signal REG_0_25_tsimcreated_xor_Q : STD_LOGIC; + signal REG_0_25_RSTF : STD_LOGIC; + signal REG_0_25_SETF : STD_LOGIC; + signal REG_0_25_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_0_25_tsimcreated_prld_Q : STD_LOGIC; + signal REG_0_25_CLKF : STD_LOGIC; + signal REG_0_25_D1 : STD_LOGIC; + signal REG_0_25_D2 : STD_LOGIC; + signal state_1_EXP : STD_LOGIC; + signal REG_0_25_D2_PT_0 : STD_LOGIC; + signal REG_0_25_D2_PT_1 : STD_LOGIC; + signal REG_0_25_D2_PT_2 : STD_LOGIC; + signal REG_0_26_Q : STD_LOGIC; + signal REG_0_26 : STD_LOGIC; + signal REG_0_26_D : STD_LOGIC; + signal REG_0_26_tsimcreated_xor_Q : STD_LOGIC; + signal REG_0_26_RSTF : STD_LOGIC; + signal REG_0_26_SETF : STD_LOGIC; + signal REG_0_26_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_0_26_tsimcreated_prld_Q : STD_LOGIC; + signal REG_0_26_CLKF : STD_LOGIC; + signal REG_0_26_D1 : STD_LOGIC; + signal REG_0_26_D2 : STD_LOGIC; + signal EXP35_EXP : STD_LOGIC; + signal REG_0_26_D2_PT_0 : STD_LOGIC; + signal REG_0_26_D2_PT_1 : STD_LOGIC; + signal REG_0_26_D2_PT_2 : STD_LOGIC; + signal REG_0_27_Q : STD_LOGIC; + signal REG_0_27 : STD_LOGIC; + signal REG_0_27_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal REG_0_27_EXP : STD_LOGIC; + signal REG_0_27_D : STD_LOGIC; + signal REG_0_27_tsimcreated_xor_Q : STD_LOGIC; + signal REG_0_27_RSTF : STD_LOGIC; + signal REG_0_27_SETF : STD_LOGIC; + signal REG_0_27_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_0_27_tsimcreated_prld_Q : STD_LOGIC; + signal REG_0_27_CLKF : STD_LOGIC; + signal REG_0_27_D1 : STD_LOGIC; + signal REG_0_27_D2 : STD_LOGIC; + signal EXP39_EXP : STD_LOGIC; + signal REG_0_27_D2_PT_0 : STD_LOGIC; + signal REG_0_27_D2_PT_1 : STD_LOGIC; + signal REG_1_23 : STD_LOGIC; + signal REG_0_28_Q : STD_LOGIC; + signal REG_0_28 : STD_LOGIC; + signal REG_0_28_D : STD_LOGIC; + signal REG_0_28_tsimcreated_xor_Q : STD_LOGIC; + signal REG_0_28_RSTF : STD_LOGIC; + signal REG_0_28_SETF : STD_LOGIC; + signal REG_0_28_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_0_28_tsimcreated_prld_Q : STD_LOGIC; + signal REG_0_28_CLKF : STD_LOGIC; + signal REG_0_28_D1 : STD_LOGIC; + signal REG_0_28_D2 : STD_LOGIC; + signal EXP26_EXP : STD_LOGIC; + signal REG_0_28_D2_PT_0 : STD_LOGIC; + signal REG_0_28_D2_PT_1 : STD_LOGIC; + signal REG_0_28_D2_PT_2 : STD_LOGIC; + signal REG_0_29_Q : STD_LOGIC; + signal REG_0_29 : STD_LOGIC; + signal REG_0_29_D : STD_LOGIC; + signal REG_0_29_tsimcreated_xor_Q : STD_LOGIC; + signal REG_0_29_RSTF : STD_LOGIC; + signal REG_0_29_SETF : STD_LOGIC; + signal REG_0_29_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_0_29_tsimcreated_prld_Q : STD_LOGIC; + signal REG_0_29_CLKF : STD_LOGIC; + signal REG_0_29_D1 : STD_LOGIC; + signal REG_0_29_D2 : STD_LOGIC; + signal REG_0_30_EXP : STD_LOGIC; + signal REG_0_29_D2_PT_0 : STD_LOGIC; + signal REG_0_29_D2_PT_1 : STD_LOGIC; + signal REG_0_29_D2_PT_2 : STD_LOGIC; + signal REG_0_3_Q : STD_LOGIC; + signal REG_0_3 : STD_LOGIC; + signal REG_0_3_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal REG_0_3_D : STD_LOGIC; + signal REG_0_3_tsimcreated_xor_Q : STD_LOGIC; + signal REG_0_3_RSTF : STD_LOGIC; + signal REG_0_3_SETF : STD_LOGIC; + signal REG_0_3_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_0_3_tsimcreated_prld_Q : STD_LOGIC; + signal REG_0_3_CLKF : STD_LOGIC; + signal REG_0_3_D1 : STD_LOGIC; + signal REG_0_3_D2 : STD_LOGIC; + signal EXP23_EXP : STD_LOGIC; + signal REG_0_3_EXP_PT_0 : STD_LOGIC; + signal REG_0_3_EXP_PT_1 : STD_LOGIC; + signal REG_0_30_Q : STD_LOGIC; + signal REG_0_30 : STD_LOGIC; + signal REG_0_30_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal REG_0_30_D : STD_LOGIC; + signal REG_0_30_tsimcreated_xor_Q : STD_LOGIC; + signal REG_0_30_RSTF : STD_LOGIC; + signal REG_0_30_SETF : STD_LOGIC; + signal REG_0_30_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_0_30_tsimcreated_prld_Q : STD_LOGIC; + signal REG_0_30_CLKF : STD_LOGIC; + signal REG_0_30_D1 : STD_LOGIC; + signal REG_0_30_D2 : STD_LOGIC; + signal EXP25_EXP : STD_LOGIC; + signal REG_0_30_EXP_PT_0 : STD_LOGIC; + signal REG_0_30_EXP_PT_1 : STD_LOGIC; + signal REG_0_31_Q : STD_LOGIC; + signal REG_0_31 : STD_LOGIC; + signal REG_0_31_D : STD_LOGIC; + signal REG_0_31_tsimcreated_xor_Q : STD_LOGIC; + signal REG_0_31_RSTF : STD_LOGIC; + signal REG_0_31_SETF : STD_LOGIC; + signal REG_0_31_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_0_31_tsimcreated_prld_Q : STD_LOGIC; + signal REG_0_31_CLKF : STD_LOGIC; + signal REG_0_31_D1 : STD_LOGIC; + signal REG_0_31_D2 : STD_LOGIC; + signal EXP24_EXP : STD_LOGIC; + signal REG_0_31_D2_PT_0 : STD_LOGIC; + signal REG_0_31_D2_PT_1 : STD_LOGIC; + signal REG_0_31_D2_PT_2 : STD_LOGIC; + signal REG_0_4_Q : STD_LOGIC; + signal REG_0_4_D : STD_LOGIC; + signal REG_0_4_tsimcreated_xor_Q : STD_LOGIC; + signal REG_0_4_RSTF : STD_LOGIC; + signal REG_0_4_SETF : STD_LOGIC; + signal REG_0_4_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_0_4_tsimcreated_prld_Q : STD_LOGIC; + signal REG_0_4_CLKF : STD_LOGIC; + signal REG_0_4_D1 : STD_LOGIC; + signal REG_0_4_D2 : STD_LOGIC; + signal REG_0_4_D2_PT_0 : STD_LOGIC; + signal REG_0_4_D2_PT_1 : STD_LOGIC; + signal REG_0_4_D2_PT_2 : STD_LOGIC; + signal REG_0_5_Q : STD_LOGIC; + signal REG_0_5 : STD_LOGIC; + signal REG_0_5_D : STD_LOGIC; + signal REG_0_5_tsimcreated_xor_Q : STD_LOGIC; + signal REG_0_5_RSTF : STD_LOGIC; + signal REG_0_5_SETF : STD_LOGIC; + signal REG_0_5_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_0_5_tsimcreated_prld_Q : STD_LOGIC; + signal REG_0_5_CLKF : STD_LOGIC; + signal REG_0_5_D1 : STD_LOGIC; + signal REG_0_5_D2 : STD_LOGIC; + signal EXP19_EXP : STD_LOGIC; + signal REG_0_5_D2_PT_0 : STD_LOGIC; + signal REG_0_5_D2_PT_1 : STD_LOGIC; + signal REG_0_5_D2_PT_2 : STD_LOGIC; + signal REG_0_6_Q : STD_LOGIC; + signal REG_0_6 : STD_LOGIC; + signal REG_0_6_D : STD_LOGIC; + signal REG_0_6_tsimcreated_xor_Q : STD_LOGIC; + signal REG_0_6_RSTF : STD_LOGIC; + signal REG_0_6_SETF : STD_LOGIC; + signal REG_0_6_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_0_6_tsimcreated_prld_Q : STD_LOGIC; + signal REG_0_6_CLKF : STD_LOGIC; + signal REG_0_6_D1 : STD_LOGIC; + signal REG_0_6_D2 : STD_LOGIC; + signal EXP20_EXP : STD_LOGIC; + signal REG_0_6_D2_PT_0 : STD_LOGIC; + signal EXP21_EXP : STD_LOGIC; + signal REG_0_6_D2_PT_1 : STD_LOGIC; + signal REG_0_6_D2_PT_2 : STD_LOGIC; + signal REG_0_6_D2_PT_3 : STD_LOGIC; + signal REG_0_7_Q : STD_LOGIC; + signal REG_0_7 : STD_LOGIC; + signal REG_0_7_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal REG_0_7_EXP : STD_LOGIC; + signal REG_0_7_D : STD_LOGIC; + signal REG_0_7_tsimcreated_xor_Q : STD_LOGIC; + signal REG_0_7_RSTF : STD_LOGIC; + signal REG_0_7_SETF : STD_LOGIC; + signal REG_0_7_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_0_7_tsimcreated_prld_Q : STD_LOGIC; + signal REG_0_7_CLKF : STD_LOGIC; + signal REG_0_7_D1 : STD_LOGIC; + signal REG_0_7_D2 : STD_LOGIC; + signal EXP46_EXP : STD_LOGIC; + signal REG_0_7_D2_PT_0 : STD_LOGIC; + signal REG_0_7_D2_PT_1 : STD_LOGIC; + signal REG_0_8 : STD_LOGIC; + signal REG_0_8_Q : STD_LOGIC; + signal REG_0_8_D : STD_LOGIC; + signal REG_0_8_tsimcreated_xor_Q : STD_LOGIC; + signal REG_0_8_RSTF : STD_LOGIC; + signal REG_0_8_SETF : STD_LOGIC; + signal REG_0_8_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_0_8_tsimcreated_prld_Q : STD_LOGIC; + signal REG_0_8_CLKF : STD_LOGIC; + signal REG_0_8_D1 : STD_LOGIC; + signal REG_0_8_D2 : STD_LOGIC; + signal REG_0_8_D2_PT_0 : STD_LOGIC; + signal REG_0_9_EXP : STD_LOGIC; + signal REG_0_8_D2_PT_1 : STD_LOGIC; + signal REG_0_8_D2_PT_2 : STD_LOGIC; + signal REG_0_8_D2_PT_3 : STD_LOGIC; + signal REG_0_9_Q : STD_LOGIC; + signal REG_0_9_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal REG_0_9_D : STD_LOGIC; + signal REG_0_9_tsimcreated_xor_Q : STD_LOGIC; + signal REG_0_9_RSTF : STD_LOGIC; + signal REG_0_9_SETF : STD_LOGIC; + signal REG_0_9_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_0_9_tsimcreated_prld_Q : STD_LOGIC; + signal REG_0_9_CLKF : STD_LOGIC; + signal REG_0_9_D1 : STD_LOGIC; + signal REG_0_9_D2 : STD_LOGIC; + signal EXP45_EXP : STD_LOGIC; + signal REG_0_9_D2_PT_0 : STD_LOGIC; + signal REG_0_9_D2_PT_1 : STD_LOGIC; + signal REG_1_0_Q : STD_LOGIC; + signal REG_1_0 : STD_LOGIC; + signal REG_1_0_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal REG_1_0_EXP : STD_LOGIC; + signal REG_1_0_D : STD_LOGIC; + signal REG_1_0_tsimcreated_xor_Q : STD_LOGIC; + signal REG_1_0_RSTF : STD_LOGIC; + signal REG_1_0_SETF : STD_LOGIC; + signal REG_1_0_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_1_0_tsimcreated_prld_Q : STD_LOGIC; + signal REG_1_0_CLKF : STD_LOGIC; + signal REG_1_0_D1 : STD_LOGIC; + signal REG_1_0_D2 : STD_LOGIC; + signal EXP52_EXP : STD_LOGIC; + signal REG_1_4 : STD_LOGIC; + signal REG_1_0_EXP_PT_0 : STD_LOGIC; + signal REG_1_0_EXP_PT_1 : STD_LOGIC; + signal REG_1_1_Q : STD_LOGIC; + signal REG_1_1 : STD_LOGIC; + signal REG_1_1_D : STD_LOGIC; + signal REG_1_1_tsimcreated_xor_Q : STD_LOGIC; + signal REG_1_1_RSTF : STD_LOGIC; + signal REG_1_1_SETF : STD_LOGIC; + signal REG_1_1_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_1_1_tsimcreated_prld_Q : STD_LOGIC; + signal REG_1_1_CLKF : STD_LOGIC; + signal REG_1_1_D1 : STD_LOGIC; + signal REG_1_1_D2 : STD_LOGIC; + signal EXP48_EXP : STD_LOGIC; + signal REG_1_1_D2_PT_0 : STD_LOGIC; + signal REG_1_1_D2_PT_1 : STD_LOGIC; + signal REG_1_1_D2_PT_2 : STD_LOGIC; + signal REG_1_10_Q : STD_LOGIC; + signal REG_1_10 : STD_LOGIC; + signal REG_1_10_D : STD_LOGIC; + signal REG_1_10_tsimcreated_xor_Q : STD_LOGIC; + signal REG_1_10_RSTF : STD_LOGIC; + signal REG_1_10_SETF : STD_LOGIC; + signal REG_1_10_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_1_10_tsimcreated_prld_Q : STD_LOGIC; + signal REG_1_10_CLKF : STD_LOGIC; + signal REG_1_10_D1 : STD_LOGIC; + signal REG_1_10_D2 : STD_LOGIC; + signal EXP43_EXP : STD_LOGIC; + signal REG_1_10_D2_PT_0 : STD_LOGIC; + signal REG_1_9 : STD_LOGIC; + signal REG_1_10_D2_PT_1 : STD_LOGIC; + signal REG_1_10_D2_PT_2 : STD_LOGIC; + signal REG_1_11_Q : STD_LOGIC; + signal REG_1_11 : STD_LOGIC; + signal REG_1_11_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal REG_1_11_EXP : STD_LOGIC; + signal REG_1_11_D : STD_LOGIC; + signal REG_1_11_tsimcreated_xor_Q : STD_LOGIC; + signal REG_1_11_RSTF : STD_LOGIC; + signal REG_1_11_SETF : STD_LOGIC; + signal REG_1_11_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_1_11_tsimcreated_prld_Q : STD_LOGIC; + signal REG_1_11_CLKF : STD_LOGIC; + signal REG_1_11_D1 : STD_LOGIC; + signal REG_1_11_D2 : STD_LOGIC; + signal EXP56_EXP : STD_LOGIC; + signal REG_1_11_D2_PT_0 : STD_LOGIC; + signal REG_1_11_D2_PT_1 : STD_LOGIC; + signal REG_1_12 : STD_LOGIC; + signal REG_1_12_Q : STD_LOGIC; + signal REG_1_12_D : STD_LOGIC; + signal REG_1_12_tsimcreated_xor_Q : STD_LOGIC; + signal REG_1_12_RSTF : STD_LOGIC; + signal REG_1_12_SETF : STD_LOGIC; + signal REG_1_12_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_1_12_tsimcreated_prld_Q : STD_LOGIC; + signal REG_1_12_CLKF : STD_LOGIC; + signal REG_1_12_D1 : STD_LOGIC; + signal REG_1_12_D2 : STD_LOGIC; + signal REG_1_12_D2_PT_0 : STD_LOGIC; + signal REG_1_13_EXP : STD_LOGIC; + signal REG_1_12_D2_PT_1 : STD_LOGIC; + signal REG_1_12_D2_PT_2 : STD_LOGIC; + signal REG_1_12_D2_PT_3 : STD_LOGIC; + signal REG_1_13_Q : STD_LOGIC; + signal REG_1_13 : STD_LOGIC; + signal REG_1_13_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal REG_1_13_D : STD_LOGIC; + signal REG_1_13_tsimcreated_xor_Q : STD_LOGIC; + signal REG_1_13_RSTF : STD_LOGIC; + signal REG_1_13_SETF : STD_LOGIC; + signal REG_1_13_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_1_13_tsimcreated_prld_Q : STD_LOGIC; + signal REG_1_13_CLKF : STD_LOGIC; + signal REG_1_13_D1 : STD_LOGIC; + signal REG_1_13_D2 : STD_LOGIC; + signal EXP55_EXP : STD_LOGIC; + signal REG_1_13_D2_PT_0 : STD_LOGIC; + signal REG_1_13_D2_PT_1 : STD_LOGIC; + signal REG_1_14_Q : STD_LOGIC; + signal REG_1_14 : STD_LOGIC; + signal REG_1_14_D : STD_LOGIC; + signal REG_1_14_tsimcreated_xor_Q : STD_LOGIC; + signal REG_1_14_RSTF : STD_LOGIC; + signal REG_1_14_SETF : STD_LOGIC; + signal REG_1_14_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_1_14_tsimcreated_prld_Q : STD_LOGIC; + signal REG_1_14_CLKF : STD_LOGIC; + signal REG_1_14_D1 : STD_LOGIC; + signal REG_1_14_D2 : STD_LOGIC; + signal EXP58_EXP : STD_LOGIC; + signal REG_1_14_D2_PT_0 : STD_LOGIC; + signal REG_1_14_D2_PT_1 : STD_LOGIC; + signal REG_1_14_D2_PT_2 : STD_LOGIC; + signal REG_1_15_Q : STD_LOGIC; + signal REG_1_15 : STD_LOGIC; + signal REG_1_15_D : STD_LOGIC; + signal REG_1_15_tsimcreated_xor_Q : STD_LOGIC; + signal REG_1_15_RSTF : STD_LOGIC; + signal REG_1_15_SETF : STD_LOGIC; + signal REG_1_15_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_1_15_tsimcreated_prld_Q : STD_LOGIC; + signal REG_1_15_CLKF : STD_LOGIC; + signal REG_1_15_D1 : STD_LOGIC; + signal REG_1_15_D2 : STD_LOGIC; + signal EXP57_EXP : STD_LOGIC; + signal REG_1_15_D2_PT_0 : STD_LOGIC; + signal REG_1_15_D2_PT_1 : STD_LOGIC; + signal REG_1_15_D2_PT_2 : STD_LOGIC; + signal REG_1_16_Q : STD_LOGIC; + signal REG_1_16 : STD_LOGIC; + signal REG_1_16_D : STD_LOGIC; + signal REG_1_16_tsimcreated_xor_Q : STD_LOGIC; + signal REG_1_16_RSTF : STD_LOGIC; + signal REG_1_16_SETF : STD_LOGIC; + signal REG_1_16_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_1_16_tsimcreated_prld_Q : STD_LOGIC; + signal REG_1_16_CLKF : STD_LOGIC; + signal REG_1_16_D1 : STD_LOGIC; + signal REG_1_16_D2 : STD_LOGIC; + signal EXP54_EXP : STD_LOGIC; + signal REG_1_16_D2_PT_0 : STD_LOGIC; + signal REG_1_16_D2_PT_1 : STD_LOGIC; + signal REG_1_16_D2_PT_2 : STD_LOGIC; + signal REG_1_17_Q : STD_LOGIC; + signal REG_1_17 : STD_LOGIC; + signal REG_1_17_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal REG_1_17_EXP : STD_LOGIC; + signal REG_1_17_D : STD_LOGIC; + signal REG_1_17_tsimcreated_xor_Q : STD_LOGIC; + signal REG_1_17_RSTF : STD_LOGIC; + signal REG_1_17_SETF : STD_LOGIC; + signal REG_1_17_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_1_17_tsimcreated_prld_Q : STD_LOGIC; + signal REG_1_17_CLKF : STD_LOGIC; + signal REG_1_17_D1 : STD_LOGIC; + signal REG_1_17_D2 : STD_LOGIC; + signal EXP61_EXP : STD_LOGIC; + signal REG_1_17_D2_PT_0 : STD_LOGIC; + signal REG_1_17_D2_PT_1 : STD_LOGIC; + signal REG_1_18 : STD_LOGIC; + signal REG_1_18_Q : STD_LOGIC; + signal REG_1_18_D : STD_LOGIC; + signal REG_1_18_tsimcreated_xor_Q : STD_LOGIC; + signal REG_1_18_RSTF : STD_LOGIC; + signal REG_1_18_SETF : STD_LOGIC; + signal REG_1_18_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_1_18_tsimcreated_prld_Q : STD_LOGIC; + signal REG_1_18_CLKF : STD_LOGIC; + signal REG_1_18_D1 : STD_LOGIC; + signal REG_1_18_D2 : STD_LOGIC; + signal REG_1_18_D2_PT_0 : STD_LOGIC; + signal REG_1_19_EXP : STD_LOGIC; + signal REG_1_18_D2_PT_1 : STD_LOGIC; + signal REG_1_18_D2_PT_2 : STD_LOGIC; + signal REG_1_18_D2_PT_3 : STD_LOGIC; + signal REG_1_19_Q : STD_LOGIC; + signal REG_1_19 : STD_LOGIC; + signal REG_1_19_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal REG_1_19_D : STD_LOGIC; + signal REG_1_19_tsimcreated_xor_Q : STD_LOGIC; + signal REG_1_19_RSTF : STD_LOGIC; + signal REG_1_19_SETF : STD_LOGIC; + signal REG_1_19_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_1_19_tsimcreated_prld_Q : STD_LOGIC; + signal REG_1_19_CLKF : STD_LOGIC; + signal REG_1_19_D1 : STD_LOGIC; + signal REG_1_19_D2 : STD_LOGIC; + signal EXP60_EXP : STD_LOGIC; + signal REG_1_19_D2_PT_0 : STD_LOGIC; + signal REG_1_19_D2_PT_1 : STD_LOGIC; + signal REG_1_2_Q : STD_LOGIC; + signal REG_1_2 : STD_LOGIC; + signal REG_1_2_D : STD_LOGIC; + signal REG_1_2_tsimcreated_xor_Q : STD_LOGIC; + signal REG_1_2_RSTF : STD_LOGIC; + signal REG_1_2_SETF : STD_LOGIC; + signal REG_1_2_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_1_2_tsimcreated_prld_Q : STD_LOGIC; + signal REG_1_2_CLKF : STD_LOGIC; + signal REG_1_2_D1 : STD_LOGIC; + signal REG_1_2_D2 : STD_LOGIC; + signal REG_1_3_EXP : STD_LOGIC; + signal REG_1_2_D2_PT_0 : STD_LOGIC; + signal REG_1_2_D2_PT_1 : STD_LOGIC; + signal REG_1_2_D2_PT_2 : STD_LOGIC; + signal REG_1_20_Q : STD_LOGIC; + signal REG_1_20 : STD_LOGIC; + signal REG_1_20_D : STD_LOGIC; + signal REG_1_20_tsimcreated_xor_Q : STD_LOGIC; + signal REG_1_20_RSTF : STD_LOGIC; + signal REG_1_20_SETF : STD_LOGIC; + signal REG_1_20_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_1_20_tsimcreated_prld_Q : STD_LOGIC; + signal REG_1_20_CLKF : STD_LOGIC; + signal REG_1_20_D1 : STD_LOGIC; + signal REG_1_20_D2 : STD_LOGIC; + signal EXP63_EXP : STD_LOGIC; + signal REG_1_20_D2_PT_0 : STD_LOGIC; + signal REG_1_20_D2_PT_1 : STD_LOGIC; + signal REG_1_20_D2_PT_2 : STD_LOGIC; + signal REG_1_21_Q : STD_LOGIC; + signal REG_1_21 : STD_LOGIC; + signal REG_1_21_D : STD_LOGIC; + signal REG_1_21_tsimcreated_xor_Q : STD_LOGIC; + signal REG_1_21_RSTF : STD_LOGIC; + signal REG_1_21_SETF : STD_LOGIC; + signal REG_1_21_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_1_21_tsimcreated_prld_Q : STD_LOGIC; + signal REG_1_21_CLKF : STD_LOGIC; + signal REG_1_21_D1 : STD_LOGIC; + signal REG_1_21_D2 : STD_LOGIC; + signal EXP62_EXP : STD_LOGIC; + signal REG_1_21_D2_PT_0 : STD_LOGIC; + signal REG_1_21_D2_PT_1 : STD_LOGIC; + signal REG_1_21_D2_PT_2 : STD_LOGIC; + signal REG_1_22_Q : STD_LOGIC; + signal REG_1_22 : STD_LOGIC; + signal REG_1_22_D : STD_LOGIC; + signal REG_1_22_tsimcreated_xor_Q : STD_LOGIC; + signal REG_1_22_RSTF : STD_LOGIC; + signal REG_1_22_SETF : STD_LOGIC; + signal REG_1_22_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_1_22_tsimcreated_prld_Q : STD_LOGIC; + signal REG_1_22_CLKF : STD_LOGIC; + signal REG_1_22_D1 : STD_LOGIC; + signal REG_1_22_D2 : STD_LOGIC; + signal EXP59_EXP : STD_LOGIC; + signal REG_1_22_D2_PT_0 : STD_LOGIC; + signal REG_1_22_D2_PT_1 : STD_LOGIC; + signal REG_1_22_D2_PT_2 : STD_LOGIC; + signal REG_1_23_Q : STD_LOGIC; + signal REG_1_23_D : STD_LOGIC; + signal REG_1_23_tsimcreated_xor_Q : STD_LOGIC; + signal REG_1_23_RSTF : STD_LOGIC; + signal REG_1_23_SETF : STD_LOGIC; + signal REG_1_23_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_1_23_tsimcreated_prld_Q : STD_LOGIC; + signal REG_1_23_CLKF : STD_LOGIC; + signal REG_1_23_D1 : STD_LOGIC; + signal REG_1_23_D2 : STD_LOGIC; + signal REG_1_23_D2_PT_0 : STD_LOGIC; + signal REG_1_24_EXP : STD_LOGIC; + signal REG_1_23_D2_PT_1 : STD_LOGIC; + signal REG_1_23_D2_PT_2 : STD_LOGIC; + signal REG_1_23_D2_PT_3 : STD_LOGIC; + signal REG_1_24_Q : STD_LOGIC; + signal REG_1_24 : STD_LOGIC; + signal REG_1_24_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal REG_1_24_D : STD_LOGIC; + signal REG_1_24_tsimcreated_xor_Q : STD_LOGIC; + signal REG_1_24_RSTF : STD_LOGIC; + signal REG_1_24_SETF : STD_LOGIC; + signal REG_1_24_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_1_24_tsimcreated_prld_Q : STD_LOGIC; + signal REG_1_24_CLKF : STD_LOGIC; + signal REG_1_24_D1 : STD_LOGIC; + signal REG_1_24_D2 : STD_LOGIC; + signal EXP38_EXP : STD_LOGIC; + signal REG_1_24_D2_PT_0 : STD_LOGIC; + signal REG_1_24_D2_PT_1 : STD_LOGIC; + signal REG_1_25_Q : STD_LOGIC; + signal REG_1_25 : STD_LOGIC; + signal REG_1_25_D : STD_LOGIC; + signal REG_1_25_tsimcreated_xor_Q : STD_LOGIC; + signal REG_1_25_RSTF : STD_LOGIC; + signal REG_1_25_SETF : STD_LOGIC; + signal REG_1_25_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_1_25_tsimcreated_prld_Q : STD_LOGIC; + signal REG_1_25_CLKF : STD_LOGIC; + signal REG_1_25_D1 : STD_LOGIC; + signal REG_1_25_D2 : STD_LOGIC; + signal EXP41_EXP : STD_LOGIC; + signal REG_1_25_D2_PT_0 : STD_LOGIC; + signal REG_1_25_D2_PT_1 : STD_LOGIC; + signal REG_1_25_D2_PT_2 : STD_LOGIC; + signal REG_1_26_Q : STD_LOGIC; + signal REG_1_26 : STD_LOGIC; + signal REG_1_26_D : STD_LOGIC; + signal REG_1_26_tsimcreated_xor_Q : STD_LOGIC; + signal REG_1_26_RSTF : STD_LOGIC; + signal REG_1_26_SETF : STD_LOGIC; + signal REG_1_26_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_1_26_tsimcreated_prld_Q : STD_LOGIC; + signal REG_1_26_CLKF : STD_LOGIC; + signal REG_1_26_D1 : STD_LOGIC; + signal REG_1_26_D2 : STD_LOGIC; + signal EXP40_EXP : STD_LOGIC; + signal REG_1_26_D2_PT_0 : STD_LOGIC; + signal REG_1_26_D2_PT_1 : STD_LOGIC; + signal REG_1_26_D2_PT_2 : STD_LOGIC; + signal REG_1_27_Q : STD_LOGIC; + signal REG_1_27 : STD_LOGIC; + signal REG_1_27_D : STD_LOGIC; + signal REG_1_27_tsimcreated_xor_Q : STD_LOGIC; + signal REG_1_27_RSTF : STD_LOGIC; + signal REG_1_27_SETF : STD_LOGIC; + signal REG_1_27_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_1_27_tsimcreated_prld_Q : STD_LOGIC; + signal REG_1_27_CLKF : STD_LOGIC; + signal REG_1_27_D1 : STD_LOGIC; + signal REG_1_27_D2 : STD_LOGIC; + signal EXP37_EXP : STD_LOGIC; + signal REG_1_27_D2_PT_0 : STD_LOGIC; + signal REG_1_27_D2_PT_1 : STD_LOGIC; + signal REG_1_27_D2_PT_2 : STD_LOGIC; + signal REG_1_28_Q : STD_LOGIC; + signal REG_1_28 : STD_LOGIC; + signal REG_1_28_D : STD_LOGIC; + signal REG_1_28_tsimcreated_xor_Q : STD_LOGIC; + signal REG_1_28_RSTF : STD_LOGIC; + signal REG_1_28_SETF : STD_LOGIC; + signal REG_1_28_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_1_28_tsimcreated_prld_Q : STD_LOGIC; + signal REG_1_28_CLKF : STD_LOGIC; + signal REG_1_28_D1 : STD_LOGIC; + signal REG_1_28_D2 : STD_LOGIC; + signal EXP68_EXP : STD_LOGIC; + signal REG_1_28_D2_PT_0 : STD_LOGIC; + signal REG_1_28_D2_PT_1 : STD_LOGIC; + signal REG_1_28_D2_PT_2 : STD_LOGIC; + signal REG_1_29_Q : STD_LOGIC; + signal REG_1_29 : STD_LOGIC; + signal REG_1_29_D : STD_LOGIC; + signal REG_1_29_tsimcreated_xor_Q : STD_LOGIC; + signal REG_1_29_RSTF : STD_LOGIC; + signal REG_1_29_SETF : STD_LOGIC; + signal REG_1_29_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_1_29_tsimcreated_prld_Q : STD_LOGIC; + signal REG_1_29_CLKF : STD_LOGIC; + signal REG_1_29_D1 : STD_LOGIC; + signal REG_1_29_D2 : STD_LOGIC; + signal EXP28_EXP : STD_LOGIC; + signal REG_1_29_D2_PT_0 : STD_LOGIC; + signal REG_1_29_D2_PT_1 : STD_LOGIC; + signal REG_1_29_D2_PT_2 : STD_LOGIC; + signal REG_1_3_Q : STD_LOGIC; + signal REG_1_3 : STD_LOGIC; + signal REG_1_3_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal REG_1_3_D : STD_LOGIC; + signal REG_1_3_tsimcreated_xor_Q : STD_LOGIC; + signal REG_1_3_RSTF : STD_LOGIC; + signal REG_1_3_SETF : STD_LOGIC; + signal REG_1_3_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_1_3_tsimcreated_prld_Q : STD_LOGIC; + signal REG_1_3_CLKF : STD_LOGIC; + signal REG_1_3_D1 : STD_LOGIC; + signal REG_1_3_D2 : STD_LOGIC; + signal EXP53_EXP : STD_LOGIC; + signal REG_1_3_EXP_PT_0 : STD_LOGIC; + signal REG_1_3_EXP_PT_1 : STD_LOGIC; + signal REG_1_30_Q : STD_LOGIC; + signal REG_1_30 : STD_LOGIC; + signal REG_1_30_D : STD_LOGIC; + signal REG_1_30_tsimcreated_xor_Q : STD_LOGIC; + signal REG_1_30_RSTF : STD_LOGIC; + signal REG_1_30_SETF : STD_LOGIC; + signal REG_1_30_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_1_30_tsimcreated_prld_Q : STD_LOGIC; + signal REG_1_30_CLKF : STD_LOGIC; + signal REG_1_30_D1 : STD_LOGIC; + signal REG_1_30_D2 : STD_LOGIC; + signal DOUT_OBUFE_EXP : STD_LOGIC; + signal REG_1_30_D2_PT_0 : STD_LOGIC; + signal REG_1_30_D2_PT_1 : STD_LOGIC; + signal REG_1_30_D2_PT_2 : STD_LOGIC; + signal REG_1_31_Q : STD_LOGIC; + signal REG_1_31 : STD_LOGIC; + signal REG_1_31_D : STD_LOGIC; + signal REG_1_31_tsimcreated_xor_Q : STD_LOGIC; + signal REG_1_31_RSTF : STD_LOGIC; + signal REG_1_31_SETF : STD_LOGIC; + signal REG_1_31_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_1_31_tsimcreated_prld_Q : STD_LOGIC; + signal REG_1_31_CLKF : STD_LOGIC; + signal REG_1_31_D1 : STD_LOGIC; + signal REG_1_31_D2 : STD_LOGIC; + signal EXP27_EXP : STD_LOGIC; + signal REG_1_31_D2_PT_0 : STD_LOGIC; + signal REG_1_31_D2_PT_1 : STD_LOGIC; + signal REG_1_31_D2_PT_2 : STD_LOGIC; + signal REG_1_4_Q : STD_LOGIC; + signal REG_1_4_D : STD_LOGIC; + signal REG_1_4_tsimcreated_xor_Q : STD_LOGIC; + signal REG_1_4_RSTF : STD_LOGIC; + signal REG_1_4_SETF : STD_LOGIC; + signal REG_1_4_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_1_4_tsimcreated_prld_Q : STD_LOGIC; + signal REG_1_4_CLKF : STD_LOGIC; + signal REG_1_4_D1 : STD_LOGIC; + signal REG_1_4_D2 : STD_LOGIC; + signal REG_1_4_D2_PT_0 : STD_LOGIC; + signal REG_1_4_D2_PT_1 : STD_LOGIC; + signal REG_1_4_D2_PT_2 : STD_LOGIC; + signal REG_1_5_Q : STD_LOGIC; + signal REG_1_5 : STD_LOGIC; + signal REG_1_5_D : STD_LOGIC; + signal REG_1_5_tsimcreated_xor_Q : STD_LOGIC; + signal REG_1_5_RSTF : STD_LOGIC; + signal REG_1_5_SETF : STD_LOGIC; + signal REG_1_5_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_1_5_tsimcreated_prld_Q : STD_LOGIC; + signal REG_1_5_CLKF : STD_LOGIC; + signal REG_1_5_D1 : STD_LOGIC; + signal REG_1_5_D2 : STD_LOGIC; + signal EXP49_EXP : STD_LOGIC; + signal REG_1_5_D2_PT_0 : STD_LOGIC; + signal REG_1_5_D2_PT_1 : STD_LOGIC; + signal REG_1_5_D2_PT_2 : STD_LOGIC; + signal REG_1_6_Q : STD_LOGIC; + signal REG_1_6 : STD_LOGIC; + signal REG_1_6_D : STD_LOGIC; + signal REG_1_6_tsimcreated_xor_Q : STD_LOGIC; + signal REG_1_6_RSTF : STD_LOGIC; + signal REG_1_6_SETF : STD_LOGIC; + signal REG_1_6_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_1_6_tsimcreated_prld_Q : STD_LOGIC; + signal REG_1_6_CLKF : STD_LOGIC; + signal REG_1_6_D1 : STD_LOGIC; + signal REG_1_6_D2 : STD_LOGIC; + signal EXP50_EXP : STD_LOGIC; + signal REG_1_6_D2_PT_0 : STD_LOGIC; + signal EXP51_EXP : STD_LOGIC; + signal REG_1_6_D2_PT_1 : STD_LOGIC; + signal REG_1_6_D2_PT_2 : STD_LOGIC; + signal REG_1_6_D2_PT_3 : STD_LOGIC; + signal REG_1_7_Q : STD_LOGIC; + signal REG_1_7 : STD_LOGIC; + signal REG_1_7_D : STD_LOGIC; + signal REG_1_7_tsimcreated_xor_Q : STD_LOGIC; + signal REG_1_7_RSTF : STD_LOGIC; + signal REG_1_7_SETF : STD_LOGIC; + signal REG_1_7_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_1_7_tsimcreated_prld_Q : STD_LOGIC; + signal REG_1_7_CLKF : STD_LOGIC; + signal REG_1_7_D1 : STD_LOGIC; + signal REG_1_7_D2 : STD_LOGIC; + signal EXP42_EXP : STD_LOGIC; + signal REG_1_7_D2_PT_0 : STD_LOGIC; + signal REG_1_7_D2_PT_1 : STD_LOGIC; + signal REG_1_7_D2_PT_2 : STD_LOGIC; + signal REG_1_8_Q : STD_LOGIC; + signal REG_1_8 : STD_LOGIC; + signal REG_1_8_D : STD_LOGIC; + signal REG_1_8_tsimcreated_xor_Q : STD_LOGIC; + signal REG_1_8_RSTF : STD_LOGIC; + signal REG_1_8_SETF : STD_LOGIC; + signal REG_1_8_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_1_8_tsimcreated_prld_Q : STD_LOGIC; + signal REG_1_8_CLKF : STD_LOGIC; + signal REG_1_8_D1 : STD_LOGIC; + signal REG_1_8_D2 : STD_LOGIC; + signal EXP47_EXP : STD_LOGIC; + signal REG_1_8_D2_PT_0 : STD_LOGIC; + signal REG_1_8_D2_PT_1 : STD_LOGIC; + signal REG_1_8_D2_PT_2 : STD_LOGIC; + signal REG_1_9_Q : STD_LOGIC; + signal REG_1_9_D : STD_LOGIC; + signal REG_1_9_tsimcreated_xor_Q : STD_LOGIC; + signal REG_1_9_RSTF : STD_LOGIC; + signal REG_1_9_SETF : STD_LOGIC; + signal REG_1_9_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal REG_1_9_tsimcreated_prld_Q : STD_LOGIC; + signal REG_1_9_CLKF : STD_LOGIC; + signal REG_1_9_D1 : STD_LOGIC; + signal REG_1_9_D2 : STD_LOGIC; + signal EXP44_EXP : STD_LOGIC; + signal REG_1_9_D2_PT_0 : STD_LOGIC; + signal REG_1_9_D2_PT_1 : STD_LOGIC; + signal REG_1_9_D2_PT_2 : STD_LOGIC; + signal DOUT_OBUFE_Q : STD_LOGIC; + signal DOUT_OBUFE_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal DOUT_OBUFE_BUFOE_OUT : STD_LOGIC; + signal DOUT_OBUFE_TRST : STD_LOGIC; + signal DOUT_OBUFE_D : STD_LOGIC; + signal DOUT_OBUFE_D1 : STD_LOGIC; + signal DOUT_OBUFE_D2 : STD_LOGIC; + signal DOUT_OBUFE_D2_PT_0 : STD_LOGIC; + signal DOUT_OBUFE_D2_PT_1 : STD_LOGIC; + signal DOUT_OBUFE_EXP_PT_0 : STD_LOGIC; + signal DOUT_OBUFE_EXP_PT_1 : STD_LOGIC; + signal state_0_Q : STD_LOGIC; + signal state_0_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal state_0_RSTF : STD_LOGIC; + signal state_0_tsimcreated_prld_Q : STD_LOGIC; + signal state_0_D : STD_LOGIC; + signal state_0_CLKF : STD_LOGIC; + signal state_0_D1 : STD_LOGIC; + signal state_0_D2 : STD_LOGIC; + signal state_0_EXP_PT_0 : STD_LOGIC; + signal state_0_EXP_PT_1 : STD_LOGIC; + signal state_1_Q : STD_LOGIC; + signal state_1_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal state_1_RSTF : STD_LOGIC; + signal state_1_tsimcreated_prld_Q : STD_LOGIC; + signal state_1_D : STD_LOGIC; + signal state_1_CLKF : STD_LOGIC; + signal state_1_D1 : STD_LOGIC; + signal state_1_D2 : STD_LOGIC; + signal state_1_EXP_PT_0 : STD_LOGIC; + signal state_1_EXP_PT_1 : STD_LOGIC; + signal CLK_SCALE_1_Q : STD_LOGIC; + signal CLK_SCALE_1_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal CLK_SCALE_1_D : STD_LOGIC; + signal CLK_SCALE_1_D1 : STD_LOGIC; + signal CLK_SCALE_1_D2 : STD_LOGIC; + signal CLK_SCALE_1_D2_PT_0 : STD_LOGIC; + signal CLK_SCALE_1_D2_PT_1 : STD_LOGIC; + signal CLK_SCALE_1_D2_PT_2 : STD_LOGIC; + signal CLK_SCALE_2_Q : STD_LOGIC; + signal CLK_SCALE_2_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal CLK_SCALE_2_D : STD_LOGIC; + signal CLK_SCALE_2_D1 : STD_LOGIC; + signal CLK_SCALE_2_D2 : STD_LOGIC; + signal CLK_SCALE_2_D2_PT_0 : STD_LOGIC; + signal CLK_SCALE_2_D2_PT_1 : STD_LOGIC; + signal CLK_SCALE_2_D2_PT_2 : STD_LOGIC; + signal CLK_SCALE_2_EXP_PT_0 : STD_LOGIC; + signal CLK_SCALE_2_EXP_PT_1 : STD_LOGIC; + signal CLK_SCALE_3_Q : STD_LOGIC; + signal CLK_SCALE_3_D : STD_LOGIC; + signal CLK_SCALE_3_D1 : STD_LOGIC; + signal CLK_SCALE_3_D2 : STD_LOGIC; + signal CLK_SCALE_3_D2_PT_0 : STD_LOGIC; + signal CLK_SCALE_3_D2_PT_1 : STD_LOGIC; + signal CLK_SCALE_3_D2_PT_2 : STD_LOGIC; + signal CLK_SCALE_4_Q : STD_LOGIC; + signal CLK_SCALE_4_D : STD_LOGIC; + signal CLK_SCALE_4_D1 : STD_LOGIC; + signal CLK_SCALE_4_D2 : STD_LOGIC; + signal CLK_SCALE_4_D2_PT_0 : STD_LOGIC; + signal CLK_SCALE_4_D2_PT_1 : STD_LOGIC; + signal CLK_SCALE_4_D2_PT_2 : STD_LOGIC; + signal CLK_SCALE_5_Q : STD_LOGIC; + signal CLK_SCALE_5_D : STD_LOGIC; + signal CLK_SCALE_5_D1 : STD_LOGIC; + signal CLK_SCALE_5_D2 : STD_LOGIC; + signal CLK_SCALE_5_D2_PT_0 : STD_LOGIC; + signal CLK_SCALE_5_D2_PT_1 : STD_LOGIC; + signal CLK_SCALE_5_D2_PT_2 : STD_LOGIC; + signal tempID_0_Q : STD_LOGIC; + signal tempID_0_D : STD_LOGIC; + signal tempID_0_tsimcreated_xor_Q : STD_LOGIC; + signal tempID_0_CLKF : STD_LOGIC; + signal tempID_0_D1 : STD_LOGIC; + signal tempID_0_D2 : STD_LOGIC; + signal tempID_0_D2_PT_0 : STD_LOGIC; + signal tempID_0_D2_PT_1 : STD_LOGIC; + signal tempID_0_D2_PT_2 : STD_LOGIC; + signal tempID_0_D2_PT_3 : STD_LOGIC; + signal BUF_IS_EMPTY_OBUF_Q_0 : STD_LOGIC; + signal BUF_IS_EMPTY_OBUF_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal BUF_IS_EMPTY_OBUF_D : STD_LOGIC; + signal BUF_IS_EMPTY_OBUF_D1 : STD_LOGIC; + signal BUF_IS_EMPTY_OBUF_D2 : STD_LOGIC; + signal BUF_IS_EMPTY_OBUF_EXP_PT_0 : STD_LOGIC; + signal BUF_IS_EMPTY_OBUF_EXP_PT_1 : STD_LOGIC; + signal BUF_IS_EMPTY_OBUF_EXP_PT_2 : STD_LOGIC; + signal BUF_IS_EMPTY_OBUF_EXP_PT_3 : STD_LOGIC; + signal SHIFT_EN_Q : STD_LOGIC; + signal SHIFT_EN_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal SHIFT_EN_RSTF : STD_LOGIC; + signal SHIFT_EN_SETF : STD_LOGIC; + signal SHIFT_EN_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal SHIFT_EN_tsimcreated_prld_Q : STD_LOGIC; + signal SHIFT_EN_D : STD_LOGIC; + signal SHIFT_EN_CLKF : STD_LOGIC; + signal SHIFT_EN_D1 : STD_LOGIC; + signal SHIFT_EN_D2 : STD_LOGIC; + signal SHIFT_EN_SHIFT_EN_RSTF_INT_UIM : STD_LOGIC; + signal SHIFT_EN_EXP_PT_0 : STD_LOGIC; + signal SHIFT_EN_EXP_PT_1 : STD_LOGIC; + signal next_state_0_Q : STD_LOGIC; + signal next_state_0_RSTF : STD_LOGIC; + signal next_state_0_SETF : STD_LOGIC; + signal next_state_0_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal next_state_0_tsimcreated_prld_Q : STD_LOGIC; + signal next_state_0_D : STD_LOGIC; + signal next_state_0_CLKF : STD_LOGIC; + signal next_state_0_D1 : STD_LOGIC; + signal next_state_0_D2 : STD_LOGIC; + signal Q_OpTx_FX_DC_19_UIM : STD_LOGIC; + signal next_state_0_next_state_0_RSTF_UIM : STD_LOGIC; + signal next_state_1_Q : STD_LOGIC; + signal next_state_1_RSTF : STD_LOGIC; + signal next_state_1_SETF : STD_LOGIC; + signal next_state_1_tsimcreated_set_and_noreset_Q : STD_LOGIC; + signal next_state_1_tsimcreated_prld_Q : STD_LOGIC; + signal next_state_1_D : STD_LOGIC; + signal next_state_1_CLKF : STD_LOGIC; + signal next_state_1_D1 : STD_LOGIC; + signal next_state_1_D2 : STD_LOGIC; + signal next_state_1_next_state_1_RSTF_UIM : STD_LOGIC; + signal CCLK_OBUF_Q : STD_LOGIC; + signal CCLK_OBUF_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal CCLK_OBUF_D : STD_LOGIC; + signal CCLK_OBUF_D1 : STD_LOGIC; + signal CCLK_OBUF_D2 : STD_LOGIC; + signal EXP64_EXP : STD_LOGIC; + signal CCLK_OBUF_D2_PT_0 : STD_LOGIC; + signal CCLK_OBUF_D2_PT_1 : STD_LOGIC; + signal CCLK_OBUF_EXP_PT_0 : STD_LOGIC; + signal CCLK_OBUF_EXP_PT_1 : STD_LOGIC; + signal CCLK_OBUF_EXP_PT_2 : STD_LOGIC; + signal CCLK_OBUF_EXP_PT_3 : STD_LOGIC; + signal buf_depth_0_buf_depth_0_RSTF_Q : STD_LOGIC; + signal buf_depth_0_buf_depth_0_RSTF_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal buf_depth_0_buf_depth_0_RSTF_D : STD_LOGIC; + signal buf_depth_0_buf_depth_0_RSTF_D1 : STD_LOGIC; + signal buf_depth_0_buf_depth_0_RSTF_D2 : STD_LOGIC; + signal buf_depth_0_buf_depth_0_RSTF_D2_PT_0 : STD_LOGIC; + signal buf_depth_0_buf_depth_0_RSTF_D2_PT_1 : STD_LOGIC; + signal buf_depth_0_buf_depth_0_RSTF_EXP_PT_0 : STD_LOGIC; + signal buf_depth_0_buf_depth_0_RSTF_EXP_PT_1 : STD_LOGIC; + signal buf_depth_0_buf_depth_0_RSTF_EXP_PT_2 : STD_LOGIC; + signal buf_depth_1_buf_depth_1_RSTF_Q : STD_LOGIC; + signal buf_depth_1_buf_depth_1_RSTF_D : STD_LOGIC; + signal buf_depth_1_buf_depth_1_RSTF_D1 : STD_LOGIC; + signal buf_depth_1_buf_depth_1_RSTF_D2 : STD_LOGIC; + signal buf_depth_1_buf_depth_1_RSTF_D2_PT_0 : STD_LOGIC; + signal buf_depth_1_buf_depth_1_RSTF_D2_PT_1 : STD_LOGIC; + signal buf_depth_1_buf_depth_1_RSTF_D2_PT_2 : STD_LOGIC; + signal SHIFT_EN_SHIFT_EN_RSTF_INT_Q : STD_LOGIC; + signal SHIFT_EN_SHIFT_EN_RSTF_INT_D : STD_LOGIC; + signal SHIFT_EN_SHIFT_EN_RSTF_INT_D1 : STD_LOGIC; + signal SHIFT_EN_SHIFT_EN_RSTF_INT_D2 : STD_LOGIC; + signal SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_0 : STD_LOGIC; + signal SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_1 : STD_LOGIC; + signal Q_OpTx_FX_DC_19_Q : STD_LOGIC; + signal Q_OpTx_FX_DC_19_D : STD_LOGIC; + signal Q_OpTx_FX_DC_19_D1 : STD_LOGIC; + signal Q_OpTx_FX_DC_19_D2 : STD_LOGIC; + signal Q_OpTx_FX_DC_19_D2_PT_0 : STD_LOGIC; + signal Q_OpTx_FX_DC_19_D2_PT_1 : STD_LOGIC; + signal next_state_0_next_state_0_RSTF_Q : STD_LOGIC; + signal next_state_0_next_state_0_RSTF_D : STD_LOGIC; + signal next_state_0_next_state_0_RSTF_D1 : STD_LOGIC; + signal next_state_0_next_state_0_RSTF_D2 : STD_LOGIC; + signal next_state_0_next_state_0_RSTF_D2_PT_0 : STD_LOGIC; + signal next_state_0_next_state_0_RSTF_D2_PT_1 : STD_LOGIC; + signal next_state_0_next_state_0_RSTF_D2_PT_2 : STD_LOGIC; + signal next_state_0_next_state_0_RSTF_D2_PT_3 : STD_LOGIC; + signal next_state_1_next_state_1_RSTF_Q : STD_LOGIC; + signal next_state_1_next_state_1_RSTF_D : STD_LOGIC; + signal next_state_1_next_state_1_RSTF_D1 : STD_LOGIC; + signal next_state_1_next_state_1_RSTF_D2 : STD_LOGIC; + signal next_state_1_next_state_1_RSTF_D2_PT_0 : STD_LOGIC; + signal next_state_1_next_state_1_RSTF_D2_PT_1 : STD_LOGIC; + signal next_state_1_next_state_1_RSTF_D2_PT_2 : STD_LOGIC; + signal next_state_1_next_state_1_RSTF_D2_PT_3 : STD_LOGIC; + signal next_state_1_next_state_1_RSTF_D2_PT_4 : STD_LOGIC; + signal EXP18_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP18_EXP_PT_0 : STD_LOGIC; + signal EXP18_EXP_PT_1 : STD_LOGIC; + signal EXP19_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP19_EXP_PT_0 : STD_LOGIC; + signal EXP19_EXP_PT_1 : STD_LOGIC; + signal EXP20_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP21_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP22_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP22_EXP_PT_0 : STD_LOGIC; + signal EXP22_EXP_PT_1 : STD_LOGIC; + signal EXP22_EXP_PT_2 : STD_LOGIC; + signal EXP23_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP23_EXP_PT_0 : STD_LOGIC; + signal EXP23_EXP_PT_1 : STD_LOGIC; + signal EXP23_EXP_PT_2 : STD_LOGIC; + signal EXP23_EXP_PT_3 : STD_LOGIC; + signal EXP24_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP24_EXP_PT_0 : STD_LOGIC; + signal EXP24_EXP_PT_1 : STD_LOGIC; + signal EXP25_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP25_EXP_PT_0 : STD_LOGIC; + signal EXP25_EXP_PT_1 : STD_LOGIC; + signal EXP25_EXP_PT_2 : STD_LOGIC; + signal EXP25_EXP_PT_3 : STD_LOGIC; + signal EXP26_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP26_EXP_PT_0 : STD_LOGIC; + signal EXP26_EXP_PT_1 : STD_LOGIC; + signal EXP27_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP27_EXP_PT_0 : STD_LOGIC; + signal EXP27_EXP_PT_1 : STD_LOGIC; + signal EXP28_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP28_EXP_PT_0 : STD_LOGIC; + signal EXP28_EXP_PT_1 : STD_LOGIC; + signal EXP29_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP29_EXP_PT_0 : STD_LOGIC; + signal EXP29_EXP_PT_1 : STD_LOGIC; + signal EXP29_EXP_PT_2 : STD_LOGIC; + signal EXP30_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP30_EXP_PT_0 : STD_LOGIC; + signal EXP30_EXP_PT_1 : STD_LOGIC; + signal EXP30_EXP_PT_2 : STD_LOGIC; + signal EXP31_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP31_EXP_PT_0 : STD_LOGIC; + signal EXP31_EXP_PT_1 : STD_LOGIC; + signal EXP32_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP32_EXP_PT_0 : STD_LOGIC; + signal EXP32_EXP_PT_1 : STD_LOGIC; + signal EXP33_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP33_EXP_PT_0 : STD_LOGIC; + signal EXP33_EXP_PT_1 : STD_LOGIC; + signal EXP33_EXP_PT_2 : STD_LOGIC; + signal EXP34_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP34_EXP_PT_0 : STD_LOGIC; + signal EXP34_EXP_PT_1 : STD_LOGIC; + signal EXP34_EXP_PT_2 : STD_LOGIC; + signal EXP35_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP35_EXP_PT_0 : STD_LOGIC; + signal EXP35_EXP_PT_1 : STD_LOGIC; + signal EXP36_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP36_EXP_PT_0 : STD_LOGIC; + signal EXP36_EXP_PT_1 : STD_LOGIC; + signal EXP37_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP37_EXP_PT_0 : STD_LOGIC; + signal EXP37_EXP_PT_1 : STD_LOGIC; + signal EXP38_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP38_EXP_PT_0 : STD_LOGIC; + signal EXP38_EXP_PT_1 : STD_LOGIC; + signal EXP38_EXP_PT_2 : STD_LOGIC; + signal EXP39_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP39_EXP_PT_0 : STD_LOGIC; + signal EXP39_EXP_PT_1 : STD_LOGIC; + signal EXP39_EXP_PT_2 : STD_LOGIC; + signal EXP40_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP40_EXP_PT_0 : STD_LOGIC; + signal EXP40_EXP_PT_1 : STD_LOGIC; + signal EXP41_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP41_EXP_PT_0 : STD_LOGIC; + signal EXP41_EXP_PT_1 : STD_LOGIC; + signal EXP42_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP42_EXP_PT_0 : STD_LOGIC; + signal EXP42_EXP_PT_1 : STD_LOGIC; + signal EXP43_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP43_EXP_PT_0 : STD_LOGIC; + signal EXP43_EXP_PT_1 : STD_LOGIC; + signal EXP44_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP44_EXP_PT_0 : STD_LOGIC; + signal EXP44_EXP_PT_1 : STD_LOGIC; + signal EXP45_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP45_EXP_PT_0 : STD_LOGIC; + signal EXP45_EXP_PT_1 : STD_LOGIC; + signal EXP45_EXP_PT_2 : STD_LOGIC; + signal EXP46_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP46_EXP_PT_0 : STD_LOGIC; + signal EXP46_EXP_PT_1 : STD_LOGIC; + signal EXP46_EXP_PT_2 : STD_LOGIC; + signal EXP47_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP47_EXP_PT_0 : STD_LOGIC; + signal EXP47_EXP_PT_1 : STD_LOGIC; + signal EXP48_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP48_EXP_PT_0 : STD_LOGIC; + signal EXP48_EXP_PT_1 : STD_LOGIC; + signal EXP49_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP49_EXP_PT_0 : STD_LOGIC; + signal EXP49_EXP_PT_1 : STD_LOGIC; + signal EXP50_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP51_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP52_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP52_EXP_PT_0 : STD_LOGIC; + signal EXP52_EXP_PT_1 : STD_LOGIC; + signal EXP52_EXP_PT_2 : STD_LOGIC; + signal EXP53_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP53_EXP_PT_0 : STD_LOGIC; + signal EXP53_EXP_PT_1 : STD_LOGIC; + signal EXP53_EXP_PT_2 : STD_LOGIC; + signal EXP53_EXP_PT_3 : STD_LOGIC; + signal EXP54_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP54_EXP_PT_0 : STD_LOGIC; + signal EXP54_EXP_PT_1 : STD_LOGIC; + signal EXP55_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP55_EXP_PT_0 : STD_LOGIC; + signal EXP55_EXP_PT_1 : STD_LOGIC; + signal EXP55_EXP_PT_2 : STD_LOGIC; + signal EXP56_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP56_EXP_PT_0 : STD_LOGIC; + signal EXP56_EXP_PT_1 : STD_LOGIC; + signal EXP56_EXP_PT_2 : STD_LOGIC; + signal EXP57_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP57_EXP_PT_0 : STD_LOGIC; + signal EXP57_EXP_PT_1 : STD_LOGIC; + signal EXP58_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP58_EXP_PT_0 : STD_LOGIC; + signal EXP58_EXP_PT_1 : STD_LOGIC; + signal EXP59_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP59_EXP_PT_0 : STD_LOGIC; + signal EXP59_EXP_PT_1 : STD_LOGIC; + signal EXP60_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP60_EXP_PT_0 : STD_LOGIC; + signal EXP60_EXP_PT_1 : STD_LOGIC; + signal EXP60_EXP_PT_2 : STD_LOGIC; + signal EXP61_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP61_EXP_PT_0 : STD_LOGIC; + signal EXP61_EXP_PT_1 : STD_LOGIC; + signal EXP61_EXP_PT_2 : STD_LOGIC; + signal EXP62_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP62_EXP_PT_0 : STD_LOGIC; + signal EXP62_EXP_PT_1 : STD_LOGIC; + signal EXP63_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP63_EXP_PT_0 : STD_LOGIC; + signal EXP63_EXP_PT_1 : STD_LOGIC; + signal EXP64_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP64_EXP_PT_0 : STD_LOGIC; + signal EXP64_EXP_PT_1 : STD_LOGIC; + signal EXP65_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP65_EXP_PT_0 : STD_LOGIC; + signal EXP65_EXP_PT_1 : STD_LOGIC; + signal EXP66_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP66_EXP_PT_0 : STD_LOGIC; + signal EXP66_EXP_PT_1 : STD_LOGIC; + signal EXP67_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP67_EXP_PT_0 : STD_LOGIC; + signal EXP67_EXP_PT_1 : STD_LOGIC; + signal EXP68_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP68_EXP_PT_0 : STD_LOGIC; + signal EXP68_EXP_PT_1 : STD_LOGIC; + signal EXP69_EXP_tsimrenamed_net_Q : STD_LOGIC; + signal EXP69_EXP_PT_0 : STD_LOGIC; + signal EXP69_EXP_PT_1 : STD_LOGIC; + signal NlwInverterSignal_SCLK_CE_IN0 : STD_LOGIC; + signal NlwInverterSignal_SCLK_CE_IN2 : STD_LOGIC; + signal NlwInverterSignal_SCLK_CE_IN3 : STD_LOGIC; + signal NlwInverterSignal_SCLK_CE_IN4 : STD_LOGIC; + signal NlwInverterSignal_SCLK_CE_IN5 : STD_LOGIC; + signal NlwInverterSignal_SCLK_CE_IN6 : STD_LOGIC; + signal NlwInverterSignal_readBufId_0_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_readBufId_0_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_readBufId_0_CE_IN0 : STD_LOGIC; + signal NlwInverterSignal_readBufId_0_CE_IN1 : STD_LOGIC; + signal NlwInverterSignal_readBufId_0_CE_IN2 : STD_LOGIC; + signal NlwInverterSignal_readBufId_0_CE_IN3 : STD_LOGIC; + signal NlwInverterSignal_readBufId_0_CE_IN4 : STD_LOGIC; + signal NlwInverterSignal_readBufId_0_CE_IN5 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_0_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_0_D2_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_0_D2_PT_0_IN2 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_0_D2_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_0_D2_PT_0_IN4 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_0_D2_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_0_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_0_D2_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_0_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_0_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_0_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_0_D2_PT_1_IN6 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_0_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_0_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_0_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_0_SETF_IN2 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_1_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_1_D2_PT_0_IN2 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_1_D2_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_1_D2_PT_0_IN4 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_1_D2_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_1_D2_PT_0_IN6 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_1_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_1_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_1_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_1_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_1_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_1_D2_PT_1_IN6 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_1_D2_PT_1_IN7 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_1_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_1_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_1_SETF_IN2 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_0_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_0_D_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_0_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_0_D2_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_0_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_0_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_0_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_0_EXP_tsimrenamed_net_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_0_EXP_tsimrenamed_net_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_0_EXP_tsimrenamed_net_IN2 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_0_EXP_tsimrenamed_net_IN3 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_0_EXP_tsimrenamed_net_IN4 : STD_LOGIC; + signal NlwInverterSignal_count_0_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_0_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_0_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_0_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_0_D2_PT_2_IN2 : STD_LOGIC; + signal NlwInverterSignal_count_0_D2_PT_2_IN3 : STD_LOGIC; + signal NlwInverterSignal_count_0_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_count_0_D2_PT_2_IN5 : STD_LOGIC; + signal NlwInverterSignal_count_0_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_0_EXP_tsimrenamed_net_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_0_EXP_tsimrenamed_net_IN3 : STD_LOGIC; + signal NlwInverterSignal_count_4_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_4_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_4_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_4_D2_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_count_4_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_count_4_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_count_4_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_count_4_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_4_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_4_D2_PT_2_IN2 : STD_LOGIC; + signal NlwInverterSignal_count_4_D2_PT_2_IN3 : STD_LOGIC; + signal NlwInverterSignal_count_4_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_count_4_D2_PT_2_IN5 : STD_LOGIC; + signal NlwInverterSignal_count_4_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_4_EXP_tsimrenamed_net_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_4_EXP_tsimrenamed_net_IN3 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_1_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_1_D_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_1_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_1_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_1_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_1_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_1_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_2_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_2_D_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_2_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_2_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_2_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_2_EXP_tsimrenamed_net_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_2_EXP_tsimrenamed_net_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_2_EXP_tsimrenamed_net_IN2 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_2_EXP_tsimrenamed_net_IN3 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_2_EXP_tsimrenamed_net_IN4 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_2_EXP_tsimrenamed_net_IN5 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_3_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_3_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_3_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_3_D2_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_3_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_3_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_3_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_3_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_1_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_1_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_1_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_1_D2_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_count_1_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_1_D2_PT_2_IN2 : STD_LOGIC; + signal NlwInverterSignal_count_1_D2_PT_3_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_1_D2_PT_3_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_1_D2_PT_3_IN2 : STD_LOGIC; + signal NlwInverterSignal_count_1_D2_PT_3_IN3 : STD_LOGIC; + signal NlwInverterSignal_count_1_D2_PT_3_IN4 : STD_LOGIC; + signal NlwInverterSignal_count_1_D2_PT_3_IN5 : STD_LOGIC; + signal NlwInverterSignal_count_1_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_2_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_2_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_2_D2_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_count_2_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_2_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_2_D2_PT_2_IN2 : STD_LOGIC; + signal NlwInverterSignal_count_2_D2_PT_2_IN3 : STD_LOGIC; + signal NlwInverterSignal_count_2_D2_PT_3_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_2_D2_PT_3_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_2_D2_PT_3_IN2 : STD_LOGIC; + signal NlwInverterSignal_count_2_D2_PT_3_IN3 : STD_LOGIC; + signal NlwInverterSignal_count_2_D2_PT_3_IN4 : STD_LOGIC; + signal NlwInverterSignal_count_2_D2_PT_3_IN5 : STD_LOGIC; + signal NlwInverterSignal_count_2_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_3_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_3_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_3_D2_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_count_3_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_3_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_3_D2_PT_2_IN2 : STD_LOGIC; + signal NlwInverterSignal_count_3_D2_PT_2_IN3 : STD_LOGIC; + signal NlwInverterSignal_count_3_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_count_3_D2_PT_3_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_3_D2_PT_3_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_3_D2_PT_3_IN2 : STD_LOGIC; + signal NlwInverterSignal_count_3_D2_PT_3_IN3 : STD_LOGIC; + signal NlwInverterSignal_count_3_D2_PT_3_IN4 : STD_LOGIC; + signal NlwInverterSignal_count_3_D2_PT_3_IN5 : STD_LOGIC; + signal NlwInverterSignal_count_3_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_4_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_4_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_4_D2_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_4_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_4_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_4_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_4_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_4_D2_PT_2_IN2 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_4_D2_PT_2_IN3 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_4_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_4_D2_PT_2_IN5 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_4_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_4_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_CNT_4_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_5_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_5_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_5_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_count_5_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_5_D2_PT_2_IN2 : STD_LOGIC; + signal NlwInverterSignal_count_5_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_5_EXP_tsimrenamed_net_IN0 : STD_LOGIC; + signal NlwInverterSignal_writeBufId_0_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_writeBufId_0_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_writeBufId_0_CE_IN0 : STD_LOGIC; + signal NlwInverterSignal_writeBufId_0_CE_IN1 : STD_LOGIC; + signal NlwInverterSignal_writeBufId_0_CE_IN2 : STD_LOGIC; + signal NlwInverterSignal_writeBufId_0_CE_IN3 : STD_LOGIC; + signal NlwInverterSignal_writeBufId_0_CE_IN4 : STD_LOGIC; + signal NlwInverterSignal_writeBufId_0_CE_IN5 : STD_LOGIC; + signal NlwInverterSignal_CLK_SCALE_0_EXP_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_CLK_SCALE_0_EXP_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_CLK_SCALE_0_EXP_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_CLK_SCALE_0_EXP_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_0_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_0_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_0_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_0_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_0_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_0_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_0_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_0_EXP_PT_0_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_0_EXP_PT_0_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_0_0_EXP_PT_0_IN6 : STD_LOGIC; + signal NlwInverterSignal_REG_0_0_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_0_EXP_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_0_EXP_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_0_0_EXP_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_0_1_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_1_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_1_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_1_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_1_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_0_1_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_1_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_1_D2_PT_2_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_1_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_0_1_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_1_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_1_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_1_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_1_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_10_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_10_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_10_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_10_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_10_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_0_10_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_10_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_10_D2_PT_2_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_10_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_0_10_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_10_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_10_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_10_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_10_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_11_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_11_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_11_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_11_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_11_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_0_11_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_11_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_11_D2_PT_2_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_11_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_0_11_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_11_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_11_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_11_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_11_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_12_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_12_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_12_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_12_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_12_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_0_12_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_12_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_12_D2_PT_2_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_12_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_0_12_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_12_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_12_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_12_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_12_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_13_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_13_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_13_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_13_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_13_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_13_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_13_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_13_EXP_PT_0_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_13_EXP_PT_0_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_0_13_EXP_PT_0_IN6 : STD_LOGIC; + signal NlwInverterSignal_REG_0_13_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_13_EXP_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_13_EXP_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_0_13_EXP_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_0_14_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_14_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_14_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_14_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_14_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_0_14_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_14_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_14_D2_PT_2_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_14_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_0_14_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_14_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_14_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_14_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_14_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_15_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_15_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_15_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_15_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_15_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_0_15_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_15_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_15_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_15_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_15_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_15_EXP_tsimrenamed_net_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_15_EXP_tsimrenamed_net_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_15_EXP_tsimrenamed_net_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_0_15_EXP_tsimrenamed_net_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_0_16_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_16_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_16_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_16_D2_PT_2_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_16_D2_PT_2_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_0_16_D2_PT_3_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_16_D2_PT_3_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_16_D2_PT_3_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_16_D2_PT_3_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_0_16_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_16_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_16_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_16_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_16_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_17_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_17_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_17_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_17_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_17_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_0_17_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_17_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_17_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_17_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_17_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_17_EXP_tsimrenamed_net_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_17_EXP_tsimrenamed_net_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_17_EXP_tsimrenamed_net_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_0_17_EXP_tsimrenamed_net_IN6 : STD_LOGIC; + signal NlwInverterSignal_REG_0_18_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_18_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_18_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_18_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_18_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_0_18_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_18_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_18_D2_PT_2_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_18_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_0_18_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_18_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_18_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_18_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_18_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_19_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_19_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_19_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_19_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_19_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_0_19_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_19_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_19_D2_PT_2_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_19_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_0_19_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_19_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_19_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_19_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_19_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_2_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_2_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_2_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_2_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_2_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_0_2_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_2_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_2_D2_PT_2_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_2_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_0_2_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_2_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_2_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_2_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_2_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_20_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_20_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_20_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_20_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_20_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_0_20_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_20_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_20_D2_PT_2_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_20_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_0_20_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_20_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_20_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_20_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_20_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_21_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_21_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_21_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_21_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_21_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_0_21_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_21_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_21_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_21_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_21_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_21_EXP_tsimrenamed_net_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_21_EXP_tsimrenamed_net_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_21_EXP_tsimrenamed_net_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_0_21_EXP_tsimrenamed_net_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_0_22_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_22_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_22_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_22_D2_PT_2_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_22_D2_PT_2_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_0_22_D2_PT_3_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_22_D2_PT_3_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_22_D2_PT_3_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_22_D2_PT_3_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_0_22_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_22_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_22_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_22_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_22_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_23_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_23_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_23_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_23_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_23_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_0_23_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_23_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_23_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_23_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_23_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_23_EXP_tsimrenamed_net_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_23_EXP_tsimrenamed_net_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_23_EXP_tsimrenamed_net_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_0_23_EXP_tsimrenamed_net_IN6 : STD_LOGIC; + signal NlwInverterSignal_REG_0_24_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_24_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_24_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_24_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_24_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_0_24_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_24_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_24_D2_PT_2_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_24_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_0_24_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_24_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_24_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_24_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_24_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_25_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_25_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_25_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_25_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_25_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_0_25_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_25_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_25_D2_PT_2_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_25_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_0_25_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_25_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_25_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_25_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_25_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_26_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_26_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_26_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_26_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_26_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_0_26_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_26_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_26_D2_PT_2_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_26_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_0_26_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_26_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_26_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_26_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_26_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_27_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_27_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_27_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_27_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_27_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_0_27_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_27_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_27_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_27_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_27_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_27_EXP_tsimrenamed_net_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_27_EXP_tsimrenamed_net_IN6 : STD_LOGIC; + signal NlwInverterSignal_REG_0_28_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_28_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_28_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_28_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_28_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_0_28_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_28_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_28_D2_PT_2_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_28_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_0_28_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_28_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_28_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_28_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_28_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_29_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_29_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_29_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_29_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_29_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_0_29_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_29_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_29_D2_PT_2_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_29_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_0_29_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_29_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_29_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_29_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_29_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_3_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_3_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_3_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_3_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_3_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_3_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_3_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_3_EXP_PT_0_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_3_EXP_PT_0_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_0_3_EXP_PT_0_IN6 : STD_LOGIC; + signal NlwInverterSignal_REG_0_3_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_3_EXP_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_3_EXP_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_0_3_EXP_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_0_30_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_30_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_30_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_30_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_30_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_30_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_30_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_30_EXP_PT_0_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_30_EXP_PT_0_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_0_30_EXP_PT_0_IN6 : STD_LOGIC; + signal NlwInverterSignal_REG_0_30_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_30_EXP_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_30_EXP_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_0_30_EXP_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_0_31_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_31_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_31_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_31_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_31_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_0_31_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_31_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_31_D2_PT_2_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_31_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_0_31_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_31_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_31_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_31_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_31_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_4_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_4_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_4_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_4_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_4_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_0_4_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_4_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_4_D2_PT_2_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_4_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_0_4_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_4_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_4_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_4_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_4_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_5_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_5_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_5_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_5_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_5_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_0_5_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_5_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_5_D2_PT_2_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_5_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_0_5_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_5_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_5_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_5_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_5_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_6_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_6_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_6_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_6_D2_PT_2_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_6_D2_PT_2_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_0_6_D2_PT_3_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_6_D2_PT_3_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_6_D2_PT_3_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_6_D2_PT_3_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_0_6_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_6_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_6_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_6_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_6_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_7_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_7_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_7_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_7_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_7_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_0_7_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_7_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_7_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_7_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_7_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_7_EXP_tsimrenamed_net_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_7_EXP_tsimrenamed_net_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_7_EXP_tsimrenamed_net_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_0_7_EXP_tsimrenamed_net_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_0_8_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_8_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_8_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_8_D2_PT_2_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_8_D2_PT_2_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_0_8_D2_PT_3_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_8_D2_PT_3_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_8_D2_PT_3_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_8_D2_PT_3_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_0_8_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_8_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_8_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_8_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_8_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_9_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_9_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_9_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_9_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_REG_0_9_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_0_9_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_9_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_9_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_9_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_0_9_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_9_EXP_tsimrenamed_net_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_0_9_EXP_tsimrenamed_net_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_0_9_EXP_tsimrenamed_net_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_0_9_EXP_tsimrenamed_net_IN6 : STD_LOGIC; + signal NlwInverterSignal_REG_1_0_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_0_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_0_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_0_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_1_0_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_0_EXP_PT_0_IN6 : STD_LOGIC; + signal NlwInverterSignal_REG_1_0_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_0_EXP_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_1_1_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_1_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_1_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_1_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_1_1_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_1_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_1_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_1_1_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_1_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_1_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_1_10_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_10_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_10_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_10_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_1_10_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_10_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_10_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_1_10_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_10_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_10_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_1_11_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_11_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_11_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_11_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_1_11_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_11_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_11_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_1_11_EXP_tsimrenamed_net_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_11_EXP_tsimrenamed_net_IN6 : STD_LOGIC; + signal NlwInverterSignal_REG_1_12_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_12_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_12_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_12_D2_PT_2_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_1_12_D2_PT_3_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_12_D2_PT_3_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_12_D2_PT_3_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_1_12_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_12_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_12_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_1_13_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_13_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_13_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_13_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_1_13_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_13_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_13_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_1_13_EXP_tsimrenamed_net_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_13_EXP_tsimrenamed_net_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_1_14_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_14_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_14_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_14_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_1_14_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_14_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_14_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_1_14_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_14_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_14_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_1_15_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_15_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_15_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_15_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_1_15_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_15_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_15_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_1_15_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_15_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_15_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_1_16_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_16_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_16_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_16_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_1_16_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_16_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_16_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_1_16_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_16_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_16_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_1_17_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_17_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_17_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_17_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_1_17_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_17_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_17_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_1_17_EXP_tsimrenamed_net_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_17_EXP_tsimrenamed_net_IN6 : STD_LOGIC; + signal NlwInverterSignal_REG_1_18_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_18_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_18_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_18_D2_PT_2_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_1_18_D2_PT_3_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_18_D2_PT_3_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_18_D2_PT_3_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_1_18_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_18_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_18_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_1_19_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_19_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_19_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_19_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_1_19_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_19_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_19_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_1_19_EXP_tsimrenamed_net_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_19_EXP_tsimrenamed_net_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_1_2_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_2_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_2_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_2_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_1_2_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_2_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_2_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_1_2_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_2_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_2_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_1_20_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_20_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_20_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_20_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_1_20_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_20_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_20_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_1_20_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_20_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_20_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_1_21_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_21_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_21_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_21_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_1_21_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_21_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_21_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_1_21_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_21_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_21_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_1_22_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_22_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_22_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_22_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_1_22_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_22_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_22_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_1_22_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_22_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_22_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_1_23_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_23_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_23_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_23_D2_PT_2_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_1_23_D2_PT_3_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_23_D2_PT_3_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_23_D2_PT_3_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_1_23_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_23_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_23_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_1_24_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_24_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_24_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_24_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_1_24_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_24_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_24_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_1_24_EXP_tsimrenamed_net_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_24_EXP_tsimrenamed_net_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_1_25_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_25_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_25_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_25_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_1_25_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_25_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_25_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_1_25_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_25_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_25_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_1_26_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_26_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_26_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_26_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_1_26_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_26_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_26_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_1_26_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_26_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_26_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_1_27_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_27_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_27_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_27_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_1_27_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_27_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_27_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_1_27_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_27_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_27_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_1_28_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_28_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_28_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_28_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_1_28_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_28_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_28_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_1_28_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_28_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_28_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_1_29_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_29_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_29_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_29_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_1_29_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_29_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_29_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_1_29_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_29_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_29_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_1_3_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_3_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_3_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_3_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_1_3_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_3_EXP_PT_0_IN6 : STD_LOGIC; + signal NlwInverterSignal_REG_1_3_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_3_EXP_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_1_30_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_30_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_30_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_30_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_1_30_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_30_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_30_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_1_30_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_30_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_30_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_1_31_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_31_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_31_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_31_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_1_31_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_31_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_31_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_1_31_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_31_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_31_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_1_4_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_4_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_4_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_4_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_1_4_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_4_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_4_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_1_4_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_4_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_4_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_1_5_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_5_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_5_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_5_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_1_5_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_5_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_5_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_1_5_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_5_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_5_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_1_6_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_6_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_6_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_6_D2_PT_2_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_1_6_D2_PT_3_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_6_D2_PT_3_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_6_D2_PT_3_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_1_6_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_6_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_6_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_1_7_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_7_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_7_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_7_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_1_7_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_7_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_7_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_1_7_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_7_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_7_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_1_8_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_8_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_8_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_8_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_1_8_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_8_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_8_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_1_8_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_8_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_8_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_REG_1_9_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_9_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_9_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_9_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_REG_1_9_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_9_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_9_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_REG_1_9_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_REG_1_9_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_REG_1_9_RSTF_IN2 : STD_LOGIC; + signal NlwInverterSignal_DOUT_OBUFE_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_DOUT_OBUFE_TRST_IN0 : STD_LOGIC; + signal NlwInverterSignal_DOUT_OBUFE_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_DOUT_OBUFE_EXP_PT_0_IN6 : STD_LOGIC; + signal NlwInverterSignal_DOUT_OBUFE_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_DOUT_OBUFE_EXP_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_state_0_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_state_0_EXP_PT_0_IN2 : STD_LOGIC; + signal NlwInverterSignal_state_0_EXP_PT_0_IN4 : STD_LOGIC; + signal NlwInverterSignal_state_0_EXP_PT_0_IN6 : STD_LOGIC; + signal NlwInverterSignal_state_0_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_state_0_EXP_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_state_0_EXP_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_state_0_EXP_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_state_1_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_state_1_EXP_PT_0_IN2 : STD_LOGIC; + signal NlwInverterSignal_state_1_EXP_PT_0_IN4 : STD_LOGIC; + signal NlwInverterSignal_state_1_EXP_PT_0_IN6 : STD_LOGIC; + signal NlwInverterSignal_state_1_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_state_1_EXP_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_state_1_EXP_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_state_1_EXP_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_CLK_SCALE_1_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_CLK_SCALE_1_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_CLK_SCALE_1_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_CLK_SCALE_1_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_CLK_SCALE_1_EXP_tsimrenamed_net_IN1 : STD_LOGIC; + signal NlwInverterSignal_CLK_SCALE_1_EXP_tsimrenamed_net_IN3 : STD_LOGIC; + signal NlwInverterSignal_CLK_SCALE_2_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_CLK_SCALE_2_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_CLK_SCALE_2_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_CLK_SCALE_2_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_CLK_SCALE_2_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_CLK_SCALE_2_EXP_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_CLK_SCALE_2_EXP_PT_0_IN2 : STD_LOGIC; + signal NlwInverterSignal_CLK_SCALE_2_EXP_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_CLK_SCALE_2_EXP_PT_0_IN4 : STD_LOGIC; + signal NlwInverterSignal_CLK_SCALE_2_EXP_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_CLK_SCALE_2_EXP_PT_0_IN6 : STD_LOGIC; + signal NlwInverterSignal_CLK_SCALE_2_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_CLK_SCALE_2_EXP_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_CLK_SCALE_2_EXP_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_CLK_SCALE_2_EXP_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_CLK_SCALE_2_EXP_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_CLK_SCALE_2_EXP_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_CLK_SCALE_3_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_CLK_SCALE_3_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_CLK_SCALE_3_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_CLK_SCALE_3_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_CLK_SCALE_4_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_CLK_SCALE_4_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_CLK_SCALE_4_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_CLK_SCALE_4_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_CLK_SCALE_5_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_CLK_SCALE_5_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_CLK_SCALE_5_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_CLK_SCALE_5_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_tempID_0_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_tempID_0_D2_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_tempID_0_D2_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_tempID_0_D2_PT_0_IN4 : STD_LOGIC; + signal NlwInverterSignal_tempID_0_D2_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_tempID_0_D2_PT_0_IN6 : STD_LOGIC; + signal NlwInverterSignal_tempID_0_D2_PT_0_IN7 : STD_LOGIC; + signal NlwInverterSignal_tempID_0_D2_PT_0_IN10 : STD_LOGIC; + signal NlwInverterSignal_tempID_0_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_tempID_0_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_tempID_0_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_tempID_0_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_tempID_0_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_tempID_0_D2_PT_1_IN6 : STD_LOGIC; + signal NlwInverterSignal_tempID_0_D2_PT_1_IN7 : STD_LOGIC; + signal NlwInverterSignal_tempID_0_D2_PT_1_IN9 : STD_LOGIC; + signal NlwInverterSignal_tempID_0_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_tempID_0_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_tempID_0_D2_PT_2_IN3 : STD_LOGIC; + signal NlwInverterSignal_tempID_0_D2_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_tempID_0_D2_PT_2_IN5 : STD_LOGIC; + signal NlwInverterSignal_tempID_0_D2_PT_2_IN6 : STD_LOGIC; + signal NlwInverterSignal_tempID_0_D2_PT_2_IN7 : STD_LOGIC; + signal NlwInverterSignal_tempID_0_D2_PT_2_IN10 : STD_LOGIC; + signal NlwInverterSignal_tempID_0_D2_PT_3_IN0 : STD_LOGIC; + signal NlwInverterSignal_tempID_0_D2_PT_3_IN1 : STD_LOGIC; + signal NlwInverterSignal_tempID_0_D2_PT_3_IN3 : STD_LOGIC; + signal NlwInverterSignal_tempID_0_D2_PT_3_IN4 : STD_LOGIC; + signal NlwInverterSignal_tempID_0_D2_PT_3_IN5 : STD_LOGIC; + signal NlwInverterSignal_tempID_0_D2_PT_3_IN6 : STD_LOGIC; + signal NlwInverterSignal_tempID_0_D2_PT_3_IN7 : STD_LOGIC; + signal NlwInverterSignal_tempID_0_D2_PT_3_IN9 : STD_LOGIC; + signal NlwInverterSignal_tempID_0_CLKF_IN0 : STD_LOGIC; + signal NlwInverterSignal_tempID_0_CLKF_IN1 : STD_LOGIC; + signal NlwInverterSignal_BUF_IS_EMPTY_OBUF_D2_IN1 : STD_LOGIC; + signal NlwInverterSignal_BUF_IS_EMPTY_OBUF_D2_IN2 : STD_LOGIC; + signal NlwInverterSignal_BUF_IS_EMPTY_OBUF_D2_IN3 : STD_LOGIC; + signal NlwInverterSignal_BUF_IS_EMPTY_OBUF_D2_IN4 : STD_LOGIC; + signal NlwInverterSignal_BUF_IS_EMPTY_OBUF_D2_IN5 : STD_LOGIC; + signal NlwInverterSignal_BUF_IS_EMPTY_OBUF_D2_IN6 : STD_LOGIC; + signal NlwInverterSignal_BUF_IS_EMPTY_OBUF_EXP_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_BUF_IS_EMPTY_OBUF_EXP_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_BUF_IS_EMPTY_OBUF_EXP_PT_3_IN0 : STD_LOGIC; + signal NlwInverterSignal_BUF_IS_EMPTY_OBUF_EXP_PT_3_IN1 : STD_LOGIC; + signal NlwInverterSignal_BUF_IS_EMPTY_OBUF_EXP_PT_3_IN2 : STD_LOGIC; + signal NlwInverterSignal_BUF_IS_EMPTY_OBUF_EXP_PT_3_IN3 : STD_LOGIC; + signal NlwInverterSignal_BUF_IS_EMPTY_OBUF_EXP_PT_3_IN4 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_EN_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_EN_SETF_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_EN_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_EN_RSTF_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_EN_RSTF_IN1 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_EN_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_EN_EXP_PT_0_IN2 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_EN_EXP_PT_0_IN4 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_EN_EXP_PT_0_IN6 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_EN_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_EN_EXP_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_EN_EXP_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_EN_EXP_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_next_state_0_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_next_state_0_SETF_IN0 : STD_LOGIC; + signal NlwInverterSignal_next_state_0_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_next_state_0_SETF_IN2 : STD_LOGIC; + signal NlwInverterSignal_next_state_0_SETF_IN3 : STD_LOGIC; + signal NlwInverterSignal_next_state_1_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; + signal NlwInverterSignal_next_state_1_SETF_IN1 : STD_LOGIC; + signal NlwInverterSignal_CCLK_OBUF_D_IN0 : STD_LOGIC; + signal NlwInverterSignal_CCLK_OBUF_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_CCLK_OBUF_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_CCLK_OBUF_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_CCLK_OBUF_EXP_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_CCLK_OBUF_EXP_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_CCLK_OBUF_EXP_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_CCLK_OBUF_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_CCLK_OBUF_EXP_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_CCLK_OBUF_EXP_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_CCLK_OBUF_EXP_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_CCLK_OBUF_EXP_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_CCLK_OBUF_EXP_PT_2_IN2 : STD_LOGIC; + signal NlwInverterSignal_CCLK_OBUF_EXP_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_CCLK_OBUF_EXP_PT_2_IN6 : STD_LOGIC; + signal NlwInverterSignal_CCLK_OBUF_EXP_PT_3_IN0 : STD_LOGIC; + signal NlwInverterSignal_CCLK_OBUF_EXP_PT_3_IN2 : STD_LOGIC; + signal NlwInverterSignal_CCLK_OBUF_EXP_PT_3_IN4 : STD_LOGIC; + signal NlwInverterSignal_CCLK_OBUF_EXP_PT_3_IN5 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_0_IN2 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_0_IN4 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_2_IN2 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_2_IN3 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_1_buf_depth_1_RSTF_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_buf_depth_1_buf_depth_1_RSTF_D2_PT_2_IN2 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_0_IN2 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_OpTx_FX_DC_19_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_OpTx_FX_DC_19_D2_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_OpTx_FX_DC_19_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_OpTx_FX_DC_19_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_OpTx_FX_DC_19_D2_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_OpTx_FX_DC_19_D2_PT_1_IN6 : STD_LOGIC; + signal NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_3_IN0 : STD_LOGIC; + signal NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_3_IN2 : STD_LOGIC; + signal NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_3_IN3 : STD_LOGIC; + signal NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_3_IN4 : STD_LOGIC; + signal NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_3_IN5 : STD_LOGIC; + signal NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_3_IN6 : STD_LOGIC; + signal NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_3_IN7 : STD_LOGIC; + signal NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_3_IN0 : STD_LOGIC; + signal NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_3_IN1 : STD_LOGIC; + signal NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_3_IN2 : STD_LOGIC; + signal NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_4_IN0 : STD_LOGIC; + signal NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_4_IN2 : STD_LOGIC; + signal NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_4_IN3 : STD_LOGIC; + signal NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_4_IN4 : STD_LOGIC; + signal NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_4_IN5 : STD_LOGIC; + signal NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_4_IN6 : STD_LOGIC; + signal NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_4_IN7 : STD_LOGIC; + signal NlwInverterSignal_EXP18_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP18_EXP_PT_0_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP18_EXP_PT_0_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP18_EXP_PT_0_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP18_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP18_EXP_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP18_EXP_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP18_EXP_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP19_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP19_EXP_PT_0_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP19_EXP_PT_0_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP19_EXP_PT_0_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP19_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP19_EXP_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP19_EXP_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP19_EXP_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP20_EXP_tsimrenamed_net_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP20_EXP_tsimrenamed_net_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP20_EXP_tsimrenamed_net_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP20_EXP_tsimrenamed_net_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP21_EXP_tsimrenamed_net_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP21_EXP_tsimrenamed_net_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP21_EXP_tsimrenamed_net_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP21_EXP_tsimrenamed_net_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP22_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP22_EXP_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_EXP22_EXP_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_EXP22_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP22_EXP_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_EXP22_EXP_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_EXP22_EXP_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP22_EXP_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP22_EXP_PT_2_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP22_EXP_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP22_EXP_PT_2_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP23_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP23_EXP_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_EXP23_EXP_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_EXP23_EXP_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP23_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP23_EXP_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_EXP23_EXP_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_EXP23_EXP_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP23_EXP_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP23_EXP_PT_2_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP23_EXP_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP23_EXP_PT_2_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP23_EXP_PT_3_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP23_EXP_PT_3_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP23_EXP_PT_3_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP23_EXP_PT_3_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP24_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP24_EXP_PT_0_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP24_EXP_PT_0_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP24_EXP_PT_0_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP24_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP24_EXP_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP24_EXP_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP24_EXP_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP25_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP25_EXP_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_EXP25_EXP_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_EXP25_EXP_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP25_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP25_EXP_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_EXP25_EXP_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_EXP25_EXP_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP25_EXP_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP25_EXP_PT_2_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP25_EXP_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP25_EXP_PT_2_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP25_EXP_PT_3_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP25_EXP_PT_3_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP25_EXP_PT_3_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP25_EXP_PT_3_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP26_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP26_EXP_PT_0_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP26_EXP_PT_0_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP26_EXP_PT_0_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP26_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP26_EXP_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP26_EXP_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP26_EXP_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP27_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP27_EXP_PT_0_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP27_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP27_EXP_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP28_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP28_EXP_PT_0_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP28_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP28_EXP_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP29_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP29_EXP_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_EXP29_EXP_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_EXP29_EXP_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP29_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP29_EXP_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP29_EXP_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP29_EXP_PT_1_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP29_EXP_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP29_EXP_PT_2_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP29_EXP_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP29_EXP_PT_2_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP30_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP30_EXP_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_EXP30_EXP_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_EXP30_EXP_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP30_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP30_EXP_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP30_EXP_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP30_EXP_PT_1_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP30_EXP_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP30_EXP_PT_2_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP30_EXP_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP30_EXP_PT_2_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP31_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP31_EXP_PT_0_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP31_EXP_PT_0_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP31_EXP_PT_0_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP31_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP31_EXP_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP31_EXP_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP31_EXP_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP32_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP32_EXP_PT_0_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP32_EXP_PT_0_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP32_EXP_PT_0_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP32_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP32_EXP_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP32_EXP_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP32_EXP_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP33_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP33_EXP_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_EXP33_EXP_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_EXP33_EXP_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP33_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP33_EXP_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP33_EXP_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP33_EXP_PT_1_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP33_EXP_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP33_EXP_PT_2_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP33_EXP_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP33_EXP_PT_2_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP34_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP34_EXP_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_EXP34_EXP_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_EXP34_EXP_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP34_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP34_EXP_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP34_EXP_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP34_EXP_PT_1_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP34_EXP_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP34_EXP_PT_2_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP34_EXP_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP34_EXP_PT_2_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP35_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP35_EXP_PT_0_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP35_EXP_PT_0_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP35_EXP_PT_0_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP35_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP35_EXP_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP35_EXP_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP35_EXP_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP36_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP36_EXP_PT_0_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP36_EXP_PT_0_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP36_EXP_PT_0_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP36_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP36_EXP_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP36_EXP_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP36_EXP_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP37_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP37_EXP_PT_0_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP37_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP37_EXP_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP38_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP38_EXP_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_EXP38_EXP_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP38_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP38_EXP_PT_1_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP38_EXP_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP38_EXP_PT_2_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP39_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP39_EXP_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_EXP39_EXP_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_EXP39_EXP_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP39_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP39_EXP_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP39_EXP_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP39_EXP_PT_1_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP39_EXP_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP39_EXP_PT_2_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP39_EXP_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP39_EXP_PT_2_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP40_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP40_EXP_PT_0_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP40_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP40_EXP_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP41_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP41_EXP_PT_0_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP41_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP41_EXP_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP42_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP42_EXP_PT_0_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP42_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP42_EXP_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP43_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP43_EXP_PT_0_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP43_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP43_EXP_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP44_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP44_EXP_PT_0_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP44_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP44_EXP_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP45_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP45_EXP_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_EXP45_EXP_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_EXP45_EXP_PT_0_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP45_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP45_EXP_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP45_EXP_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP45_EXP_PT_1_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP45_EXP_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP45_EXP_PT_2_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP45_EXP_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP45_EXP_PT_2_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP46_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP46_EXP_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_EXP46_EXP_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_EXP46_EXP_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP46_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP46_EXP_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP46_EXP_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP46_EXP_PT_1_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP46_EXP_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP46_EXP_PT_2_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP46_EXP_PT_2_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP46_EXP_PT_2_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP47_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP47_EXP_PT_0_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP47_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP47_EXP_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP48_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP48_EXP_PT_0_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP48_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP48_EXP_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP49_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP49_EXP_PT_0_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP49_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP49_EXP_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP50_EXP_tsimrenamed_net_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP50_EXP_tsimrenamed_net_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP51_EXP_tsimrenamed_net_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP51_EXP_tsimrenamed_net_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP52_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP52_EXP_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_EXP52_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP52_EXP_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP52_EXP_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP52_EXP_PT_2_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP53_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP53_EXP_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_EXP53_EXP_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP53_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP53_EXP_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_EXP53_EXP_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP53_EXP_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP53_EXP_PT_2_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP53_EXP_PT_3_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP53_EXP_PT_3_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP54_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP54_EXP_PT_0_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP54_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP54_EXP_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP55_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP55_EXP_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_EXP55_EXP_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP55_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP55_EXP_PT_1_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP55_EXP_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP55_EXP_PT_2_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP56_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP56_EXP_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_EXP56_EXP_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP56_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP56_EXP_PT_1_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP56_EXP_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP56_EXP_PT_2_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP57_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP57_EXP_PT_0_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP57_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP57_EXP_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP58_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP58_EXP_PT_0_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP58_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP58_EXP_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP59_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP59_EXP_PT_0_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP59_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP59_EXP_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP60_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP60_EXP_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_EXP60_EXP_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP60_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP60_EXP_PT_1_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP60_EXP_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP60_EXP_PT_2_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP61_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP61_EXP_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_EXP61_EXP_PT_0_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP61_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP61_EXP_PT_1_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP61_EXP_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP61_EXP_PT_2_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP62_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP62_EXP_PT_0_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP62_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP62_EXP_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP63_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP63_EXP_PT_0_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP63_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP63_EXP_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP64_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP64_EXP_PT_0_IN1 : STD_LOGIC; + signal NlwInverterSignal_EXP64_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP65_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP65_EXP_PT_0_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP65_EXP_PT_0_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP65_EXP_PT_0_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP65_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP65_EXP_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP65_EXP_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP65_EXP_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP66_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP66_EXP_PT_0_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP66_EXP_PT_0_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP66_EXP_PT_0_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP66_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP66_EXP_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP66_EXP_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP66_EXP_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP67_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP67_EXP_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_EXP67_EXP_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP68_EXP_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP68_EXP_PT_0_IN6 : STD_LOGIC; + signal NlwInverterSignal_EXP68_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP68_EXP_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP69_EXP_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_EXP69_EXP_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_EXP69_EXP_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_EXP69_EXP_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_EXP69_EXP_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_EXP69_EXP_PT_1_IN5 : STD_LOGIC; + signal NlwInverterSignal_EXP69_EXP_PT_1_IN6 : STD_LOGIC; + signal count : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal readBufId : STD_LOGIC_VECTOR ( 0 downto 0 ); + signal buf_depth : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal writeBufId : STD_LOGIC_VECTOR ( 0 downto 0 ); + signal SHIFT_CNT : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal CLK_SCALE : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal tempID : STD_LOGIC_VECTOR ( 0 downto 0 ); + signal state : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal next_state : STD_LOGIC_VECTOR ( 1 downto 0 ); +begin + FCLKIO_0_1 : X_BUF + port map ( + I => CLK, + O => FCLKIO_0 + ); + RES_IBUF_2 : X_BUF + port map ( + I => RES, + O => RES_IBUF + ); + LOAD_PRESCALER_IBUF_3 : X_BUF + port map ( + I => LOAD_PRESCALER, + O => LOAD_PRESCALER_IBUF + ); + LOAD_SREG_IBUF_4 : X_BUF + port map ( + I => LOAD_SREG, + O => LOAD_SREG_IBUF + ); + CCLK_PRESCALER_0_IBUF_5 : X_BUF + port map ( + I => CCLK_PRESCALER(0), + O => CCLK_PRESCALER_0_IBUF + ); + DIN_0_IBUF_6 : X_BUF + port map ( + I => DIN(0), + O => DIN_0_IBUF + ); + DIN_1_IBUF_7 : X_BUF + port map ( + I => DIN(1), + O => DIN_1_IBUF + ); + DIN_10_IBUF_8 : X_BUF + port map ( + I => DIN(10), + O => DIN_10_IBUF + ); + DIN_11_IBUF_9 : X_BUF + port map ( + I => DIN(11), + O => DIN_11_IBUF + ); + DIN_12_IBUF_10 : X_BUF + port map ( + I => DIN(12), + O => DIN_12_IBUF + ); + DIN_13_IBUF_11 : X_BUF + port map ( + I => DIN(13), + O => DIN_13_IBUF + ); + DIN_14_IBUF_12 : X_BUF + port map ( + I => DIN(14), + O => DIN_14_IBUF + ); + DIN_15_IBUF_13 : X_BUF + port map ( + I => DIN(15), + O => DIN_15_IBUF + ); + DIN_16_IBUF_14 : X_BUF + port map ( + I => DIN(16), + O => DIN_16_IBUF + ); + DIN_17_IBUF_15 : X_BUF + port map ( + I => DIN(17), + O => DIN_17_IBUF + ); + DIN_18_IBUF_16 : X_BUF + port map ( + I => DIN(18), + O => DIN_18_IBUF + ); + DIN_19_IBUF_17 : X_BUF + port map ( + I => DIN(19), + O => DIN_19_IBUF + ); + DIN_2_IBUF_18 : X_BUF + port map ( + I => DIN(2), + O => DIN_2_IBUF + ); + DIN_20_IBUF_19 : X_BUF + port map ( + I => DIN(20), + O => DIN_20_IBUF + ); + DIN_21_IBUF_20 : X_BUF + port map ( + I => DIN(21), + O => DIN_21_IBUF + ); + DIN_22_IBUF_21 : X_BUF + port map ( + I => DIN(22), + O => DIN_22_IBUF + ); + DIN_23_IBUF_22 : X_BUF + port map ( + I => DIN(23), + O => DIN_23_IBUF + ); + DIN_24_IBUF_23 : X_BUF + port map ( + I => DIN(24), + O => DIN_24_IBUF + ); + DIN_25_IBUF_24 : X_BUF + port map ( + I => DIN(25), + O => DIN_25_IBUF + ); + DIN_26_IBUF_25 : X_BUF + port map ( + I => DIN(26), + O => DIN_26_IBUF + ); + DIN_27_IBUF_26 : X_BUF + port map ( + I => DIN(27), + O => DIN_27_IBUF + ); + DIN_28_IBUF_27 : X_BUF + port map ( + I => DIN(28), + O => DIN_28_IBUF + ); + DIN_29_IBUF_28 : X_BUF + port map ( + I => DIN(29), + O => DIN_29_IBUF + ); + DIN_3_IBUF_29 : X_BUF + port map ( + I => DIN(3), + O => DIN_3_IBUF + ); + DIN_30_IBUF_30 : X_BUF + port map ( + I => DIN(30), + O => DIN_30_IBUF + ); + DIN_31_IBUF_31 : X_BUF + port map ( + I => DIN(31), + O => DIN_31_IBUF + ); + DIN_4_IBUF_32 : X_BUF + port map ( + I => DIN(4), + O => DIN_4_IBUF + ); + DIN_5_IBUF_33 : X_BUF + port map ( + I => DIN(5), + O => DIN_5_IBUF + ); + DIN_6_IBUF_34 : X_BUF + port map ( + I => DIN(6), + O => DIN_6_IBUF + ); + DIN_7_IBUF_35 : X_BUF + port map ( + I => DIN(7), + O => DIN_7_IBUF + ); + DIN_8_IBUF_36 : X_BUF + port map ( + I => DIN(8), + O => DIN_8_IBUF + ); + DIN_9_IBUF_37 : X_BUF + port map ( + I => DIN(9), + O => DIN_9_IBUF + ); + DONE_IBUF_38 : X_BUF + port map ( + I => DONE, + O => DONE_IBUF + ); + nINIT_B_IBUF_39 : X_BUF + port map ( + I => nINIT_B, + O => nINIT_B_IBUF + ); + CCLK_PRESCALER_1_IBUF_40 : X_BUF + port map ( + I => CCLK_PRESCALER(1), + O => CCLK_PRESCALER_1_IBUF + ); + CCLK_PRESCALER_2_IBUF_41 : X_BUF + port map ( + I => CCLK_PRESCALER(2), + O => CCLK_PRESCALER_2_IBUF + ); + CCLK_PRESCALER_3_IBUF_42 : X_BUF + port map ( + I => CCLK_PRESCALER(3), + O => CCLK_PRESCALER_3_IBUF + ); + CCLK_PRESCALER_4_IBUF_43 : X_BUF + port map ( + I => CCLK_PRESCALER(4), + O => CCLK_PRESCALER_4_IBUF + ); + CCLK_PRESCALER_5_IBUF_44 : X_BUF + port map ( + I => CCLK_PRESCALER(5), + O => CCLK_PRESCALER_5_IBUF + ); + DOUT_45 : X_TRI + port map ( + I => DOUT_OBUFE, + CTL => DOUT_OBUFE_OE, + O => DOUT + ); + BUF_IS_EMPTY_46 : X_BUF + port map ( + I => BUF_IS_EMPTY_OBUF_Q, + O => BUF_IS_EMPTY + ); + CCLK_47 : X_BUF + port map ( + I => CCLK_OBUF, + O => CCLK + ); + SCLK_48 : X_BUF + port map ( + I => SCLK_Q, + O => SCLK + ); + SCLK_tsimcreated_xor_Q_49 : X_XOR2 + port map ( + I0 => SCLK_D, + I1 => SCLK_Q, + O => SCLK_tsimcreated_xor_Q + ); + SCLK_REG : X_FF + port map ( + I => SCLK_tsimcreated_xor_Q, + CE => SCLK_CE, + CLK => FCLKIO_0, + SET => SCLK_SETF, + RST => PRLD, + O => SCLK_Q + ); + SCLK_D_50 : X_XOR2 + port map ( + I0 => SCLK_D1, + I1 => SCLK_D2, + O => SCLK_D + ); + SCLK_D1_51 : X_ZERO + port map ( + O => SCLK_D1 + ); + SCLK_D2_52 : X_ONE + port map ( + O => SCLK_D2 + ); + SCLK_SETF_53 : X_AND2 + port map ( + I0 => RES_IBUF, + I1 => RES_IBUF, + O => SCLK_SETF + ); + SCLK_CE_54 : X_AND7 + port map ( + I0 => NlwInverterSignal_SCLK_CE_IN0, + I1 => count(0), + I2 => NlwInverterSignal_SCLK_CE_IN2, + I3 => NlwInverterSignal_SCLK_CE_IN3, + I4 => NlwInverterSignal_SCLK_CE_IN4, + I5 => NlwInverterSignal_SCLK_CE_IN5, + I6 => NlwInverterSignal_SCLK_CE_IN6, + O => SCLK_CE + ); + readBufId_0_Q_55 : X_BUF + port map ( + I => readBufId_0_Q, + O => readBufId(0) + ); + readBufId_0_tsimcreated_prld_Q_56 : X_OR2 + port map ( + I0 => readBufId_0_RSTF, + I1 => PRLD, + O => readBufId_0_tsimcreated_prld_Q + ); + readBufId_0_REG : X_FF + port map ( + I => readBufId_0_D, + CE => readBufId_0_CE, + CLK => readBufId_0_CLKF, + SET => Gnd, + RST => readBufId_0_tsimcreated_prld_Q, + O => readBufId_0_Q + ); + Gnd_57 : X_ZERO + port map ( + O => Gnd + ); + readBufId_0_D_58 : X_XOR2 + port map ( + I0 => readBufId_0_D1, + I1 => readBufId_0_D2, + O => readBufId_0_D + ); + readBufId_0_D1_59 : X_ZERO + port map ( + O => readBufId_0_D1 + ); + readBufId_0_D2_PT_0_60 : X_AND2 + port map ( + I0 => buf_depth(0), + I1 => writeBufId(0), + O => readBufId_0_D2_PT_0 + ); + readBufId_0_D2_PT_1_61 : X_AND2 + port map ( + I0 => writeBufId(0), + I1 => buf_depth(1), + O => readBufId_0_D2_PT_1 + ); + readBufId_0_D2_62 : X_OR2 + port map ( + I0 => readBufId_0_D2_PT_0, + I1 => readBufId_0_D2_PT_1, + O => readBufId_0_D2 + ); + readBufId_0_CLKF_63 : X_AND2 + port map ( + I0 => NlwInverterSignal_readBufId_0_CLKF_IN0, + I1 => NlwInverterSignal_readBufId_0_CLKF_IN1, + O => readBufId_0_CLKF + ); + readBufId_0_RSTF_64 : X_AND2 + port map ( + I0 => RES_IBUF, + I1 => RES_IBUF, + O => readBufId_0_RSTF + ); + readBufId_0_CE_65 : X_AND7 + port map ( + I0 => NlwInverterSignal_readBufId_0_CE_IN0, + I1 => NlwInverterSignal_readBufId_0_CE_IN1, + I2 => NlwInverterSignal_readBufId_0_CE_IN2, + I3 => NlwInverterSignal_readBufId_0_CE_IN3, + I4 => NlwInverterSignal_readBufId_0_CE_IN4, + I5 => NlwInverterSignal_readBufId_0_CE_IN5, + I6 => SHIFT_EN, + O => readBufId_0_CE + ); + buf_depth_0_Q_66 : X_BUF + port map ( + I => buf_depth_0_Q, + O => buf_depth(0) + ); + buf_depth_0_tsimcreated_xor_Q_67 : X_XOR2 + port map ( + I0 => buf_depth_0_D, + I1 => buf_depth_0_Q, + O => buf_depth_0_tsimcreated_xor_Q + ); + buf_depth_0_tsimcreated_set_and_noreset_Q_68 : X_AND2 + port map ( + I0 => NlwInverterSignal_buf_depth_0_tsimcreated_set_and_noreset_IN0, + I1 => buf_depth_0_SETF, + O => buf_depth_0_tsimcreated_set_and_noreset_Q + ); + buf_depth_0_tsimcreated_prld_Q_69 : X_OR2 + port map ( + I0 => buf_depth_0_RSTF, + I1 => PRLD, + O => buf_depth_0_tsimcreated_prld_Q + ); + buf_depth_0_REG : X_FF + port map ( + I => buf_depth_0_tsimcreated_xor_Q, + CE => Vcc, + CLK => buf_depth_0_CLKF, + SET => buf_depth_0_tsimcreated_set_and_noreset_Q, + RST => buf_depth_0_tsimcreated_prld_Q, + O => buf_depth_0_Q + ); + Vcc_70 : X_ONE + port map ( + O => Vcc + ); + buf_depth_0_D_71 : X_XOR2 + port map ( + I0 => buf_depth_0_D1, + I1 => buf_depth_0_D2, + O => buf_depth_0_D + ); + buf_depth_0_D1_72 : X_ZERO + port map ( + O => buf_depth_0_D1 + ); + buf_depth_0_D2_PT_0_73 : X_AND7 + port map ( + I0 => buf_depth(0), + I1 => NlwInverterSignal_buf_depth_0_D2_PT_0_IN1, + I2 => NlwInverterSignal_buf_depth_0_D2_PT_0_IN2, + I3 => NlwInverterSignal_buf_depth_0_D2_PT_0_IN3, + I4 => NlwInverterSignal_buf_depth_0_D2_PT_0_IN4, + I5 => NlwInverterSignal_buf_depth_0_D2_PT_0_IN5, + I6 => SHIFT_EN, + O => buf_depth_0_D2_PT_0 + ); + buf_depth_0_D2_PT_1_74 : X_AND8 + port map ( + I0 => NlwInverterSignal_buf_depth_0_D2_PT_1_IN0, + I1 => buf_depth(1), + I2 => NlwInverterSignal_buf_depth_0_D2_PT_1_IN2, + I3 => NlwInverterSignal_buf_depth_0_D2_PT_1_IN3, + I4 => NlwInverterSignal_buf_depth_0_D2_PT_1_IN4, + I5 => NlwInverterSignal_buf_depth_0_D2_PT_1_IN5, + I6 => NlwInverterSignal_buf_depth_0_D2_PT_1_IN6, + I7 => SHIFT_EN, + O => buf_depth_0_D2_PT_1 + ); + buf_depth_0_D2_75 : X_OR2 + port map ( + I0 => buf_depth_0_D2_PT_0, + I1 => buf_depth_0_D2_PT_1, + O => buf_depth_0_D2 + ); + buf_depth_0_CLKF_76 : X_AND2 + port map ( + I0 => NlwInverterSignal_buf_depth_0_CLKF_IN0, + I1 => NlwInverterSignal_buf_depth_0_CLKF_IN1, + O => buf_depth_0_CLKF + ); + buf_depth_0_SETF_77 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_buf_depth_0_SETF_IN1, + I2 => NlwInverterSignal_buf_depth_0_SETF_IN2, + O => buf_depth_0_SETF + ); + buf_depth_0_RSTF_78 : X_AND2 + port map ( + I0 => buf_depth_0_buf_depth_0_RSTF_UIM, + I1 => buf_depth_0_buf_depth_0_RSTF_UIM, + O => buf_depth_0_RSTF + ); + buf_depth_1_Q_79 : X_BUF + port map ( + I => buf_depth_1_Q, + O => buf_depth(1) + ); + buf_depth_1_tsimcreated_xor_Q_80 : X_XOR2 + port map ( + I0 => buf_depth_1_D, + I1 => buf_depth_1_Q, + O => buf_depth_1_tsimcreated_xor_Q + ); + buf_depth_1_tsimcreated_set_and_noreset_Q_81 : X_AND2 + port map ( + I0 => NlwInverterSignal_buf_depth_1_tsimcreated_set_and_noreset_IN0, + I1 => buf_depth_1_SETF, + O => buf_depth_1_tsimcreated_set_and_noreset_Q + ); + buf_depth_1_tsimcreated_prld_Q_82 : X_OR2 + port map ( + I0 => buf_depth_1_RSTF, + I1 => PRLD, + O => buf_depth_1_tsimcreated_prld_Q + ); + buf_depth_1_REG : X_FF + port map ( + I => buf_depth_1_tsimcreated_xor_Q, + CE => Vcc, + CLK => buf_depth_1_CLKF, + SET => buf_depth_1_tsimcreated_set_and_noreset_Q, + RST => buf_depth_1_tsimcreated_prld_Q, + O => buf_depth_1_Q + ); + buf_depth_1_D_83 : X_XOR2 + port map ( + I0 => buf_depth_1_D1, + I1 => buf_depth_1_D2, + O => buf_depth_1_D + ); + buf_depth_1_D1_84 : X_ZERO + port map ( + O => buf_depth_1_D1 + ); + buf_depth_1_D2_PT_0_85 : X_AND8 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => buf_depth(0), + I2 => NlwInverterSignal_buf_depth_1_D2_PT_0_IN2, + I3 => NlwInverterSignal_buf_depth_1_D2_PT_0_IN3, + I4 => NlwInverterSignal_buf_depth_1_D2_PT_0_IN4, + I5 => NlwInverterSignal_buf_depth_1_D2_PT_0_IN5, + I6 => NlwInverterSignal_buf_depth_1_D2_PT_0_IN6, + I7 => SHIFT_EN, + O => buf_depth_1_D2_PT_0 + ); + buf_depth_1_D2_PT_1_86 : X_AND16 + port map ( + I0 => NlwInverterSignal_buf_depth_1_D2_PT_1_IN0, + I1 => NlwInverterSignal_buf_depth_1_D2_PT_1_IN1, + I2 => buf_depth(1), + I3 => NlwInverterSignal_buf_depth_1_D2_PT_1_IN3, + I4 => NlwInverterSignal_buf_depth_1_D2_PT_1_IN4, + I5 => NlwInverterSignal_buf_depth_1_D2_PT_1_IN5, + I6 => NlwInverterSignal_buf_depth_1_D2_PT_1_IN6, + I7 => NlwInverterSignal_buf_depth_1_D2_PT_1_IN7, + I8 => SHIFT_EN, + I9 => Vcc, + I10 => Vcc, + I11 => Vcc, + I12 => Vcc, + I13 => Vcc, + I14 => Vcc, + I15 => Vcc, + O => buf_depth_1_D2_PT_1 + ); + buf_depth_1_D2_87 : X_OR2 + port map ( + I0 => buf_depth_1_D2_PT_0, + I1 => buf_depth_1_D2_PT_1, + O => buf_depth_1_D2 + ); + buf_depth_1_CLKF_88 : X_AND2 + port map ( + I0 => NlwInverterSignal_buf_depth_1_CLKF_IN0, + I1 => NlwInverterSignal_buf_depth_1_CLKF_IN1, + O => buf_depth_1_CLKF + ); + buf_depth_1_SETF_89 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => buf_depth(0), + I2 => NlwInverterSignal_buf_depth_1_SETF_IN2, + O => buf_depth_1_SETF + ); + buf_depth_1_RSTF_90 : X_AND2 + port map ( + I0 => buf_depth_1_buf_depth_1_RSTF_UIM, + I1 => buf_depth_1_buf_depth_1_RSTF_UIM, + O => buf_depth_1_RSTF + ); + SHIFT_CNT_0_Q_91 : X_BUF + port map ( + I => SHIFT_CNT_0_Q, + O => SHIFT_CNT(0) + ); + SHIFT_CNT_0_EXP_92 : X_BUF + port map ( + I => SHIFT_CNT_0_EXP_tsimrenamed_net_Q, + O => SHIFT_CNT_0_EXP + ); + SHIFT_CNT_0_tsimcreated_xor_Q_93 : X_XOR2 + port map ( + I0 => SHIFT_CNT_0_D, + I1 => SHIFT_CNT_0_Q, + O => SHIFT_CNT_0_tsimcreated_xor_Q + ); + SHIFT_CNT_0_tsimcreated_set_and_noreset_Q_94 : X_AND2 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_0_tsimcreated_set_and_noreset_IN0, + I1 => SHIFT_CNT_0_SETF, + O => SHIFT_CNT_0_tsimcreated_set_and_noreset_Q + ); + SHIFT_CNT_0_tsimcreated_prld_Q_95 : X_OR2 + port map ( + I0 => SHIFT_CNT_0_RSTF, + I1 => PRLD, + O => SHIFT_CNT_0_tsimcreated_prld_Q + ); + SHIFT_CNT_0_REG : X_FF + port map ( + I => SHIFT_CNT_0_tsimcreated_xor_Q, + CE => Vcc, + CLK => SHIFT_CNT_0_CLKF, + SET => SHIFT_CNT_0_tsimcreated_set_and_noreset_Q, + RST => SHIFT_CNT_0_tsimcreated_prld_Q, + O => SHIFT_CNT_0_Q + ); + SHIFT_CNT_0_D_96 : X_XOR2 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_0_D_IN0, + I1 => SHIFT_CNT_0_D2, + O => SHIFT_CNT_0_D + ); + SHIFT_CNT_0_D1_97 : X_ZERO + port map ( + O => SHIFT_CNT_0_D1 + ); + SHIFT_CNT_0_D2_PT_0_98 : X_AND2 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_0_D2_PT_0_IN0, + I1 => NlwInverterSignal_SHIFT_CNT_0_D2_PT_0_IN1, + O => SHIFT_CNT_0_D2_PT_0 + ); + SHIFT_CNT_0_D2_PT_1_99 : X_AND2 + port map ( + I0 => EXP69_EXP, + I1 => EXP69_EXP, + O => SHIFT_CNT_0_D2_PT_1 + ); + SHIFT_CNT_0_D2_100 : X_OR2 + port map ( + I0 => SHIFT_CNT_0_D2_PT_0, + I1 => SHIFT_CNT_0_D2_PT_1, + O => SHIFT_CNT_0_D2 + ); + SHIFT_CNT_0_CLKF_101 : X_AND2 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_0_CLKF_IN0, + I1 => NlwInverterSignal_SHIFT_CNT_0_CLKF_IN1, + O => SHIFT_CNT_0_CLKF + ); + SHIFT_CNT_0_SETF_102 : X_AND2 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_SHIFT_CNT_0_SETF_IN1, + O => SHIFT_CNT_0_SETF + ); + SHIFT_CNT_0_RSTF_103 : X_AND2 + port map ( + I0 => RES_IBUF, + I1 => RES_IBUF, + O => SHIFT_CNT_0_RSTF + ); + SHIFT_CNT_0_EXP_tsimrenamed_net_Q_104 : X_AND7 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_0_EXP_tsimrenamed_net_IN0, + I1 => NlwInverterSignal_SHIFT_CNT_0_EXP_tsimrenamed_net_IN1, + I2 => NlwInverterSignal_SHIFT_CNT_0_EXP_tsimrenamed_net_IN2, + I3 => NlwInverterSignal_SHIFT_CNT_0_EXP_tsimrenamed_net_IN3, + I4 => NlwInverterSignal_SHIFT_CNT_0_EXP_tsimrenamed_net_IN4, + I5 => SHIFT_CNT(4), + I6 => SHIFT_EN, + O => SHIFT_CNT_0_EXP_tsimrenamed_net_Q + ); + count_0_Q_105 : X_BUF + port map ( + I => count_0_Q, + O => count(0) + ); + count_0_EXP_106 : X_BUF + port map ( + I => count_0_EXP_tsimrenamed_net_Q, + O => count_0_EXP + ); + count_0_tsimcreated_set_and_noreset_Q_107 : X_AND2 + port map ( + I0 => NlwInverterSignal_count_0_tsimcreated_set_and_noreset_IN0, + I1 => count_0_SETF, + O => count_0_tsimcreated_set_and_noreset_Q + ); + count_0_tsimcreated_prld_Q_108 : X_OR2 + port map ( + I0 => count_0_RSTF, + I1 => PRLD, + O => count_0_tsimcreated_prld_Q + ); + count_0_REG : X_FF + port map ( + I => count_0_D, + CE => Vcc, + CLK => FCLKIO_0, + SET => count_0_tsimcreated_set_and_noreset_Q, + RST => count_0_tsimcreated_prld_Q, + O => count_0_Q + ); + count_0_D_109 : X_XOR2 + port map ( + I0 => count_0_D1, + I1 => count_0_D2, + O => count_0_D + ); + count_0_D1_110 : X_ZERO + port map ( + O => count_0_D1 + ); + count_0_D2_PT_0_111 : X_AND2 + port map ( + I0 => EXP67_EXP, + I1 => EXP67_EXP, + O => count_0_D2_PT_0 + ); + count_0_D2_PT_1_112 : X_AND3 + port map ( + I0 => RES_IBUF, + I1 => NlwInverterSignal_count_0_D2_PT_1_IN1, + I2 => CLK_SCALE(0), + O => count_0_D2_PT_1 + ); + count_0_D2_PT_2_113 : X_AND7 + port map ( + I0 => NlwInverterSignal_count_0_D2_PT_2_IN0, + I1 => NlwInverterSignal_count_0_D2_PT_2_IN1, + I2 => NlwInverterSignal_count_0_D2_PT_2_IN2, + I3 => NlwInverterSignal_count_0_D2_PT_2_IN3, + I4 => NlwInverterSignal_count_0_D2_PT_2_IN4, + I5 => NlwInverterSignal_count_0_D2_PT_2_IN5, + I6 => CLK_SCALE(0), + O => count_0_D2_PT_2 + ); + count_0_D2_114 : X_OR3 + port map ( + I0 => count_0_D2_PT_0, + I1 => count_0_D2_PT_1, + I2 => count_0_D2_PT_2, + O => count_0_D2 + ); + count_0_SETF_115 : X_AND2 + port map ( + I0 => RES_IBUF, + I1 => CLK_SCALE(0), + O => count_0_SETF + ); + count_0_RSTF_116 : X_AND2 + port map ( + I0 => RES_IBUF, + I1 => NlwInverterSignal_count_0_RSTF_IN1, + O => count_0_RSTF + ); + count_0_EXP_tsimrenamed_net_Q_117 : X_AND4 + port map ( + I0 => RES_IBUF, + I1 => NlwInverterSignal_count_0_EXP_tsimrenamed_net_IN1, + I2 => count(2), + I3 => NlwInverterSignal_count_0_EXP_tsimrenamed_net_IN3, + O => count_0_EXP_tsimrenamed_net_Q + ); + count_4_Q_118 : X_BUF + port map ( + I => count_4_Q, + O => count(4) + ); + count_4_EXP_119 : X_BUF + port map ( + I => count_4_EXP_tsimrenamed_net_Q, + O => count_4_EXP + ); + count_4_tsimcreated_xor_Q_120 : X_XOR2 + port map ( + I0 => count_4_D, + I1 => count_4_Q, + O => count_4_tsimcreated_xor_Q + ); + count_4_tsimcreated_set_and_noreset_Q_121 : X_AND2 + port map ( + I0 => NlwInverterSignal_count_4_tsimcreated_set_and_noreset_IN0, + I1 => count_4_SETF, + O => count_4_tsimcreated_set_and_noreset_Q + ); + count_4_tsimcreated_prld_Q_122 : X_OR2 + port map ( + I0 => count_4_RSTF, + I1 => PRLD, + O => count_4_tsimcreated_prld_Q + ); + count_4_REG : X_FF + port map ( + I => count_4_tsimcreated_xor_Q, + CE => Vcc, + CLK => FCLKIO_0, + SET => count_4_tsimcreated_set_and_noreset_Q, + RST => count_4_tsimcreated_prld_Q, + O => count_4_Q + ); + count_4_D_123 : X_XOR2 + port map ( + I0 => count_4_D1, + I1 => count_4_D2, + O => count_4_D + ); + count_4_D1_124 : X_ZERO + port map ( + O => count_4_D1 + ); + count_4_D2_PT_0_125 : X_AND2 + port map ( + I0 => CLK_SCALE_0_EXP, + I1 => CLK_SCALE_0_EXP, + O => count_4_D2_PT_0 + ); + count_4_D2_PT_1_126 : X_AND6 + port map ( + I0 => NlwInverterSignal_count_4_D2_PT_1_IN0, + I1 => NlwInverterSignal_count_4_D2_PT_1_IN1, + I2 => NlwInverterSignal_count_4_D2_PT_1_IN2, + I3 => NlwInverterSignal_count_4_D2_PT_1_IN3, + I4 => NlwInverterSignal_count_4_D2_PT_1_IN4, + I5 => NlwInverterSignal_count_4_D2_PT_1_IN5, + O => count_4_D2_PT_1 + ); + count_4_D2_PT_2_127 : X_AND7 + port map ( + I0 => NlwInverterSignal_count_4_D2_PT_2_IN0, + I1 => NlwInverterSignal_count_4_D2_PT_2_IN1, + I2 => NlwInverterSignal_count_4_D2_PT_2_IN2, + I3 => NlwInverterSignal_count_4_D2_PT_2_IN3, + I4 => NlwInverterSignal_count_4_D2_PT_2_IN4, + I5 => NlwInverterSignal_count_4_D2_PT_2_IN5, + I6 => CLK_SCALE(4), + O => count_4_D2_PT_2 + ); + count_4_D2_128 : X_OR3 + port map ( + I0 => count_4_D2_PT_0, + I1 => count_4_D2_PT_1, + I2 => count_4_D2_PT_2, + O => count_4_D2 + ); + count_4_SETF_129 : X_AND2 + port map ( + I0 => RES_IBUF, + I1 => CLK_SCALE(4), + O => count_4_SETF + ); + count_4_RSTF_130 : X_AND2 + port map ( + I0 => RES_IBUF, + I1 => NlwInverterSignal_count_4_RSTF_IN1, + O => count_4_RSTF + ); + count_4_EXP_tsimrenamed_net_Q_131 : X_AND4 + port map ( + I0 => RES_IBUF, + I1 => NlwInverterSignal_count_4_EXP_tsimrenamed_net_IN1, + I2 => count(3), + I3 => NlwInverterSignal_count_4_EXP_tsimrenamed_net_IN3, + O => count_4_EXP_tsimrenamed_net_Q + ); + SHIFT_CNT_1_Q_132 : X_BUF + port map ( + I => SHIFT_CNT_1_Q, + O => SHIFT_CNT(1) + ); + SHIFT_CNT_1_tsimcreated_xor_Q_133 : X_XOR2 + port map ( + I0 => SHIFT_CNT_1_D, + I1 => SHIFT_CNT_1_Q, + O => SHIFT_CNT_1_tsimcreated_xor_Q + ); + SHIFT_CNT_1_tsimcreated_set_and_noreset_Q_134 : X_AND2 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_1_tsimcreated_set_and_noreset_IN0, + I1 => SHIFT_CNT_1_SETF, + O => SHIFT_CNT_1_tsimcreated_set_and_noreset_Q + ); + SHIFT_CNT_1_tsimcreated_prld_Q_135 : X_OR2 + port map ( + I0 => SHIFT_CNT_1_RSTF, + I1 => PRLD, + O => SHIFT_CNT_1_tsimcreated_prld_Q + ); + SHIFT_CNT_1_REG : X_FF + port map ( + I => SHIFT_CNT_1_tsimcreated_xor_Q, + CE => Vcc, + CLK => SHIFT_CNT_1_CLKF, + SET => SHIFT_CNT_1_tsimcreated_set_and_noreset_Q, + RST => SHIFT_CNT_1_tsimcreated_prld_Q, + O => SHIFT_CNT_1_Q + ); + SHIFT_CNT_1_D_136 : X_XOR2 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_1_D_IN0, + I1 => SHIFT_CNT_1_D2, + O => SHIFT_CNT_1_D + ); + SHIFT_CNT_1_D1_137 : X_ZERO + port map ( + O => SHIFT_CNT_1_D1 + ); + SHIFT_CNT_1_D2_PT_0_138 : X_AND2 + port map ( + I0 => SHIFT_CNT(0), + I1 => SHIFT_CNT(0), + O => SHIFT_CNT_1_D2_PT_0 + ); + SHIFT_CNT_1_D2_PT_1_139 : X_AND2 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_1_D2_PT_1_IN0, + I1 => NlwInverterSignal_SHIFT_CNT_1_D2_PT_1_IN1, + O => SHIFT_CNT_1_D2_PT_1 + ); + SHIFT_CNT_1_D2_PT_2_140 : X_AND2 + port map ( + I0 => SHIFT_CNT_2_EXP, + I1 => SHIFT_CNT_2_EXP, + O => SHIFT_CNT_1_D2_PT_2 + ); + SHIFT_CNT_1_D2_PT_3_141 : X_AND2 + port map ( + I0 => SHIFT_CNT_3_EXP, + I1 => SHIFT_CNT_3_EXP, + O => SHIFT_CNT_1_D2_PT_3 + ); + SHIFT_CNT_1_D2_142 : X_OR4 + port map ( + I0 => SHIFT_CNT_1_D2_PT_0, + I1 => SHIFT_CNT_1_D2_PT_1, + I2 => SHIFT_CNT_1_D2_PT_2, + I3 => SHIFT_CNT_1_D2_PT_3, + O => SHIFT_CNT_1_D2 + ); + SHIFT_CNT_1_CLKF_143 : X_AND2 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_1_CLKF_IN0, + I1 => NlwInverterSignal_SHIFT_CNT_1_CLKF_IN1, + O => SHIFT_CNT_1_CLKF + ); + SHIFT_CNT_1_SETF_144 : X_AND2 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_SHIFT_CNT_1_SETF_IN1, + O => SHIFT_CNT_1_SETF + ); + SHIFT_CNT_1_RSTF_145 : X_AND2 + port map ( + I0 => RES_IBUF, + I1 => RES_IBUF, + O => SHIFT_CNT_1_RSTF + ); + SHIFT_CNT_2_Q_146 : X_BUF + port map ( + I => SHIFT_CNT_2_Q, + O => SHIFT_CNT(2) + ); + SHIFT_CNT_2_EXP_147 : X_BUF + port map ( + I => SHIFT_CNT_2_EXP_tsimrenamed_net_Q, + O => SHIFT_CNT_2_EXP + ); + SHIFT_CNT_2_tsimcreated_xor_Q_148 : X_XOR2 + port map ( + I0 => SHIFT_CNT_2_D, + I1 => SHIFT_CNT_2_Q, + O => SHIFT_CNT_2_tsimcreated_xor_Q + ); + SHIFT_CNT_2_tsimcreated_set_and_noreset_Q_149 : X_AND2 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_2_tsimcreated_set_and_noreset_IN0, + I1 => SHIFT_CNT_2_SETF, + O => SHIFT_CNT_2_tsimcreated_set_and_noreset_Q + ); + SHIFT_CNT_2_tsimcreated_prld_Q_150 : X_OR2 + port map ( + I0 => SHIFT_CNT_2_RSTF, + I1 => PRLD, + O => SHIFT_CNT_2_tsimcreated_prld_Q + ); + SHIFT_CNT_2_REG : X_FF + port map ( + I => SHIFT_CNT_2_tsimcreated_xor_Q, + CE => Vcc, + CLK => SHIFT_CNT_2_CLKF, + SET => SHIFT_CNT_2_tsimcreated_set_and_noreset_Q, + RST => SHIFT_CNT_2_tsimcreated_prld_Q, + O => SHIFT_CNT_2_Q + ); + SHIFT_CNT_2_D_151 : X_XOR2 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_2_D_IN0, + I1 => SHIFT_CNT_2_D2, + O => SHIFT_CNT_2_D + ); + SHIFT_CNT_2_D1_152 : X_ZERO + port map ( + O => SHIFT_CNT_2_D1 + ); + SHIFT_CNT_2_D2_PT_0_153 : X_AND2 + port map ( + I0 => SHIFT_CNT(0), + I1 => SHIFT_CNT(0), + O => SHIFT_CNT_2_D2_PT_0 + ); + SHIFT_CNT_2_D2_PT_1_154 : X_AND2 + port map ( + I0 => BUF_IS_EMPTY_OBUF_EXP, + I1 => BUF_IS_EMPTY_OBUF_EXP, + O => SHIFT_CNT_2_D2_PT_1 + ); + SHIFT_CNT_2_D2_155 : X_OR2 + port map ( + I0 => SHIFT_CNT_2_D2_PT_0, + I1 => SHIFT_CNT_2_D2_PT_1, + O => SHIFT_CNT_2_D2 + ); + SHIFT_CNT_2_CLKF_156 : X_AND2 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_2_CLKF_IN0, + I1 => NlwInverterSignal_SHIFT_CNT_2_CLKF_IN1, + O => SHIFT_CNT_2_CLKF + ); + SHIFT_CNT_2_SETF_157 : X_AND2 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_SHIFT_CNT_2_SETF_IN1, + O => SHIFT_CNT_2_SETF + ); + SHIFT_CNT_2_RSTF_158 : X_AND2 + port map ( + I0 => RES_IBUF, + I1 => RES_IBUF, + O => SHIFT_CNT_2_RSTF + ); + SHIFT_CNT_2_EXP_tsimrenamed_net_Q_159 : X_AND6 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_2_EXP_tsimrenamed_net_IN0, + I1 => NlwInverterSignal_SHIFT_CNT_2_EXP_tsimrenamed_net_IN1, + I2 => NlwInverterSignal_SHIFT_CNT_2_EXP_tsimrenamed_net_IN2, + I3 => NlwInverterSignal_SHIFT_CNT_2_EXP_tsimrenamed_net_IN3, + I4 => NlwInverterSignal_SHIFT_CNT_2_EXP_tsimrenamed_net_IN4, + I5 => NlwInverterSignal_SHIFT_CNT_2_EXP_tsimrenamed_net_IN5, + O => SHIFT_CNT_2_EXP_tsimrenamed_net_Q + ); + SHIFT_CNT_3_Q_160 : X_BUF + port map ( + I => SHIFT_CNT_3_Q, + O => SHIFT_CNT(3) + ); + SHIFT_CNT_3_EXP_161 : X_BUF + port map ( + I => SHIFT_CNT_3_EXP_tsimrenamed_net_Q, + O => SHIFT_CNT_3_EXP + ); + SHIFT_CNT_3_tsimcreated_xor_Q_162 : X_XOR2 + port map ( + I0 => SHIFT_CNT_3_D, + I1 => SHIFT_CNT_3_Q, + O => SHIFT_CNT_3_tsimcreated_xor_Q + ); + SHIFT_CNT_3_tsimcreated_set_and_noreset_Q_163 : X_AND2 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_3_tsimcreated_set_and_noreset_IN0, + I1 => SHIFT_CNT_3_SETF, + O => SHIFT_CNT_3_tsimcreated_set_and_noreset_Q + ); + SHIFT_CNT_3_tsimcreated_prld_Q_164 : X_OR2 + port map ( + I0 => SHIFT_CNT_3_RSTF, + I1 => PRLD, + O => SHIFT_CNT_3_tsimcreated_prld_Q + ); + SHIFT_CNT_3_REG : X_FF + port map ( + I => SHIFT_CNT_3_tsimcreated_xor_Q, + CE => Vcc, + CLK => SHIFT_CNT_3_CLKF, + SET => SHIFT_CNT_3_tsimcreated_set_and_noreset_Q, + RST => SHIFT_CNT_3_tsimcreated_prld_Q, + O => SHIFT_CNT_3_Q + ); + SHIFT_CNT_3_D_165 : X_XOR2 + port map ( + I0 => SHIFT_CNT_3_D1, + I1 => SHIFT_CNT_3_D2, + O => SHIFT_CNT_3_D + ); + SHIFT_CNT_3_D1_166 : X_ZERO + port map ( + O => SHIFT_CNT_3_D1 + ); + SHIFT_CNT_3_D2_PT_0_167 : X_AND2 + port map ( + I0 => buf_depth_0_buf_depth_0_RSTF_EXP, + I1 => buf_depth_0_buf_depth_0_RSTF_EXP, + O => SHIFT_CNT_3_D2_PT_0 + ); + SHIFT_CNT_3_D2_PT_1_168 : X_AND6 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_3_D2_PT_1_IN0, + I1 => NlwInverterSignal_SHIFT_CNT_3_D2_PT_1_IN1, + I2 => NlwInverterSignal_SHIFT_CNT_3_D2_PT_1_IN2, + I3 => NlwInverterSignal_SHIFT_CNT_3_D2_PT_1_IN3, + I4 => SHIFT_CNT(3), + I5 => SHIFT_EN, + O => SHIFT_CNT_3_D2_PT_1 + ); + SHIFT_CNT_3_D2_169 : X_OR2 + port map ( + I0 => SHIFT_CNT_3_D2_PT_0, + I1 => SHIFT_CNT_3_D2_PT_1, + O => SHIFT_CNT_3_D2 + ); + SHIFT_CNT_3_CLKF_170 : X_AND2 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_3_CLKF_IN0, + I1 => NlwInverterSignal_SHIFT_CNT_3_CLKF_IN1, + O => SHIFT_CNT_3_CLKF + ); + SHIFT_CNT_3_SETF_171 : X_AND2 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_SHIFT_CNT_3_SETF_IN1, + O => SHIFT_CNT_3_SETF + ); + SHIFT_CNT_3_RSTF_172 : X_AND2 + port map ( + I0 => RES_IBUF, + I1 => RES_IBUF, + O => SHIFT_CNT_3_RSTF + ); + SHIFT_CNT_3_EXP_tsimrenamed_net_Q_173 : X_AND2 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => LOAD_SREG_IBUF, + O => SHIFT_CNT_3_EXP_tsimrenamed_net_Q + ); + count_1_Q_174 : X_BUF + port map ( + I => count_1_Q, + O => count(1) + ); + count_1_tsimcreated_xor_Q_175 : X_XOR2 + port map ( + I0 => count_1_D, + I1 => count_1_Q, + O => count_1_tsimcreated_xor_Q + ); + count_1_tsimcreated_set_and_noreset_Q_176 : X_AND2 + port map ( + I0 => NlwInverterSignal_count_1_tsimcreated_set_and_noreset_IN0, + I1 => count_1_SETF, + O => count_1_tsimcreated_set_and_noreset_Q + ); + count_1_tsimcreated_prld_Q_177 : X_OR2 + port map ( + I0 => count_1_RSTF, + I1 => PRLD, + O => count_1_tsimcreated_prld_Q + ); + count_1_REG : X_FF + port map ( + I => count_1_tsimcreated_xor_Q, + CE => Vcc, + CLK => FCLKIO_0, + SET => count_1_tsimcreated_set_and_noreset_Q, + RST => count_1_tsimcreated_prld_Q, + O => count_1_Q + ); + count_1_D_178 : X_XOR2 + port map ( + I0 => count_1_D1, + I1 => count_1_D2, + O => count_1_D + ); + count_1_D1_179 : X_ZERO + port map ( + O => count_1_D1 + ); + count_1_D2_PT_0_180 : X_AND2 + port map ( + I0 => CLK_SCALE_1_EXP, + I1 => CLK_SCALE_1_EXP, + O => count_1_D2_PT_0 + ); + count_1_D2_PT_1_181 : X_AND3 + port map ( + I0 => NlwInverterSignal_count_1_D2_PT_1_IN0, + I1 => NlwInverterSignal_count_1_D2_PT_1_IN1, + I2 => NlwInverterSignal_count_1_D2_PT_1_IN2, + O => count_1_D2_PT_1 + ); + count_1_D2_PT_2_182 : X_AND4 + port map ( + I0 => RES_IBUF, + I1 => NlwInverterSignal_count_1_D2_PT_2_IN1, + I2 => NlwInverterSignal_count_1_D2_PT_2_IN2, + I3 => CLK_SCALE(1), + O => count_1_D2_PT_2 + ); + count_1_D2_PT_3_183 : X_AND7 + port map ( + I0 => NlwInverterSignal_count_1_D2_PT_3_IN0, + I1 => NlwInverterSignal_count_1_D2_PT_3_IN1, + I2 => NlwInverterSignal_count_1_D2_PT_3_IN2, + I3 => NlwInverterSignal_count_1_D2_PT_3_IN3, + I4 => NlwInverterSignal_count_1_D2_PT_3_IN4, + I5 => NlwInverterSignal_count_1_D2_PT_3_IN5, + I6 => CLK_SCALE(1), + O => count_1_D2_PT_3 + ); + count_1_D2_184 : X_OR4 + port map ( + I0 => count_1_D2_PT_0, + I1 => count_1_D2_PT_1, + I2 => count_1_D2_PT_2, + I3 => count_1_D2_PT_3, + O => count_1_D2 + ); + count_1_SETF_185 : X_AND2 + port map ( + I0 => RES_IBUF, + I1 => CLK_SCALE(1), + O => count_1_SETF + ); + count_1_RSTF_186 : X_AND2 + port map ( + I0 => RES_IBUF, + I1 => NlwInverterSignal_count_1_RSTF_IN1, + O => count_1_RSTF + ); + count_2_Q_187 : X_BUF + port map ( + I => count_2_Q, + O => count(2) + ); + count_2_tsimcreated_xor_Q_188 : X_XOR2 + port map ( + I0 => count_2_D, + I1 => count_2_Q, + O => count_2_tsimcreated_xor_Q + ); + count_2_tsimcreated_set_and_noreset_Q_189 : X_AND2 + port map ( + I0 => NlwInverterSignal_count_2_tsimcreated_set_and_noreset_IN0, + I1 => count_2_SETF, + O => count_2_tsimcreated_set_and_noreset_Q + ); + count_2_tsimcreated_prld_Q_190 : X_OR2 + port map ( + I0 => count_2_RSTF, + I1 => PRLD, + O => count_2_tsimcreated_prld_Q + ); + count_2_REG : X_FF + port map ( + I => count_2_tsimcreated_xor_Q, + CE => Vcc, + CLK => FCLKIO_0, + SET => count_2_tsimcreated_set_and_noreset_Q, + RST => count_2_tsimcreated_prld_Q, + O => count_2_Q + ); + count_2_D_191 : X_XOR2 + port map ( + I0 => count_2_D1, + I1 => count_2_D2, + O => count_2_D + ); + count_2_D1_192 : X_ZERO + port map ( + O => count_2_D1 + ); + count_2_D2_PT_0_193 : X_AND2 + port map ( + I0 => count_0_EXP, + I1 => count_0_EXP, + O => count_2_D2_PT_0 + ); + count_2_D2_PT_1_194 : X_AND4 + port map ( + I0 => RES_IBUF, + I1 => NlwInverterSignal_count_2_D2_PT_1_IN1, + I2 => NlwInverterSignal_count_2_D2_PT_1_IN2, + I3 => CLK_SCALE(2), + O => count_2_D2_PT_1 + ); + count_2_D2_PT_2_195 : X_AND4 + port map ( + I0 => NlwInverterSignal_count_2_D2_PT_2_IN0, + I1 => NlwInverterSignal_count_2_D2_PT_2_IN1, + I2 => NlwInverterSignal_count_2_D2_PT_2_IN2, + I3 => NlwInverterSignal_count_2_D2_PT_2_IN3, + O => count_2_D2_PT_2 + ); + count_2_D2_PT_3_196 : X_AND7 + port map ( + I0 => NlwInverterSignal_count_2_D2_PT_3_IN0, + I1 => NlwInverterSignal_count_2_D2_PT_3_IN1, + I2 => NlwInverterSignal_count_2_D2_PT_3_IN2, + I3 => NlwInverterSignal_count_2_D2_PT_3_IN3, + I4 => NlwInverterSignal_count_2_D2_PT_3_IN4, + I5 => NlwInverterSignal_count_2_D2_PT_3_IN5, + I6 => CLK_SCALE(2), + O => count_2_D2_PT_3 + ); + count_2_D2_197 : X_OR4 + port map ( + I0 => count_2_D2_PT_0, + I1 => count_2_D2_PT_1, + I2 => count_2_D2_PT_2, + I3 => count_2_D2_PT_3, + O => count_2_D2 + ); + count_2_SETF_198 : X_AND2 + port map ( + I0 => RES_IBUF, + I1 => CLK_SCALE(2), + O => count_2_SETF + ); + count_2_RSTF_199 : X_AND2 + port map ( + I0 => RES_IBUF, + I1 => NlwInverterSignal_count_2_RSTF_IN1, + O => count_2_RSTF + ); + count_3_Q_200 : X_BUF + port map ( + I => count_3_Q, + O => count(3) + ); + count_3_tsimcreated_xor_Q_201 : X_XOR2 + port map ( + I0 => count_3_D, + I1 => count_3_Q, + O => count_3_tsimcreated_xor_Q + ); + count_3_tsimcreated_set_and_noreset_Q_202 : X_AND2 + port map ( + I0 => NlwInverterSignal_count_3_tsimcreated_set_and_noreset_IN0, + I1 => count_3_SETF, + O => count_3_tsimcreated_set_and_noreset_Q + ); + count_3_tsimcreated_prld_Q_203 : X_OR2 + port map ( + I0 => count_3_RSTF, + I1 => PRLD, + O => count_3_tsimcreated_prld_Q + ); + count_3_REG : X_FF + port map ( + I => count_3_tsimcreated_xor_Q, + CE => Vcc, + CLK => FCLKIO_0, + SET => count_3_tsimcreated_set_and_noreset_Q, + RST => count_3_tsimcreated_prld_Q, + O => count_3_Q + ); + count_3_D_204 : X_XOR2 + port map ( + I0 => count_3_D1, + I1 => count_3_D2, + O => count_3_D + ); + count_3_D1_205 : X_ZERO + port map ( + O => count_3_D1 + ); + count_3_D2_PT_0_206 : X_AND2 + port map ( + I0 => count_4_EXP, + I1 => count_4_EXP, + O => count_3_D2_PT_0 + ); + count_3_D2_PT_1_207 : X_AND4 + port map ( + I0 => RES_IBUF, + I1 => NlwInverterSignal_count_3_D2_PT_1_IN1, + I2 => NlwInverterSignal_count_3_D2_PT_1_IN2, + I3 => CLK_SCALE(3), + O => count_3_D2_PT_1 + ); + count_3_D2_PT_2_208 : X_AND5 + port map ( + I0 => NlwInverterSignal_count_3_D2_PT_2_IN0, + I1 => NlwInverterSignal_count_3_D2_PT_2_IN1, + I2 => NlwInverterSignal_count_3_D2_PT_2_IN2, + I3 => NlwInverterSignal_count_3_D2_PT_2_IN3, + I4 => NlwInverterSignal_count_3_D2_PT_2_IN4, + O => count_3_D2_PT_2 + ); + count_3_D2_PT_3_209 : X_AND7 + port map ( + I0 => NlwInverterSignal_count_3_D2_PT_3_IN0, + I1 => NlwInverterSignal_count_3_D2_PT_3_IN1, + I2 => NlwInverterSignal_count_3_D2_PT_3_IN2, + I3 => NlwInverterSignal_count_3_D2_PT_3_IN3, + I4 => NlwInverterSignal_count_3_D2_PT_3_IN4, + I5 => NlwInverterSignal_count_3_D2_PT_3_IN5, + I6 => CLK_SCALE(3), + O => count_3_D2_PT_3 + ); + count_3_D2_210 : X_OR4 + port map ( + I0 => count_3_D2_PT_0, + I1 => count_3_D2_PT_1, + I2 => count_3_D2_PT_2, + I3 => count_3_D2_PT_3, + O => count_3_D2 + ); + count_3_SETF_211 : X_AND2 + port map ( + I0 => RES_IBUF, + I1 => CLK_SCALE(3), + O => count_3_SETF + ); + count_3_RSTF_212 : X_AND2 + port map ( + I0 => RES_IBUF, + I1 => NlwInverterSignal_count_3_RSTF_IN1, + O => count_3_RSTF + ); + SHIFT_CNT_4_Q_213 : X_BUF + port map ( + I => SHIFT_CNT_4_Q, + O => SHIFT_CNT(4) + ); + SHIFT_CNT_4_tsimcreated_xor_Q_214 : X_XOR2 + port map ( + I0 => SHIFT_CNT_4_D, + I1 => SHIFT_CNT_4_Q, + O => SHIFT_CNT_4_tsimcreated_xor_Q + ); + SHIFT_CNT_4_tsimcreated_set_and_noreset_Q_215 : X_AND2 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_4_tsimcreated_set_and_noreset_IN0, + I1 => SHIFT_CNT_4_SETF, + O => SHIFT_CNT_4_tsimcreated_set_and_noreset_Q + ); + SHIFT_CNT_4_tsimcreated_prld_Q_216 : X_OR2 + port map ( + I0 => SHIFT_CNT_4_RSTF, + I1 => PRLD, + O => SHIFT_CNT_4_tsimcreated_prld_Q + ); + SHIFT_CNT_4_REG : X_FF + port map ( + I => SHIFT_CNT_4_tsimcreated_xor_Q, + CE => Vcc, + CLK => SHIFT_CNT_4_CLKF, + SET => SHIFT_CNT_4_tsimcreated_set_and_noreset_Q, + RST => SHIFT_CNT_4_tsimcreated_prld_Q, + O => SHIFT_CNT_4_Q + ); + SHIFT_CNT_4_D_217 : X_XOR2 + port map ( + I0 => SHIFT_CNT_4_D1, + I1 => SHIFT_CNT_4_D2, + O => SHIFT_CNT_4_D + ); + SHIFT_CNT_4_D1_218 : X_ZERO + port map ( + O => SHIFT_CNT_4_D1 + ); + SHIFT_CNT_4_D2_PT_0_219 : X_AND2 + port map ( + I0 => SHIFT_CNT_0_EXP, + I1 => SHIFT_CNT_0_EXP, + O => SHIFT_CNT_4_D2_PT_0 + ); + SHIFT_CNT_4_D2_PT_1_220 : X_AND7 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_4_D2_PT_1_IN0, + I1 => buf_depth(0), + I2 => NlwInverterSignal_SHIFT_CNT_4_D2_PT_1_IN2, + I3 => NlwInverterSignal_SHIFT_CNT_4_D2_PT_1_IN3, + I4 => NlwInverterSignal_SHIFT_CNT_4_D2_PT_1_IN4, + I5 => NlwInverterSignal_SHIFT_CNT_4_D2_PT_1_IN5, + I6 => SHIFT_EN, + O => SHIFT_CNT_4_D2_PT_1 + ); + SHIFT_CNT_4_D2_PT_2_221 : X_AND7 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_4_D2_PT_2_IN0, + I1 => buf_depth(1), + I2 => NlwInverterSignal_SHIFT_CNT_4_D2_PT_2_IN2, + I3 => NlwInverterSignal_SHIFT_CNT_4_D2_PT_2_IN3, + I4 => NlwInverterSignal_SHIFT_CNT_4_D2_PT_2_IN4, + I5 => NlwInverterSignal_SHIFT_CNT_4_D2_PT_2_IN5, + I6 => SHIFT_EN, + O => SHIFT_CNT_4_D2_PT_2 + ); + SHIFT_CNT_4_D2_222 : X_OR3 + port map ( + I0 => SHIFT_CNT_4_D2_PT_0, + I1 => SHIFT_CNT_4_D2_PT_1, + I2 => SHIFT_CNT_4_D2_PT_2, + O => SHIFT_CNT_4_D2 + ); + SHIFT_CNT_4_CLKF_223 : X_AND2 + port map ( + I0 => NlwInverterSignal_SHIFT_CNT_4_CLKF_IN0, + I1 => NlwInverterSignal_SHIFT_CNT_4_CLKF_IN1, + O => SHIFT_CNT_4_CLKF + ); + SHIFT_CNT_4_SETF_224 : X_AND2 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_SHIFT_CNT_4_SETF_IN1, + O => SHIFT_CNT_4_SETF + ); + SHIFT_CNT_4_RSTF_225 : X_AND2 + port map ( + I0 => RES_IBUF, + I1 => RES_IBUF, + O => SHIFT_CNT_4_RSTF + ); + count_5_Q_226 : X_BUF + port map ( + I => count_5_Q, + O => count(5) + ); + count_5_EXP_227 : X_BUF + port map ( + I => count_5_EXP_tsimrenamed_net_Q, + O => count_5_EXP + ); + count_5_tsimcreated_xor_Q_228 : X_XOR2 + port map ( + I0 => count_5_D, + I1 => count_5_Q, + O => count_5_tsimcreated_xor_Q + ); + count_5_tsimcreated_set_and_noreset_Q_229 : X_AND2 + port map ( + I0 => NlwInverterSignal_count_5_tsimcreated_set_and_noreset_IN0, + I1 => count_5_SETF, + O => count_5_tsimcreated_set_and_noreset_Q + ); + count_5_tsimcreated_prld_Q_230 : X_OR2 + port map ( + I0 => count_5_RSTF, + I1 => PRLD, + O => count_5_tsimcreated_prld_Q + ); + count_5_REG : X_FF + port map ( + I => count_5_tsimcreated_xor_Q, + CE => Vcc, + CLK => FCLKIO_0, + SET => count_5_tsimcreated_set_and_noreset_Q, + RST => count_5_tsimcreated_prld_Q, + O => count_5_Q + ); + count_5_D_231 : X_XOR2 + port map ( + I0 => count_5_D1, + I1 => count_5_D2, + O => count_5_D + ); + count_5_D1_232 : X_ZERO + port map ( + O => count_5_D1 + ); + count_5_D2_PT_0_233 : X_AND2 + port map ( + I0 => CLK_SCALE_2_EXP, + I1 => CLK_SCALE_2_EXP, + O => count_5_D2_PT_0 + ); + count_5_D2_PT_1_234 : X_AND4 + port map ( + I0 => RES_IBUF, + I1 => NlwInverterSignal_count_5_D2_PT_1_IN1, + I2 => count(5), + I3 => NlwInverterSignal_count_5_D2_PT_1_IN3, + O => count_5_D2_PT_1 + ); + count_5_D2_PT_2_235 : X_AND4 + port map ( + I0 => RES_IBUF, + I1 => NlwInverterSignal_count_5_D2_PT_2_IN1, + I2 => NlwInverterSignal_count_5_D2_PT_2_IN2, + I3 => CLK_SCALE(5), + O => count_5_D2_PT_2 + ); + count_5_D2_236 : X_OR3 + port map ( + I0 => count_5_D2_PT_0, + I1 => count_5_D2_PT_1, + I2 => count_5_D2_PT_2, + O => count_5_D2 + ); + count_5_SETF_237 : X_AND2 + port map ( + I0 => RES_IBUF, + I1 => CLK_SCALE(5), + O => count_5_SETF + ); + count_5_RSTF_238 : X_AND2 + port map ( + I0 => RES_IBUF, + I1 => NlwInverterSignal_count_5_RSTF_IN1, + O => count_5_RSTF + ); + count_5_EXP_tsimrenamed_net_Q_239 : X_AND2 + port map ( + I0 => NlwInverterSignal_count_5_EXP_tsimrenamed_net_IN0, + I1 => CLK_SCALE(0), + O => count_5_EXP_tsimrenamed_net_Q + ); + writeBufId_0_Q_240 : X_BUF + port map ( + I => writeBufId_0_Q, + O => writeBufId(0) + ); + writeBufId_0_tsimcreated_prld_Q_241 : X_OR2 + port map ( + I0 => writeBufId_0_RSTF, + I1 => PRLD, + O => writeBufId_0_tsimcreated_prld_Q + ); + writeBufId_0_REG : X_FF + port map ( + I => writeBufId_0_D, + CE => writeBufId_0_CE, + CLK => writeBufId_0_CLKF, + SET => Gnd, + RST => writeBufId_0_tsimcreated_prld_Q, + O => writeBufId_0_Q + ); + writeBufId_0_D_242 : X_XOR2 + port map ( + I0 => writeBufId_0_D1, + I1 => writeBufId_0_D2, + O => writeBufId_0_D + ); + writeBufId_0_D1_243 : X_ZERO + port map ( + O => writeBufId_0_D1 + ); + writeBufId_0_D2_PT_0_244 : X_AND2 + port map ( + I0 => buf_depth(0), + I1 => tempID(0), + O => writeBufId_0_D2_PT_0 + ); + writeBufId_0_D2_PT_1_245 : X_AND2 + port map ( + I0 => buf_depth(1), + I1 => tempID(0), + O => writeBufId_0_D2_PT_1 + ); + writeBufId_0_D2_246 : X_OR2 + port map ( + I0 => writeBufId_0_D2_PT_0, + I1 => writeBufId_0_D2_PT_1, + O => writeBufId_0_D2 + ); + writeBufId_0_CLKF_247 : X_AND2 + port map ( + I0 => NlwInverterSignal_writeBufId_0_CLKF_IN0, + I1 => NlwInverterSignal_writeBufId_0_CLKF_IN1, + O => writeBufId_0_CLKF + ); + writeBufId_0_RSTF_248 : X_AND2 + port map ( + I0 => RES_IBUF, + I1 => RES_IBUF, + O => writeBufId_0_RSTF + ); + writeBufId_0_CE_249 : X_AND7 + port map ( + I0 => NlwInverterSignal_writeBufId_0_CE_IN0, + I1 => NlwInverterSignal_writeBufId_0_CE_IN1, + I2 => NlwInverterSignal_writeBufId_0_CE_IN2, + I3 => NlwInverterSignal_writeBufId_0_CE_IN3, + I4 => NlwInverterSignal_writeBufId_0_CE_IN4, + I5 => NlwInverterSignal_writeBufId_0_CE_IN5, + I6 => SHIFT_EN, + O => writeBufId_0_CE + ); + CLK_SCALE_0_Q_250 : X_BUF + port map ( + I => CLK_SCALE_0_Q, + O => CLK_SCALE(0) + ); + CLK_SCALE_0_EXP_251 : X_BUF + port map ( + I => CLK_SCALE_0_EXP_tsimrenamed_net_Q, + O => CLK_SCALE_0_EXP + ); + CLK_SCALE_0_Q_252 : X_BUF + port map ( + I => CLK_SCALE_0_D, + O => CLK_SCALE_0_Q + ); + CLK_SCALE_0_D_253 : X_XOR2 + port map ( + I0 => CLK_SCALE_0_D1, + I1 => CLK_SCALE_0_D2, + O => CLK_SCALE_0_D + ); + CLK_SCALE_0_D1_254 : X_ZERO + port map ( + O => CLK_SCALE_0_D1 + ); + CLK_SCALE_0_D2_PT_0_255 : X_AND2 + port map ( + I0 => RES_IBUF, + I1 => RES_IBUF, + O => CLK_SCALE_0_D2_PT_0 + ); + CLK_SCALE_0_D2_PT_1_256 : X_AND2 + port map ( + I0 => count_5_EXP, + I1 => count_5_EXP, + O => CLK_SCALE_0_D2_PT_1 + ); + CLK_SCALE_0_D2_PT_2_257 : X_AND2 + port map ( + I0 => LOAD_PRESCALER_IBUF, + I1 => CCLK_PRESCALER_0_IBUF, + O => CLK_SCALE_0_D2_PT_2 + ); + CLK_SCALE_0_D2_PT_3_258 : X_AND2 + port map ( + I0 => CLK_SCALE(0), + I1 => CCLK_PRESCALER_0_IBUF, + O => CLK_SCALE_0_D2_PT_3 + ); + CLK_SCALE_0_D2_259 : X_OR4 + port map ( + I0 => CLK_SCALE_0_D2_PT_0, + I1 => CLK_SCALE_0_D2_PT_1, + I2 => CLK_SCALE_0_D2_PT_2, + I3 => CLK_SCALE_0_D2_PT_3, + O => CLK_SCALE_0_D2 + ); + CLK_SCALE_0_EXP_PT_0_260 : X_AND4 + port map ( + I0 => RES_IBUF, + I1 => NlwInverterSignal_CLK_SCALE_0_EXP_PT_0_IN1, + I2 => count(4), + I3 => NlwInverterSignal_CLK_SCALE_0_EXP_PT_0_IN3, + O => CLK_SCALE_0_EXP_PT_0 + ); + CLK_SCALE_0_EXP_PT_1_261 : X_AND4 + port map ( + I0 => RES_IBUF, + I1 => NlwInverterSignal_CLK_SCALE_0_EXP_PT_1_IN1, + I2 => NlwInverterSignal_CLK_SCALE_0_EXP_PT_1_IN2, + I3 => CLK_SCALE(4), + O => CLK_SCALE_0_EXP_PT_1 + ); + CLK_SCALE_0_EXP_tsimrenamed_net_Q_262 : X_OR2 + port map ( + I0 => CLK_SCALE_0_EXP_PT_0, + I1 => CLK_SCALE_0_EXP_PT_1, + O => CLK_SCALE_0_EXP_tsimrenamed_net_Q + ); + REG_0_0_263 : X_BUF + port map ( + I => REG_0_0_Q, + O => REG_0_0 + ); + REG_0_0_EXP_264 : X_BUF + port map ( + I => REG_0_0_EXP_tsimrenamed_net_Q, + O => REG_0_0_EXP + ); + REG_0_0_tsimcreated_xor_Q_265 : X_XOR2 + port map ( + I0 => REG_0_0_D, + I1 => REG_0_0_Q, + O => REG_0_0_tsimcreated_xor_Q + ); + REG_0_0_tsimcreated_set_and_noreset_Q_266 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_0_tsimcreated_set_and_noreset_IN0, + I1 => REG_0_0_SETF, + O => REG_0_0_tsimcreated_set_and_noreset_Q + ); + REG_0_0_tsimcreated_prld_Q_267 : X_OR2 + port map ( + I0 => REG_0_0_RSTF, + I1 => PRLD, + O => REG_0_0_tsimcreated_prld_Q + ); + REG_0_0_REG : X_FF + port map ( + I => REG_0_0_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_0_0_CLKF, + SET => REG_0_0_tsimcreated_set_and_noreset_Q, + RST => REG_0_0_tsimcreated_prld_Q, + O => REG_0_0_Q + ); + REG_0_0_D_268 : X_XOR2 + port map ( + I0 => REG_0_0_D1, + I1 => REG_0_0_D2, + O => REG_0_0_D + ); + REG_0_0_D1_269 : X_ZERO + port map ( + O => REG_0_0_D1 + ); + REG_0_0_D2_270 : X_AND2 + port map ( + I0 => EXP22_EXP, + I1 => EXP22_EXP, + O => REG_0_0_D2 + ); + REG_0_0_CLKF_271 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_0_CLKF_IN0, + I1 => NlwInverterSignal_REG_0_0_CLKF_IN1, + O => REG_0_0_CLKF + ); + REG_0_0_SETF_272 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_0_SETF_IN1, + I2 => DIN_0_IBUF, + O => REG_0_0_SETF + ); + REG_0_0_RSTF_273 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_0_RSTF_IN1, + I2 => NlwInverterSignal_REG_0_0_RSTF_IN2, + O => REG_0_0_RSTF + ); + REG_0_0_EXP_PT_0_274 : X_AND7 + port map ( + I0 => NlwInverterSignal_REG_0_0_EXP_PT_0_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_REG_0_0_EXP_PT_0_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_REG_0_0_EXP_PT_0_IN4, + I5 => REG_0_4, + I6 => NlwInverterSignal_REG_0_0_EXP_PT_0_IN6, + O => REG_0_0_EXP_PT_0 + ); + REG_0_0_EXP_PT_1_275 : X_AND7 + port map ( + I0 => NlwInverterSignal_REG_0_0_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_REG_0_0_EXP_PT_1_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_REG_0_0_EXP_PT_1_IN4, + I5 => NlwInverterSignal_REG_0_0_EXP_PT_1_IN5, + I6 => DIN_4_IBUF, + O => REG_0_0_EXP_PT_1 + ); + REG_0_0_EXP_tsimrenamed_net_Q_276 : X_OR2 + port map ( + I0 => REG_0_0_EXP_PT_0, + I1 => REG_0_0_EXP_PT_1, + O => REG_0_0_EXP_tsimrenamed_net_Q + ); + REG_0_1_277 : X_BUF + port map ( + I => REG_0_1_Q, + O => REG_0_1 + ); + REG_0_1_tsimcreated_xor_Q_278 : X_XOR2 + port map ( + I0 => REG_0_1_D, + I1 => REG_0_1_Q, + O => REG_0_1_tsimcreated_xor_Q + ); + REG_0_1_tsimcreated_set_and_noreset_Q_279 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_1_tsimcreated_set_and_noreset_IN0, + I1 => REG_0_1_SETF, + O => REG_0_1_tsimcreated_set_and_noreset_Q + ); + REG_0_1_tsimcreated_prld_Q_280 : X_OR2 + port map ( + I0 => REG_0_1_RSTF, + I1 => PRLD, + O => REG_0_1_tsimcreated_prld_Q + ); + REG_0_1_REG : X_FF + port map ( + I => REG_0_1_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_0_1_CLKF, + SET => REG_0_1_tsimcreated_set_and_noreset_Q, + RST => REG_0_1_tsimcreated_prld_Q, + O => REG_0_1_Q + ); + REG_0_1_D_281 : X_XOR2 + port map ( + I0 => REG_0_1_D1, + I1 => REG_0_1_D2, + O => REG_0_1_D + ); + REG_0_1_D1_282 : X_ZERO + port map ( + O => REG_0_1_D1 + ); + REG_0_1_D2_PT_0_283 : X_AND2 + port map ( + I0 => EXP18_EXP, + I1 => EXP18_EXP, + O => REG_0_1_D2_PT_0 + ); + REG_0_1_D2_PT_1_284 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_1_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_0_1_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_1_D2_PT_1_IN3, + I4 => REG_0_0, + I5 => NlwInverterSignal_REG_0_1_D2_PT_1_IN5, + O => REG_0_1_D2_PT_1 + ); + REG_0_1_D2_PT_2_285 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_1_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_0_1_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_1_D2_PT_2_IN3, + I4 => NlwInverterSignal_REG_0_1_D2_PT_2_IN4, + I5 => REG_0_1, + O => REG_0_1_D2_PT_2 + ); + REG_0_1_D2_286 : X_OR3 + port map ( + I0 => REG_0_1_D2_PT_0, + I1 => REG_0_1_D2_PT_1, + I2 => REG_0_1_D2_PT_2, + O => REG_0_1_D2 + ); + REG_0_1_CLKF_287 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_1_CLKF_IN0, + I1 => NlwInverterSignal_REG_0_1_CLKF_IN1, + O => REG_0_1_CLKF + ); + REG_0_1_SETF_288 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_1_SETF_IN1, + I2 => DIN_1_IBUF, + O => REG_0_1_SETF + ); + REG_0_1_RSTF_289 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_1_RSTF_IN1, + I2 => NlwInverterSignal_REG_0_1_RSTF_IN2, + O => REG_0_1_RSTF + ); + REG_0_10_290 : X_BUF + port map ( + I => REG_0_10_Q, + O => REG_0_10 + ); + REG_0_10_tsimcreated_xor_Q_291 : X_XOR2 + port map ( + I0 => REG_0_10_D, + I1 => REG_0_10_Q, + O => REG_0_10_tsimcreated_xor_Q + ); + REG_0_10_tsimcreated_set_and_noreset_Q_292 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_10_tsimcreated_set_and_noreset_IN0, + I1 => REG_0_10_SETF, + O => REG_0_10_tsimcreated_set_and_noreset_Q + ); + REG_0_10_tsimcreated_prld_Q_293 : X_OR2 + port map ( + I0 => REG_0_10_RSTF, + I1 => PRLD, + O => REG_0_10_tsimcreated_prld_Q + ); + REG_0_10_REG : X_FF + port map ( + I => REG_0_10_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_0_10_CLKF, + SET => REG_0_10_tsimcreated_set_and_noreset_Q, + RST => REG_0_10_tsimcreated_prld_Q, + O => REG_0_10_Q + ); + REG_0_10_D_294 : X_XOR2 + port map ( + I0 => REG_0_10_D1, + I1 => REG_0_10_D2, + O => REG_0_10_D + ); + REG_0_10_D1_295 : X_ZERO + port map ( + O => REG_0_10_D1 + ); + REG_0_10_D2_PT_0_296 : X_AND2 + port map ( + I0 => EXP65_EXP, + I1 => EXP65_EXP, + O => REG_0_10_D2_PT_0 + ); + REG_0_10_D2_PT_1_297 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_10_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_0_10_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_10_D2_PT_1_IN3, + I4 => REG_0_10, + I5 => NlwInverterSignal_REG_0_10_D2_PT_1_IN5, + O => REG_0_10_D2_PT_1 + ); + REG_0_10_D2_PT_2_298 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_10_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_0_10_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_10_D2_PT_2_IN3, + I4 => NlwInverterSignal_REG_0_10_D2_PT_2_IN4, + I5 => REG_0_9, + O => REG_0_10_D2_PT_2 + ); + REG_0_10_D2_299 : X_OR3 + port map ( + I0 => REG_0_10_D2_PT_0, + I1 => REG_0_10_D2_PT_1, + I2 => REG_0_10_D2_PT_2, + O => REG_0_10_D2 + ); + REG_0_10_CLKF_300 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_10_CLKF_IN0, + I1 => NlwInverterSignal_REG_0_10_CLKF_IN1, + O => REG_0_10_CLKF + ); + REG_0_10_SETF_301 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_10_SETF_IN1, + I2 => DIN_10_IBUF, + O => REG_0_10_SETF + ); + REG_0_10_RSTF_302 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_10_RSTF_IN1, + I2 => NlwInverterSignal_REG_0_10_RSTF_IN2, + O => REG_0_10_RSTF + ); + REG_0_11_303 : X_BUF + port map ( + I => REG_0_11_Q, + O => REG_0_11 + ); + REG_0_11_tsimcreated_xor_Q_304 : X_XOR2 + port map ( + I0 => REG_0_11_D, + I1 => REG_0_11_Q, + O => REG_0_11_tsimcreated_xor_Q + ); + REG_0_11_tsimcreated_set_and_noreset_Q_305 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_11_tsimcreated_set_and_noreset_IN0, + I1 => REG_0_11_SETF, + O => REG_0_11_tsimcreated_set_and_noreset_Q + ); + REG_0_11_tsimcreated_prld_Q_306 : X_OR2 + port map ( + I0 => REG_0_11_RSTF, + I1 => PRLD, + O => REG_0_11_tsimcreated_prld_Q + ); + REG_0_11_REG : X_FF + port map ( + I => REG_0_11_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_0_11_CLKF, + SET => REG_0_11_tsimcreated_set_and_noreset_Q, + RST => REG_0_11_tsimcreated_prld_Q, + O => REG_0_11_Q + ); + REG_0_11_D_307 : X_XOR2 + port map ( + I0 => REG_0_11_D1, + I1 => REG_0_11_D2, + O => REG_0_11_D + ); + REG_0_11_D1_308 : X_ZERO + port map ( + O => REG_0_11_D1 + ); + REG_0_11_D2_PT_0_309 : X_AND2 + port map ( + I0 => SHIFT_EN_EXP, + I1 => SHIFT_EN_EXP, + O => REG_0_11_D2_PT_0 + ); + REG_0_11_D2_PT_1_310 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_11_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_0_11_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_11_D2_PT_1_IN3, + I4 => REG_0_10, + I5 => NlwInverterSignal_REG_0_11_D2_PT_1_IN5, + O => REG_0_11_D2_PT_1 + ); + REG_0_11_D2_PT_2_311 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_11_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_0_11_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_11_D2_PT_2_IN3, + I4 => NlwInverterSignal_REG_0_11_D2_PT_2_IN4, + I5 => REG_0_11, + O => REG_0_11_D2_PT_2 + ); + REG_0_11_D2_312 : X_OR3 + port map ( + I0 => REG_0_11_D2_PT_0, + I1 => REG_0_11_D2_PT_1, + I2 => REG_0_11_D2_PT_2, + O => REG_0_11_D2 + ); + REG_0_11_CLKF_313 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_11_CLKF_IN0, + I1 => NlwInverterSignal_REG_0_11_CLKF_IN1, + O => REG_0_11_CLKF + ); + REG_0_11_SETF_314 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_11_SETF_IN1, + I2 => DIN_11_IBUF, + O => REG_0_11_SETF + ); + REG_0_11_RSTF_315 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_11_RSTF_IN1, + I2 => NlwInverterSignal_REG_0_11_RSTF_IN2, + O => REG_0_11_RSTF + ); + REG_0_12_316 : X_BUF + port map ( + I => REG_0_12_Q, + O => REG_0_12 + ); + REG_0_12_tsimcreated_xor_Q_317 : X_XOR2 + port map ( + I0 => REG_0_12_D, + I1 => REG_0_12_Q, + O => REG_0_12_tsimcreated_xor_Q + ); + REG_0_12_tsimcreated_set_and_noreset_Q_318 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_12_tsimcreated_set_and_noreset_IN0, + I1 => REG_0_12_SETF, + O => REG_0_12_tsimcreated_set_and_noreset_Q + ); + REG_0_12_tsimcreated_prld_Q_319 : X_OR2 + port map ( + I0 => REG_0_12_RSTF, + I1 => PRLD, + O => REG_0_12_tsimcreated_prld_Q + ); + REG_0_12_REG : X_FF + port map ( + I => REG_0_12_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_0_12_CLKF, + SET => REG_0_12_tsimcreated_set_and_noreset_Q, + RST => REG_0_12_tsimcreated_prld_Q, + O => REG_0_12_Q + ); + REG_0_12_D_320 : X_XOR2 + port map ( + I0 => REG_0_12_D1, + I1 => REG_0_12_D2, + O => REG_0_12_D + ); + REG_0_12_D1_321 : X_ZERO + port map ( + O => REG_0_12_D1 + ); + REG_0_12_D2_PT_0_322 : X_AND2 + port map ( + I0 => REG_0_13_EXP, + I1 => REG_0_13_EXP, + O => REG_0_12_D2_PT_0 + ); + REG_0_12_D2_PT_1_323 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_12_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_0_12_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_12_D2_PT_1_IN3, + I4 => REG_0_11, + I5 => NlwInverterSignal_REG_0_12_D2_PT_1_IN5, + O => REG_0_12_D2_PT_1 + ); + REG_0_12_D2_PT_2_324 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_12_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_0_12_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_12_D2_PT_2_IN3, + I4 => NlwInverterSignal_REG_0_12_D2_PT_2_IN4, + I5 => REG_0_12, + O => REG_0_12_D2_PT_2 + ); + REG_0_12_D2_325 : X_OR3 + port map ( + I0 => REG_0_12_D2_PT_0, + I1 => REG_0_12_D2_PT_1, + I2 => REG_0_12_D2_PT_2, + O => REG_0_12_D2 + ); + REG_0_12_CLKF_326 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_12_CLKF_IN0, + I1 => NlwInverterSignal_REG_0_12_CLKF_IN1, + O => REG_0_12_CLKF + ); + REG_0_12_SETF_327 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_12_SETF_IN1, + I2 => DIN_12_IBUF, + O => REG_0_12_SETF + ); + REG_0_12_RSTF_328 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_12_RSTF_IN1, + I2 => NlwInverterSignal_REG_0_12_RSTF_IN2, + O => REG_0_12_RSTF + ); + REG_0_13_329 : X_BUF + port map ( + I => REG_0_13_Q, + O => REG_0_13 + ); + REG_0_13_EXP_330 : X_BUF + port map ( + I => REG_0_13_EXP_tsimrenamed_net_Q, + O => REG_0_13_EXP + ); + REG_0_13_tsimcreated_xor_Q_331 : X_XOR2 + port map ( + I0 => REG_0_13_D, + I1 => REG_0_13_Q, + O => REG_0_13_tsimcreated_xor_Q + ); + REG_0_13_tsimcreated_set_and_noreset_Q_332 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_13_tsimcreated_set_and_noreset_IN0, + I1 => REG_0_13_SETF, + O => REG_0_13_tsimcreated_set_and_noreset_Q + ); + REG_0_13_tsimcreated_prld_Q_333 : X_OR2 + port map ( + I0 => REG_0_13_RSTF, + I1 => PRLD, + O => REG_0_13_tsimcreated_prld_Q + ); + REG_0_13_REG : X_FF + port map ( + I => REG_0_13_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_0_13_CLKF, + SET => REG_0_13_tsimcreated_set_and_noreset_Q, + RST => REG_0_13_tsimcreated_prld_Q, + O => REG_0_13_Q + ); + REG_0_13_D_334 : X_XOR2 + port map ( + I0 => REG_0_13_D1, + I1 => REG_0_13_D2, + O => REG_0_13_D + ); + REG_0_13_D1_335 : X_ZERO + port map ( + O => REG_0_13_D1 + ); + REG_0_13_D2_336 : X_AND2 + port map ( + I0 => CCLK_OBUF_EXP, + I1 => CCLK_OBUF_EXP, + O => REG_0_13_D2 + ); + REG_0_13_CLKF_337 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_13_CLKF_IN0, + I1 => NlwInverterSignal_REG_0_13_CLKF_IN1, + O => REG_0_13_CLKF + ); + REG_0_13_SETF_338 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_13_SETF_IN1, + I2 => DIN_13_IBUF, + O => REG_0_13_SETF + ); + REG_0_13_RSTF_339 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_13_RSTF_IN1, + I2 => NlwInverterSignal_REG_0_13_RSTF_IN2, + O => REG_0_13_RSTF + ); + REG_0_13_EXP_PT_0_340 : X_AND7 + port map ( + I0 => NlwInverterSignal_REG_0_13_EXP_PT_0_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_REG_0_13_EXP_PT_0_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_REG_0_13_EXP_PT_0_IN4, + I5 => DIN_12_IBUF, + I6 => NlwInverterSignal_REG_0_13_EXP_PT_0_IN6, + O => REG_0_13_EXP_PT_0 + ); + REG_0_13_EXP_PT_1_341 : X_AND7 + port map ( + I0 => NlwInverterSignal_REG_0_13_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_REG_0_13_EXP_PT_1_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_REG_0_13_EXP_PT_1_IN4, + I5 => NlwInverterSignal_REG_0_13_EXP_PT_1_IN5, + I6 => REG_0_12, + O => REG_0_13_EXP_PT_1 + ); + REG_0_13_EXP_tsimrenamed_net_Q_342 : X_OR2 + port map ( + I0 => REG_0_13_EXP_PT_0, + I1 => REG_0_13_EXP_PT_1, + O => REG_0_13_EXP_tsimrenamed_net_Q + ); + REG_0_14_343 : X_BUF + port map ( + I => REG_0_14_Q, + O => REG_0_14 + ); + REG_0_14_tsimcreated_xor_Q_344 : X_XOR2 + port map ( + I0 => REG_0_14_D, + I1 => REG_0_14_Q, + O => REG_0_14_tsimcreated_xor_Q + ); + REG_0_14_tsimcreated_set_and_noreset_Q_345 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_14_tsimcreated_set_and_noreset_IN0, + I1 => REG_0_14_SETF, + O => REG_0_14_tsimcreated_set_and_noreset_Q + ); + REG_0_14_tsimcreated_prld_Q_346 : X_OR2 + port map ( + I0 => REG_0_14_RSTF, + I1 => PRLD, + O => REG_0_14_tsimcreated_prld_Q + ); + REG_0_14_REG : X_FF + port map ( + I => REG_0_14_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_0_14_CLKF, + SET => REG_0_14_tsimcreated_set_and_noreset_Q, + RST => REG_0_14_tsimcreated_prld_Q, + O => REG_0_14_Q + ); + REG_0_14_D_347 : X_XOR2 + port map ( + I0 => REG_0_14_D1, + I1 => REG_0_14_D2, + O => REG_0_14_D + ); + REG_0_14_D1_348 : X_ZERO + port map ( + O => REG_0_14_D1 + ); + REG_0_14_D2_PT_0_349 : X_AND2 + port map ( + I0 => EXP66_EXP, + I1 => EXP66_EXP, + O => REG_0_14_D2_PT_0 + ); + REG_0_14_D2_PT_1_350 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_14_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_0_14_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_14_D2_PT_1_IN3, + I4 => REG_0_13, + I5 => NlwInverterSignal_REG_0_14_D2_PT_1_IN5, + O => REG_0_14_D2_PT_1 + ); + REG_0_14_D2_PT_2_351 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_14_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_0_14_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_14_D2_PT_2_IN3, + I4 => NlwInverterSignal_REG_0_14_D2_PT_2_IN4, + I5 => REG_0_14, + O => REG_0_14_D2_PT_2 + ); + REG_0_14_D2_352 : X_OR3 + port map ( + I0 => REG_0_14_D2_PT_0, + I1 => REG_0_14_D2_PT_1, + I2 => REG_0_14_D2_PT_2, + O => REG_0_14_D2 + ); + REG_0_14_CLKF_353 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_14_CLKF_IN0, + I1 => NlwInverterSignal_REG_0_14_CLKF_IN1, + O => REG_0_14_CLKF + ); + REG_0_14_SETF_354 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_14_SETF_IN1, + I2 => DIN_14_IBUF, + O => REG_0_14_SETF + ); + REG_0_14_RSTF_355 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_14_RSTF_IN1, + I2 => NlwInverterSignal_REG_0_14_RSTF_IN2, + O => REG_0_14_RSTF + ); + REG_0_15_356 : X_BUF + port map ( + I => REG_0_15_Q, + O => REG_0_15 + ); + REG_0_15_EXP_357 : X_BUF + port map ( + I => REG_0_15_EXP_tsimrenamed_net_Q, + O => REG_0_15_EXP + ); + REG_0_15_tsimcreated_xor_Q_358 : X_XOR2 + port map ( + I0 => REG_0_15_D, + I1 => REG_0_15_Q, + O => REG_0_15_tsimcreated_xor_Q + ); + REG_0_15_tsimcreated_set_and_noreset_Q_359 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_15_tsimcreated_set_and_noreset_IN0, + I1 => REG_0_15_SETF, + O => REG_0_15_tsimcreated_set_and_noreset_Q + ); + REG_0_15_tsimcreated_prld_Q_360 : X_OR2 + port map ( + I0 => REG_0_15_RSTF, + I1 => PRLD, + O => REG_0_15_tsimcreated_prld_Q + ); + REG_0_15_REG : X_FF + port map ( + I => REG_0_15_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_0_15_CLKF, + SET => REG_0_15_tsimcreated_set_and_noreset_Q, + RST => REG_0_15_tsimcreated_prld_Q, + O => REG_0_15_Q + ); + REG_0_15_D_361 : X_XOR2 + port map ( + I0 => REG_0_15_D1, + I1 => REG_0_15_D2, + O => REG_0_15_D + ); + REG_0_15_D1_362 : X_ZERO + port map ( + O => REG_0_15_D1 + ); + REG_0_15_D2_PT_0_363 : X_AND2 + port map ( + I0 => EXP30_EXP, + I1 => EXP30_EXP, + O => REG_0_15_D2_PT_0 + ); + REG_0_15_D2_PT_1_364 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_15_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_0_15_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_15_D2_PT_1_IN3, + I4 => NlwInverterSignal_REG_0_15_D2_PT_1_IN4, + I5 => REG_0_15, + O => REG_0_15_D2_PT_1 + ); + REG_0_15_D2_365 : X_OR2 + port map ( + I0 => REG_0_15_D2_PT_0, + I1 => REG_0_15_D2_PT_1, + O => REG_0_15_D2 + ); + REG_0_15_CLKF_366 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_15_CLKF_IN0, + I1 => NlwInverterSignal_REG_0_15_CLKF_IN1, + O => REG_0_15_CLKF + ); + REG_0_15_SETF_367 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_15_SETF_IN1, + I2 => DIN_15_IBUF, + O => REG_0_15_SETF + ); + REG_0_15_RSTF_368 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_15_RSTF_IN1, + I2 => NlwInverterSignal_REG_0_15_RSTF_IN2, + O => REG_0_15_RSTF + ); + REG_0_15_EXP_tsimrenamed_net_Q_369 : X_AND7 + port map ( + I0 => NlwInverterSignal_REG_0_15_EXP_tsimrenamed_net_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_REG_0_15_EXP_tsimrenamed_net_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_REG_0_15_EXP_tsimrenamed_net_IN4, + I5 => NlwInverterSignal_REG_0_15_EXP_tsimrenamed_net_IN5, + I6 => DIN_16_IBUF, + O => REG_0_15_EXP_tsimrenamed_net_Q + ); + REG_0_16_370 : X_BUF + port map ( + I => REG_0_16_Q, + O => REG_0_16 + ); + REG_0_16_tsimcreated_xor_Q_371 : X_XOR2 + port map ( + I0 => REG_0_16_D, + I1 => REG_0_16_Q, + O => REG_0_16_tsimcreated_xor_Q + ); + REG_0_16_tsimcreated_set_and_noreset_Q_372 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_16_tsimcreated_set_and_noreset_IN0, + I1 => REG_0_16_SETF, + O => REG_0_16_tsimcreated_set_and_noreset_Q + ); + REG_0_16_tsimcreated_prld_Q_373 : X_OR2 + port map ( + I0 => REG_0_16_RSTF, + I1 => PRLD, + O => REG_0_16_tsimcreated_prld_Q + ); + REG_0_16_REG : X_FF + port map ( + I => REG_0_16_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_0_16_CLKF, + SET => REG_0_16_tsimcreated_set_and_noreset_Q, + RST => REG_0_16_tsimcreated_prld_Q, + O => REG_0_16_Q + ); + REG_0_16_D_374 : X_XOR2 + port map ( + I0 => REG_0_16_D1, + I1 => REG_0_16_D2, + O => REG_0_16_D + ); + REG_0_16_D1_375 : X_ZERO + port map ( + O => REG_0_16_D1 + ); + REG_0_16_D2_PT_0_376 : X_AND2 + port map ( + I0 => REG_0_15_EXP, + I1 => REG_0_15_EXP, + O => REG_0_16_D2_PT_0 + ); + REG_0_16_D2_PT_1_377 : X_AND2 + port map ( + I0 => REG_0_17_EXP, + I1 => REG_0_17_EXP, + O => REG_0_16_D2_PT_1 + ); + REG_0_16_D2_PT_2_378 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_16_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_0_16_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_16_D2_PT_2_IN3, + I4 => REG_0_15, + I5 => NlwInverterSignal_REG_0_16_D2_PT_2_IN5, + O => REG_0_16_D2_PT_2 + ); + REG_0_16_D2_PT_3_379 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_16_D2_PT_3_IN0, + I1 => NlwInverterSignal_REG_0_16_D2_PT_3_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_16_D2_PT_3_IN3, + I4 => NlwInverterSignal_REG_0_16_D2_PT_3_IN4, + I5 => REG_0_16, + O => REG_0_16_D2_PT_3 + ); + REG_0_16_D2_380 : X_OR4 + port map ( + I0 => REG_0_16_D2_PT_0, + I1 => REG_0_16_D2_PT_1, + I2 => REG_0_16_D2_PT_2, + I3 => REG_0_16_D2_PT_3, + O => REG_0_16_D2 + ); + REG_0_16_CLKF_381 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_16_CLKF_IN0, + I1 => NlwInverterSignal_REG_0_16_CLKF_IN1, + O => REG_0_16_CLKF + ); + REG_0_16_SETF_382 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_16_SETF_IN1, + I2 => DIN_16_IBUF, + O => REG_0_16_SETF + ); + REG_0_16_RSTF_383 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_16_RSTF_IN1, + I2 => NlwInverterSignal_REG_0_16_RSTF_IN2, + O => REG_0_16_RSTF + ); + REG_0_17_384 : X_BUF + port map ( + I => REG_0_17_Q, + O => REG_0_17 + ); + REG_0_17_EXP_385 : X_BUF + port map ( + I => REG_0_17_EXP_tsimrenamed_net_Q, + O => REG_0_17_EXP + ); + REG_0_17_tsimcreated_xor_Q_386 : X_XOR2 + port map ( + I0 => REG_0_17_D, + I1 => REG_0_17_Q, + O => REG_0_17_tsimcreated_xor_Q + ); + REG_0_17_tsimcreated_set_and_noreset_Q_387 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_17_tsimcreated_set_and_noreset_IN0, + I1 => REG_0_17_SETF, + O => REG_0_17_tsimcreated_set_and_noreset_Q + ); + REG_0_17_tsimcreated_prld_Q_388 : X_OR2 + port map ( + I0 => REG_0_17_RSTF, + I1 => PRLD, + O => REG_0_17_tsimcreated_prld_Q + ); + REG_0_17_REG : X_FF + port map ( + I => REG_0_17_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_0_17_CLKF, + SET => REG_0_17_tsimcreated_set_and_noreset_Q, + RST => REG_0_17_tsimcreated_prld_Q, + O => REG_0_17_Q + ); + REG_0_17_D_389 : X_XOR2 + port map ( + I0 => REG_0_17_D1, + I1 => REG_0_17_D2, + O => REG_0_17_D + ); + REG_0_17_D1_390 : X_ZERO + port map ( + O => REG_0_17_D1 + ); + REG_0_17_D2_PT_0_391 : X_AND2 + port map ( + I0 => EXP29_EXP, + I1 => EXP29_EXP, + O => REG_0_17_D2_PT_0 + ); + REG_0_17_D2_PT_1_392 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_17_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_0_17_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_17_D2_PT_1_IN3, + I4 => NlwInverterSignal_REG_0_17_D2_PT_1_IN4, + I5 => REG_0_17, + O => REG_0_17_D2_PT_1 + ); + REG_0_17_D2_393 : X_OR2 + port map ( + I0 => REG_0_17_D2_PT_0, + I1 => REG_0_17_D2_PT_1, + O => REG_0_17_D2 + ); + REG_0_17_CLKF_394 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_17_CLKF_IN0, + I1 => NlwInverterSignal_REG_0_17_CLKF_IN1, + O => REG_0_17_CLKF + ); + REG_0_17_SETF_395 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_17_SETF_IN1, + I2 => DIN_17_IBUF, + O => REG_0_17_SETF + ); + REG_0_17_RSTF_396 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_17_RSTF_IN1, + I2 => NlwInverterSignal_REG_0_17_RSTF_IN2, + O => REG_0_17_RSTF + ); + REG_0_17_EXP_tsimrenamed_net_Q_397 : X_AND7 + port map ( + I0 => NlwInverterSignal_REG_0_17_EXP_tsimrenamed_net_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_REG_0_17_EXP_tsimrenamed_net_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_REG_0_17_EXP_tsimrenamed_net_IN4, + I5 => REG_0_16, + I6 => NlwInverterSignal_REG_0_17_EXP_tsimrenamed_net_IN6, + O => REG_0_17_EXP_tsimrenamed_net_Q + ); + REG_0_18_398 : X_BUF + port map ( + I => REG_0_18_Q, + O => REG_0_18 + ); + REG_0_18_tsimcreated_xor_Q_399 : X_XOR2 + port map ( + I0 => REG_0_18_D, + I1 => REG_0_18_Q, + O => REG_0_18_tsimcreated_xor_Q + ); + REG_0_18_tsimcreated_set_and_noreset_Q_400 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_18_tsimcreated_set_and_noreset_IN0, + I1 => REG_0_18_SETF, + O => REG_0_18_tsimcreated_set_and_noreset_Q + ); + REG_0_18_tsimcreated_prld_Q_401 : X_OR2 + port map ( + I0 => REG_0_18_RSTF, + I1 => PRLD, + O => REG_0_18_tsimcreated_prld_Q + ); + REG_0_18_REG : X_FF + port map ( + I => REG_0_18_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_0_18_CLKF, + SET => REG_0_18_tsimcreated_set_and_noreset_Q, + RST => REG_0_18_tsimcreated_prld_Q, + O => REG_0_18_Q + ); + REG_0_18_D_402 : X_XOR2 + port map ( + I0 => REG_0_18_D1, + I1 => REG_0_18_D2, + O => REG_0_18_D + ); + REG_0_18_D1_403 : X_ZERO + port map ( + O => REG_0_18_D1 + ); + REG_0_18_D2_PT_0_404 : X_AND2 + port map ( + I0 => EXP32_EXP, + I1 => EXP32_EXP, + O => REG_0_18_D2_PT_0 + ); + REG_0_18_D2_PT_1_405 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_18_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_0_18_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_18_D2_PT_1_IN3, + I4 => REG_0_17, + I5 => NlwInverterSignal_REG_0_18_D2_PT_1_IN5, + O => REG_0_18_D2_PT_1 + ); + REG_0_18_D2_PT_2_406 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_18_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_0_18_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_18_D2_PT_2_IN3, + I4 => NlwInverterSignal_REG_0_18_D2_PT_2_IN4, + I5 => REG_0_18, + O => REG_0_18_D2_PT_2 + ); + REG_0_18_D2_407 : X_OR3 + port map ( + I0 => REG_0_18_D2_PT_0, + I1 => REG_0_18_D2_PT_1, + I2 => REG_0_18_D2_PT_2, + O => REG_0_18_D2 + ); + REG_0_18_CLKF_408 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_18_CLKF_IN0, + I1 => NlwInverterSignal_REG_0_18_CLKF_IN1, + O => REG_0_18_CLKF + ); + REG_0_18_SETF_409 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_18_SETF_IN1, + I2 => DIN_18_IBUF, + O => REG_0_18_SETF + ); + REG_0_18_RSTF_410 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_18_RSTF_IN1, + I2 => NlwInverterSignal_REG_0_18_RSTF_IN2, + O => REG_0_18_RSTF + ); + REG_0_19_411 : X_BUF + port map ( + I => REG_0_19_Q, + O => REG_0_19 + ); + REG_0_19_tsimcreated_xor_Q_412 : X_XOR2 + port map ( + I0 => REG_0_19_D, + I1 => REG_0_19_Q, + O => REG_0_19_tsimcreated_xor_Q + ); + REG_0_19_tsimcreated_set_and_noreset_Q_413 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_19_tsimcreated_set_and_noreset_IN0, + I1 => REG_0_19_SETF, + O => REG_0_19_tsimcreated_set_and_noreset_Q + ); + REG_0_19_tsimcreated_prld_Q_414 : X_OR2 + port map ( + I0 => REG_0_19_RSTF, + I1 => PRLD, + O => REG_0_19_tsimcreated_prld_Q + ); + REG_0_19_REG : X_FF + port map ( + I => REG_0_19_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_0_19_CLKF, + SET => REG_0_19_tsimcreated_set_and_noreset_Q, + RST => REG_0_19_tsimcreated_prld_Q, + O => REG_0_19_Q + ); + REG_0_19_D_415 : X_XOR2 + port map ( + I0 => REG_0_19_D1, + I1 => REG_0_19_D2, + O => REG_0_19_D + ); + REG_0_19_D1_416 : X_ZERO + port map ( + O => REG_0_19_D1 + ); + REG_0_19_D2_PT_0_417 : X_AND2 + port map ( + I0 => state_0_EXP, + I1 => state_0_EXP, + O => REG_0_19_D2_PT_0 + ); + REG_0_19_D2_PT_1_418 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_19_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_0_19_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_19_D2_PT_1_IN3, + I4 => REG_0_18, + I5 => NlwInverterSignal_REG_0_19_D2_PT_1_IN5, + O => REG_0_19_D2_PT_1 + ); + REG_0_19_D2_PT_2_419 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_19_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_0_19_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_19_D2_PT_2_IN3, + I4 => NlwInverterSignal_REG_0_19_D2_PT_2_IN4, + I5 => REG_0_19, + O => REG_0_19_D2_PT_2 + ); + REG_0_19_D2_420 : X_OR3 + port map ( + I0 => REG_0_19_D2_PT_0, + I1 => REG_0_19_D2_PT_1, + I2 => REG_0_19_D2_PT_2, + O => REG_0_19_D2 + ); + REG_0_19_CLKF_421 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_19_CLKF_IN0, + I1 => NlwInverterSignal_REG_0_19_CLKF_IN1, + O => REG_0_19_CLKF + ); + REG_0_19_SETF_422 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_19_SETF_IN1, + I2 => DIN_19_IBUF, + O => REG_0_19_SETF + ); + REG_0_19_RSTF_423 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_19_RSTF_IN1, + I2 => NlwInverterSignal_REG_0_19_RSTF_IN2, + O => REG_0_19_RSTF + ); + REG_0_2_424 : X_BUF + port map ( + I => REG_0_2_Q, + O => REG_0_2 + ); + REG_0_2_tsimcreated_xor_Q_425 : X_XOR2 + port map ( + I0 => REG_0_2_D, + I1 => REG_0_2_Q, + O => REG_0_2_tsimcreated_xor_Q + ); + REG_0_2_tsimcreated_set_and_noreset_Q_426 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_2_tsimcreated_set_and_noreset_IN0, + I1 => REG_0_2_SETF, + O => REG_0_2_tsimcreated_set_and_noreset_Q + ); + REG_0_2_tsimcreated_prld_Q_427 : X_OR2 + port map ( + I0 => REG_0_2_RSTF, + I1 => PRLD, + O => REG_0_2_tsimcreated_prld_Q + ); + REG_0_2_REG : X_FF + port map ( + I => REG_0_2_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_0_2_CLKF, + SET => REG_0_2_tsimcreated_set_and_noreset_Q, + RST => REG_0_2_tsimcreated_prld_Q, + O => REG_0_2_Q + ); + REG_0_2_D_428 : X_XOR2 + port map ( + I0 => REG_0_2_D1, + I1 => REG_0_2_D2, + O => REG_0_2_D + ); + REG_0_2_D1_429 : X_ZERO + port map ( + O => REG_0_2_D1 + ); + REG_0_2_D2_PT_0_430 : X_AND2 + port map ( + I0 => REG_0_3_EXP, + I1 => REG_0_3_EXP, + O => REG_0_2_D2_PT_0 + ); + REG_0_2_D2_PT_1_431 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_2_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_0_2_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_2_D2_PT_1_IN3, + I4 => REG_0_1, + I5 => NlwInverterSignal_REG_0_2_D2_PT_1_IN5, + O => REG_0_2_D2_PT_1 + ); + REG_0_2_D2_PT_2_432 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_2_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_0_2_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_2_D2_PT_2_IN3, + I4 => NlwInverterSignal_REG_0_2_D2_PT_2_IN4, + I5 => REG_0_2, + O => REG_0_2_D2_PT_2 + ); + REG_0_2_D2_433 : X_OR3 + port map ( + I0 => REG_0_2_D2_PT_0, + I1 => REG_0_2_D2_PT_1, + I2 => REG_0_2_D2_PT_2, + O => REG_0_2_D2 + ); + REG_0_2_CLKF_434 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_2_CLKF_IN0, + I1 => NlwInverterSignal_REG_0_2_CLKF_IN1, + O => REG_0_2_CLKF + ); + REG_0_2_SETF_435 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_2_SETF_IN1, + I2 => DIN_2_IBUF, + O => REG_0_2_SETF + ); + REG_0_2_RSTF_436 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_2_RSTF_IN1, + I2 => NlwInverterSignal_REG_0_2_RSTF_IN2, + O => REG_0_2_RSTF + ); + REG_0_20_437 : X_BUF + port map ( + I => REG_0_20_Q, + O => REG_0_20 + ); + REG_0_20_tsimcreated_xor_Q_438 : X_XOR2 + port map ( + I0 => REG_0_20_D, + I1 => REG_0_20_Q, + O => REG_0_20_tsimcreated_xor_Q + ); + REG_0_20_tsimcreated_set_and_noreset_Q_439 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_20_tsimcreated_set_and_noreset_IN0, + I1 => REG_0_20_SETF, + O => REG_0_20_tsimcreated_set_and_noreset_Q + ); + REG_0_20_tsimcreated_prld_Q_440 : X_OR2 + port map ( + I0 => REG_0_20_RSTF, + I1 => PRLD, + O => REG_0_20_tsimcreated_prld_Q + ); + REG_0_20_REG : X_FF + port map ( + I => REG_0_20_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_0_20_CLKF, + SET => REG_0_20_tsimcreated_set_and_noreset_Q, + RST => REG_0_20_tsimcreated_prld_Q, + O => REG_0_20_Q + ); + REG_0_20_D_441 : X_XOR2 + port map ( + I0 => REG_0_20_D1, + I1 => REG_0_20_D2, + O => REG_0_20_D + ); + REG_0_20_D1_442 : X_ZERO + port map ( + O => REG_0_20_D1 + ); + REG_0_20_D2_PT_0_443 : X_AND2 + port map ( + I0 => EXP31_EXP, + I1 => EXP31_EXP, + O => REG_0_20_D2_PT_0 + ); + REG_0_20_D2_PT_1_444 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_20_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_0_20_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_20_D2_PT_1_IN3, + I4 => REG_0_19, + I5 => NlwInverterSignal_REG_0_20_D2_PT_1_IN5, + O => REG_0_20_D2_PT_1 + ); + REG_0_20_D2_PT_2_445 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_20_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_0_20_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_20_D2_PT_2_IN3, + I4 => NlwInverterSignal_REG_0_20_D2_PT_2_IN4, + I5 => REG_0_20, + O => REG_0_20_D2_PT_2 + ); + REG_0_20_D2_446 : X_OR3 + port map ( + I0 => REG_0_20_D2_PT_0, + I1 => REG_0_20_D2_PT_1, + I2 => REG_0_20_D2_PT_2, + O => REG_0_20_D2 + ); + REG_0_20_CLKF_447 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_20_CLKF_IN0, + I1 => NlwInverterSignal_REG_0_20_CLKF_IN1, + O => REG_0_20_CLKF + ); + REG_0_20_SETF_448 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_20_SETF_IN1, + I2 => DIN_20_IBUF, + O => REG_0_20_SETF + ); + REG_0_20_RSTF_449 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_20_RSTF_IN1, + I2 => NlwInverterSignal_REG_0_20_RSTF_IN2, + O => REG_0_20_RSTF + ); + REG_0_21_450 : X_BUF + port map ( + I => REG_0_21_Q, + O => REG_0_21 + ); + REG_0_21_EXP_451 : X_BUF + port map ( + I => REG_0_21_EXP_tsimrenamed_net_Q, + O => REG_0_21_EXP + ); + REG_0_21_tsimcreated_xor_Q_452 : X_XOR2 + port map ( + I0 => REG_0_21_D, + I1 => REG_0_21_Q, + O => REG_0_21_tsimcreated_xor_Q + ); + REG_0_21_tsimcreated_set_and_noreset_Q_453 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_21_tsimcreated_set_and_noreset_IN0, + I1 => REG_0_21_SETF, + O => REG_0_21_tsimcreated_set_and_noreset_Q + ); + REG_0_21_tsimcreated_prld_Q_454 : X_OR2 + port map ( + I0 => REG_0_21_RSTF, + I1 => PRLD, + O => REG_0_21_tsimcreated_prld_Q + ); + REG_0_21_REG : X_FF + port map ( + I => REG_0_21_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_0_21_CLKF, + SET => REG_0_21_tsimcreated_set_and_noreset_Q, + RST => REG_0_21_tsimcreated_prld_Q, + O => REG_0_21_Q + ); + REG_0_21_D_455 : X_XOR2 + port map ( + I0 => REG_0_21_D1, + I1 => REG_0_21_D2, + O => REG_0_21_D + ); + REG_0_21_D1_456 : X_ZERO + port map ( + O => REG_0_21_D1 + ); + REG_0_21_D2_PT_0_457 : X_AND2 + port map ( + I0 => EXP34_EXP, + I1 => EXP34_EXP, + O => REG_0_21_D2_PT_0 + ); + REG_0_21_D2_PT_1_458 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_21_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_0_21_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_21_D2_PT_1_IN3, + I4 => NlwInverterSignal_REG_0_21_D2_PT_1_IN4, + I5 => REG_0_21, + O => REG_0_21_D2_PT_1 + ); + REG_0_21_D2_459 : X_OR2 + port map ( + I0 => REG_0_21_D2_PT_0, + I1 => REG_0_21_D2_PT_1, + O => REG_0_21_D2 + ); + REG_0_21_CLKF_460 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_21_CLKF_IN0, + I1 => NlwInverterSignal_REG_0_21_CLKF_IN1, + O => REG_0_21_CLKF + ); + REG_0_21_SETF_461 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_21_SETF_IN1, + I2 => DIN_21_IBUF, + O => REG_0_21_SETF + ); + REG_0_21_RSTF_462 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_21_RSTF_IN1, + I2 => NlwInverterSignal_REG_0_21_RSTF_IN2, + O => REG_0_21_RSTF + ); + REG_0_21_EXP_tsimrenamed_net_Q_463 : X_AND7 + port map ( + I0 => NlwInverterSignal_REG_0_21_EXP_tsimrenamed_net_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_REG_0_21_EXP_tsimrenamed_net_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_REG_0_21_EXP_tsimrenamed_net_IN4, + I5 => NlwInverterSignal_REG_0_21_EXP_tsimrenamed_net_IN5, + I6 => DIN_22_IBUF, + O => REG_0_21_EXP_tsimrenamed_net_Q + ); + REG_0_22_464 : X_BUF + port map ( + I => REG_0_22_Q, + O => REG_0_22 + ); + REG_0_22_tsimcreated_xor_Q_465 : X_XOR2 + port map ( + I0 => REG_0_22_D, + I1 => REG_0_22_Q, + O => REG_0_22_tsimcreated_xor_Q + ); + REG_0_22_tsimcreated_set_and_noreset_Q_466 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_22_tsimcreated_set_and_noreset_IN0, + I1 => REG_0_22_SETF, + O => REG_0_22_tsimcreated_set_and_noreset_Q + ); + REG_0_22_tsimcreated_prld_Q_467 : X_OR2 + port map ( + I0 => REG_0_22_RSTF, + I1 => PRLD, + O => REG_0_22_tsimcreated_prld_Q + ); + REG_0_22_REG : X_FF + port map ( + I => REG_0_22_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_0_22_CLKF, + SET => REG_0_22_tsimcreated_set_and_noreset_Q, + RST => REG_0_22_tsimcreated_prld_Q, + O => REG_0_22_Q + ); + REG_0_22_D_468 : X_XOR2 + port map ( + I0 => REG_0_22_D1, + I1 => REG_0_22_D2, + O => REG_0_22_D + ); + REG_0_22_D1_469 : X_ZERO + port map ( + O => REG_0_22_D1 + ); + REG_0_22_D2_PT_0_470 : X_AND2 + port map ( + I0 => REG_0_21_EXP, + I1 => REG_0_21_EXP, + O => REG_0_22_D2_PT_0 + ); + REG_0_22_D2_PT_1_471 : X_AND2 + port map ( + I0 => REG_0_23_EXP, + I1 => REG_0_23_EXP, + O => REG_0_22_D2_PT_1 + ); + REG_0_22_D2_PT_2_472 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_22_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_0_22_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_22_D2_PT_2_IN3, + I4 => REG_0_21, + I5 => NlwInverterSignal_REG_0_22_D2_PT_2_IN5, + O => REG_0_22_D2_PT_2 + ); + REG_0_22_D2_PT_3_473 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_22_D2_PT_3_IN0, + I1 => NlwInverterSignal_REG_0_22_D2_PT_3_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_22_D2_PT_3_IN3, + I4 => NlwInverterSignal_REG_0_22_D2_PT_3_IN4, + I5 => REG_0_22, + O => REG_0_22_D2_PT_3 + ); + REG_0_22_D2_474 : X_OR4 + port map ( + I0 => REG_0_22_D2_PT_0, + I1 => REG_0_22_D2_PT_1, + I2 => REG_0_22_D2_PT_2, + I3 => REG_0_22_D2_PT_3, + O => REG_0_22_D2 + ); + REG_0_22_CLKF_475 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_22_CLKF_IN0, + I1 => NlwInverterSignal_REG_0_22_CLKF_IN1, + O => REG_0_22_CLKF + ); + REG_0_22_SETF_476 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_22_SETF_IN1, + I2 => DIN_22_IBUF, + O => REG_0_22_SETF + ); + REG_0_22_RSTF_477 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_22_RSTF_IN1, + I2 => NlwInverterSignal_REG_0_22_RSTF_IN2, + O => REG_0_22_RSTF + ); + REG_0_23_478 : X_BUF + port map ( + I => REG_0_23_Q, + O => REG_0_23 + ); + REG_0_23_EXP_479 : X_BUF + port map ( + I => REG_0_23_EXP_tsimrenamed_net_Q, + O => REG_0_23_EXP + ); + REG_0_23_tsimcreated_xor_Q_480 : X_XOR2 + port map ( + I0 => REG_0_23_D, + I1 => REG_0_23_Q, + O => REG_0_23_tsimcreated_xor_Q + ); + REG_0_23_tsimcreated_set_and_noreset_Q_481 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_23_tsimcreated_set_and_noreset_IN0, + I1 => REG_0_23_SETF, + O => REG_0_23_tsimcreated_set_and_noreset_Q + ); + REG_0_23_tsimcreated_prld_Q_482 : X_OR2 + port map ( + I0 => REG_0_23_RSTF, + I1 => PRLD, + O => REG_0_23_tsimcreated_prld_Q + ); + REG_0_23_REG : X_FF + port map ( + I => REG_0_23_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_0_23_CLKF, + SET => REG_0_23_tsimcreated_set_and_noreset_Q, + RST => REG_0_23_tsimcreated_prld_Q, + O => REG_0_23_Q + ); + REG_0_23_D_483 : X_XOR2 + port map ( + I0 => REG_0_23_D1, + I1 => REG_0_23_D2, + O => REG_0_23_D + ); + REG_0_23_D1_484 : X_ZERO + port map ( + O => REG_0_23_D1 + ); + REG_0_23_D2_PT_0_485 : X_AND2 + port map ( + I0 => EXP33_EXP, + I1 => EXP33_EXP, + O => REG_0_23_D2_PT_0 + ); + REG_0_23_D2_PT_1_486 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_23_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_0_23_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_23_D2_PT_1_IN3, + I4 => NlwInverterSignal_REG_0_23_D2_PT_1_IN4, + I5 => REG_0_23, + O => REG_0_23_D2_PT_1 + ); + REG_0_23_D2_487 : X_OR2 + port map ( + I0 => REG_0_23_D2_PT_0, + I1 => REG_0_23_D2_PT_1, + O => REG_0_23_D2 + ); + REG_0_23_CLKF_488 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_23_CLKF_IN0, + I1 => NlwInverterSignal_REG_0_23_CLKF_IN1, + O => REG_0_23_CLKF + ); + REG_0_23_SETF_489 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_23_SETF_IN1, + I2 => DIN_23_IBUF, + O => REG_0_23_SETF + ); + REG_0_23_RSTF_490 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_23_RSTF_IN1, + I2 => NlwInverterSignal_REG_0_23_RSTF_IN2, + O => REG_0_23_RSTF + ); + REG_0_23_EXP_tsimrenamed_net_Q_491 : X_AND7 + port map ( + I0 => NlwInverterSignal_REG_0_23_EXP_tsimrenamed_net_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_REG_0_23_EXP_tsimrenamed_net_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_REG_0_23_EXP_tsimrenamed_net_IN4, + I5 => REG_0_22, + I6 => NlwInverterSignal_REG_0_23_EXP_tsimrenamed_net_IN6, + O => REG_0_23_EXP_tsimrenamed_net_Q + ); + REG_0_24_492 : X_BUF + port map ( + I => REG_0_24_Q, + O => REG_0_24 + ); + REG_0_24_tsimcreated_xor_Q_493 : X_XOR2 + port map ( + I0 => REG_0_24_D, + I1 => REG_0_24_Q, + O => REG_0_24_tsimcreated_xor_Q + ); + REG_0_24_tsimcreated_set_and_noreset_Q_494 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_24_tsimcreated_set_and_noreset_IN0, + I1 => REG_0_24_SETF, + O => REG_0_24_tsimcreated_set_and_noreset_Q + ); + REG_0_24_tsimcreated_prld_Q_495 : X_OR2 + port map ( + I0 => REG_0_24_RSTF, + I1 => PRLD, + O => REG_0_24_tsimcreated_prld_Q + ); + REG_0_24_REG : X_FF + port map ( + I => REG_0_24_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_0_24_CLKF, + SET => REG_0_24_tsimcreated_set_and_noreset_Q, + RST => REG_0_24_tsimcreated_prld_Q, + O => REG_0_24_Q + ); + REG_0_24_D_496 : X_XOR2 + port map ( + I0 => REG_0_24_D1, + I1 => REG_0_24_D2, + O => REG_0_24_D + ); + REG_0_24_D1_497 : X_ZERO + port map ( + O => REG_0_24_D1 + ); + REG_0_24_D2_PT_0_498 : X_AND2 + port map ( + I0 => EXP36_EXP, + I1 => EXP36_EXP, + O => REG_0_24_D2_PT_0 + ); + REG_0_24_D2_PT_1_499 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_24_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_0_24_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_24_D2_PT_1_IN3, + I4 => REG_0_23, + I5 => NlwInverterSignal_REG_0_24_D2_PT_1_IN5, + O => REG_0_24_D2_PT_1 + ); + REG_0_24_D2_PT_2_500 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_24_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_0_24_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_24_D2_PT_2_IN3, + I4 => NlwInverterSignal_REG_0_24_D2_PT_2_IN4, + I5 => REG_0_24, + O => REG_0_24_D2_PT_2 + ); + REG_0_24_D2_501 : X_OR3 + port map ( + I0 => REG_0_24_D2_PT_0, + I1 => REG_0_24_D2_PT_1, + I2 => REG_0_24_D2_PT_2, + O => REG_0_24_D2 + ); + REG_0_24_CLKF_502 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_24_CLKF_IN0, + I1 => NlwInverterSignal_REG_0_24_CLKF_IN1, + O => REG_0_24_CLKF + ); + REG_0_24_SETF_503 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_24_SETF_IN1, + I2 => DIN_24_IBUF, + O => REG_0_24_SETF + ); + REG_0_24_RSTF_504 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_24_RSTF_IN1, + I2 => NlwInverterSignal_REG_0_24_RSTF_IN2, + O => REG_0_24_RSTF + ); + REG_0_25_505 : X_BUF + port map ( + I => REG_0_25_Q, + O => REG_0_25 + ); + REG_0_25_tsimcreated_xor_Q_506 : X_XOR2 + port map ( + I0 => REG_0_25_D, + I1 => REG_0_25_Q, + O => REG_0_25_tsimcreated_xor_Q + ); + REG_0_25_tsimcreated_set_and_noreset_Q_507 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_25_tsimcreated_set_and_noreset_IN0, + I1 => REG_0_25_SETF, + O => REG_0_25_tsimcreated_set_and_noreset_Q + ); + REG_0_25_tsimcreated_prld_Q_508 : X_OR2 + port map ( + I0 => REG_0_25_RSTF, + I1 => PRLD, + O => REG_0_25_tsimcreated_prld_Q + ); + REG_0_25_REG : X_FF + port map ( + I => REG_0_25_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_0_25_CLKF, + SET => REG_0_25_tsimcreated_set_and_noreset_Q, + RST => REG_0_25_tsimcreated_prld_Q, + O => REG_0_25_Q + ); + REG_0_25_D_509 : X_XOR2 + port map ( + I0 => REG_0_25_D1, + I1 => REG_0_25_D2, + O => REG_0_25_D + ); + REG_0_25_D1_510 : X_ZERO + port map ( + O => REG_0_25_D1 + ); + REG_0_25_D2_PT_0_511 : X_AND2 + port map ( + I0 => state_1_EXP, + I1 => state_1_EXP, + O => REG_0_25_D2_PT_0 + ); + REG_0_25_D2_PT_1_512 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_25_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_0_25_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_25_D2_PT_1_IN3, + I4 => REG_0_24, + I5 => NlwInverterSignal_REG_0_25_D2_PT_1_IN5, + O => REG_0_25_D2_PT_1 + ); + REG_0_25_D2_PT_2_513 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_25_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_0_25_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_25_D2_PT_2_IN3, + I4 => NlwInverterSignal_REG_0_25_D2_PT_2_IN4, + I5 => REG_0_25, + O => REG_0_25_D2_PT_2 + ); + REG_0_25_D2_514 : X_OR3 + port map ( + I0 => REG_0_25_D2_PT_0, + I1 => REG_0_25_D2_PT_1, + I2 => REG_0_25_D2_PT_2, + O => REG_0_25_D2 + ); + REG_0_25_CLKF_515 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_25_CLKF_IN0, + I1 => NlwInverterSignal_REG_0_25_CLKF_IN1, + O => REG_0_25_CLKF + ); + REG_0_25_SETF_516 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_25_SETF_IN1, + I2 => DIN_25_IBUF, + O => REG_0_25_SETF + ); + REG_0_25_RSTF_517 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_25_RSTF_IN1, + I2 => NlwInverterSignal_REG_0_25_RSTF_IN2, + O => REG_0_25_RSTF + ); + REG_0_26_518 : X_BUF + port map ( + I => REG_0_26_Q, + O => REG_0_26 + ); + REG_0_26_tsimcreated_xor_Q_519 : X_XOR2 + port map ( + I0 => REG_0_26_D, + I1 => REG_0_26_Q, + O => REG_0_26_tsimcreated_xor_Q + ); + REG_0_26_tsimcreated_set_and_noreset_Q_520 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_26_tsimcreated_set_and_noreset_IN0, + I1 => REG_0_26_SETF, + O => REG_0_26_tsimcreated_set_and_noreset_Q + ); + REG_0_26_tsimcreated_prld_Q_521 : X_OR2 + port map ( + I0 => REG_0_26_RSTF, + I1 => PRLD, + O => REG_0_26_tsimcreated_prld_Q + ); + REG_0_26_REG : X_FF + port map ( + I => REG_0_26_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_0_26_CLKF, + SET => REG_0_26_tsimcreated_set_and_noreset_Q, + RST => REG_0_26_tsimcreated_prld_Q, + O => REG_0_26_Q + ); + REG_0_26_D_522 : X_XOR2 + port map ( + I0 => REG_0_26_D1, + I1 => REG_0_26_D2, + O => REG_0_26_D + ); + REG_0_26_D1_523 : X_ZERO + port map ( + O => REG_0_26_D1 + ); + REG_0_26_D2_PT_0_524 : X_AND2 + port map ( + I0 => EXP35_EXP, + I1 => EXP35_EXP, + O => REG_0_26_D2_PT_0 + ); + REG_0_26_D2_PT_1_525 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_26_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_0_26_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_26_D2_PT_1_IN3, + I4 => REG_0_25, + I5 => NlwInverterSignal_REG_0_26_D2_PT_1_IN5, + O => REG_0_26_D2_PT_1 + ); + REG_0_26_D2_PT_2_526 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_26_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_0_26_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_26_D2_PT_2_IN3, + I4 => NlwInverterSignal_REG_0_26_D2_PT_2_IN4, + I5 => REG_0_26, + O => REG_0_26_D2_PT_2 + ); + REG_0_26_D2_527 : X_OR3 + port map ( + I0 => REG_0_26_D2_PT_0, + I1 => REG_0_26_D2_PT_1, + I2 => REG_0_26_D2_PT_2, + O => REG_0_26_D2 + ); + REG_0_26_CLKF_528 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_26_CLKF_IN0, + I1 => NlwInverterSignal_REG_0_26_CLKF_IN1, + O => REG_0_26_CLKF + ); + REG_0_26_SETF_529 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_26_SETF_IN1, + I2 => DIN_26_IBUF, + O => REG_0_26_SETF + ); + REG_0_26_RSTF_530 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_26_RSTF_IN1, + I2 => NlwInverterSignal_REG_0_26_RSTF_IN2, + O => REG_0_26_RSTF + ); + REG_0_27_531 : X_BUF + port map ( + I => REG_0_27_Q, + O => REG_0_27 + ); + REG_0_27_EXP_532 : X_BUF + port map ( + I => REG_0_27_EXP_tsimrenamed_net_Q, + O => REG_0_27_EXP + ); + REG_0_27_tsimcreated_xor_Q_533 : X_XOR2 + port map ( + I0 => REG_0_27_D, + I1 => REG_0_27_Q, + O => REG_0_27_tsimcreated_xor_Q + ); + REG_0_27_tsimcreated_set_and_noreset_Q_534 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_27_tsimcreated_set_and_noreset_IN0, + I1 => REG_0_27_SETF, + O => REG_0_27_tsimcreated_set_and_noreset_Q + ); + REG_0_27_tsimcreated_prld_Q_535 : X_OR2 + port map ( + I0 => REG_0_27_RSTF, + I1 => PRLD, + O => REG_0_27_tsimcreated_prld_Q + ); + REG_0_27_REG : X_FF + port map ( + I => REG_0_27_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_0_27_CLKF, + SET => REG_0_27_tsimcreated_set_and_noreset_Q, + RST => REG_0_27_tsimcreated_prld_Q, + O => REG_0_27_Q + ); + REG_0_27_D_536 : X_XOR2 + port map ( + I0 => REG_0_27_D1, + I1 => REG_0_27_D2, + O => REG_0_27_D + ); + REG_0_27_D1_537 : X_ZERO + port map ( + O => REG_0_27_D1 + ); + REG_0_27_D2_PT_0_538 : X_AND2 + port map ( + I0 => EXP39_EXP, + I1 => EXP39_EXP, + O => REG_0_27_D2_PT_0 + ); + REG_0_27_D2_PT_1_539 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_27_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_0_27_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_27_D2_PT_1_IN3, + I4 => NlwInverterSignal_REG_0_27_D2_PT_1_IN4, + I5 => REG_0_27, + O => REG_0_27_D2_PT_1 + ); + REG_0_27_D2_540 : X_OR2 + port map ( + I0 => REG_0_27_D2_PT_0, + I1 => REG_0_27_D2_PT_1, + O => REG_0_27_D2 + ); + REG_0_27_CLKF_541 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_27_CLKF_IN0, + I1 => NlwInverterSignal_REG_0_27_CLKF_IN1, + O => REG_0_27_CLKF + ); + REG_0_27_SETF_542 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_27_SETF_IN1, + I2 => DIN_27_IBUF, + O => REG_0_27_SETF + ); + REG_0_27_RSTF_543 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_27_RSTF_IN1, + I2 => NlwInverterSignal_REG_0_27_RSTF_IN2, + O => REG_0_27_RSTF + ); + REG_0_27_EXP_tsimrenamed_net_Q_544 : X_AND7 + port map ( + I0 => NlwInverterSignal_REG_0_27_EXP_tsimrenamed_net_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => DIN_23_IBUF, + I6 => NlwInverterSignal_REG_0_27_EXP_tsimrenamed_net_IN6, + O => REG_0_27_EXP_tsimrenamed_net_Q + ); + REG_0_28_545 : X_BUF + port map ( + I => REG_0_28_Q, + O => REG_0_28 + ); + REG_0_28_tsimcreated_xor_Q_546 : X_XOR2 + port map ( + I0 => REG_0_28_D, + I1 => REG_0_28_Q, + O => REG_0_28_tsimcreated_xor_Q + ); + REG_0_28_tsimcreated_set_and_noreset_Q_547 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_28_tsimcreated_set_and_noreset_IN0, + I1 => REG_0_28_SETF, + O => REG_0_28_tsimcreated_set_and_noreset_Q + ); + REG_0_28_tsimcreated_prld_Q_548 : X_OR2 + port map ( + I0 => REG_0_28_RSTF, + I1 => PRLD, + O => REG_0_28_tsimcreated_prld_Q + ); + REG_0_28_REG : X_FF + port map ( + I => REG_0_28_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_0_28_CLKF, + SET => REG_0_28_tsimcreated_set_and_noreset_Q, + RST => REG_0_28_tsimcreated_prld_Q, + O => REG_0_28_Q + ); + REG_0_28_D_549 : X_XOR2 + port map ( + I0 => REG_0_28_D1, + I1 => REG_0_28_D2, + O => REG_0_28_D + ); + REG_0_28_D1_550 : X_ZERO + port map ( + O => REG_0_28_D1 + ); + REG_0_28_D2_PT_0_551 : X_AND2 + port map ( + I0 => EXP26_EXP, + I1 => EXP26_EXP, + O => REG_0_28_D2_PT_0 + ); + REG_0_28_D2_PT_1_552 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_28_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_0_28_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_28_D2_PT_1_IN3, + I4 => REG_0_27, + I5 => NlwInverterSignal_REG_0_28_D2_PT_1_IN5, + O => REG_0_28_D2_PT_1 + ); + REG_0_28_D2_PT_2_553 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_28_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_0_28_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_28_D2_PT_2_IN3, + I4 => NlwInverterSignal_REG_0_28_D2_PT_2_IN4, + I5 => REG_0_28, + O => REG_0_28_D2_PT_2 + ); + REG_0_28_D2_554 : X_OR3 + port map ( + I0 => REG_0_28_D2_PT_0, + I1 => REG_0_28_D2_PT_1, + I2 => REG_0_28_D2_PT_2, + O => REG_0_28_D2 + ); + REG_0_28_CLKF_555 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_28_CLKF_IN0, + I1 => NlwInverterSignal_REG_0_28_CLKF_IN1, + O => REG_0_28_CLKF + ); + REG_0_28_SETF_556 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_28_SETF_IN1, + I2 => DIN_28_IBUF, + O => REG_0_28_SETF + ); + REG_0_28_RSTF_557 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_28_RSTF_IN1, + I2 => NlwInverterSignal_REG_0_28_RSTF_IN2, + O => REG_0_28_RSTF + ); + REG_0_29_558 : X_BUF + port map ( + I => REG_0_29_Q, + O => REG_0_29 + ); + REG_0_29_tsimcreated_xor_Q_559 : X_XOR2 + port map ( + I0 => REG_0_29_D, + I1 => REG_0_29_Q, + O => REG_0_29_tsimcreated_xor_Q + ); + REG_0_29_tsimcreated_set_and_noreset_Q_560 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_29_tsimcreated_set_and_noreset_IN0, + I1 => REG_0_29_SETF, + O => REG_0_29_tsimcreated_set_and_noreset_Q + ); + REG_0_29_tsimcreated_prld_Q_561 : X_OR2 + port map ( + I0 => REG_0_29_RSTF, + I1 => PRLD, + O => REG_0_29_tsimcreated_prld_Q + ); + REG_0_29_REG : X_FF + port map ( + I => REG_0_29_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_0_29_CLKF, + SET => REG_0_29_tsimcreated_set_and_noreset_Q, + RST => REG_0_29_tsimcreated_prld_Q, + O => REG_0_29_Q + ); + REG_0_29_D_562 : X_XOR2 + port map ( + I0 => REG_0_29_D1, + I1 => REG_0_29_D2, + O => REG_0_29_D + ); + REG_0_29_D1_563 : X_ZERO + port map ( + O => REG_0_29_D1 + ); + REG_0_29_D2_PT_0_564 : X_AND2 + port map ( + I0 => REG_0_30_EXP, + I1 => REG_0_30_EXP, + O => REG_0_29_D2_PT_0 + ); + REG_0_29_D2_PT_1_565 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_29_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_0_29_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_29_D2_PT_1_IN3, + I4 => REG_0_28, + I5 => NlwInverterSignal_REG_0_29_D2_PT_1_IN5, + O => REG_0_29_D2_PT_1 + ); + REG_0_29_D2_PT_2_566 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_29_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_0_29_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_29_D2_PT_2_IN3, + I4 => NlwInverterSignal_REG_0_29_D2_PT_2_IN4, + I5 => REG_0_29, + O => REG_0_29_D2_PT_2 + ); + REG_0_29_D2_567 : X_OR3 + port map ( + I0 => REG_0_29_D2_PT_0, + I1 => REG_0_29_D2_PT_1, + I2 => REG_0_29_D2_PT_2, + O => REG_0_29_D2 + ); + REG_0_29_CLKF_568 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_29_CLKF_IN0, + I1 => NlwInverterSignal_REG_0_29_CLKF_IN1, + O => REG_0_29_CLKF + ); + REG_0_29_SETF_569 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_29_SETF_IN1, + I2 => DIN_29_IBUF, + O => REG_0_29_SETF + ); + REG_0_29_RSTF_570 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_29_RSTF_IN1, + I2 => NlwInverterSignal_REG_0_29_RSTF_IN2, + O => REG_0_29_RSTF + ); + REG_0_3_571 : X_BUF + port map ( + I => REG_0_3_Q, + O => REG_0_3 + ); + REG_0_3_EXP_572 : X_BUF + port map ( + I => REG_0_3_EXP_tsimrenamed_net_Q, + O => REG_0_3_EXP + ); + REG_0_3_tsimcreated_xor_Q_573 : X_XOR2 + port map ( + I0 => REG_0_3_D, + I1 => REG_0_3_Q, + O => REG_0_3_tsimcreated_xor_Q + ); + REG_0_3_tsimcreated_set_and_noreset_Q_574 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_3_tsimcreated_set_and_noreset_IN0, + I1 => REG_0_3_SETF, + O => REG_0_3_tsimcreated_set_and_noreset_Q + ); + REG_0_3_tsimcreated_prld_Q_575 : X_OR2 + port map ( + I0 => REG_0_3_RSTF, + I1 => PRLD, + O => REG_0_3_tsimcreated_prld_Q + ); + REG_0_3_REG : X_FF + port map ( + I => REG_0_3_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_0_3_CLKF, + SET => REG_0_3_tsimcreated_set_and_noreset_Q, + RST => REG_0_3_tsimcreated_prld_Q, + O => REG_0_3_Q + ); + REG_0_3_D_576 : X_XOR2 + port map ( + I0 => REG_0_3_D1, + I1 => REG_0_3_D2, + O => REG_0_3_D + ); + REG_0_3_D1_577 : X_ZERO + port map ( + O => REG_0_3_D1 + ); + REG_0_3_D2_578 : X_AND2 + port map ( + I0 => EXP23_EXP, + I1 => EXP23_EXP, + O => REG_0_3_D2 + ); + REG_0_3_CLKF_579 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_3_CLKF_IN0, + I1 => NlwInverterSignal_REG_0_3_CLKF_IN1, + O => REG_0_3_CLKF + ); + REG_0_3_SETF_580 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_3_SETF_IN1, + I2 => DIN_3_IBUF, + O => REG_0_3_SETF + ); + REG_0_3_RSTF_581 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_3_RSTF_IN1, + I2 => NlwInverterSignal_REG_0_3_RSTF_IN2, + O => REG_0_3_RSTF + ); + REG_0_3_EXP_PT_0_582 : X_AND7 + port map ( + I0 => NlwInverterSignal_REG_0_3_EXP_PT_0_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_REG_0_3_EXP_PT_0_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_REG_0_3_EXP_PT_0_IN4, + I5 => DIN_2_IBUF, + I6 => NlwInverterSignal_REG_0_3_EXP_PT_0_IN6, + O => REG_0_3_EXP_PT_0 + ); + REG_0_3_EXP_PT_1_583 : X_AND7 + port map ( + I0 => NlwInverterSignal_REG_0_3_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_REG_0_3_EXP_PT_1_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_REG_0_3_EXP_PT_1_IN4, + I5 => NlwInverterSignal_REG_0_3_EXP_PT_1_IN5, + I6 => REG_0_2, + O => REG_0_3_EXP_PT_1 + ); + REG_0_3_EXP_tsimrenamed_net_Q_584 : X_OR2 + port map ( + I0 => REG_0_3_EXP_PT_0, + I1 => REG_0_3_EXP_PT_1, + O => REG_0_3_EXP_tsimrenamed_net_Q + ); + REG_0_30_585 : X_BUF + port map ( + I => REG_0_30_Q, + O => REG_0_30 + ); + REG_0_30_EXP_586 : X_BUF + port map ( + I => REG_0_30_EXP_tsimrenamed_net_Q, + O => REG_0_30_EXP + ); + REG_0_30_tsimcreated_xor_Q_587 : X_XOR2 + port map ( + I0 => REG_0_30_D, + I1 => REG_0_30_Q, + O => REG_0_30_tsimcreated_xor_Q + ); + REG_0_30_tsimcreated_set_and_noreset_Q_588 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_30_tsimcreated_set_and_noreset_IN0, + I1 => REG_0_30_SETF, + O => REG_0_30_tsimcreated_set_and_noreset_Q + ); + REG_0_30_tsimcreated_prld_Q_589 : X_OR2 + port map ( + I0 => REG_0_30_RSTF, + I1 => PRLD, + O => REG_0_30_tsimcreated_prld_Q + ); + REG_0_30_REG : X_FF + port map ( + I => REG_0_30_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_0_30_CLKF, + SET => REG_0_30_tsimcreated_set_and_noreset_Q, + RST => REG_0_30_tsimcreated_prld_Q, + O => REG_0_30_Q + ); + REG_0_30_D_590 : X_XOR2 + port map ( + I0 => REG_0_30_D1, + I1 => REG_0_30_D2, + O => REG_0_30_D + ); + REG_0_30_D1_591 : X_ZERO + port map ( + O => REG_0_30_D1 + ); + REG_0_30_D2_592 : X_AND2 + port map ( + I0 => EXP25_EXP, + I1 => EXP25_EXP, + O => REG_0_30_D2 + ); + REG_0_30_CLKF_593 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_30_CLKF_IN0, + I1 => NlwInverterSignal_REG_0_30_CLKF_IN1, + O => REG_0_30_CLKF + ); + REG_0_30_SETF_594 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_30_SETF_IN1, + I2 => DIN_30_IBUF, + O => REG_0_30_SETF + ); + REG_0_30_RSTF_595 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_30_RSTF_IN1, + I2 => NlwInverterSignal_REG_0_30_RSTF_IN2, + O => REG_0_30_RSTF + ); + REG_0_30_EXP_PT_0_596 : X_AND7 + port map ( + I0 => NlwInverterSignal_REG_0_30_EXP_PT_0_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_REG_0_30_EXP_PT_0_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_REG_0_30_EXP_PT_0_IN4, + I5 => DIN_29_IBUF, + I6 => NlwInverterSignal_REG_0_30_EXP_PT_0_IN6, + O => REG_0_30_EXP_PT_0 + ); + REG_0_30_EXP_PT_1_597 : X_AND7 + port map ( + I0 => NlwInverterSignal_REG_0_30_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_REG_0_30_EXP_PT_1_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_REG_0_30_EXP_PT_1_IN4, + I5 => NlwInverterSignal_REG_0_30_EXP_PT_1_IN5, + I6 => REG_0_29, + O => REG_0_30_EXP_PT_1 + ); + REG_0_30_EXP_tsimrenamed_net_Q_598 : X_OR2 + port map ( + I0 => REG_0_30_EXP_PT_0, + I1 => REG_0_30_EXP_PT_1, + O => REG_0_30_EXP_tsimrenamed_net_Q + ); + REG_0_31_599 : X_BUF + port map ( + I => REG_0_31_Q, + O => REG_0_31 + ); + REG_0_31_tsimcreated_xor_Q_600 : X_XOR2 + port map ( + I0 => REG_0_31_D, + I1 => REG_0_31_Q, + O => REG_0_31_tsimcreated_xor_Q + ); + REG_0_31_tsimcreated_set_and_noreset_Q_601 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_31_tsimcreated_set_and_noreset_IN0, + I1 => REG_0_31_SETF, + O => REG_0_31_tsimcreated_set_and_noreset_Q + ); + REG_0_31_tsimcreated_prld_Q_602 : X_OR2 + port map ( + I0 => REG_0_31_RSTF, + I1 => PRLD, + O => REG_0_31_tsimcreated_prld_Q + ); + REG_0_31_REG : X_FF + port map ( + I => REG_0_31_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_0_31_CLKF, + SET => REG_0_31_tsimcreated_set_and_noreset_Q, + RST => REG_0_31_tsimcreated_prld_Q, + O => REG_0_31_Q + ); + REG_0_31_D_603 : X_XOR2 + port map ( + I0 => REG_0_31_D1, + I1 => REG_0_31_D2, + O => REG_0_31_D + ); + REG_0_31_D1_604 : X_ZERO + port map ( + O => REG_0_31_D1 + ); + REG_0_31_D2_PT_0_605 : X_AND2 + port map ( + I0 => EXP24_EXP, + I1 => EXP24_EXP, + O => REG_0_31_D2_PT_0 + ); + REG_0_31_D2_PT_1_606 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_31_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_0_31_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_31_D2_PT_1_IN3, + I4 => REG_0_30, + I5 => NlwInverterSignal_REG_0_31_D2_PT_1_IN5, + O => REG_0_31_D2_PT_1 + ); + REG_0_31_D2_PT_2_607 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_31_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_0_31_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_31_D2_PT_2_IN3, + I4 => NlwInverterSignal_REG_0_31_D2_PT_2_IN4, + I5 => REG_0_31, + O => REG_0_31_D2_PT_2 + ); + REG_0_31_D2_608 : X_OR3 + port map ( + I0 => REG_0_31_D2_PT_0, + I1 => REG_0_31_D2_PT_1, + I2 => REG_0_31_D2_PT_2, + O => REG_0_31_D2 + ); + REG_0_31_CLKF_609 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_31_CLKF_IN0, + I1 => NlwInverterSignal_REG_0_31_CLKF_IN1, + O => REG_0_31_CLKF + ); + REG_0_31_SETF_610 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_31_SETF_IN1, + I2 => DIN_31_IBUF, + O => REG_0_31_SETF + ); + REG_0_31_RSTF_611 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_31_RSTF_IN1, + I2 => NlwInverterSignal_REG_0_31_RSTF_IN2, + O => REG_0_31_RSTF + ); + REG_0_4_612 : X_BUF + port map ( + I => REG_0_4_Q, + O => REG_0_4 + ); + REG_0_4_tsimcreated_xor_Q_613 : X_XOR2 + port map ( + I0 => REG_0_4_D, + I1 => REG_0_4_Q, + O => REG_0_4_tsimcreated_xor_Q + ); + REG_0_4_tsimcreated_set_and_noreset_Q_614 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_4_tsimcreated_set_and_noreset_IN0, + I1 => REG_0_4_SETF, + O => REG_0_4_tsimcreated_set_and_noreset_Q + ); + REG_0_4_tsimcreated_prld_Q_615 : X_OR2 + port map ( + I0 => REG_0_4_RSTF, + I1 => PRLD, + O => REG_0_4_tsimcreated_prld_Q + ); + REG_0_4_REG : X_FF + port map ( + I => REG_0_4_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_0_4_CLKF, + SET => REG_0_4_tsimcreated_set_and_noreset_Q, + RST => REG_0_4_tsimcreated_prld_Q, + O => REG_0_4_Q + ); + REG_0_4_D_616 : X_XOR2 + port map ( + I0 => REG_0_4_D1, + I1 => REG_0_4_D2, + O => REG_0_4_D + ); + REG_0_4_D1_617 : X_ZERO + port map ( + O => REG_0_4_D1 + ); + REG_0_4_D2_PT_0_618 : X_AND2 + port map ( + I0 => REG_0_0_EXP, + I1 => REG_0_0_EXP, + O => REG_0_4_D2_PT_0 + ); + REG_0_4_D2_PT_1_619 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_4_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_0_4_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_4_D2_PT_1_IN3, + I4 => REG_0_4, + I5 => NlwInverterSignal_REG_0_4_D2_PT_1_IN5, + O => REG_0_4_D2_PT_1 + ); + REG_0_4_D2_PT_2_620 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_4_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_0_4_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_4_D2_PT_2_IN3, + I4 => NlwInverterSignal_REG_0_4_D2_PT_2_IN4, + I5 => REG_0_3, + O => REG_0_4_D2_PT_2 + ); + REG_0_4_D2_621 : X_OR3 + port map ( + I0 => REG_0_4_D2_PT_0, + I1 => REG_0_4_D2_PT_1, + I2 => REG_0_4_D2_PT_2, + O => REG_0_4_D2 + ); + REG_0_4_CLKF_622 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_4_CLKF_IN0, + I1 => NlwInverterSignal_REG_0_4_CLKF_IN1, + O => REG_0_4_CLKF + ); + REG_0_4_SETF_623 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_4_SETF_IN1, + I2 => DIN_4_IBUF, + O => REG_0_4_SETF + ); + REG_0_4_RSTF_624 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_4_RSTF_IN1, + I2 => NlwInverterSignal_REG_0_4_RSTF_IN2, + O => REG_0_4_RSTF + ); + REG_0_5_625 : X_BUF + port map ( + I => REG_0_5_Q, + O => REG_0_5 + ); + REG_0_5_tsimcreated_xor_Q_626 : X_XOR2 + port map ( + I0 => REG_0_5_D, + I1 => REG_0_5_Q, + O => REG_0_5_tsimcreated_xor_Q + ); + REG_0_5_tsimcreated_set_and_noreset_Q_627 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_5_tsimcreated_set_and_noreset_IN0, + I1 => REG_0_5_SETF, + O => REG_0_5_tsimcreated_set_and_noreset_Q + ); + REG_0_5_tsimcreated_prld_Q_628 : X_OR2 + port map ( + I0 => REG_0_5_RSTF, + I1 => PRLD, + O => REG_0_5_tsimcreated_prld_Q + ); + REG_0_5_REG : X_FF + port map ( + I => REG_0_5_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_0_5_CLKF, + SET => REG_0_5_tsimcreated_set_and_noreset_Q, + RST => REG_0_5_tsimcreated_prld_Q, + O => REG_0_5_Q + ); + REG_0_5_D_629 : X_XOR2 + port map ( + I0 => REG_0_5_D1, + I1 => REG_0_5_D2, + O => REG_0_5_D + ); + REG_0_5_D1_630 : X_ZERO + port map ( + O => REG_0_5_D1 + ); + REG_0_5_D2_PT_0_631 : X_AND2 + port map ( + I0 => EXP19_EXP, + I1 => EXP19_EXP, + O => REG_0_5_D2_PT_0 + ); + REG_0_5_D2_PT_1_632 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_5_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_0_5_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_5_D2_PT_1_IN3, + I4 => REG_0_4, + I5 => NlwInverterSignal_REG_0_5_D2_PT_1_IN5, + O => REG_0_5_D2_PT_1 + ); + REG_0_5_D2_PT_2_633 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_5_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_0_5_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_5_D2_PT_2_IN3, + I4 => NlwInverterSignal_REG_0_5_D2_PT_2_IN4, + I5 => REG_0_5, + O => REG_0_5_D2_PT_2 + ); + REG_0_5_D2_634 : X_OR3 + port map ( + I0 => REG_0_5_D2_PT_0, + I1 => REG_0_5_D2_PT_1, + I2 => REG_0_5_D2_PT_2, + O => REG_0_5_D2 + ); + REG_0_5_CLKF_635 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_5_CLKF_IN0, + I1 => NlwInverterSignal_REG_0_5_CLKF_IN1, + O => REG_0_5_CLKF + ); + REG_0_5_SETF_636 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_5_SETF_IN1, + I2 => DIN_5_IBUF, + O => REG_0_5_SETF + ); + REG_0_5_RSTF_637 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_5_RSTF_IN1, + I2 => NlwInverterSignal_REG_0_5_RSTF_IN2, + O => REG_0_5_RSTF + ); + REG_0_6_638 : X_BUF + port map ( + I => REG_0_6_Q, + O => REG_0_6 + ); + REG_0_6_tsimcreated_xor_Q_639 : X_XOR2 + port map ( + I0 => REG_0_6_D, + I1 => REG_0_6_Q, + O => REG_0_6_tsimcreated_xor_Q + ); + REG_0_6_tsimcreated_set_and_noreset_Q_640 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_6_tsimcreated_set_and_noreset_IN0, + I1 => REG_0_6_SETF, + O => REG_0_6_tsimcreated_set_and_noreset_Q + ); + REG_0_6_tsimcreated_prld_Q_641 : X_OR2 + port map ( + I0 => REG_0_6_RSTF, + I1 => PRLD, + O => REG_0_6_tsimcreated_prld_Q + ); + REG_0_6_REG : X_FF + port map ( + I => REG_0_6_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_0_6_CLKF, + SET => REG_0_6_tsimcreated_set_and_noreset_Q, + RST => REG_0_6_tsimcreated_prld_Q, + O => REG_0_6_Q + ); + REG_0_6_D_642 : X_XOR2 + port map ( + I0 => REG_0_6_D1, + I1 => REG_0_6_D2, + O => REG_0_6_D + ); + REG_0_6_D1_643 : X_ZERO + port map ( + O => REG_0_6_D1 + ); + REG_0_6_D2_PT_0_644 : X_AND2 + port map ( + I0 => EXP20_EXP, + I1 => EXP20_EXP, + O => REG_0_6_D2_PT_0 + ); + REG_0_6_D2_PT_1_645 : X_AND2 + port map ( + I0 => EXP21_EXP, + I1 => EXP21_EXP, + O => REG_0_6_D2_PT_1 + ); + REG_0_6_D2_PT_2_646 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_6_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_0_6_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_6_D2_PT_2_IN3, + I4 => REG_0_5, + I5 => NlwInverterSignal_REG_0_6_D2_PT_2_IN5, + O => REG_0_6_D2_PT_2 + ); + REG_0_6_D2_PT_3_647 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_6_D2_PT_3_IN0, + I1 => NlwInverterSignal_REG_0_6_D2_PT_3_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_6_D2_PT_3_IN3, + I4 => NlwInverterSignal_REG_0_6_D2_PT_3_IN4, + I5 => REG_0_6, + O => REG_0_6_D2_PT_3 + ); + REG_0_6_D2_648 : X_OR4 + port map ( + I0 => REG_0_6_D2_PT_0, + I1 => REG_0_6_D2_PT_1, + I2 => REG_0_6_D2_PT_2, + I3 => REG_0_6_D2_PT_3, + O => REG_0_6_D2 + ); + REG_0_6_CLKF_649 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_6_CLKF_IN0, + I1 => NlwInverterSignal_REG_0_6_CLKF_IN1, + O => REG_0_6_CLKF + ); + REG_0_6_SETF_650 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_6_SETF_IN1, + I2 => DIN_6_IBUF, + O => REG_0_6_SETF + ); + REG_0_6_RSTF_651 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_6_RSTF_IN1, + I2 => NlwInverterSignal_REG_0_6_RSTF_IN2, + O => REG_0_6_RSTF + ); + REG_0_7_652 : X_BUF + port map ( + I => REG_0_7_Q, + O => REG_0_7 + ); + REG_0_7_EXP_653 : X_BUF + port map ( + I => REG_0_7_EXP_tsimrenamed_net_Q, + O => REG_0_7_EXP + ); + REG_0_7_tsimcreated_xor_Q_654 : X_XOR2 + port map ( + I0 => REG_0_7_D, + I1 => REG_0_7_Q, + O => REG_0_7_tsimcreated_xor_Q + ); + REG_0_7_tsimcreated_set_and_noreset_Q_655 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_7_tsimcreated_set_and_noreset_IN0, + I1 => REG_0_7_SETF, + O => REG_0_7_tsimcreated_set_and_noreset_Q + ); + REG_0_7_tsimcreated_prld_Q_656 : X_OR2 + port map ( + I0 => REG_0_7_RSTF, + I1 => PRLD, + O => REG_0_7_tsimcreated_prld_Q + ); + REG_0_7_REG : X_FF + port map ( + I => REG_0_7_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_0_7_CLKF, + SET => REG_0_7_tsimcreated_set_and_noreset_Q, + RST => REG_0_7_tsimcreated_prld_Q, + O => REG_0_7_Q + ); + REG_0_7_D_657 : X_XOR2 + port map ( + I0 => REG_0_7_D1, + I1 => REG_0_7_D2, + O => REG_0_7_D + ); + REG_0_7_D1_658 : X_ZERO + port map ( + O => REG_0_7_D1 + ); + REG_0_7_D2_PT_0_659 : X_AND2 + port map ( + I0 => EXP46_EXP, + I1 => EXP46_EXP, + O => REG_0_7_D2_PT_0 + ); + REG_0_7_D2_PT_1_660 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_7_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_0_7_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_7_D2_PT_1_IN3, + I4 => NlwInverterSignal_REG_0_7_D2_PT_1_IN4, + I5 => REG_0_7, + O => REG_0_7_D2_PT_1 + ); + REG_0_7_D2_661 : X_OR2 + port map ( + I0 => REG_0_7_D2_PT_0, + I1 => REG_0_7_D2_PT_1, + O => REG_0_7_D2 + ); + REG_0_7_CLKF_662 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_7_CLKF_IN0, + I1 => NlwInverterSignal_REG_0_7_CLKF_IN1, + O => REG_0_7_CLKF + ); + REG_0_7_SETF_663 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_7_SETF_IN1, + I2 => DIN_7_IBUF, + O => REG_0_7_SETF + ); + REG_0_7_RSTF_664 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_7_RSTF_IN1, + I2 => NlwInverterSignal_REG_0_7_RSTF_IN2, + O => REG_0_7_RSTF + ); + REG_0_7_EXP_tsimrenamed_net_Q_665 : X_AND7 + port map ( + I0 => NlwInverterSignal_REG_0_7_EXP_tsimrenamed_net_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_REG_0_7_EXP_tsimrenamed_net_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_REG_0_7_EXP_tsimrenamed_net_IN4, + I5 => NlwInverterSignal_REG_0_7_EXP_tsimrenamed_net_IN5, + I6 => DIN_8_IBUF, + O => REG_0_7_EXP_tsimrenamed_net_Q + ); + REG_0_8_666 : X_BUF + port map ( + I => REG_0_8_Q, + O => REG_0_8 + ); + REG_0_8_tsimcreated_xor_Q_667 : X_XOR2 + port map ( + I0 => REG_0_8_D, + I1 => REG_0_8_Q, + O => REG_0_8_tsimcreated_xor_Q + ); + REG_0_8_tsimcreated_set_and_noreset_Q_668 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_8_tsimcreated_set_and_noreset_IN0, + I1 => REG_0_8_SETF, + O => REG_0_8_tsimcreated_set_and_noreset_Q + ); + REG_0_8_tsimcreated_prld_Q_669 : X_OR2 + port map ( + I0 => REG_0_8_RSTF, + I1 => PRLD, + O => REG_0_8_tsimcreated_prld_Q + ); + REG_0_8_REG : X_FF + port map ( + I => REG_0_8_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_0_8_CLKF, + SET => REG_0_8_tsimcreated_set_and_noreset_Q, + RST => REG_0_8_tsimcreated_prld_Q, + O => REG_0_8_Q + ); + REG_0_8_D_670 : X_XOR2 + port map ( + I0 => REG_0_8_D1, + I1 => REG_0_8_D2, + O => REG_0_8_D + ); + REG_0_8_D1_671 : X_ZERO + port map ( + O => REG_0_8_D1 + ); + REG_0_8_D2_PT_0_672 : X_AND2 + port map ( + I0 => REG_0_7_EXP, + I1 => REG_0_7_EXP, + O => REG_0_8_D2_PT_0 + ); + REG_0_8_D2_PT_1_673 : X_AND2 + port map ( + I0 => REG_0_9_EXP, + I1 => REG_0_9_EXP, + O => REG_0_8_D2_PT_1 + ); + REG_0_8_D2_PT_2_674 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_8_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_0_8_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_8_D2_PT_2_IN3, + I4 => REG_0_7, + I5 => NlwInverterSignal_REG_0_8_D2_PT_2_IN5, + O => REG_0_8_D2_PT_2 + ); + REG_0_8_D2_PT_3_675 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_8_D2_PT_3_IN0, + I1 => NlwInverterSignal_REG_0_8_D2_PT_3_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_8_D2_PT_3_IN3, + I4 => NlwInverterSignal_REG_0_8_D2_PT_3_IN4, + I5 => REG_0_8, + O => REG_0_8_D2_PT_3 + ); + REG_0_8_D2_676 : X_OR4 + port map ( + I0 => REG_0_8_D2_PT_0, + I1 => REG_0_8_D2_PT_1, + I2 => REG_0_8_D2_PT_2, + I3 => REG_0_8_D2_PT_3, + O => REG_0_8_D2 + ); + REG_0_8_CLKF_677 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_8_CLKF_IN0, + I1 => NlwInverterSignal_REG_0_8_CLKF_IN1, + O => REG_0_8_CLKF + ); + REG_0_8_SETF_678 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_8_SETF_IN1, + I2 => DIN_8_IBUF, + O => REG_0_8_SETF + ); + REG_0_8_RSTF_679 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_8_RSTF_IN1, + I2 => NlwInverterSignal_REG_0_8_RSTF_IN2, + O => REG_0_8_RSTF + ); + REG_0_9_680 : X_BUF + port map ( + I => REG_0_9_Q, + O => REG_0_9 + ); + REG_0_9_EXP_681 : X_BUF + port map ( + I => REG_0_9_EXP_tsimrenamed_net_Q, + O => REG_0_9_EXP + ); + REG_0_9_tsimcreated_xor_Q_682 : X_XOR2 + port map ( + I0 => REG_0_9_D, + I1 => REG_0_9_Q, + O => REG_0_9_tsimcreated_xor_Q + ); + REG_0_9_tsimcreated_set_and_noreset_Q_683 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_9_tsimcreated_set_and_noreset_IN0, + I1 => REG_0_9_SETF, + O => REG_0_9_tsimcreated_set_and_noreset_Q + ); + REG_0_9_tsimcreated_prld_Q_684 : X_OR2 + port map ( + I0 => REG_0_9_RSTF, + I1 => PRLD, + O => REG_0_9_tsimcreated_prld_Q + ); + REG_0_9_REG : X_FF + port map ( + I => REG_0_9_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_0_9_CLKF, + SET => REG_0_9_tsimcreated_set_and_noreset_Q, + RST => REG_0_9_tsimcreated_prld_Q, + O => REG_0_9_Q + ); + REG_0_9_D_685 : X_XOR2 + port map ( + I0 => REG_0_9_D1, + I1 => REG_0_9_D2, + O => REG_0_9_D + ); + REG_0_9_D1_686 : X_ZERO + port map ( + O => REG_0_9_D1 + ); + REG_0_9_D2_PT_0_687 : X_AND2 + port map ( + I0 => EXP45_EXP, + I1 => EXP45_EXP, + O => REG_0_9_D2_PT_0 + ); + REG_0_9_D2_PT_1_688 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_0_9_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_0_9_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_REG_0_9_D2_PT_1_IN3, + I4 => REG_0_9, + I5 => NlwInverterSignal_REG_0_9_D2_PT_1_IN5, + O => REG_0_9_D2_PT_1 + ); + REG_0_9_D2_689 : X_OR2 + port map ( + I0 => REG_0_9_D2_PT_0, + I1 => REG_0_9_D2_PT_1, + O => REG_0_9_D2 + ); + REG_0_9_CLKF_690 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_0_9_CLKF_IN0, + I1 => NlwInverterSignal_REG_0_9_CLKF_IN1, + O => REG_0_9_CLKF + ); + REG_0_9_SETF_691 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_9_SETF_IN1, + I2 => DIN_9_IBUF, + O => REG_0_9_SETF + ); + REG_0_9_RSTF_692 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_REG_0_9_RSTF_IN1, + I2 => NlwInverterSignal_REG_0_9_RSTF_IN2, + O => REG_0_9_RSTF + ); + REG_0_9_EXP_tsimrenamed_net_Q_693 : X_AND7 + port map ( + I0 => NlwInverterSignal_REG_0_9_EXP_tsimrenamed_net_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_REG_0_9_EXP_tsimrenamed_net_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_REG_0_9_EXP_tsimrenamed_net_IN4, + I5 => REG_0_8, + I6 => NlwInverterSignal_REG_0_9_EXP_tsimrenamed_net_IN6, + O => REG_0_9_EXP_tsimrenamed_net_Q + ); + REG_1_0_694 : X_BUF + port map ( + I => REG_1_0_Q, + O => REG_1_0 + ); + REG_1_0_EXP_695 : X_BUF + port map ( + I => REG_1_0_EXP_tsimrenamed_net_Q, + O => REG_1_0_EXP + ); + REG_1_0_tsimcreated_xor_Q_696 : X_XOR2 + port map ( + I0 => REG_1_0_D, + I1 => REG_1_0_Q, + O => REG_1_0_tsimcreated_xor_Q + ); + REG_1_0_tsimcreated_set_and_noreset_Q_697 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_0_tsimcreated_set_and_noreset_IN0, + I1 => REG_1_0_SETF, + O => REG_1_0_tsimcreated_set_and_noreset_Q + ); + REG_1_0_tsimcreated_prld_Q_698 : X_OR2 + port map ( + I0 => REG_1_0_RSTF, + I1 => PRLD, + O => REG_1_0_tsimcreated_prld_Q + ); + REG_1_0_REG : X_FF + port map ( + I => REG_1_0_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_1_0_CLKF, + SET => REG_1_0_tsimcreated_set_and_noreset_Q, + RST => REG_1_0_tsimcreated_prld_Q, + O => REG_1_0_Q + ); + REG_1_0_D_699 : X_XOR2 + port map ( + I0 => REG_1_0_D1, + I1 => REG_1_0_D2, + O => REG_1_0_D + ); + REG_1_0_D1_700 : X_ZERO + port map ( + O => REG_1_0_D1 + ); + REG_1_0_D2_701 : X_AND2 + port map ( + I0 => EXP52_EXP, + I1 => EXP52_EXP, + O => REG_1_0_D2 + ); + REG_1_0_CLKF_702 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_0_CLKF_IN0, + I1 => NlwInverterSignal_REG_1_0_CLKF_IN1, + O => REG_1_0_CLKF + ); + REG_1_0_SETF_703 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => DIN_0_IBUF, + O => REG_1_0_SETF + ); + REG_1_0_RSTF_704 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => NlwInverterSignal_REG_1_0_RSTF_IN2, + O => REG_1_0_RSTF + ); + REG_1_0_EXP_PT_0_705 : X_AND7 + port map ( + I0 => NlwInverterSignal_REG_1_0_EXP_PT_0_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => DIN_4_IBUF, + I6 => NlwInverterSignal_REG_1_0_EXP_PT_0_IN6, + O => REG_1_0_EXP_PT_0 + ); + REG_1_0_EXP_PT_1_706 : X_AND7 + port map ( + I0 => NlwInverterSignal_REG_1_0_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => NlwInverterSignal_REG_1_0_EXP_PT_1_IN5, + I6 => REG_1_4, + O => REG_1_0_EXP_PT_1 + ); + REG_1_0_EXP_tsimrenamed_net_Q_707 : X_OR2 + port map ( + I0 => REG_1_0_EXP_PT_0, + I1 => REG_1_0_EXP_PT_1, + O => REG_1_0_EXP_tsimrenamed_net_Q + ); + REG_1_1_708 : X_BUF + port map ( + I => REG_1_1_Q, + O => REG_1_1 + ); + REG_1_1_tsimcreated_xor_Q_709 : X_XOR2 + port map ( + I0 => REG_1_1_D, + I1 => REG_1_1_Q, + O => REG_1_1_tsimcreated_xor_Q + ); + REG_1_1_tsimcreated_set_and_noreset_Q_710 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_1_tsimcreated_set_and_noreset_IN0, + I1 => REG_1_1_SETF, + O => REG_1_1_tsimcreated_set_and_noreset_Q + ); + REG_1_1_tsimcreated_prld_Q_711 : X_OR2 + port map ( + I0 => REG_1_1_RSTF, + I1 => PRLD, + O => REG_1_1_tsimcreated_prld_Q + ); + REG_1_1_REG : X_FF + port map ( + I => REG_1_1_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_1_1_CLKF, + SET => REG_1_1_tsimcreated_set_and_noreset_Q, + RST => REG_1_1_tsimcreated_prld_Q, + O => REG_1_1_Q + ); + REG_1_1_D_712 : X_XOR2 + port map ( + I0 => REG_1_1_D1, + I1 => REG_1_1_D2, + O => REG_1_1_D + ); + REG_1_1_D1_713 : X_ZERO + port map ( + O => REG_1_1_D1 + ); + REG_1_1_D2_PT_0_714 : X_AND2 + port map ( + I0 => EXP48_EXP, + I1 => EXP48_EXP, + O => REG_1_1_D2_PT_0 + ); + REG_1_1_D2_PT_1_715 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_1_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_1_1_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => REG_1_0, + I5 => NlwInverterSignal_REG_1_1_D2_PT_1_IN5, + O => REG_1_1_D2_PT_1 + ); + REG_1_1_D2_PT_2_716 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_1_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_1_1_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => NlwInverterSignal_REG_1_1_D2_PT_2_IN4, + I5 => REG_1_1, + O => REG_1_1_D2_PT_2 + ); + REG_1_1_D2_717 : X_OR3 + port map ( + I0 => REG_1_1_D2_PT_0, + I1 => REG_1_1_D2_PT_1, + I2 => REG_1_1_D2_PT_2, + O => REG_1_1_D2 + ); + REG_1_1_CLKF_718 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_1_CLKF_IN0, + I1 => NlwInverterSignal_REG_1_1_CLKF_IN1, + O => REG_1_1_CLKF + ); + REG_1_1_SETF_719 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => DIN_1_IBUF, + O => REG_1_1_SETF + ); + REG_1_1_RSTF_720 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => NlwInverterSignal_REG_1_1_RSTF_IN2, + O => REG_1_1_RSTF + ); + REG_1_10_721 : X_BUF + port map ( + I => REG_1_10_Q, + O => REG_1_10 + ); + REG_1_10_tsimcreated_xor_Q_722 : X_XOR2 + port map ( + I0 => REG_1_10_D, + I1 => REG_1_10_Q, + O => REG_1_10_tsimcreated_xor_Q + ); + REG_1_10_tsimcreated_set_and_noreset_Q_723 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_10_tsimcreated_set_and_noreset_IN0, + I1 => REG_1_10_SETF, + O => REG_1_10_tsimcreated_set_and_noreset_Q + ); + REG_1_10_tsimcreated_prld_Q_724 : X_OR2 + port map ( + I0 => REG_1_10_RSTF, + I1 => PRLD, + O => REG_1_10_tsimcreated_prld_Q + ); + REG_1_10_REG : X_FF + port map ( + I => REG_1_10_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_1_10_CLKF, + SET => REG_1_10_tsimcreated_set_and_noreset_Q, + RST => REG_1_10_tsimcreated_prld_Q, + O => REG_1_10_Q + ); + REG_1_10_D_725 : X_XOR2 + port map ( + I0 => REG_1_10_D1, + I1 => REG_1_10_D2, + O => REG_1_10_D + ); + REG_1_10_D1_726 : X_ZERO + port map ( + O => REG_1_10_D1 + ); + REG_1_10_D2_PT_0_727 : X_AND2 + port map ( + I0 => EXP43_EXP, + I1 => EXP43_EXP, + O => REG_1_10_D2_PT_0 + ); + REG_1_10_D2_PT_1_728 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_10_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_1_10_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => REG_1_10, + I5 => NlwInverterSignal_REG_1_10_D2_PT_1_IN5, + O => REG_1_10_D2_PT_1 + ); + REG_1_10_D2_PT_2_729 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_10_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_1_10_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => NlwInverterSignal_REG_1_10_D2_PT_2_IN4, + I5 => REG_1_9, + O => REG_1_10_D2_PT_2 + ); + REG_1_10_D2_730 : X_OR3 + port map ( + I0 => REG_1_10_D2_PT_0, + I1 => REG_1_10_D2_PT_1, + I2 => REG_1_10_D2_PT_2, + O => REG_1_10_D2 + ); + REG_1_10_CLKF_731 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_10_CLKF_IN0, + I1 => NlwInverterSignal_REG_1_10_CLKF_IN1, + O => REG_1_10_CLKF + ); + REG_1_10_SETF_732 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => DIN_10_IBUF, + O => REG_1_10_SETF + ); + REG_1_10_RSTF_733 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => NlwInverterSignal_REG_1_10_RSTF_IN2, + O => REG_1_10_RSTF + ); + REG_1_11_734 : X_BUF + port map ( + I => REG_1_11_Q, + O => REG_1_11 + ); + REG_1_11_EXP_735 : X_BUF + port map ( + I => REG_1_11_EXP_tsimrenamed_net_Q, + O => REG_1_11_EXP + ); + REG_1_11_tsimcreated_xor_Q_736 : X_XOR2 + port map ( + I0 => REG_1_11_D, + I1 => REG_1_11_Q, + O => REG_1_11_tsimcreated_xor_Q + ); + REG_1_11_tsimcreated_set_and_noreset_Q_737 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_11_tsimcreated_set_and_noreset_IN0, + I1 => REG_1_11_SETF, + O => REG_1_11_tsimcreated_set_and_noreset_Q + ); + REG_1_11_tsimcreated_prld_Q_738 : X_OR2 + port map ( + I0 => REG_1_11_RSTF, + I1 => PRLD, + O => REG_1_11_tsimcreated_prld_Q + ); + REG_1_11_REG : X_FF + port map ( + I => REG_1_11_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_1_11_CLKF, + SET => REG_1_11_tsimcreated_set_and_noreset_Q, + RST => REG_1_11_tsimcreated_prld_Q, + O => REG_1_11_Q + ); + REG_1_11_D_739 : X_XOR2 + port map ( + I0 => REG_1_11_D1, + I1 => REG_1_11_D2, + O => REG_1_11_D + ); + REG_1_11_D1_740 : X_ZERO + port map ( + O => REG_1_11_D1 + ); + REG_1_11_D2_PT_0_741 : X_AND2 + port map ( + I0 => EXP56_EXP, + I1 => EXP56_EXP, + O => REG_1_11_D2_PT_0 + ); + REG_1_11_D2_PT_1_742 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_11_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_1_11_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => NlwInverterSignal_REG_1_11_D2_PT_1_IN4, + I5 => REG_1_11, + O => REG_1_11_D2_PT_1 + ); + REG_1_11_D2_743 : X_OR2 + port map ( + I0 => REG_1_11_D2_PT_0, + I1 => REG_1_11_D2_PT_1, + O => REG_1_11_D2 + ); + REG_1_11_CLKF_744 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_11_CLKF_IN0, + I1 => NlwInverterSignal_REG_1_11_CLKF_IN1, + O => REG_1_11_CLKF + ); + REG_1_11_SETF_745 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => DIN_11_IBUF, + O => REG_1_11_SETF + ); + REG_1_11_RSTF_746 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => NlwInverterSignal_REG_1_11_RSTF_IN2, + O => REG_1_11_RSTF + ); + REG_1_11_EXP_tsimrenamed_net_Q_747 : X_AND7 + port map ( + I0 => NlwInverterSignal_REG_1_11_EXP_tsimrenamed_net_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => DIN_12_IBUF, + I6 => NlwInverterSignal_REG_1_11_EXP_tsimrenamed_net_IN6, + O => REG_1_11_EXP_tsimrenamed_net_Q + ); + REG_1_12_748 : X_BUF + port map ( + I => REG_1_12_Q, + O => REG_1_12 + ); + REG_1_12_tsimcreated_xor_Q_749 : X_XOR2 + port map ( + I0 => REG_1_12_D, + I1 => REG_1_12_Q, + O => REG_1_12_tsimcreated_xor_Q + ); + REG_1_12_tsimcreated_set_and_noreset_Q_750 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_12_tsimcreated_set_and_noreset_IN0, + I1 => REG_1_12_SETF, + O => REG_1_12_tsimcreated_set_and_noreset_Q + ); + REG_1_12_tsimcreated_prld_Q_751 : X_OR2 + port map ( + I0 => REG_1_12_RSTF, + I1 => PRLD, + O => REG_1_12_tsimcreated_prld_Q + ); + REG_1_12_REG : X_FF + port map ( + I => REG_1_12_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_1_12_CLKF, + SET => REG_1_12_tsimcreated_set_and_noreset_Q, + RST => REG_1_12_tsimcreated_prld_Q, + O => REG_1_12_Q + ); + REG_1_12_D_752 : X_XOR2 + port map ( + I0 => REG_1_12_D1, + I1 => REG_1_12_D2, + O => REG_1_12_D + ); + REG_1_12_D1_753 : X_ZERO + port map ( + O => REG_1_12_D1 + ); + REG_1_12_D2_PT_0_754 : X_AND2 + port map ( + I0 => REG_1_11_EXP, + I1 => REG_1_11_EXP, + O => REG_1_12_D2_PT_0 + ); + REG_1_12_D2_PT_1_755 : X_AND2 + port map ( + I0 => REG_1_13_EXP, + I1 => REG_1_13_EXP, + O => REG_1_12_D2_PT_1 + ); + REG_1_12_D2_PT_2_756 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_12_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_1_12_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => REG_1_11, + I5 => NlwInverterSignal_REG_1_12_D2_PT_2_IN5, + O => REG_1_12_D2_PT_2 + ); + REG_1_12_D2_PT_3_757 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_12_D2_PT_3_IN0, + I1 => NlwInverterSignal_REG_1_12_D2_PT_3_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => NlwInverterSignal_REG_1_12_D2_PT_3_IN4, + I5 => REG_1_12, + O => REG_1_12_D2_PT_3 + ); + REG_1_12_D2_758 : X_OR4 + port map ( + I0 => REG_1_12_D2_PT_0, + I1 => REG_1_12_D2_PT_1, + I2 => REG_1_12_D2_PT_2, + I3 => REG_1_12_D2_PT_3, + O => REG_1_12_D2 + ); + REG_1_12_CLKF_759 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_12_CLKF_IN0, + I1 => NlwInverterSignal_REG_1_12_CLKF_IN1, + O => REG_1_12_CLKF + ); + REG_1_12_SETF_760 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => DIN_12_IBUF, + O => REG_1_12_SETF + ); + REG_1_12_RSTF_761 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => NlwInverterSignal_REG_1_12_RSTF_IN2, + O => REG_1_12_RSTF + ); + REG_1_13_762 : X_BUF + port map ( + I => REG_1_13_Q, + O => REG_1_13 + ); + REG_1_13_EXP_763 : X_BUF + port map ( + I => REG_1_13_EXP_tsimrenamed_net_Q, + O => REG_1_13_EXP + ); + REG_1_13_tsimcreated_xor_Q_764 : X_XOR2 + port map ( + I0 => REG_1_13_D, + I1 => REG_1_13_Q, + O => REG_1_13_tsimcreated_xor_Q + ); + REG_1_13_tsimcreated_set_and_noreset_Q_765 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_13_tsimcreated_set_and_noreset_IN0, + I1 => REG_1_13_SETF, + O => REG_1_13_tsimcreated_set_and_noreset_Q + ); + REG_1_13_tsimcreated_prld_Q_766 : X_OR2 + port map ( + I0 => REG_1_13_RSTF, + I1 => PRLD, + O => REG_1_13_tsimcreated_prld_Q + ); + REG_1_13_REG : X_FF + port map ( + I => REG_1_13_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_1_13_CLKF, + SET => REG_1_13_tsimcreated_set_and_noreset_Q, + RST => REG_1_13_tsimcreated_prld_Q, + O => REG_1_13_Q + ); + REG_1_13_D_767 : X_XOR2 + port map ( + I0 => REG_1_13_D1, + I1 => REG_1_13_D2, + O => REG_1_13_D + ); + REG_1_13_D1_768 : X_ZERO + port map ( + O => REG_1_13_D1 + ); + REG_1_13_D2_PT_0_769 : X_AND2 + port map ( + I0 => EXP55_EXP, + I1 => EXP55_EXP, + O => REG_1_13_D2_PT_0 + ); + REG_1_13_D2_PT_1_770 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_13_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_1_13_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => NlwInverterSignal_REG_1_13_D2_PT_1_IN4, + I5 => REG_1_13, + O => REG_1_13_D2_PT_1 + ); + REG_1_13_D2_771 : X_OR2 + port map ( + I0 => REG_1_13_D2_PT_0, + I1 => REG_1_13_D2_PT_1, + O => REG_1_13_D2 + ); + REG_1_13_CLKF_772 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_13_CLKF_IN0, + I1 => NlwInverterSignal_REG_1_13_CLKF_IN1, + O => REG_1_13_CLKF + ); + REG_1_13_SETF_773 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => DIN_13_IBUF, + O => REG_1_13_SETF + ); + REG_1_13_RSTF_774 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => NlwInverterSignal_REG_1_13_RSTF_IN2, + O => REG_1_13_RSTF + ); + REG_1_13_EXP_tsimrenamed_net_Q_775 : X_AND7 + port map ( + I0 => NlwInverterSignal_REG_1_13_EXP_tsimrenamed_net_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => NlwInverterSignal_REG_1_13_EXP_tsimrenamed_net_IN5, + I6 => REG_1_12, + O => REG_1_13_EXP_tsimrenamed_net_Q + ); + REG_1_14_776 : X_BUF + port map ( + I => REG_1_14_Q, + O => REG_1_14 + ); + REG_1_14_tsimcreated_xor_Q_777 : X_XOR2 + port map ( + I0 => REG_1_14_D, + I1 => REG_1_14_Q, + O => REG_1_14_tsimcreated_xor_Q + ); + REG_1_14_tsimcreated_set_and_noreset_Q_778 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_14_tsimcreated_set_and_noreset_IN0, + I1 => REG_1_14_SETF, + O => REG_1_14_tsimcreated_set_and_noreset_Q + ); + REG_1_14_tsimcreated_prld_Q_779 : X_OR2 + port map ( + I0 => REG_1_14_RSTF, + I1 => PRLD, + O => REG_1_14_tsimcreated_prld_Q + ); + REG_1_14_REG : X_FF + port map ( + I => REG_1_14_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_1_14_CLKF, + SET => REG_1_14_tsimcreated_set_and_noreset_Q, + RST => REG_1_14_tsimcreated_prld_Q, + O => REG_1_14_Q + ); + REG_1_14_D_780 : X_XOR2 + port map ( + I0 => REG_1_14_D1, + I1 => REG_1_14_D2, + O => REG_1_14_D + ); + REG_1_14_D1_781 : X_ZERO + port map ( + O => REG_1_14_D1 + ); + REG_1_14_D2_PT_0_782 : X_AND2 + port map ( + I0 => EXP58_EXP, + I1 => EXP58_EXP, + O => REG_1_14_D2_PT_0 + ); + REG_1_14_D2_PT_1_783 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_14_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_1_14_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => REG_1_13, + I5 => NlwInverterSignal_REG_1_14_D2_PT_1_IN5, + O => REG_1_14_D2_PT_1 + ); + REG_1_14_D2_PT_2_784 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_14_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_1_14_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => NlwInverterSignal_REG_1_14_D2_PT_2_IN4, + I5 => REG_1_14, + O => REG_1_14_D2_PT_2 + ); + REG_1_14_D2_785 : X_OR3 + port map ( + I0 => REG_1_14_D2_PT_0, + I1 => REG_1_14_D2_PT_1, + I2 => REG_1_14_D2_PT_2, + O => REG_1_14_D2 + ); + REG_1_14_CLKF_786 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_14_CLKF_IN0, + I1 => NlwInverterSignal_REG_1_14_CLKF_IN1, + O => REG_1_14_CLKF + ); + REG_1_14_SETF_787 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => DIN_14_IBUF, + O => REG_1_14_SETF + ); + REG_1_14_RSTF_788 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => NlwInverterSignal_REG_1_14_RSTF_IN2, + O => REG_1_14_RSTF + ); + REG_1_15_789 : X_BUF + port map ( + I => REG_1_15_Q, + O => REG_1_15 + ); + REG_1_15_tsimcreated_xor_Q_790 : X_XOR2 + port map ( + I0 => REG_1_15_D, + I1 => REG_1_15_Q, + O => REG_1_15_tsimcreated_xor_Q + ); + REG_1_15_tsimcreated_set_and_noreset_Q_791 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_15_tsimcreated_set_and_noreset_IN0, + I1 => REG_1_15_SETF, + O => REG_1_15_tsimcreated_set_and_noreset_Q + ); + REG_1_15_tsimcreated_prld_Q_792 : X_OR2 + port map ( + I0 => REG_1_15_RSTF, + I1 => PRLD, + O => REG_1_15_tsimcreated_prld_Q + ); + REG_1_15_REG : X_FF + port map ( + I => REG_1_15_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_1_15_CLKF, + SET => REG_1_15_tsimcreated_set_and_noreset_Q, + RST => REG_1_15_tsimcreated_prld_Q, + O => REG_1_15_Q + ); + REG_1_15_D_793 : X_XOR2 + port map ( + I0 => REG_1_15_D1, + I1 => REG_1_15_D2, + O => REG_1_15_D + ); + REG_1_15_D1_794 : X_ZERO + port map ( + O => REG_1_15_D1 + ); + REG_1_15_D2_PT_0_795 : X_AND2 + port map ( + I0 => EXP57_EXP, + I1 => EXP57_EXP, + O => REG_1_15_D2_PT_0 + ); + REG_1_15_D2_PT_1_796 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_15_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_1_15_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => REG_1_14, + I5 => NlwInverterSignal_REG_1_15_D2_PT_1_IN5, + O => REG_1_15_D2_PT_1 + ); + REG_1_15_D2_PT_2_797 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_15_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_1_15_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => NlwInverterSignal_REG_1_15_D2_PT_2_IN4, + I5 => REG_1_15, + O => REG_1_15_D2_PT_2 + ); + REG_1_15_D2_798 : X_OR3 + port map ( + I0 => REG_1_15_D2_PT_0, + I1 => REG_1_15_D2_PT_1, + I2 => REG_1_15_D2_PT_2, + O => REG_1_15_D2 + ); + REG_1_15_CLKF_799 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_15_CLKF_IN0, + I1 => NlwInverterSignal_REG_1_15_CLKF_IN1, + O => REG_1_15_CLKF + ); + REG_1_15_SETF_800 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => DIN_15_IBUF, + O => REG_1_15_SETF + ); + REG_1_15_RSTF_801 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => NlwInverterSignal_REG_1_15_RSTF_IN2, + O => REG_1_15_RSTF + ); + REG_1_16_802 : X_BUF + port map ( + I => REG_1_16_Q, + O => REG_1_16 + ); + REG_1_16_tsimcreated_xor_Q_803 : X_XOR2 + port map ( + I0 => REG_1_16_D, + I1 => REG_1_16_Q, + O => REG_1_16_tsimcreated_xor_Q + ); + REG_1_16_tsimcreated_set_and_noreset_Q_804 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_16_tsimcreated_set_and_noreset_IN0, + I1 => REG_1_16_SETF, + O => REG_1_16_tsimcreated_set_and_noreset_Q + ); + REG_1_16_tsimcreated_prld_Q_805 : X_OR2 + port map ( + I0 => REG_1_16_RSTF, + I1 => PRLD, + O => REG_1_16_tsimcreated_prld_Q + ); + REG_1_16_REG : X_FF + port map ( + I => REG_1_16_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_1_16_CLKF, + SET => REG_1_16_tsimcreated_set_and_noreset_Q, + RST => REG_1_16_tsimcreated_prld_Q, + O => REG_1_16_Q + ); + REG_1_16_D_806 : X_XOR2 + port map ( + I0 => REG_1_16_D1, + I1 => REG_1_16_D2, + O => REG_1_16_D + ); + REG_1_16_D1_807 : X_ZERO + port map ( + O => REG_1_16_D1 + ); + REG_1_16_D2_PT_0_808 : X_AND2 + port map ( + I0 => EXP54_EXP, + I1 => EXP54_EXP, + O => REG_1_16_D2_PT_0 + ); + REG_1_16_D2_PT_1_809 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_16_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_1_16_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => REG_1_15, + I5 => NlwInverterSignal_REG_1_16_D2_PT_1_IN5, + O => REG_1_16_D2_PT_1 + ); + REG_1_16_D2_PT_2_810 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_16_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_1_16_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => NlwInverterSignal_REG_1_16_D2_PT_2_IN4, + I5 => REG_1_16, + O => REG_1_16_D2_PT_2 + ); + REG_1_16_D2_811 : X_OR3 + port map ( + I0 => REG_1_16_D2_PT_0, + I1 => REG_1_16_D2_PT_1, + I2 => REG_1_16_D2_PT_2, + O => REG_1_16_D2 + ); + REG_1_16_CLKF_812 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_16_CLKF_IN0, + I1 => NlwInverterSignal_REG_1_16_CLKF_IN1, + O => REG_1_16_CLKF + ); + REG_1_16_SETF_813 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => DIN_16_IBUF, + O => REG_1_16_SETF + ); + REG_1_16_RSTF_814 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => NlwInverterSignal_REG_1_16_RSTF_IN2, + O => REG_1_16_RSTF + ); + REG_1_17_815 : X_BUF + port map ( + I => REG_1_17_Q, + O => REG_1_17 + ); + REG_1_17_EXP_816 : X_BUF + port map ( + I => REG_1_17_EXP_tsimrenamed_net_Q, + O => REG_1_17_EXP + ); + REG_1_17_tsimcreated_xor_Q_817 : X_XOR2 + port map ( + I0 => REG_1_17_D, + I1 => REG_1_17_Q, + O => REG_1_17_tsimcreated_xor_Q + ); + REG_1_17_tsimcreated_set_and_noreset_Q_818 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_17_tsimcreated_set_and_noreset_IN0, + I1 => REG_1_17_SETF, + O => REG_1_17_tsimcreated_set_and_noreset_Q + ); + REG_1_17_tsimcreated_prld_Q_819 : X_OR2 + port map ( + I0 => REG_1_17_RSTF, + I1 => PRLD, + O => REG_1_17_tsimcreated_prld_Q + ); + REG_1_17_REG : X_FF + port map ( + I => REG_1_17_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_1_17_CLKF, + SET => REG_1_17_tsimcreated_set_and_noreset_Q, + RST => REG_1_17_tsimcreated_prld_Q, + O => REG_1_17_Q + ); + REG_1_17_D_820 : X_XOR2 + port map ( + I0 => REG_1_17_D1, + I1 => REG_1_17_D2, + O => REG_1_17_D + ); + REG_1_17_D1_821 : X_ZERO + port map ( + O => REG_1_17_D1 + ); + REG_1_17_D2_PT_0_822 : X_AND2 + port map ( + I0 => EXP61_EXP, + I1 => EXP61_EXP, + O => REG_1_17_D2_PT_0 + ); + REG_1_17_D2_PT_1_823 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_17_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_1_17_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => NlwInverterSignal_REG_1_17_D2_PT_1_IN4, + I5 => REG_1_17, + O => REG_1_17_D2_PT_1 + ); + REG_1_17_D2_824 : X_OR2 + port map ( + I0 => REG_1_17_D2_PT_0, + I1 => REG_1_17_D2_PT_1, + O => REG_1_17_D2 + ); + REG_1_17_CLKF_825 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_17_CLKF_IN0, + I1 => NlwInverterSignal_REG_1_17_CLKF_IN1, + O => REG_1_17_CLKF + ); + REG_1_17_SETF_826 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => DIN_17_IBUF, + O => REG_1_17_SETF + ); + REG_1_17_RSTF_827 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => NlwInverterSignal_REG_1_17_RSTF_IN2, + O => REG_1_17_RSTF + ); + REG_1_17_EXP_tsimrenamed_net_Q_828 : X_AND7 + port map ( + I0 => NlwInverterSignal_REG_1_17_EXP_tsimrenamed_net_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => DIN_18_IBUF, + I6 => NlwInverterSignal_REG_1_17_EXP_tsimrenamed_net_IN6, + O => REG_1_17_EXP_tsimrenamed_net_Q + ); + REG_1_18_829 : X_BUF + port map ( + I => REG_1_18_Q, + O => REG_1_18 + ); + REG_1_18_tsimcreated_xor_Q_830 : X_XOR2 + port map ( + I0 => REG_1_18_D, + I1 => REG_1_18_Q, + O => REG_1_18_tsimcreated_xor_Q + ); + REG_1_18_tsimcreated_set_and_noreset_Q_831 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_18_tsimcreated_set_and_noreset_IN0, + I1 => REG_1_18_SETF, + O => REG_1_18_tsimcreated_set_and_noreset_Q + ); + REG_1_18_tsimcreated_prld_Q_832 : X_OR2 + port map ( + I0 => REG_1_18_RSTF, + I1 => PRLD, + O => REG_1_18_tsimcreated_prld_Q + ); + REG_1_18_REG : X_FF + port map ( + I => REG_1_18_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_1_18_CLKF, + SET => REG_1_18_tsimcreated_set_and_noreset_Q, + RST => REG_1_18_tsimcreated_prld_Q, + O => REG_1_18_Q + ); + REG_1_18_D_833 : X_XOR2 + port map ( + I0 => REG_1_18_D1, + I1 => REG_1_18_D2, + O => REG_1_18_D + ); + REG_1_18_D1_834 : X_ZERO + port map ( + O => REG_1_18_D1 + ); + REG_1_18_D2_PT_0_835 : X_AND2 + port map ( + I0 => REG_1_17_EXP, + I1 => REG_1_17_EXP, + O => REG_1_18_D2_PT_0 + ); + REG_1_18_D2_PT_1_836 : X_AND2 + port map ( + I0 => REG_1_19_EXP, + I1 => REG_1_19_EXP, + O => REG_1_18_D2_PT_1 + ); + REG_1_18_D2_PT_2_837 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_18_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_1_18_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => REG_1_17, + I5 => NlwInverterSignal_REG_1_18_D2_PT_2_IN5, + O => REG_1_18_D2_PT_2 + ); + REG_1_18_D2_PT_3_838 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_18_D2_PT_3_IN0, + I1 => NlwInverterSignal_REG_1_18_D2_PT_3_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => NlwInverterSignal_REG_1_18_D2_PT_3_IN4, + I5 => REG_1_18, + O => REG_1_18_D2_PT_3 + ); + REG_1_18_D2_839 : X_OR4 + port map ( + I0 => REG_1_18_D2_PT_0, + I1 => REG_1_18_D2_PT_1, + I2 => REG_1_18_D2_PT_2, + I3 => REG_1_18_D2_PT_3, + O => REG_1_18_D2 + ); + REG_1_18_CLKF_840 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_18_CLKF_IN0, + I1 => NlwInverterSignal_REG_1_18_CLKF_IN1, + O => REG_1_18_CLKF + ); + REG_1_18_SETF_841 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => DIN_18_IBUF, + O => REG_1_18_SETF + ); + REG_1_18_RSTF_842 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => NlwInverterSignal_REG_1_18_RSTF_IN2, + O => REG_1_18_RSTF + ); + REG_1_19_843 : X_BUF + port map ( + I => REG_1_19_Q, + O => REG_1_19 + ); + REG_1_19_EXP_844 : X_BUF + port map ( + I => REG_1_19_EXP_tsimrenamed_net_Q, + O => REG_1_19_EXP + ); + REG_1_19_tsimcreated_xor_Q_845 : X_XOR2 + port map ( + I0 => REG_1_19_D, + I1 => REG_1_19_Q, + O => REG_1_19_tsimcreated_xor_Q + ); + REG_1_19_tsimcreated_set_and_noreset_Q_846 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_19_tsimcreated_set_and_noreset_IN0, + I1 => REG_1_19_SETF, + O => REG_1_19_tsimcreated_set_and_noreset_Q + ); + REG_1_19_tsimcreated_prld_Q_847 : X_OR2 + port map ( + I0 => REG_1_19_RSTF, + I1 => PRLD, + O => REG_1_19_tsimcreated_prld_Q + ); + REG_1_19_REG : X_FF + port map ( + I => REG_1_19_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_1_19_CLKF, + SET => REG_1_19_tsimcreated_set_and_noreset_Q, + RST => REG_1_19_tsimcreated_prld_Q, + O => REG_1_19_Q + ); + REG_1_19_D_848 : X_XOR2 + port map ( + I0 => REG_1_19_D1, + I1 => REG_1_19_D2, + O => REG_1_19_D + ); + REG_1_19_D1_849 : X_ZERO + port map ( + O => REG_1_19_D1 + ); + REG_1_19_D2_PT_0_850 : X_AND2 + port map ( + I0 => EXP60_EXP, + I1 => EXP60_EXP, + O => REG_1_19_D2_PT_0 + ); + REG_1_19_D2_PT_1_851 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_19_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_1_19_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => NlwInverterSignal_REG_1_19_D2_PT_1_IN4, + I5 => REG_1_19, + O => REG_1_19_D2_PT_1 + ); + REG_1_19_D2_852 : X_OR2 + port map ( + I0 => REG_1_19_D2_PT_0, + I1 => REG_1_19_D2_PT_1, + O => REG_1_19_D2 + ); + REG_1_19_CLKF_853 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_19_CLKF_IN0, + I1 => NlwInverterSignal_REG_1_19_CLKF_IN1, + O => REG_1_19_CLKF + ); + REG_1_19_SETF_854 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => DIN_19_IBUF, + O => REG_1_19_SETF + ); + REG_1_19_RSTF_855 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => NlwInverterSignal_REG_1_19_RSTF_IN2, + O => REG_1_19_RSTF + ); + REG_1_19_EXP_tsimrenamed_net_Q_856 : X_AND7 + port map ( + I0 => NlwInverterSignal_REG_1_19_EXP_tsimrenamed_net_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => NlwInverterSignal_REG_1_19_EXP_tsimrenamed_net_IN5, + I6 => REG_1_18, + O => REG_1_19_EXP_tsimrenamed_net_Q + ); + REG_1_2_857 : X_BUF + port map ( + I => REG_1_2_Q, + O => REG_1_2 + ); + REG_1_2_tsimcreated_xor_Q_858 : X_XOR2 + port map ( + I0 => REG_1_2_D, + I1 => REG_1_2_Q, + O => REG_1_2_tsimcreated_xor_Q + ); + REG_1_2_tsimcreated_set_and_noreset_Q_859 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_2_tsimcreated_set_and_noreset_IN0, + I1 => REG_1_2_SETF, + O => REG_1_2_tsimcreated_set_and_noreset_Q + ); + REG_1_2_tsimcreated_prld_Q_860 : X_OR2 + port map ( + I0 => REG_1_2_RSTF, + I1 => PRLD, + O => REG_1_2_tsimcreated_prld_Q + ); + REG_1_2_REG : X_FF + port map ( + I => REG_1_2_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_1_2_CLKF, + SET => REG_1_2_tsimcreated_set_and_noreset_Q, + RST => REG_1_2_tsimcreated_prld_Q, + O => REG_1_2_Q + ); + REG_1_2_D_861 : X_XOR2 + port map ( + I0 => REG_1_2_D1, + I1 => REG_1_2_D2, + O => REG_1_2_D + ); + REG_1_2_D1_862 : X_ZERO + port map ( + O => REG_1_2_D1 + ); + REG_1_2_D2_PT_0_863 : X_AND2 + port map ( + I0 => REG_1_3_EXP, + I1 => REG_1_3_EXP, + O => REG_1_2_D2_PT_0 + ); + REG_1_2_D2_PT_1_864 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_2_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_1_2_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => REG_1_1, + I5 => NlwInverterSignal_REG_1_2_D2_PT_1_IN5, + O => REG_1_2_D2_PT_1 + ); + REG_1_2_D2_PT_2_865 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_2_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_1_2_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => NlwInverterSignal_REG_1_2_D2_PT_2_IN4, + I5 => REG_1_2, + O => REG_1_2_D2_PT_2 + ); + REG_1_2_D2_866 : X_OR3 + port map ( + I0 => REG_1_2_D2_PT_0, + I1 => REG_1_2_D2_PT_1, + I2 => REG_1_2_D2_PT_2, + O => REG_1_2_D2 + ); + REG_1_2_CLKF_867 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_2_CLKF_IN0, + I1 => NlwInverterSignal_REG_1_2_CLKF_IN1, + O => REG_1_2_CLKF + ); + REG_1_2_SETF_868 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => DIN_2_IBUF, + O => REG_1_2_SETF + ); + REG_1_2_RSTF_869 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => NlwInverterSignal_REG_1_2_RSTF_IN2, + O => REG_1_2_RSTF + ); + REG_1_20_870 : X_BUF + port map ( + I => REG_1_20_Q, + O => REG_1_20 + ); + REG_1_20_tsimcreated_xor_Q_871 : X_XOR2 + port map ( + I0 => REG_1_20_D, + I1 => REG_1_20_Q, + O => REG_1_20_tsimcreated_xor_Q + ); + REG_1_20_tsimcreated_set_and_noreset_Q_872 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_20_tsimcreated_set_and_noreset_IN0, + I1 => REG_1_20_SETF, + O => REG_1_20_tsimcreated_set_and_noreset_Q + ); + REG_1_20_tsimcreated_prld_Q_873 : X_OR2 + port map ( + I0 => REG_1_20_RSTF, + I1 => PRLD, + O => REG_1_20_tsimcreated_prld_Q + ); + REG_1_20_REG : X_FF + port map ( + I => REG_1_20_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_1_20_CLKF, + SET => REG_1_20_tsimcreated_set_and_noreset_Q, + RST => REG_1_20_tsimcreated_prld_Q, + O => REG_1_20_Q + ); + REG_1_20_D_874 : X_XOR2 + port map ( + I0 => REG_1_20_D1, + I1 => REG_1_20_D2, + O => REG_1_20_D + ); + REG_1_20_D1_875 : X_ZERO + port map ( + O => REG_1_20_D1 + ); + REG_1_20_D2_PT_0_876 : X_AND2 + port map ( + I0 => EXP63_EXP, + I1 => EXP63_EXP, + O => REG_1_20_D2_PT_0 + ); + REG_1_20_D2_PT_1_877 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_20_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_1_20_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => REG_1_19, + I5 => NlwInverterSignal_REG_1_20_D2_PT_1_IN5, + O => REG_1_20_D2_PT_1 + ); + REG_1_20_D2_PT_2_878 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_20_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_1_20_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => NlwInverterSignal_REG_1_20_D2_PT_2_IN4, + I5 => REG_1_20, + O => REG_1_20_D2_PT_2 + ); + REG_1_20_D2_879 : X_OR3 + port map ( + I0 => REG_1_20_D2_PT_0, + I1 => REG_1_20_D2_PT_1, + I2 => REG_1_20_D2_PT_2, + O => REG_1_20_D2 + ); + REG_1_20_CLKF_880 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_20_CLKF_IN0, + I1 => NlwInverterSignal_REG_1_20_CLKF_IN1, + O => REG_1_20_CLKF + ); + REG_1_20_SETF_881 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => DIN_20_IBUF, + O => REG_1_20_SETF + ); + REG_1_20_RSTF_882 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => NlwInverterSignal_REG_1_20_RSTF_IN2, + O => REG_1_20_RSTF + ); + REG_1_21_883 : X_BUF + port map ( + I => REG_1_21_Q, + O => REG_1_21 + ); + REG_1_21_tsimcreated_xor_Q_884 : X_XOR2 + port map ( + I0 => REG_1_21_D, + I1 => REG_1_21_Q, + O => REG_1_21_tsimcreated_xor_Q + ); + REG_1_21_tsimcreated_set_and_noreset_Q_885 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_21_tsimcreated_set_and_noreset_IN0, + I1 => REG_1_21_SETF, + O => REG_1_21_tsimcreated_set_and_noreset_Q + ); + REG_1_21_tsimcreated_prld_Q_886 : X_OR2 + port map ( + I0 => REG_1_21_RSTF, + I1 => PRLD, + O => REG_1_21_tsimcreated_prld_Q + ); + REG_1_21_REG : X_FF + port map ( + I => REG_1_21_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_1_21_CLKF, + SET => REG_1_21_tsimcreated_set_and_noreset_Q, + RST => REG_1_21_tsimcreated_prld_Q, + O => REG_1_21_Q + ); + REG_1_21_D_887 : X_XOR2 + port map ( + I0 => REG_1_21_D1, + I1 => REG_1_21_D2, + O => REG_1_21_D + ); + REG_1_21_D1_888 : X_ZERO + port map ( + O => REG_1_21_D1 + ); + REG_1_21_D2_PT_0_889 : X_AND2 + port map ( + I0 => EXP62_EXP, + I1 => EXP62_EXP, + O => REG_1_21_D2_PT_0 + ); + REG_1_21_D2_PT_1_890 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_21_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_1_21_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => REG_1_20, + I5 => NlwInverterSignal_REG_1_21_D2_PT_1_IN5, + O => REG_1_21_D2_PT_1 + ); + REG_1_21_D2_PT_2_891 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_21_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_1_21_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => NlwInverterSignal_REG_1_21_D2_PT_2_IN4, + I5 => REG_1_21, + O => REG_1_21_D2_PT_2 + ); + REG_1_21_D2_892 : X_OR3 + port map ( + I0 => REG_1_21_D2_PT_0, + I1 => REG_1_21_D2_PT_1, + I2 => REG_1_21_D2_PT_2, + O => REG_1_21_D2 + ); + REG_1_21_CLKF_893 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_21_CLKF_IN0, + I1 => NlwInverterSignal_REG_1_21_CLKF_IN1, + O => REG_1_21_CLKF + ); + REG_1_21_SETF_894 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => DIN_21_IBUF, + O => REG_1_21_SETF + ); + REG_1_21_RSTF_895 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => NlwInverterSignal_REG_1_21_RSTF_IN2, + O => REG_1_21_RSTF + ); + REG_1_22_896 : X_BUF + port map ( + I => REG_1_22_Q, + O => REG_1_22 + ); + REG_1_22_tsimcreated_xor_Q_897 : X_XOR2 + port map ( + I0 => REG_1_22_D, + I1 => REG_1_22_Q, + O => REG_1_22_tsimcreated_xor_Q + ); + REG_1_22_tsimcreated_set_and_noreset_Q_898 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_22_tsimcreated_set_and_noreset_IN0, + I1 => REG_1_22_SETF, + O => REG_1_22_tsimcreated_set_and_noreset_Q + ); + REG_1_22_tsimcreated_prld_Q_899 : X_OR2 + port map ( + I0 => REG_1_22_RSTF, + I1 => PRLD, + O => REG_1_22_tsimcreated_prld_Q + ); + REG_1_22_REG : X_FF + port map ( + I => REG_1_22_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_1_22_CLKF, + SET => REG_1_22_tsimcreated_set_and_noreset_Q, + RST => REG_1_22_tsimcreated_prld_Q, + O => REG_1_22_Q + ); + REG_1_22_D_900 : X_XOR2 + port map ( + I0 => REG_1_22_D1, + I1 => REG_1_22_D2, + O => REG_1_22_D + ); + REG_1_22_D1_901 : X_ZERO + port map ( + O => REG_1_22_D1 + ); + REG_1_22_D2_PT_0_902 : X_AND2 + port map ( + I0 => EXP59_EXP, + I1 => EXP59_EXP, + O => REG_1_22_D2_PT_0 + ); + REG_1_22_D2_PT_1_903 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_22_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_1_22_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => REG_1_21, + I5 => NlwInverterSignal_REG_1_22_D2_PT_1_IN5, + O => REG_1_22_D2_PT_1 + ); + REG_1_22_D2_PT_2_904 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_22_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_1_22_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => NlwInverterSignal_REG_1_22_D2_PT_2_IN4, + I5 => REG_1_22, + O => REG_1_22_D2_PT_2 + ); + REG_1_22_D2_905 : X_OR3 + port map ( + I0 => REG_1_22_D2_PT_0, + I1 => REG_1_22_D2_PT_1, + I2 => REG_1_22_D2_PT_2, + O => REG_1_22_D2 + ); + REG_1_22_CLKF_906 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_22_CLKF_IN0, + I1 => NlwInverterSignal_REG_1_22_CLKF_IN1, + O => REG_1_22_CLKF + ); + REG_1_22_SETF_907 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => DIN_22_IBUF, + O => REG_1_22_SETF + ); + REG_1_22_RSTF_908 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => NlwInverterSignal_REG_1_22_RSTF_IN2, + O => REG_1_22_RSTF + ); + REG_1_23_909 : X_BUF + port map ( + I => REG_1_23_Q, + O => REG_1_23 + ); + REG_1_23_tsimcreated_xor_Q_910 : X_XOR2 + port map ( + I0 => REG_1_23_D, + I1 => REG_1_23_Q, + O => REG_1_23_tsimcreated_xor_Q + ); + REG_1_23_tsimcreated_set_and_noreset_Q_911 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_23_tsimcreated_set_and_noreset_IN0, + I1 => REG_1_23_SETF, + O => REG_1_23_tsimcreated_set_and_noreset_Q + ); + REG_1_23_tsimcreated_prld_Q_912 : X_OR2 + port map ( + I0 => REG_1_23_RSTF, + I1 => PRLD, + O => REG_1_23_tsimcreated_prld_Q + ); + REG_1_23_REG : X_FF + port map ( + I => REG_1_23_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_1_23_CLKF, + SET => REG_1_23_tsimcreated_set_and_noreset_Q, + RST => REG_1_23_tsimcreated_prld_Q, + O => REG_1_23_Q + ); + REG_1_23_D_913 : X_XOR2 + port map ( + I0 => REG_1_23_D1, + I1 => REG_1_23_D2, + O => REG_1_23_D + ); + REG_1_23_D1_914 : X_ZERO + port map ( + O => REG_1_23_D1 + ); + REG_1_23_D2_PT_0_915 : X_AND2 + port map ( + I0 => REG_0_27_EXP, + I1 => REG_0_27_EXP, + O => REG_1_23_D2_PT_0 + ); + REG_1_23_D2_PT_1_916 : X_AND2 + port map ( + I0 => REG_1_24_EXP, + I1 => REG_1_24_EXP, + O => REG_1_23_D2_PT_1 + ); + REG_1_23_D2_PT_2_917 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_23_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_1_23_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => REG_1_23, + I5 => NlwInverterSignal_REG_1_23_D2_PT_2_IN5, + O => REG_1_23_D2_PT_2 + ); + REG_1_23_D2_PT_3_918 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_23_D2_PT_3_IN0, + I1 => NlwInverterSignal_REG_1_23_D2_PT_3_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => NlwInverterSignal_REG_1_23_D2_PT_3_IN4, + I5 => REG_1_22, + O => REG_1_23_D2_PT_3 + ); + REG_1_23_D2_919 : X_OR4 + port map ( + I0 => REG_1_23_D2_PT_0, + I1 => REG_1_23_D2_PT_1, + I2 => REG_1_23_D2_PT_2, + I3 => REG_1_23_D2_PT_3, + O => REG_1_23_D2 + ); + REG_1_23_CLKF_920 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_23_CLKF_IN0, + I1 => NlwInverterSignal_REG_1_23_CLKF_IN1, + O => REG_1_23_CLKF + ); + REG_1_23_SETF_921 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => DIN_23_IBUF, + O => REG_1_23_SETF + ); + REG_1_23_RSTF_922 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => NlwInverterSignal_REG_1_23_RSTF_IN2, + O => REG_1_23_RSTF + ); + REG_1_24_923 : X_BUF + port map ( + I => REG_1_24_Q, + O => REG_1_24 + ); + REG_1_24_EXP_924 : X_BUF + port map ( + I => REG_1_24_EXP_tsimrenamed_net_Q, + O => REG_1_24_EXP + ); + REG_1_24_tsimcreated_xor_Q_925 : X_XOR2 + port map ( + I0 => REG_1_24_D, + I1 => REG_1_24_Q, + O => REG_1_24_tsimcreated_xor_Q + ); + REG_1_24_tsimcreated_set_and_noreset_Q_926 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_24_tsimcreated_set_and_noreset_IN0, + I1 => REG_1_24_SETF, + O => REG_1_24_tsimcreated_set_and_noreset_Q + ); + REG_1_24_tsimcreated_prld_Q_927 : X_OR2 + port map ( + I0 => REG_1_24_RSTF, + I1 => PRLD, + O => REG_1_24_tsimcreated_prld_Q + ); + REG_1_24_REG : X_FF + port map ( + I => REG_1_24_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_1_24_CLKF, + SET => REG_1_24_tsimcreated_set_and_noreset_Q, + RST => REG_1_24_tsimcreated_prld_Q, + O => REG_1_24_Q + ); + REG_1_24_D_928 : X_XOR2 + port map ( + I0 => REG_1_24_D1, + I1 => REG_1_24_D2, + O => REG_1_24_D + ); + REG_1_24_D1_929 : X_ZERO + port map ( + O => REG_1_24_D1 + ); + REG_1_24_D2_PT_0_930 : X_AND2 + port map ( + I0 => EXP38_EXP, + I1 => EXP38_EXP, + O => REG_1_24_D2_PT_0 + ); + REG_1_24_D2_PT_1_931 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_24_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_1_24_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => NlwInverterSignal_REG_1_24_D2_PT_1_IN4, + I5 => REG_1_24, + O => REG_1_24_D2_PT_1 + ); + REG_1_24_D2_932 : X_OR2 + port map ( + I0 => REG_1_24_D2_PT_0, + I1 => REG_1_24_D2_PT_1, + O => REG_1_24_D2 + ); + REG_1_24_CLKF_933 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_24_CLKF_IN0, + I1 => NlwInverterSignal_REG_1_24_CLKF_IN1, + O => REG_1_24_CLKF + ); + REG_1_24_SETF_934 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => DIN_24_IBUF, + O => REG_1_24_SETF + ); + REG_1_24_RSTF_935 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => NlwInverterSignal_REG_1_24_RSTF_IN2, + O => REG_1_24_RSTF + ); + REG_1_24_EXP_tsimrenamed_net_Q_936 : X_AND7 + port map ( + I0 => NlwInverterSignal_REG_1_24_EXP_tsimrenamed_net_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => NlwInverterSignal_REG_1_24_EXP_tsimrenamed_net_IN5, + I6 => REG_1_23, + O => REG_1_24_EXP_tsimrenamed_net_Q + ); + REG_1_25_937 : X_BUF + port map ( + I => REG_1_25_Q, + O => REG_1_25 + ); + REG_1_25_tsimcreated_xor_Q_938 : X_XOR2 + port map ( + I0 => REG_1_25_D, + I1 => REG_1_25_Q, + O => REG_1_25_tsimcreated_xor_Q + ); + REG_1_25_tsimcreated_set_and_noreset_Q_939 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_25_tsimcreated_set_and_noreset_IN0, + I1 => REG_1_25_SETF, + O => REG_1_25_tsimcreated_set_and_noreset_Q + ); + REG_1_25_tsimcreated_prld_Q_940 : X_OR2 + port map ( + I0 => REG_1_25_RSTF, + I1 => PRLD, + O => REG_1_25_tsimcreated_prld_Q + ); + REG_1_25_REG : X_FF + port map ( + I => REG_1_25_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_1_25_CLKF, + SET => REG_1_25_tsimcreated_set_and_noreset_Q, + RST => REG_1_25_tsimcreated_prld_Q, + O => REG_1_25_Q + ); + REG_1_25_D_941 : X_XOR2 + port map ( + I0 => REG_1_25_D1, + I1 => REG_1_25_D2, + O => REG_1_25_D + ); + REG_1_25_D1_942 : X_ZERO + port map ( + O => REG_1_25_D1 + ); + REG_1_25_D2_PT_0_943 : X_AND2 + port map ( + I0 => EXP41_EXP, + I1 => EXP41_EXP, + O => REG_1_25_D2_PT_0 + ); + REG_1_25_D2_PT_1_944 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_25_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_1_25_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => REG_1_24, + I5 => NlwInverterSignal_REG_1_25_D2_PT_1_IN5, + O => REG_1_25_D2_PT_1 + ); + REG_1_25_D2_PT_2_945 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_25_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_1_25_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => NlwInverterSignal_REG_1_25_D2_PT_2_IN4, + I5 => REG_1_25, + O => REG_1_25_D2_PT_2 + ); + REG_1_25_D2_946 : X_OR3 + port map ( + I0 => REG_1_25_D2_PT_0, + I1 => REG_1_25_D2_PT_1, + I2 => REG_1_25_D2_PT_2, + O => REG_1_25_D2 + ); + REG_1_25_CLKF_947 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_25_CLKF_IN0, + I1 => NlwInverterSignal_REG_1_25_CLKF_IN1, + O => REG_1_25_CLKF + ); + REG_1_25_SETF_948 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => DIN_25_IBUF, + O => REG_1_25_SETF + ); + REG_1_25_RSTF_949 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => NlwInverterSignal_REG_1_25_RSTF_IN2, + O => REG_1_25_RSTF + ); + REG_1_26_950 : X_BUF + port map ( + I => REG_1_26_Q, + O => REG_1_26 + ); + REG_1_26_tsimcreated_xor_Q_951 : X_XOR2 + port map ( + I0 => REG_1_26_D, + I1 => REG_1_26_Q, + O => REG_1_26_tsimcreated_xor_Q + ); + REG_1_26_tsimcreated_set_and_noreset_Q_952 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_26_tsimcreated_set_and_noreset_IN0, + I1 => REG_1_26_SETF, + O => REG_1_26_tsimcreated_set_and_noreset_Q + ); + REG_1_26_tsimcreated_prld_Q_953 : X_OR2 + port map ( + I0 => REG_1_26_RSTF, + I1 => PRLD, + O => REG_1_26_tsimcreated_prld_Q + ); + REG_1_26_REG : X_FF + port map ( + I => REG_1_26_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_1_26_CLKF, + SET => REG_1_26_tsimcreated_set_and_noreset_Q, + RST => REG_1_26_tsimcreated_prld_Q, + O => REG_1_26_Q + ); + REG_1_26_D_954 : X_XOR2 + port map ( + I0 => REG_1_26_D1, + I1 => REG_1_26_D2, + O => REG_1_26_D + ); + REG_1_26_D1_955 : X_ZERO + port map ( + O => REG_1_26_D1 + ); + REG_1_26_D2_PT_0_956 : X_AND2 + port map ( + I0 => EXP40_EXP, + I1 => EXP40_EXP, + O => REG_1_26_D2_PT_0 + ); + REG_1_26_D2_PT_1_957 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_26_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_1_26_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => REG_1_25, + I5 => NlwInverterSignal_REG_1_26_D2_PT_1_IN5, + O => REG_1_26_D2_PT_1 + ); + REG_1_26_D2_PT_2_958 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_26_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_1_26_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => NlwInverterSignal_REG_1_26_D2_PT_2_IN4, + I5 => REG_1_26, + O => REG_1_26_D2_PT_2 + ); + REG_1_26_D2_959 : X_OR3 + port map ( + I0 => REG_1_26_D2_PT_0, + I1 => REG_1_26_D2_PT_1, + I2 => REG_1_26_D2_PT_2, + O => REG_1_26_D2 + ); + REG_1_26_CLKF_960 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_26_CLKF_IN0, + I1 => NlwInverterSignal_REG_1_26_CLKF_IN1, + O => REG_1_26_CLKF + ); + REG_1_26_SETF_961 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => DIN_26_IBUF, + O => REG_1_26_SETF + ); + REG_1_26_RSTF_962 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => NlwInverterSignal_REG_1_26_RSTF_IN2, + O => REG_1_26_RSTF + ); + REG_1_27_963 : X_BUF + port map ( + I => REG_1_27_Q, + O => REG_1_27 + ); + REG_1_27_tsimcreated_xor_Q_964 : X_XOR2 + port map ( + I0 => REG_1_27_D, + I1 => REG_1_27_Q, + O => REG_1_27_tsimcreated_xor_Q + ); + REG_1_27_tsimcreated_set_and_noreset_Q_965 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_27_tsimcreated_set_and_noreset_IN0, + I1 => REG_1_27_SETF, + O => REG_1_27_tsimcreated_set_and_noreset_Q + ); + REG_1_27_tsimcreated_prld_Q_966 : X_OR2 + port map ( + I0 => REG_1_27_RSTF, + I1 => PRLD, + O => REG_1_27_tsimcreated_prld_Q + ); + REG_1_27_REG : X_FF + port map ( + I => REG_1_27_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_1_27_CLKF, + SET => REG_1_27_tsimcreated_set_and_noreset_Q, + RST => REG_1_27_tsimcreated_prld_Q, + O => REG_1_27_Q + ); + REG_1_27_D_967 : X_XOR2 + port map ( + I0 => REG_1_27_D1, + I1 => REG_1_27_D2, + O => REG_1_27_D + ); + REG_1_27_D1_968 : X_ZERO + port map ( + O => REG_1_27_D1 + ); + REG_1_27_D2_PT_0_969 : X_AND2 + port map ( + I0 => EXP37_EXP, + I1 => EXP37_EXP, + O => REG_1_27_D2_PT_0 + ); + REG_1_27_D2_PT_1_970 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_27_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_1_27_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => REG_1_26, + I5 => NlwInverterSignal_REG_1_27_D2_PT_1_IN5, + O => REG_1_27_D2_PT_1 + ); + REG_1_27_D2_PT_2_971 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_27_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_1_27_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => NlwInverterSignal_REG_1_27_D2_PT_2_IN4, + I5 => REG_1_27, + O => REG_1_27_D2_PT_2 + ); + REG_1_27_D2_972 : X_OR3 + port map ( + I0 => REG_1_27_D2_PT_0, + I1 => REG_1_27_D2_PT_1, + I2 => REG_1_27_D2_PT_2, + O => REG_1_27_D2 + ); + REG_1_27_CLKF_973 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_27_CLKF_IN0, + I1 => NlwInverterSignal_REG_1_27_CLKF_IN1, + O => REG_1_27_CLKF + ); + REG_1_27_SETF_974 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => DIN_27_IBUF, + O => REG_1_27_SETF + ); + REG_1_27_RSTF_975 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => NlwInverterSignal_REG_1_27_RSTF_IN2, + O => REG_1_27_RSTF + ); + REG_1_28_976 : X_BUF + port map ( + I => REG_1_28_Q, + O => REG_1_28 + ); + REG_1_28_tsimcreated_xor_Q_977 : X_XOR2 + port map ( + I0 => REG_1_28_D, + I1 => REG_1_28_Q, + O => REG_1_28_tsimcreated_xor_Q + ); + REG_1_28_tsimcreated_set_and_noreset_Q_978 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_28_tsimcreated_set_and_noreset_IN0, + I1 => REG_1_28_SETF, + O => REG_1_28_tsimcreated_set_and_noreset_Q + ); + REG_1_28_tsimcreated_prld_Q_979 : X_OR2 + port map ( + I0 => REG_1_28_RSTF, + I1 => PRLD, + O => REG_1_28_tsimcreated_prld_Q + ); + REG_1_28_REG : X_FF + port map ( + I => REG_1_28_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_1_28_CLKF, + SET => REG_1_28_tsimcreated_set_and_noreset_Q, + RST => REG_1_28_tsimcreated_prld_Q, + O => REG_1_28_Q + ); + REG_1_28_D_980 : X_XOR2 + port map ( + I0 => REG_1_28_D1, + I1 => REG_1_28_D2, + O => REG_1_28_D + ); + REG_1_28_D1_981 : X_ZERO + port map ( + O => REG_1_28_D1 + ); + REG_1_28_D2_PT_0_982 : X_AND2 + port map ( + I0 => EXP68_EXP, + I1 => EXP68_EXP, + O => REG_1_28_D2_PT_0 + ); + REG_1_28_D2_PT_1_983 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_28_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_1_28_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => REG_1_27, + I5 => NlwInverterSignal_REG_1_28_D2_PT_1_IN5, + O => REG_1_28_D2_PT_1 + ); + REG_1_28_D2_PT_2_984 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_28_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_1_28_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => NlwInverterSignal_REG_1_28_D2_PT_2_IN4, + I5 => REG_1_28, + O => REG_1_28_D2_PT_2 + ); + REG_1_28_D2_985 : X_OR3 + port map ( + I0 => REG_1_28_D2_PT_0, + I1 => REG_1_28_D2_PT_1, + I2 => REG_1_28_D2_PT_2, + O => REG_1_28_D2 + ); + REG_1_28_CLKF_986 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_28_CLKF_IN0, + I1 => NlwInverterSignal_REG_1_28_CLKF_IN1, + O => REG_1_28_CLKF + ); + REG_1_28_SETF_987 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => DIN_28_IBUF, + O => REG_1_28_SETF + ); + REG_1_28_RSTF_988 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => NlwInverterSignal_REG_1_28_RSTF_IN2, + O => REG_1_28_RSTF + ); + REG_1_29_989 : X_BUF + port map ( + I => REG_1_29_Q, + O => REG_1_29 + ); + REG_1_29_tsimcreated_xor_Q_990 : X_XOR2 + port map ( + I0 => REG_1_29_D, + I1 => REG_1_29_Q, + O => REG_1_29_tsimcreated_xor_Q + ); + REG_1_29_tsimcreated_set_and_noreset_Q_991 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_29_tsimcreated_set_and_noreset_IN0, + I1 => REG_1_29_SETF, + O => REG_1_29_tsimcreated_set_and_noreset_Q + ); + REG_1_29_tsimcreated_prld_Q_992 : X_OR2 + port map ( + I0 => REG_1_29_RSTF, + I1 => PRLD, + O => REG_1_29_tsimcreated_prld_Q + ); + REG_1_29_REG : X_FF + port map ( + I => REG_1_29_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_1_29_CLKF, + SET => REG_1_29_tsimcreated_set_and_noreset_Q, + RST => REG_1_29_tsimcreated_prld_Q, + O => REG_1_29_Q + ); + REG_1_29_D_993 : X_XOR2 + port map ( + I0 => REG_1_29_D1, + I1 => REG_1_29_D2, + O => REG_1_29_D + ); + REG_1_29_D1_994 : X_ZERO + port map ( + O => REG_1_29_D1 + ); + REG_1_29_D2_PT_0_995 : X_AND2 + port map ( + I0 => EXP28_EXP, + I1 => EXP28_EXP, + O => REG_1_29_D2_PT_0 + ); + REG_1_29_D2_PT_1_996 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_29_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_1_29_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => REG_1_28, + I5 => NlwInverterSignal_REG_1_29_D2_PT_1_IN5, + O => REG_1_29_D2_PT_1 + ); + REG_1_29_D2_PT_2_997 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_29_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_1_29_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => NlwInverterSignal_REG_1_29_D2_PT_2_IN4, + I5 => REG_1_29, + O => REG_1_29_D2_PT_2 + ); + REG_1_29_D2_998 : X_OR3 + port map ( + I0 => REG_1_29_D2_PT_0, + I1 => REG_1_29_D2_PT_1, + I2 => REG_1_29_D2_PT_2, + O => REG_1_29_D2 + ); + REG_1_29_CLKF_999 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_29_CLKF_IN0, + I1 => NlwInverterSignal_REG_1_29_CLKF_IN1, + O => REG_1_29_CLKF + ); + REG_1_29_SETF_1000 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => DIN_29_IBUF, + O => REG_1_29_SETF + ); + REG_1_29_RSTF_1001 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => NlwInverterSignal_REG_1_29_RSTF_IN2, + O => REG_1_29_RSTF + ); + REG_1_3_1002 : X_BUF + port map ( + I => REG_1_3_Q, + O => REG_1_3 + ); + REG_1_3_EXP_1003 : X_BUF + port map ( + I => REG_1_3_EXP_tsimrenamed_net_Q, + O => REG_1_3_EXP + ); + REG_1_3_tsimcreated_xor_Q_1004 : X_XOR2 + port map ( + I0 => REG_1_3_D, + I1 => REG_1_3_Q, + O => REG_1_3_tsimcreated_xor_Q + ); + REG_1_3_tsimcreated_set_and_noreset_Q_1005 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_3_tsimcreated_set_and_noreset_IN0, + I1 => REG_1_3_SETF, + O => REG_1_3_tsimcreated_set_and_noreset_Q + ); + REG_1_3_tsimcreated_prld_Q_1006 : X_OR2 + port map ( + I0 => REG_1_3_RSTF, + I1 => PRLD, + O => REG_1_3_tsimcreated_prld_Q + ); + REG_1_3_REG : X_FF + port map ( + I => REG_1_3_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_1_3_CLKF, + SET => REG_1_3_tsimcreated_set_and_noreset_Q, + RST => REG_1_3_tsimcreated_prld_Q, + O => REG_1_3_Q + ); + REG_1_3_D_1007 : X_XOR2 + port map ( + I0 => REG_1_3_D1, + I1 => REG_1_3_D2, + O => REG_1_3_D + ); + REG_1_3_D1_1008 : X_ZERO + port map ( + O => REG_1_3_D1 + ); + REG_1_3_D2_1009 : X_AND2 + port map ( + I0 => EXP53_EXP, + I1 => EXP53_EXP, + O => REG_1_3_D2 + ); + REG_1_3_CLKF_1010 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_3_CLKF_IN0, + I1 => NlwInverterSignal_REG_1_3_CLKF_IN1, + O => REG_1_3_CLKF + ); + REG_1_3_SETF_1011 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => DIN_3_IBUF, + O => REG_1_3_SETF + ); + REG_1_3_RSTF_1012 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => NlwInverterSignal_REG_1_3_RSTF_IN2, + O => REG_1_3_RSTF + ); + REG_1_3_EXP_PT_0_1013 : X_AND7 + port map ( + I0 => NlwInverterSignal_REG_1_3_EXP_PT_0_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => DIN_2_IBUF, + I6 => NlwInverterSignal_REG_1_3_EXP_PT_0_IN6, + O => REG_1_3_EXP_PT_0 + ); + REG_1_3_EXP_PT_1_1014 : X_AND7 + port map ( + I0 => NlwInverterSignal_REG_1_3_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => NlwInverterSignal_REG_1_3_EXP_PT_1_IN5, + I6 => REG_1_2, + O => REG_1_3_EXP_PT_1 + ); + REG_1_3_EXP_tsimrenamed_net_Q_1015 : X_OR2 + port map ( + I0 => REG_1_3_EXP_PT_0, + I1 => REG_1_3_EXP_PT_1, + O => REG_1_3_EXP_tsimrenamed_net_Q + ); + REG_1_30_1016 : X_BUF + port map ( + I => REG_1_30_Q, + O => REG_1_30 + ); + REG_1_30_tsimcreated_xor_Q_1017 : X_XOR2 + port map ( + I0 => REG_1_30_D, + I1 => REG_1_30_Q, + O => REG_1_30_tsimcreated_xor_Q + ); + REG_1_30_tsimcreated_set_and_noreset_Q_1018 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_30_tsimcreated_set_and_noreset_IN0, + I1 => REG_1_30_SETF, + O => REG_1_30_tsimcreated_set_and_noreset_Q + ); + REG_1_30_tsimcreated_prld_Q_1019 : X_OR2 + port map ( + I0 => REG_1_30_RSTF, + I1 => PRLD, + O => REG_1_30_tsimcreated_prld_Q + ); + REG_1_30_REG : X_FF + port map ( + I => REG_1_30_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_1_30_CLKF, + SET => REG_1_30_tsimcreated_set_and_noreset_Q, + RST => REG_1_30_tsimcreated_prld_Q, + O => REG_1_30_Q + ); + REG_1_30_D_1020 : X_XOR2 + port map ( + I0 => REG_1_30_D1, + I1 => REG_1_30_D2, + O => REG_1_30_D + ); + REG_1_30_D1_1021 : X_ZERO + port map ( + O => REG_1_30_D1 + ); + REG_1_30_D2_PT_0_1022 : X_AND2 + port map ( + I0 => DOUT_OBUFE_EXP, + I1 => DOUT_OBUFE_EXP, + O => REG_1_30_D2_PT_0 + ); + REG_1_30_D2_PT_1_1023 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_30_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_1_30_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => REG_1_29, + I5 => NlwInverterSignal_REG_1_30_D2_PT_1_IN5, + O => REG_1_30_D2_PT_1 + ); + REG_1_30_D2_PT_2_1024 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_30_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_1_30_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => NlwInverterSignal_REG_1_30_D2_PT_2_IN4, + I5 => REG_1_30, + O => REG_1_30_D2_PT_2 + ); + REG_1_30_D2_1025 : X_OR3 + port map ( + I0 => REG_1_30_D2_PT_0, + I1 => REG_1_30_D2_PT_1, + I2 => REG_1_30_D2_PT_2, + O => REG_1_30_D2 + ); + REG_1_30_CLKF_1026 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_30_CLKF_IN0, + I1 => NlwInverterSignal_REG_1_30_CLKF_IN1, + O => REG_1_30_CLKF + ); + REG_1_30_SETF_1027 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => DIN_30_IBUF, + O => REG_1_30_SETF + ); + REG_1_30_RSTF_1028 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => NlwInverterSignal_REG_1_30_RSTF_IN2, + O => REG_1_30_RSTF + ); + REG_1_31_1029 : X_BUF + port map ( + I => REG_1_31_Q, + O => REG_1_31 + ); + REG_1_31_tsimcreated_xor_Q_1030 : X_XOR2 + port map ( + I0 => REG_1_31_D, + I1 => REG_1_31_Q, + O => REG_1_31_tsimcreated_xor_Q + ); + REG_1_31_tsimcreated_set_and_noreset_Q_1031 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_31_tsimcreated_set_and_noreset_IN0, + I1 => REG_1_31_SETF, + O => REG_1_31_tsimcreated_set_and_noreset_Q + ); + REG_1_31_tsimcreated_prld_Q_1032 : X_OR2 + port map ( + I0 => REG_1_31_RSTF, + I1 => PRLD, + O => REG_1_31_tsimcreated_prld_Q + ); + REG_1_31_REG : X_FF + port map ( + I => REG_1_31_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_1_31_CLKF, + SET => REG_1_31_tsimcreated_set_and_noreset_Q, + RST => REG_1_31_tsimcreated_prld_Q, + O => REG_1_31_Q + ); + REG_1_31_D_1033 : X_XOR2 + port map ( + I0 => REG_1_31_D1, + I1 => REG_1_31_D2, + O => REG_1_31_D + ); + REG_1_31_D1_1034 : X_ZERO + port map ( + O => REG_1_31_D1 + ); + REG_1_31_D2_PT_0_1035 : X_AND2 + port map ( + I0 => EXP27_EXP, + I1 => EXP27_EXP, + O => REG_1_31_D2_PT_0 + ); + REG_1_31_D2_PT_1_1036 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_31_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_1_31_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => REG_1_30, + I5 => NlwInverterSignal_REG_1_31_D2_PT_1_IN5, + O => REG_1_31_D2_PT_1 + ); + REG_1_31_D2_PT_2_1037 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_31_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_1_31_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => NlwInverterSignal_REG_1_31_D2_PT_2_IN4, + I5 => REG_1_31, + O => REG_1_31_D2_PT_2 + ); + REG_1_31_D2_1038 : X_OR3 + port map ( + I0 => REG_1_31_D2_PT_0, + I1 => REG_1_31_D2_PT_1, + I2 => REG_1_31_D2_PT_2, + O => REG_1_31_D2 + ); + REG_1_31_CLKF_1039 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_31_CLKF_IN0, + I1 => NlwInverterSignal_REG_1_31_CLKF_IN1, + O => REG_1_31_CLKF + ); + REG_1_31_SETF_1040 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => DIN_31_IBUF, + O => REG_1_31_SETF + ); + REG_1_31_RSTF_1041 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => NlwInverterSignal_REG_1_31_RSTF_IN2, + O => REG_1_31_RSTF + ); + REG_1_4_1042 : X_BUF + port map ( + I => REG_1_4_Q, + O => REG_1_4 + ); + REG_1_4_tsimcreated_xor_Q_1043 : X_XOR2 + port map ( + I0 => REG_1_4_D, + I1 => REG_1_4_Q, + O => REG_1_4_tsimcreated_xor_Q + ); + REG_1_4_tsimcreated_set_and_noreset_Q_1044 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_4_tsimcreated_set_and_noreset_IN0, + I1 => REG_1_4_SETF, + O => REG_1_4_tsimcreated_set_and_noreset_Q + ); + REG_1_4_tsimcreated_prld_Q_1045 : X_OR2 + port map ( + I0 => REG_1_4_RSTF, + I1 => PRLD, + O => REG_1_4_tsimcreated_prld_Q + ); + REG_1_4_REG : X_FF + port map ( + I => REG_1_4_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_1_4_CLKF, + SET => REG_1_4_tsimcreated_set_and_noreset_Q, + RST => REG_1_4_tsimcreated_prld_Q, + O => REG_1_4_Q + ); + REG_1_4_D_1046 : X_XOR2 + port map ( + I0 => REG_1_4_D1, + I1 => REG_1_4_D2, + O => REG_1_4_D + ); + REG_1_4_D1_1047 : X_ZERO + port map ( + O => REG_1_4_D1 + ); + REG_1_4_D2_PT_0_1048 : X_AND2 + port map ( + I0 => REG_1_0_EXP, + I1 => REG_1_0_EXP, + O => REG_1_4_D2_PT_0 + ); + REG_1_4_D2_PT_1_1049 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_4_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_1_4_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => REG_1_4, + I5 => NlwInverterSignal_REG_1_4_D2_PT_1_IN5, + O => REG_1_4_D2_PT_1 + ); + REG_1_4_D2_PT_2_1050 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_4_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_1_4_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => NlwInverterSignal_REG_1_4_D2_PT_2_IN4, + I5 => REG_1_3, + O => REG_1_4_D2_PT_2 + ); + REG_1_4_D2_1051 : X_OR3 + port map ( + I0 => REG_1_4_D2_PT_0, + I1 => REG_1_4_D2_PT_1, + I2 => REG_1_4_D2_PT_2, + O => REG_1_4_D2 + ); + REG_1_4_CLKF_1052 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_4_CLKF_IN0, + I1 => NlwInverterSignal_REG_1_4_CLKF_IN1, + O => REG_1_4_CLKF + ); + REG_1_4_SETF_1053 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => DIN_4_IBUF, + O => REG_1_4_SETF + ); + REG_1_4_RSTF_1054 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => NlwInverterSignal_REG_1_4_RSTF_IN2, + O => REG_1_4_RSTF + ); + REG_1_5_1055 : X_BUF + port map ( + I => REG_1_5_Q, + O => REG_1_5 + ); + REG_1_5_tsimcreated_xor_Q_1056 : X_XOR2 + port map ( + I0 => REG_1_5_D, + I1 => REG_1_5_Q, + O => REG_1_5_tsimcreated_xor_Q + ); + REG_1_5_tsimcreated_set_and_noreset_Q_1057 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_5_tsimcreated_set_and_noreset_IN0, + I1 => REG_1_5_SETF, + O => REG_1_5_tsimcreated_set_and_noreset_Q + ); + REG_1_5_tsimcreated_prld_Q_1058 : X_OR2 + port map ( + I0 => REG_1_5_RSTF, + I1 => PRLD, + O => REG_1_5_tsimcreated_prld_Q + ); + REG_1_5_REG : X_FF + port map ( + I => REG_1_5_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_1_5_CLKF, + SET => REG_1_5_tsimcreated_set_and_noreset_Q, + RST => REG_1_5_tsimcreated_prld_Q, + O => REG_1_5_Q + ); + REG_1_5_D_1059 : X_XOR2 + port map ( + I0 => REG_1_5_D1, + I1 => REG_1_5_D2, + O => REG_1_5_D + ); + REG_1_5_D1_1060 : X_ZERO + port map ( + O => REG_1_5_D1 + ); + REG_1_5_D2_PT_0_1061 : X_AND2 + port map ( + I0 => EXP49_EXP, + I1 => EXP49_EXP, + O => REG_1_5_D2_PT_0 + ); + REG_1_5_D2_PT_1_1062 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_5_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_1_5_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => REG_1_4, + I5 => NlwInverterSignal_REG_1_5_D2_PT_1_IN5, + O => REG_1_5_D2_PT_1 + ); + REG_1_5_D2_PT_2_1063 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_5_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_1_5_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => NlwInverterSignal_REG_1_5_D2_PT_2_IN4, + I5 => REG_1_5, + O => REG_1_5_D2_PT_2 + ); + REG_1_5_D2_1064 : X_OR3 + port map ( + I0 => REG_1_5_D2_PT_0, + I1 => REG_1_5_D2_PT_1, + I2 => REG_1_5_D2_PT_2, + O => REG_1_5_D2 + ); + REG_1_5_CLKF_1065 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_5_CLKF_IN0, + I1 => NlwInverterSignal_REG_1_5_CLKF_IN1, + O => REG_1_5_CLKF + ); + REG_1_5_SETF_1066 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => DIN_5_IBUF, + O => REG_1_5_SETF + ); + REG_1_5_RSTF_1067 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => NlwInverterSignal_REG_1_5_RSTF_IN2, + O => REG_1_5_RSTF + ); + REG_1_6_1068 : X_BUF + port map ( + I => REG_1_6_Q, + O => REG_1_6 + ); + REG_1_6_tsimcreated_xor_Q_1069 : X_XOR2 + port map ( + I0 => REG_1_6_D, + I1 => REG_1_6_Q, + O => REG_1_6_tsimcreated_xor_Q + ); + REG_1_6_tsimcreated_set_and_noreset_Q_1070 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_6_tsimcreated_set_and_noreset_IN0, + I1 => REG_1_6_SETF, + O => REG_1_6_tsimcreated_set_and_noreset_Q + ); + REG_1_6_tsimcreated_prld_Q_1071 : X_OR2 + port map ( + I0 => REG_1_6_RSTF, + I1 => PRLD, + O => REG_1_6_tsimcreated_prld_Q + ); + REG_1_6_REG : X_FF + port map ( + I => REG_1_6_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_1_6_CLKF, + SET => REG_1_6_tsimcreated_set_and_noreset_Q, + RST => REG_1_6_tsimcreated_prld_Q, + O => REG_1_6_Q + ); + REG_1_6_D_1072 : X_XOR2 + port map ( + I0 => REG_1_6_D1, + I1 => REG_1_6_D2, + O => REG_1_6_D + ); + REG_1_6_D1_1073 : X_ZERO + port map ( + O => REG_1_6_D1 + ); + REG_1_6_D2_PT_0_1074 : X_AND2 + port map ( + I0 => EXP50_EXP, + I1 => EXP50_EXP, + O => REG_1_6_D2_PT_0 + ); + REG_1_6_D2_PT_1_1075 : X_AND2 + port map ( + I0 => EXP51_EXP, + I1 => EXP51_EXP, + O => REG_1_6_D2_PT_1 + ); + REG_1_6_D2_PT_2_1076 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_6_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_1_6_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => REG_1_5, + I5 => NlwInverterSignal_REG_1_6_D2_PT_2_IN5, + O => REG_1_6_D2_PT_2 + ); + REG_1_6_D2_PT_3_1077 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_6_D2_PT_3_IN0, + I1 => NlwInverterSignal_REG_1_6_D2_PT_3_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => NlwInverterSignal_REG_1_6_D2_PT_3_IN4, + I5 => REG_1_6, + O => REG_1_6_D2_PT_3 + ); + REG_1_6_D2_1078 : X_OR4 + port map ( + I0 => REG_1_6_D2_PT_0, + I1 => REG_1_6_D2_PT_1, + I2 => REG_1_6_D2_PT_2, + I3 => REG_1_6_D2_PT_3, + O => REG_1_6_D2 + ); + REG_1_6_CLKF_1079 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_6_CLKF_IN0, + I1 => NlwInverterSignal_REG_1_6_CLKF_IN1, + O => REG_1_6_CLKF + ); + REG_1_6_SETF_1080 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => DIN_6_IBUF, + O => REG_1_6_SETF + ); + REG_1_6_RSTF_1081 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => NlwInverterSignal_REG_1_6_RSTF_IN2, + O => REG_1_6_RSTF + ); + REG_1_7_1082 : X_BUF + port map ( + I => REG_1_7_Q, + O => REG_1_7 + ); + REG_1_7_tsimcreated_xor_Q_1083 : X_XOR2 + port map ( + I0 => REG_1_7_D, + I1 => REG_1_7_Q, + O => REG_1_7_tsimcreated_xor_Q + ); + REG_1_7_tsimcreated_set_and_noreset_Q_1084 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_7_tsimcreated_set_and_noreset_IN0, + I1 => REG_1_7_SETF, + O => REG_1_7_tsimcreated_set_and_noreset_Q + ); + REG_1_7_tsimcreated_prld_Q_1085 : X_OR2 + port map ( + I0 => REG_1_7_RSTF, + I1 => PRLD, + O => REG_1_7_tsimcreated_prld_Q + ); + REG_1_7_REG : X_FF + port map ( + I => REG_1_7_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_1_7_CLKF, + SET => REG_1_7_tsimcreated_set_and_noreset_Q, + RST => REG_1_7_tsimcreated_prld_Q, + O => REG_1_7_Q + ); + REG_1_7_D_1086 : X_XOR2 + port map ( + I0 => REG_1_7_D1, + I1 => REG_1_7_D2, + O => REG_1_7_D + ); + REG_1_7_D1_1087 : X_ZERO + port map ( + O => REG_1_7_D1 + ); + REG_1_7_D2_PT_0_1088 : X_AND2 + port map ( + I0 => EXP42_EXP, + I1 => EXP42_EXP, + O => REG_1_7_D2_PT_0 + ); + REG_1_7_D2_PT_1_1089 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_7_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_1_7_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => REG_1_6, + I5 => NlwInverterSignal_REG_1_7_D2_PT_1_IN5, + O => REG_1_7_D2_PT_1 + ); + REG_1_7_D2_PT_2_1090 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_7_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_1_7_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => NlwInverterSignal_REG_1_7_D2_PT_2_IN4, + I5 => REG_1_7, + O => REG_1_7_D2_PT_2 + ); + REG_1_7_D2_1091 : X_OR3 + port map ( + I0 => REG_1_7_D2_PT_0, + I1 => REG_1_7_D2_PT_1, + I2 => REG_1_7_D2_PT_2, + O => REG_1_7_D2 + ); + REG_1_7_CLKF_1092 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_7_CLKF_IN0, + I1 => NlwInverterSignal_REG_1_7_CLKF_IN1, + O => REG_1_7_CLKF + ); + REG_1_7_SETF_1093 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => DIN_7_IBUF, + O => REG_1_7_SETF + ); + REG_1_7_RSTF_1094 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => NlwInverterSignal_REG_1_7_RSTF_IN2, + O => REG_1_7_RSTF + ); + REG_1_8_1095 : X_BUF + port map ( + I => REG_1_8_Q, + O => REG_1_8 + ); + REG_1_8_tsimcreated_xor_Q_1096 : X_XOR2 + port map ( + I0 => REG_1_8_D, + I1 => REG_1_8_Q, + O => REG_1_8_tsimcreated_xor_Q + ); + REG_1_8_tsimcreated_set_and_noreset_Q_1097 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_8_tsimcreated_set_and_noreset_IN0, + I1 => REG_1_8_SETF, + O => REG_1_8_tsimcreated_set_and_noreset_Q + ); + REG_1_8_tsimcreated_prld_Q_1098 : X_OR2 + port map ( + I0 => REG_1_8_RSTF, + I1 => PRLD, + O => REG_1_8_tsimcreated_prld_Q + ); + REG_1_8_REG : X_FF + port map ( + I => REG_1_8_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_1_8_CLKF, + SET => REG_1_8_tsimcreated_set_and_noreset_Q, + RST => REG_1_8_tsimcreated_prld_Q, + O => REG_1_8_Q + ); + REG_1_8_D_1099 : X_XOR2 + port map ( + I0 => REG_1_8_D1, + I1 => REG_1_8_D2, + O => REG_1_8_D + ); + REG_1_8_D1_1100 : X_ZERO + port map ( + O => REG_1_8_D1 + ); + REG_1_8_D2_PT_0_1101 : X_AND2 + port map ( + I0 => EXP47_EXP, + I1 => EXP47_EXP, + O => REG_1_8_D2_PT_0 + ); + REG_1_8_D2_PT_1_1102 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_8_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_1_8_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => REG_1_7, + I5 => NlwInverterSignal_REG_1_8_D2_PT_1_IN5, + O => REG_1_8_D2_PT_1 + ); + REG_1_8_D2_PT_2_1103 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_8_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_1_8_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => NlwInverterSignal_REG_1_8_D2_PT_2_IN4, + I5 => REG_1_8, + O => REG_1_8_D2_PT_2 + ); + REG_1_8_D2_1104 : X_OR3 + port map ( + I0 => REG_1_8_D2_PT_0, + I1 => REG_1_8_D2_PT_1, + I2 => REG_1_8_D2_PT_2, + O => REG_1_8_D2 + ); + REG_1_8_CLKF_1105 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_8_CLKF_IN0, + I1 => NlwInverterSignal_REG_1_8_CLKF_IN1, + O => REG_1_8_CLKF + ); + REG_1_8_SETF_1106 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => DIN_8_IBUF, + O => REG_1_8_SETF + ); + REG_1_8_RSTF_1107 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => NlwInverterSignal_REG_1_8_RSTF_IN2, + O => REG_1_8_RSTF + ); + REG_1_9_1108 : X_BUF + port map ( + I => REG_1_9_Q, + O => REG_1_9 + ); + REG_1_9_tsimcreated_xor_Q_1109 : X_XOR2 + port map ( + I0 => REG_1_9_D, + I1 => REG_1_9_Q, + O => REG_1_9_tsimcreated_xor_Q + ); + REG_1_9_tsimcreated_set_and_noreset_Q_1110 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_9_tsimcreated_set_and_noreset_IN0, + I1 => REG_1_9_SETF, + O => REG_1_9_tsimcreated_set_and_noreset_Q + ); + REG_1_9_tsimcreated_prld_Q_1111 : X_OR2 + port map ( + I0 => REG_1_9_RSTF, + I1 => PRLD, + O => REG_1_9_tsimcreated_prld_Q + ); + REG_1_9_REG : X_FF + port map ( + I => REG_1_9_tsimcreated_xor_Q, + CE => Vcc, + CLK => REG_1_9_CLKF, + SET => REG_1_9_tsimcreated_set_and_noreset_Q, + RST => REG_1_9_tsimcreated_prld_Q, + O => REG_1_9_Q + ); + REG_1_9_D_1112 : X_XOR2 + port map ( + I0 => REG_1_9_D1, + I1 => REG_1_9_D2, + O => REG_1_9_D + ); + REG_1_9_D1_1113 : X_ZERO + port map ( + O => REG_1_9_D1 + ); + REG_1_9_D2_PT_0_1114 : X_AND2 + port map ( + I0 => EXP44_EXP, + I1 => EXP44_EXP, + O => REG_1_9_D2_PT_0 + ); + REG_1_9_D2_PT_1_1115 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_9_D2_PT_1_IN0, + I1 => NlwInverterSignal_REG_1_9_D2_PT_1_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => REG_1_9, + I5 => NlwInverterSignal_REG_1_9_D2_PT_1_IN5, + O => REG_1_9_D2_PT_1 + ); + REG_1_9_D2_PT_2_1116 : X_AND6 + port map ( + I0 => NlwInverterSignal_REG_1_9_D2_PT_2_IN0, + I1 => NlwInverterSignal_REG_1_9_D2_PT_2_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => NlwInverterSignal_REG_1_9_D2_PT_2_IN4, + I5 => REG_1_8, + O => REG_1_9_D2_PT_2 + ); + REG_1_9_D2_1117 : X_OR3 + port map ( + I0 => REG_1_9_D2_PT_0, + I1 => REG_1_9_D2_PT_1, + I2 => REG_1_9_D2_PT_2, + O => REG_1_9_D2 + ); + REG_1_9_CLKF_1118 : X_AND2 + port map ( + I0 => NlwInverterSignal_REG_1_9_CLKF_IN0, + I1 => NlwInverterSignal_REG_1_9_CLKF_IN1, + O => REG_1_9_CLKF + ); + REG_1_9_SETF_1119 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => DIN_9_IBUF, + O => REG_1_9_SETF + ); + REG_1_9_RSTF_1120 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => writeBufId(0), + I2 => NlwInverterSignal_REG_1_9_RSTF_IN2, + O => REG_1_9_RSTF + ); + DOUT_OBUFE_1121 : X_BUF + port map ( + I => DOUT_OBUFE_Q, + O => DOUT_OBUFE + ); + DOUT_OBUFE_EXP_1122 : X_BUF + port map ( + I => DOUT_OBUFE_EXP_tsimrenamed_net_Q, + O => DOUT_OBUFE_EXP + ); + DOUT_OBUFE_OE_1123 : X_BUF + port map ( + I => DOUT_OBUFE_BUFOE_OUT, + O => DOUT_OBUFE_OE + ); + DOUT_OBUFE_BUFOE_OUT_1124 : X_BUF + port map ( + I => DOUT_OBUFE_TRST, + O => DOUT_OBUFE_BUFOE_OUT + ); + DOUT_OBUFE_Q_1125 : X_BUF + port map ( + I => DOUT_OBUFE_D, + O => DOUT_OBUFE_Q + ); + DOUT_OBUFE_D_1126 : X_XOR2 + port map ( + I0 => DOUT_OBUFE_D1, + I1 => DOUT_OBUFE_D2, + O => DOUT_OBUFE_D + ); + DOUT_OBUFE_D1_1127 : X_ZERO + port map ( + O => DOUT_OBUFE_D1 + ); + DOUT_OBUFE_D2_PT_0_1128 : X_AND2 + port map ( + I0 => readBufId(0), + I1 => REG_1_31, + O => DOUT_OBUFE_D2_PT_0 + ); + DOUT_OBUFE_D2_PT_1_1129 : X_AND2 + port map ( + I0 => NlwInverterSignal_DOUT_OBUFE_D2_PT_1_IN0, + I1 => REG_0_31, + O => DOUT_OBUFE_D2_PT_1 + ); + DOUT_OBUFE_D2_1130 : X_OR2 + port map ( + I0 => DOUT_OBUFE_D2_PT_0, + I1 => DOUT_OBUFE_D2_PT_1, + O => DOUT_OBUFE_D2 + ); + DOUT_OBUFE_TRST_1131 : X_AND2 + port map ( + I0 => NlwInverterSignal_DOUT_OBUFE_TRST_IN0, + I1 => nINIT_B_IBUF, + O => DOUT_OBUFE_TRST + ); + DOUT_OBUFE_EXP_PT_0_1132 : X_AND7 + port map ( + I0 => NlwInverterSignal_DOUT_OBUFE_EXP_PT_0_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => DIN_30_IBUF, + I6 => NlwInverterSignal_DOUT_OBUFE_EXP_PT_0_IN6, + O => DOUT_OBUFE_EXP_PT_0 + ); + DOUT_OBUFE_EXP_PT_1_1133 : X_AND7 + port map ( + I0 => NlwInverterSignal_DOUT_OBUFE_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => NlwInverterSignal_DOUT_OBUFE_EXP_PT_1_IN5, + I6 => REG_1_30, + O => DOUT_OBUFE_EXP_PT_1 + ); + DOUT_OBUFE_EXP_tsimrenamed_net_Q_1134 : X_OR2 + port map ( + I0 => DOUT_OBUFE_EXP_PT_0, + I1 => DOUT_OBUFE_EXP_PT_1, + O => DOUT_OBUFE_EXP_tsimrenamed_net_Q + ); + state_0_Q_1135 : X_BUF + port map ( + I => state_0_Q, + O => state(0) + ); + state_0_EXP_1136 : X_BUF + port map ( + I => state_0_EXP_tsimrenamed_net_Q, + O => state_0_EXP + ); + state_0_tsimcreated_prld_Q_1137 : X_OR2 + port map ( + I0 => state_0_RSTF, + I1 => PRLD, + O => state_0_tsimcreated_prld_Q + ); + state_0_REG : X_FF + port map ( + I => state_0_D, + CE => Vcc, + CLK => state_0_CLKF, + SET => Gnd, + RST => state_0_tsimcreated_prld_Q, + O => state_0_Q + ); + state_0_D_1138 : X_XOR2 + port map ( + I0 => state_0_D1, + I1 => state_0_D2, + O => state_0_D + ); + state_0_D1_1139 : X_ZERO + port map ( + O => state_0_D1 + ); + state_0_D2_1140 : X_AND2 + port map ( + I0 => next_state(0), + I1 => next_state(0), + O => state_0_D2 + ); + state_0_CLKF_1141 : X_AND2 + port map ( + I0 => SCLK, + I1 => SCLK, + O => state_0_CLKF + ); + state_0_RSTF_1142 : X_AND2 + port map ( + I0 => RES_IBUF, + I1 => RES_IBUF, + O => state_0_RSTF + ); + state_0_EXP_PT_0_1143 : X_AND7 + port map ( + I0 => NlwInverterSignal_state_0_EXP_PT_0_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_state_0_EXP_PT_0_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_state_0_EXP_PT_0_IN4, + I5 => DIN_19_IBUF, + I6 => NlwInverterSignal_state_0_EXP_PT_0_IN6, + O => state_0_EXP_PT_0 + ); + state_0_EXP_PT_1_1144 : X_AND7 + port map ( + I0 => NlwInverterSignal_state_0_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_state_0_EXP_PT_1_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_state_0_EXP_PT_1_IN4, + I5 => NlwInverterSignal_state_0_EXP_PT_1_IN5, + I6 => REG_0_19, + O => state_0_EXP_PT_1 + ); + state_0_EXP_tsimrenamed_net_Q_1145 : X_OR2 + port map ( + I0 => state_0_EXP_PT_0, + I1 => state_0_EXP_PT_1, + O => state_0_EXP_tsimrenamed_net_Q + ); + state_1_Q_1146 : X_BUF + port map ( + I => state_1_Q, + O => state(1) + ); + state_1_EXP_1147 : X_BUF + port map ( + I => state_1_EXP_tsimrenamed_net_Q, + O => state_1_EXP + ); + state_1_tsimcreated_prld_Q_1148 : X_OR2 + port map ( + I0 => state_1_RSTF, + I1 => PRLD, + O => state_1_tsimcreated_prld_Q + ); + state_1_REG : X_FF + port map ( + I => state_1_D, + CE => Vcc, + CLK => state_1_CLKF, + SET => Gnd, + RST => state_1_tsimcreated_prld_Q, + O => state_1_Q + ); + state_1_D_1149 : X_XOR2 + port map ( + I0 => state_1_D1, + I1 => state_1_D2, + O => state_1_D + ); + state_1_D1_1150 : X_ZERO + port map ( + O => state_1_D1 + ); + state_1_D2_1151 : X_AND2 + port map ( + I0 => next_state(1), + I1 => next_state(1), + O => state_1_D2 + ); + state_1_CLKF_1152 : X_AND2 + port map ( + I0 => SCLK, + I1 => SCLK, + O => state_1_CLKF + ); + state_1_RSTF_1153 : X_AND2 + port map ( + I0 => RES_IBUF, + I1 => RES_IBUF, + O => state_1_RSTF + ); + state_1_EXP_PT_0_1154 : X_AND7 + port map ( + I0 => NlwInverterSignal_state_1_EXP_PT_0_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_state_1_EXP_PT_0_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_state_1_EXP_PT_0_IN4, + I5 => DIN_25_IBUF, + I6 => NlwInverterSignal_state_1_EXP_PT_0_IN6, + O => state_1_EXP_PT_0 + ); + state_1_EXP_PT_1_1155 : X_AND7 + port map ( + I0 => NlwInverterSignal_state_1_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_state_1_EXP_PT_1_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_state_1_EXP_PT_1_IN4, + I5 => NlwInverterSignal_state_1_EXP_PT_1_IN5, + I6 => REG_0_25, + O => state_1_EXP_PT_1 + ); + state_1_EXP_tsimrenamed_net_Q_1156 : X_OR2 + port map ( + I0 => state_1_EXP_PT_0, + I1 => state_1_EXP_PT_1, + O => state_1_EXP_tsimrenamed_net_Q + ); + CLK_SCALE_1_Q_1157 : X_BUF + port map ( + I => CLK_SCALE_1_Q, + O => CLK_SCALE(1) + ); + CLK_SCALE_1_EXP_1158 : X_BUF + port map ( + I => CLK_SCALE_1_EXP_tsimrenamed_net_Q, + O => CLK_SCALE_1_EXP + ); + CLK_SCALE_1_Q_1159 : X_BUF + port map ( + I => CLK_SCALE_1_D, + O => CLK_SCALE_1_Q + ); + CLK_SCALE_1_D_1160 : X_XOR2 + port map ( + I0 => CLK_SCALE_1_D1, + I1 => CLK_SCALE_1_D2, + O => CLK_SCALE_1_D + ); + CLK_SCALE_1_D1_1161 : X_ZERO + port map ( + O => CLK_SCALE_1_D1 + ); + CLK_SCALE_1_D2_PT_0_1162 : X_AND3 + port map ( + I0 => NlwInverterSignal_CLK_SCALE_1_D2_PT_0_IN0, + I1 => LOAD_PRESCALER_IBUF, + I2 => CCLK_PRESCALER_1_IBUF, + O => CLK_SCALE_1_D2_PT_0 + ); + CLK_SCALE_1_D2_PT_1_1163 : X_AND3 + port map ( + I0 => NlwInverterSignal_CLK_SCALE_1_D2_PT_1_IN0, + I1 => NlwInverterSignal_CLK_SCALE_1_D2_PT_1_IN1, + I2 => CLK_SCALE(1), + O => CLK_SCALE_1_D2_PT_1 + ); + CLK_SCALE_1_D2_PT_2_1164 : X_AND3 + port map ( + I0 => NlwInverterSignal_CLK_SCALE_1_D2_PT_2_IN0, + I1 => CLK_SCALE(1), + I2 => CCLK_PRESCALER_1_IBUF, + O => CLK_SCALE_1_D2_PT_2 + ); + CLK_SCALE_1_D2_1165 : X_OR3 + port map ( + I0 => CLK_SCALE_1_D2_PT_0, + I1 => CLK_SCALE_1_D2_PT_1, + I2 => CLK_SCALE_1_D2_PT_2, + O => CLK_SCALE_1_D2 + ); + CLK_SCALE_1_EXP_tsimrenamed_net_Q_1166 : X_AND4 + port map ( + I0 => RES_IBUF, + I1 => NlwInverterSignal_CLK_SCALE_1_EXP_tsimrenamed_net_IN1, + I2 => count(1), + I3 => NlwInverterSignal_CLK_SCALE_1_EXP_tsimrenamed_net_IN3, + O => CLK_SCALE_1_EXP_tsimrenamed_net_Q + ); + CLK_SCALE_2_Q_1167 : X_BUF + port map ( + I => CLK_SCALE_2_Q, + O => CLK_SCALE(2) + ); + CLK_SCALE_2_EXP_1168 : X_BUF + port map ( + I => CLK_SCALE_2_EXP_tsimrenamed_net_Q, + O => CLK_SCALE_2_EXP + ); + CLK_SCALE_2_Q_1169 : X_BUF + port map ( + I => CLK_SCALE_2_D, + O => CLK_SCALE_2_Q + ); + CLK_SCALE_2_D_1170 : X_XOR2 + port map ( + I0 => CLK_SCALE_2_D1, + I1 => CLK_SCALE_2_D2, + O => CLK_SCALE_2_D + ); + CLK_SCALE_2_D1_1171 : X_ZERO + port map ( + O => CLK_SCALE_2_D1 + ); + CLK_SCALE_2_D2_PT_0_1172 : X_AND3 + port map ( + I0 => NlwInverterSignal_CLK_SCALE_2_D2_PT_0_IN0, + I1 => LOAD_PRESCALER_IBUF, + I2 => CCLK_PRESCALER_2_IBUF, + O => CLK_SCALE_2_D2_PT_0 + ); + CLK_SCALE_2_D2_PT_1_1173 : X_AND3 + port map ( + I0 => NlwInverterSignal_CLK_SCALE_2_D2_PT_1_IN0, + I1 => NlwInverterSignal_CLK_SCALE_2_D2_PT_1_IN1, + I2 => CLK_SCALE(2), + O => CLK_SCALE_2_D2_PT_1 + ); + CLK_SCALE_2_D2_PT_2_1174 : X_AND3 + port map ( + I0 => NlwInverterSignal_CLK_SCALE_2_D2_PT_2_IN0, + I1 => CLK_SCALE(2), + I2 => CCLK_PRESCALER_2_IBUF, + O => CLK_SCALE_2_D2_PT_2 + ); + CLK_SCALE_2_D2_1175 : X_OR3 + port map ( + I0 => CLK_SCALE_2_D2_PT_0, + I1 => CLK_SCALE_2_D2_PT_1, + I2 => CLK_SCALE_2_D2_PT_2, + O => CLK_SCALE_2_D2 + ); + CLK_SCALE_2_EXP_PT_0_1176 : X_AND7 + port map ( + I0 => NlwInverterSignal_CLK_SCALE_2_EXP_PT_0_IN0, + I1 => NlwInverterSignal_CLK_SCALE_2_EXP_PT_0_IN1, + I2 => NlwInverterSignal_CLK_SCALE_2_EXP_PT_0_IN2, + I3 => NlwInverterSignal_CLK_SCALE_2_EXP_PT_0_IN3, + I4 => NlwInverterSignal_CLK_SCALE_2_EXP_PT_0_IN4, + I5 => NlwInverterSignal_CLK_SCALE_2_EXP_PT_0_IN5, + I6 => NlwInverterSignal_CLK_SCALE_2_EXP_PT_0_IN6, + O => CLK_SCALE_2_EXP_PT_0 + ); + CLK_SCALE_2_EXP_PT_1_1177 : X_AND7 + port map ( + I0 => NlwInverterSignal_CLK_SCALE_2_EXP_PT_1_IN0, + I1 => NlwInverterSignal_CLK_SCALE_2_EXP_PT_1_IN1, + I2 => NlwInverterSignal_CLK_SCALE_2_EXP_PT_1_IN2, + I3 => NlwInverterSignal_CLK_SCALE_2_EXP_PT_1_IN3, + I4 => NlwInverterSignal_CLK_SCALE_2_EXP_PT_1_IN4, + I5 => NlwInverterSignal_CLK_SCALE_2_EXP_PT_1_IN5, + I6 => CLK_SCALE(5), + O => CLK_SCALE_2_EXP_PT_1 + ); + CLK_SCALE_2_EXP_tsimrenamed_net_Q_1178 : X_OR2 + port map ( + I0 => CLK_SCALE_2_EXP_PT_0, + I1 => CLK_SCALE_2_EXP_PT_1, + O => CLK_SCALE_2_EXP_tsimrenamed_net_Q + ); + CLK_SCALE_3_Q_1179 : X_BUF + port map ( + I => CLK_SCALE_3_Q, + O => CLK_SCALE(3) + ); + CLK_SCALE_3_Q_1180 : X_BUF + port map ( + I => CLK_SCALE_3_D, + O => CLK_SCALE_3_Q + ); + CLK_SCALE_3_D_1181 : X_XOR2 + port map ( + I0 => CLK_SCALE_3_D1, + I1 => CLK_SCALE_3_D2, + O => CLK_SCALE_3_D + ); + CLK_SCALE_3_D1_1182 : X_ZERO + port map ( + O => CLK_SCALE_3_D1 + ); + CLK_SCALE_3_D2_PT_0_1183 : X_AND3 + port map ( + I0 => NlwInverterSignal_CLK_SCALE_3_D2_PT_0_IN0, + I1 => LOAD_PRESCALER_IBUF, + I2 => CCLK_PRESCALER_3_IBUF, + O => CLK_SCALE_3_D2_PT_0 + ); + CLK_SCALE_3_D2_PT_1_1184 : X_AND3 + port map ( + I0 => NlwInverterSignal_CLK_SCALE_3_D2_PT_1_IN0, + I1 => NlwInverterSignal_CLK_SCALE_3_D2_PT_1_IN1, + I2 => CLK_SCALE(3), + O => CLK_SCALE_3_D2_PT_1 + ); + CLK_SCALE_3_D2_PT_2_1185 : X_AND3 + port map ( + I0 => NlwInverterSignal_CLK_SCALE_3_D2_PT_2_IN0, + I1 => CLK_SCALE(3), + I2 => CCLK_PRESCALER_3_IBUF, + O => CLK_SCALE_3_D2_PT_2 + ); + CLK_SCALE_3_D2_1186 : X_OR3 + port map ( + I0 => CLK_SCALE_3_D2_PT_0, + I1 => CLK_SCALE_3_D2_PT_1, + I2 => CLK_SCALE_3_D2_PT_2, + O => CLK_SCALE_3_D2 + ); + CLK_SCALE_4_Q_1187 : X_BUF + port map ( + I => CLK_SCALE_4_Q, + O => CLK_SCALE(4) + ); + CLK_SCALE_4_Q_1188 : X_BUF + port map ( + I => CLK_SCALE_4_D, + O => CLK_SCALE_4_Q + ); + CLK_SCALE_4_D_1189 : X_XOR2 + port map ( + I0 => CLK_SCALE_4_D1, + I1 => CLK_SCALE_4_D2, + O => CLK_SCALE_4_D + ); + CLK_SCALE_4_D1_1190 : X_ZERO + port map ( + O => CLK_SCALE_4_D1 + ); + CLK_SCALE_4_D2_PT_0_1191 : X_AND3 + port map ( + I0 => NlwInverterSignal_CLK_SCALE_4_D2_PT_0_IN0, + I1 => LOAD_PRESCALER_IBUF, + I2 => CCLK_PRESCALER_4_IBUF, + O => CLK_SCALE_4_D2_PT_0 + ); + CLK_SCALE_4_D2_PT_1_1192 : X_AND3 + port map ( + I0 => NlwInverterSignal_CLK_SCALE_4_D2_PT_1_IN0, + I1 => NlwInverterSignal_CLK_SCALE_4_D2_PT_1_IN1, + I2 => CLK_SCALE(4), + O => CLK_SCALE_4_D2_PT_1 + ); + CLK_SCALE_4_D2_PT_2_1193 : X_AND3 + port map ( + I0 => NlwInverterSignal_CLK_SCALE_4_D2_PT_2_IN0, + I1 => CLK_SCALE(4), + I2 => CCLK_PRESCALER_4_IBUF, + O => CLK_SCALE_4_D2_PT_2 + ); + CLK_SCALE_4_D2_1194 : X_OR3 + port map ( + I0 => CLK_SCALE_4_D2_PT_0, + I1 => CLK_SCALE_4_D2_PT_1, + I2 => CLK_SCALE_4_D2_PT_2, + O => CLK_SCALE_4_D2 + ); + CLK_SCALE_5_Q_1195 : X_BUF + port map ( + I => CLK_SCALE_5_Q, + O => CLK_SCALE(5) + ); + CLK_SCALE_5_Q_1196 : X_BUF + port map ( + I => CLK_SCALE_5_D, + O => CLK_SCALE_5_Q + ); + CLK_SCALE_5_D_1197 : X_XOR2 + port map ( + I0 => CLK_SCALE_5_D1, + I1 => CLK_SCALE_5_D2, + O => CLK_SCALE_5_D + ); + CLK_SCALE_5_D1_1198 : X_ZERO + port map ( + O => CLK_SCALE_5_D1 + ); + CLK_SCALE_5_D2_PT_0_1199 : X_AND3 + port map ( + I0 => NlwInverterSignal_CLK_SCALE_5_D2_PT_0_IN0, + I1 => LOAD_PRESCALER_IBUF, + I2 => CCLK_PRESCALER_5_IBUF, + O => CLK_SCALE_5_D2_PT_0 + ); + CLK_SCALE_5_D2_PT_1_1200 : X_AND3 + port map ( + I0 => NlwInverterSignal_CLK_SCALE_5_D2_PT_1_IN0, + I1 => NlwInverterSignal_CLK_SCALE_5_D2_PT_1_IN1, + I2 => CLK_SCALE(5), + O => CLK_SCALE_5_D2_PT_1 + ); + CLK_SCALE_5_D2_PT_2_1201 : X_AND3 + port map ( + I0 => NlwInverterSignal_CLK_SCALE_5_D2_PT_2_IN0, + I1 => CLK_SCALE(5), + I2 => CCLK_PRESCALER_5_IBUF, + O => CLK_SCALE_5_D2_PT_2 + ); + CLK_SCALE_5_D2_1202 : X_OR3 + port map ( + I0 => CLK_SCALE_5_D2_PT_0, + I1 => CLK_SCALE_5_D2_PT_1, + I2 => CLK_SCALE_5_D2_PT_2, + O => CLK_SCALE_5_D2 + ); + tempID_0_Q_1203 : X_BUF + port map ( + I => tempID_0_Q, + O => tempID(0) + ); + tempID_0_tsimcreated_xor_Q_1204 : X_XOR2 + port map ( + I0 => tempID_0_D, + I1 => tempID_0_Q, + O => tempID_0_tsimcreated_xor_Q + ); + tempID_0_REG : X_FF + port map ( + I => tempID_0_tsimcreated_xor_Q, + CE => Vcc, + CLK => tempID_0_CLKF, + SET => Gnd, + RST => PRLD, + O => tempID_0_Q + ); + tempID_0_D_1205 : X_XOR2 + port map ( + I0 => tempID_0_D1, + I1 => tempID_0_D2, + O => tempID_0_D + ); + tempID_0_D1_1206 : X_ZERO + port map ( + O => tempID_0_D1 + ); + tempID_0_D2_PT_0_1207 : X_AND16 + port map ( + I0 => NlwInverterSignal_tempID_0_D2_PT_0_IN0, + I1 => NlwInverterSignal_tempID_0_D2_PT_0_IN1, + I2 => buf_depth(0), + I3 => NlwInverterSignal_tempID_0_D2_PT_0_IN3, + I4 => NlwInverterSignal_tempID_0_D2_PT_0_IN4, + I5 => NlwInverterSignal_tempID_0_D2_PT_0_IN5, + I6 => NlwInverterSignal_tempID_0_D2_PT_0_IN6, + I7 => NlwInverterSignal_tempID_0_D2_PT_0_IN7, + I8 => SHIFT_EN, + I9 => readBufId(0), + I10 => NlwInverterSignal_tempID_0_D2_PT_0_IN10, + I11 => Vcc, + I12 => Vcc, + I13 => Vcc, + I14 => Vcc, + I15 => Vcc, + O => tempID_0_D2_PT_0 + ); + tempID_0_D2_PT_1_1208 : X_AND16 + port map ( + I0 => NlwInverterSignal_tempID_0_D2_PT_1_IN0, + I1 => NlwInverterSignal_tempID_0_D2_PT_1_IN1, + I2 => buf_depth(0), + I3 => NlwInverterSignal_tempID_0_D2_PT_1_IN3, + I4 => NlwInverterSignal_tempID_0_D2_PT_1_IN4, + I5 => NlwInverterSignal_tempID_0_D2_PT_1_IN5, + I6 => NlwInverterSignal_tempID_0_D2_PT_1_IN6, + I7 => NlwInverterSignal_tempID_0_D2_PT_1_IN7, + I8 => SHIFT_EN, + I9 => NlwInverterSignal_tempID_0_D2_PT_1_IN9, + I10 => tempID(0), + I11 => Vcc, + I12 => Vcc, + I13 => Vcc, + I14 => Vcc, + I15 => Vcc, + O => tempID_0_D2_PT_1 + ); + tempID_0_D2_PT_2_1209 : X_AND16 + port map ( + I0 => NlwInverterSignal_tempID_0_D2_PT_2_IN0, + I1 => NlwInverterSignal_tempID_0_D2_PT_2_IN1, + I2 => buf_depth(1), + I3 => NlwInverterSignal_tempID_0_D2_PT_2_IN3, + I4 => NlwInverterSignal_tempID_0_D2_PT_2_IN4, + I5 => NlwInverterSignal_tempID_0_D2_PT_2_IN5, + I6 => NlwInverterSignal_tempID_0_D2_PT_2_IN6, + I7 => NlwInverterSignal_tempID_0_D2_PT_2_IN7, + I8 => SHIFT_EN, + I9 => readBufId(0), + I10 => NlwInverterSignal_tempID_0_D2_PT_2_IN10, + I11 => Vcc, + I12 => Vcc, + I13 => Vcc, + I14 => Vcc, + I15 => Vcc, + O => tempID_0_D2_PT_2 + ); + tempID_0_D2_PT_3_1210 : X_AND16 + port map ( + I0 => NlwInverterSignal_tempID_0_D2_PT_3_IN0, + I1 => NlwInverterSignal_tempID_0_D2_PT_3_IN1, + I2 => buf_depth(1), + I3 => NlwInverterSignal_tempID_0_D2_PT_3_IN3, + I4 => NlwInverterSignal_tempID_0_D2_PT_3_IN4, + I5 => NlwInverterSignal_tempID_0_D2_PT_3_IN5, + I6 => NlwInverterSignal_tempID_0_D2_PT_3_IN6, + I7 => NlwInverterSignal_tempID_0_D2_PT_3_IN7, + I8 => SHIFT_EN, + I9 => NlwInverterSignal_tempID_0_D2_PT_3_IN9, + I10 => tempID(0), + I11 => Vcc, + I12 => Vcc, + I13 => Vcc, + I14 => Vcc, + I15 => Vcc, + O => tempID_0_D2_PT_3 + ); + tempID_0_D2_1211 : X_OR4 + port map ( + I0 => tempID_0_D2_PT_0, + I1 => tempID_0_D2_PT_1, + I2 => tempID_0_D2_PT_2, + I3 => tempID_0_D2_PT_3, + O => tempID_0_D2 + ); + tempID_0_CLKF_1212 : X_AND2 + port map ( + I0 => NlwInverterSignal_tempID_0_CLKF_IN0, + I1 => NlwInverterSignal_tempID_0_CLKF_IN1, + O => tempID_0_CLKF + ); + BUF_IS_EMPTY_OBUF_Q_1213 : X_BUF + port map ( + I => BUF_IS_EMPTY_OBUF_Q_0, + O => BUF_IS_EMPTY_OBUF_Q + ); + BUF_IS_EMPTY_OBUF_EXP_1214 : X_BUF + port map ( + I => BUF_IS_EMPTY_OBUF_EXP_tsimrenamed_net_Q, + O => BUF_IS_EMPTY_OBUF_EXP + ); + BUF_IS_EMPTY_OBUF_Q_1215 : X_BUF + port map ( + I => BUF_IS_EMPTY_OBUF_D, + O => BUF_IS_EMPTY_OBUF_Q_0 + ); + BUF_IS_EMPTY_OBUF_D_1216 : X_XOR2 + port map ( + I0 => BUF_IS_EMPTY_OBUF_D1, + I1 => BUF_IS_EMPTY_OBUF_D2, + O => BUF_IS_EMPTY_OBUF_D + ); + BUF_IS_EMPTY_OBUF_D1_1217 : X_ZERO + port map ( + O => BUF_IS_EMPTY_OBUF_D1 + ); + BUF_IS_EMPTY_OBUF_D2_1218 : X_AND7 + port map ( + I0 => buf_depth(0), + I1 => NlwInverterSignal_BUF_IS_EMPTY_OBUF_D2_IN1, + I2 => NlwInverterSignal_BUF_IS_EMPTY_OBUF_D2_IN2, + I3 => NlwInverterSignal_BUF_IS_EMPTY_OBUF_D2_IN3, + I4 => NlwInverterSignal_BUF_IS_EMPTY_OBUF_D2_IN4, + I5 => NlwInverterSignal_BUF_IS_EMPTY_OBUF_D2_IN5, + I6 => NlwInverterSignal_BUF_IS_EMPTY_OBUF_D2_IN6, + O => BUF_IS_EMPTY_OBUF_D2 + ); + BUF_IS_EMPTY_OBUF_EXP_PT_0_1219 : X_AND2 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => LOAD_SREG_IBUF, + O => BUF_IS_EMPTY_OBUF_EXP_PT_0 + ); + BUF_IS_EMPTY_OBUF_EXP_PT_1_1220 : X_AND2 + port map ( + I0 => SHIFT_CNT(1), + I1 => SHIFT_CNT(1), + O => BUF_IS_EMPTY_OBUF_EXP_PT_1 + ); + BUF_IS_EMPTY_OBUF_EXP_PT_2_1221 : X_AND2 + port map ( + I0 => NlwInverterSignal_BUF_IS_EMPTY_OBUF_EXP_PT_2_IN0, + I1 => NlwInverterSignal_BUF_IS_EMPTY_OBUF_EXP_PT_2_IN1, + O => BUF_IS_EMPTY_OBUF_EXP_PT_2 + ); + BUF_IS_EMPTY_OBUF_EXP_PT_3_1222 : X_AND5 + port map ( + I0 => NlwInverterSignal_BUF_IS_EMPTY_OBUF_EXP_PT_3_IN0, + I1 => NlwInverterSignal_BUF_IS_EMPTY_OBUF_EXP_PT_3_IN1, + I2 => NlwInverterSignal_BUF_IS_EMPTY_OBUF_EXP_PT_3_IN2, + I3 => NlwInverterSignal_BUF_IS_EMPTY_OBUF_EXP_PT_3_IN3, + I4 => NlwInverterSignal_BUF_IS_EMPTY_OBUF_EXP_PT_3_IN4, + O => BUF_IS_EMPTY_OBUF_EXP_PT_3 + ); + BUF_IS_EMPTY_OBUF_EXP_tsimrenamed_net_Q_1223 : X_OR4 + port map ( + I0 => BUF_IS_EMPTY_OBUF_EXP_PT_0, + I1 => BUF_IS_EMPTY_OBUF_EXP_PT_1, + I2 => BUF_IS_EMPTY_OBUF_EXP_PT_2, + I3 => BUF_IS_EMPTY_OBUF_EXP_PT_3, + O => BUF_IS_EMPTY_OBUF_EXP_tsimrenamed_net_Q + ); + SHIFT_EN_1224 : X_BUF + port map ( + I => SHIFT_EN_Q, + O => SHIFT_EN + ); + SHIFT_EN_EXP_1225 : X_BUF + port map ( + I => SHIFT_EN_EXP_tsimrenamed_net_Q, + O => SHIFT_EN_EXP + ); + SHIFT_EN_tsimcreated_set_and_noreset_Q_1226 : X_AND2 + port map ( + I0 => NlwInverterSignal_SHIFT_EN_tsimcreated_set_and_noreset_IN0, + I1 => SHIFT_EN_SETF, + O => SHIFT_EN_tsimcreated_set_and_noreset_Q + ); + SHIFT_EN_tsimcreated_prld_Q_1227 : X_OR2 + port map ( + I0 => SHIFT_EN_RSTF, + I1 => PRLD, + O => SHIFT_EN_tsimcreated_prld_Q + ); + SHIFT_EN_REG : X_FF + port map ( + I => SHIFT_EN_D, + CE => Vcc, + CLK => SHIFT_EN_CLKF, + SET => SHIFT_EN_tsimcreated_set_and_noreset_Q, + RST => SHIFT_EN_tsimcreated_prld_Q, + O => SHIFT_EN_Q + ); + SHIFT_EN_D_1228 : X_XOR2 + port map ( + I0 => SHIFT_EN_D1, + I1 => SHIFT_EN_D2, + O => SHIFT_EN_D + ); + SHIFT_EN_D1_1229 : X_ZERO + port map ( + O => SHIFT_EN_D1 + ); + SHIFT_EN_D2_1230 : X_ZERO + port map ( + O => SHIFT_EN_D2 + ); + SHIFT_EN_CLKF_1231 : X_ZERO + port map ( + O => SHIFT_EN_CLKF + ); + SHIFT_EN_SETF_1232 : X_AND3 + port map ( + I0 => NlwInverterSignal_SHIFT_EN_SETF_IN0, + I1 => NlwInverterSignal_SHIFT_EN_SETF_IN1, + I2 => state(1), + O => SHIFT_EN_SETF + ); + SHIFT_EN_RSTF_1233 : X_AND2 + port map ( + I0 => NlwInverterSignal_SHIFT_EN_RSTF_IN0, + I1 => NlwInverterSignal_SHIFT_EN_RSTF_IN1, + O => SHIFT_EN_RSTF + ); + SHIFT_EN_EXP_PT_0_1234 : X_AND7 + port map ( + I0 => NlwInverterSignal_SHIFT_EN_EXP_PT_0_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_SHIFT_EN_EXP_PT_0_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_SHIFT_EN_EXP_PT_0_IN4, + I5 => DIN_11_IBUF, + I6 => NlwInverterSignal_SHIFT_EN_EXP_PT_0_IN6, + O => SHIFT_EN_EXP_PT_0 + ); + SHIFT_EN_EXP_PT_1_1235 : X_AND7 + port map ( + I0 => NlwInverterSignal_SHIFT_EN_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_SHIFT_EN_EXP_PT_1_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_SHIFT_EN_EXP_PT_1_IN4, + I5 => NlwInverterSignal_SHIFT_EN_EXP_PT_1_IN5, + I6 => REG_0_11, + O => SHIFT_EN_EXP_PT_1 + ); + SHIFT_EN_EXP_tsimrenamed_net_Q_1236 : X_OR2 + port map ( + I0 => SHIFT_EN_EXP_PT_0, + I1 => SHIFT_EN_EXP_PT_1, + O => SHIFT_EN_EXP_tsimrenamed_net_Q + ); + next_state_0_Q_1237 : X_BUF + port map ( + I => next_state_0_Q, + O => next_state(0) + ); + next_state_0_tsimcreated_set_and_noreset_Q_1238 : X_AND2 + port map ( + I0 => NlwInverterSignal_next_state_0_tsimcreated_set_and_noreset_IN0, + I1 => next_state_0_SETF, + O => next_state_0_tsimcreated_set_and_noreset_Q + ); + next_state_0_tsimcreated_prld_Q_1239 : X_OR2 + port map ( + I0 => next_state_0_RSTF, + I1 => PRLD, + O => next_state_0_tsimcreated_prld_Q + ); + next_state_0_REG : X_FF + port map ( + I => next_state_0_D, + CE => Vcc, + CLK => next_state_0_CLKF, + SET => next_state_0_tsimcreated_set_and_noreset_Q, + RST => next_state_0_tsimcreated_prld_Q, + O => next_state_0_Q + ); + next_state_0_D_1240 : X_XOR2 + port map ( + I0 => next_state_0_D1, + I1 => next_state_0_D2, + O => next_state_0_D + ); + next_state_0_D1_1241 : X_ZERO + port map ( + O => next_state_0_D1 + ); + next_state_0_D2_1242 : X_ZERO + port map ( + O => next_state_0_D2 + ); + next_state_0_CLKF_1243 : X_ZERO + port map ( + O => next_state_0_CLKF + ); + next_state_0_SETF_1244 : X_AND4 + port map ( + I0 => NlwInverterSignal_next_state_0_SETF_IN0, + I1 => NlwInverterSignal_next_state_0_SETF_IN1, + I2 => NlwInverterSignal_next_state_0_SETF_IN2, + I3 => NlwInverterSignal_next_state_0_SETF_IN3, + O => next_state_0_SETF + ); + next_state_0_RSTF_1245 : X_AND2 + port map ( + I0 => next_state_0_next_state_0_RSTF_UIM, + I1 => next_state_0_next_state_0_RSTF_UIM, + O => next_state_0_RSTF + ); + next_state_1_Q_1246 : X_BUF + port map ( + I => next_state_1_Q, + O => next_state(1) + ); + next_state_1_tsimcreated_set_and_noreset_Q_1247 : X_AND2 + port map ( + I0 => NlwInverterSignal_next_state_1_tsimcreated_set_and_noreset_IN0, + I1 => next_state_1_SETF, + O => next_state_1_tsimcreated_set_and_noreset_Q + ); + next_state_1_tsimcreated_prld_Q_1248 : X_OR2 + port map ( + I0 => next_state_1_RSTF, + I1 => PRLD, + O => next_state_1_tsimcreated_prld_Q + ); + next_state_1_REG : X_FF + port map ( + I => next_state_1_D, + CE => Vcc, + CLK => next_state_1_CLKF, + SET => next_state_1_tsimcreated_set_and_noreset_Q, + RST => next_state_1_tsimcreated_prld_Q, + O => next_state_1_Q + ); + next_state_1_D_1249 : X_XOR2 + port map ( + I0 => next_state_1_D1, + I1 => next_state_1_D2, + O => next_state_1_D + ); + next_state_1_D1_1250 : X_ZERO + port map ( + O => next_state_1_D1 + ); + next_state_1_D2_1251 : X_ZERO + port map ( + O => next_state_1_D2 + ); + next_state_1_CLKF_1252 : X_ZERO + port map ( + O => next_state_1_CLKF + ); + next_state_1_SETF_1253 : X_AND2 + port map ( + I0 => SHIFT_EN_SHIFT_EN_RSTF_INT_UIM, + I1 => NlwInverterSignal_next_state_1_SETF_IN1, + O => next_state_1_SETF + ); + next_state_1_RSTF_1254 : X_AND2 + port map ( + I0 => next_state_1_next_state_1_RSTF_UIM, + I1 => next_state_1_next_state_1_RSTF_UIM, + O => next_state_1_RSTF + ); + CCLK_OBUF_1255 : X_BUF + port map ( + I => CCLK_OBUF_Q, + O => CCLK_OBUF + ); + CCLK_OBUF_EXP_1256 : X_BUF + port map ( + I => CCLK_OBUF_EXP_tsimrenamed_net_Q, + O => CCLK_OBUF_EXP + ); + CCLK_OBUF_Q_1257 : X_BUF + port map ( + I => CCLK_OBUF_D, + O => CCLK_OBUF_Q + ); + CCLK_OBUF_D_1258 : X_XOR2 + port map ( + I0 => NlwInverterSignal_CCLK_OBUF_D_IN0, + I1 => CCLK_OBUF_D2, + O => CCLK_OBUF_D + ); + CCLK_OBUF_D1_1259 : X_ZERO + port map ( + O => CCLK_OBUF_D1 + ); + CCLK_OBUF_D2_PT_0_1260 : X_AND2 + port map ( + I0 => EXP64_EXP, + I1 => EXP64_EXP, + O => CCLK_OBUF_D2_PT_0 + ); + CCLK_OBUF_D2_PT_1_1261 : X_AND3 + port map ( + I0 => NlwInverterSignal_CCLK_OBUF_D2_PT_1_IN0, + I1 => NlwInverterSignal_CCLK_OBUF_D2_PT_1_IN1, + I2 => state(0), + O => CCLK_OBUF_D2_PT_1 + ); + CCLK_OBUF_D2_1262 : X_OR2 + port map ( + I0 => CCLK_OBUF_D2_PT_0, + I1 => CCLK_OBUF_D2_PT_1, + O => CCLK_OBUF_D2 + ); + CCLK_OBUF_EXP_PT_0_1263 : X_AND6 + port map ( + I0 => NlwInverterSignal_CCLK_OBUF_EXP_PT_0_IN0, + I1 => NlwInverterSignal_CCLK_OBUF_EXP_PT_0_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_CCLK_OBUF_EXP_PT_0_IN3, + I4 => REG_0_12, + I5 => NlwInverterSignal_CCLK_OBUF_EXP_PT_0_IN5, + O => CCLK_OBUF_EXP_PT_0 + ); + CCLK_OBUF_EXP_PT_1_1264 : X_AND6 + port map ( + I0 => NlwInverterSignal_CCLK_OBUF_EXP_PT_1_IN0, + I1 => NlwInverterSignal_CCLK_OBUF_EXP_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_CCLK_OBUF_EXP_PT_1_IN3, + I4 => NlwInverterSignal_CCLK_OBUF_EXP_PT_1_IN4, + I5 => REG_0_13, + O => CCLK_OBUF_EXP_PT_1 + ); + CCLK_OBUF_EXP_PT_2_1265 : X_AND7 + port map ( + I0 => NlwInverterSignal_CCLK_OBUF_EXP_PT_2_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_CCLK_OBUF_EXP_PT_2_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_CCLK_OBUF_EXP_PT_2_IN4, + I5 => DIN_13_IBUF, + I6 => NlwInverterSignal_CCLK_OBUF_EXP_PT_2_IN6, + O => CCLK_OBUF_EXP_PT_2 + ); + CCLK_OBUF_EXP_PT_3_1266 : X_AND7 + port map ( + I0 => NlwInverterSignal_CCLK_OBUF_EXP_PT_3_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_CCLK_OBUF_EXP_PT_3_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_CCLK_OBUF_EXP_PT_3_IN4, + I5 => NlwInverterSignal_CCLK_OBUF_EXP_PT_3_IN5, + I6 => REG_0_13, + O => CCLK_OBUF_EXP_PT_3 + ); + CCLK_OBUF_EXP_tsimrenamed_net_Q_1267 : X_OR4 + port map ( + I0 => CCLK_OBUF_EXP_PT_0, + I1 => CCLK_OBUF_EXP_PT_1, + I2 => CCLK_OBUF_EXP_PT_2, + I3 => CCLK_OBUF_EXP_PT_3, + O => CCLK_OBUF_EXP_tsimrenamed_net_Q + ); + buf_depth_0_buf_depth_0_RSTF_UIM_1268 : X_BUF + port map ( + I => buf_depth_0_buf_depth_0_RSTF_Q, + O => buf_depth_0_buf_depth_0_RSTF_UIM + ); + buf_depth_0_buf_depth_0_RSTF_EXP_1269 : X_BUF + port map ( + I => buf_depth_0_buf_depth_0_RSTF_EXP_tsimrenamed_net_Q, + O => buf_depth_0_buf_depth_0_RSTF_EXP + ); + buf_depth_0_buf_depth_0_RSTF_Q_1270 : X_BUF + port map ( + I => buf_depth_0_buf_depth_0_RSTF_D, + O => buf_depth_0_buf_depth_0_RSTF_Q + ); + buf_depth_0_buf_depth_0_RSTF_D_1271 : X_XOR2 + port map ( + I0 => buf_depth_0_buf_depth_0_RSTF_D1, + I1 => buf_depth_0_buf_depth_0_RSTF_D2, + O => buf_depth_0_buf_depth_0_RSTF_D + ); + buf_depth_0_buf_depth_0_RSTF_D1_1272 : X_ZERO + port map ( + O => buf_depth_0_buf_depth_0_RSTF_D1 + ); + buf_depth_0_buf_depth_0_RSTF_D2_PT_0_1273 : X_AND2 + port map ( + I0 => RES_IBUF, + I1 => RES_IBUF, + O => buf_depth_0_buf_depth_0_RSTF_D2_PT_0 + ); + buf_depth_0_buf_depth_0_RSTF_D2_PT_1_1274 : X_AND2 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => buf_depth(0), + O => buf_depth_0_buf_depth_0_RSTF_D2_PT_1 + ); + buf_depth_0_buf_depth_0_RSTF_D2_1275 : X_OR2 + port map ( + I0 => buf_depth_0_buf_depth_0_RSTF_D2_PT_0, + I1 => buf_depth_0_buf_depth_0_RSTF_D2_PT_1, + O => buf_depth_0_buf_depth_0_RSTF_D2 + ); + buf_depth_0_buf_depth_0_RSTF_EXP_PT_0_1276 : X_AND6 + port map ( + I0 => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_0_IN0, + I1 => buf_depth(0), + I2 => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_0_IN2, + I3 => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_0_IN3, + I4 => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_0_IN4, + I5 => SHIFT_EN, + O => buf_depth_0_buf_depth_0_RSTF_EXP_PT_0 + ); + buf_depth_0_buf_depth_0_RSTF_EXP_PT_1_1277 : X_AND6 + port map ( + I0 => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_1_IN0, + I1 => buf_depth(1), + I2 => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_1_IN2, + I3 => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_1_IN3, + I4 => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_1_IN4, + I5 => SHIFT_EN, + O => buf_depth_0_buf_depth_0_RSTF_EXP_PT_1 + ); + buf_depth_0_buf_depth_0_RSTF_EXP_PT_2_1278 : X_AND6 + port map ( + I0 => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_2_IN0, + I1 => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_2_IN1, + I2 => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_2_IN2, + I3 => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_2_IN3, + I4 => SHIFT_CNT(4), + I5 => SHIFT_EN, + O => buf_depth_0_buf_depth_0_RSTF_EXP_PT_2 + ); + buf_depth_0_buf_depth_0_RSTF_EXP_tsimrenamed_net_Q_1279 : X_OR3 + port map ( + I0 => buf_depth_0_buf_depth_0_RSTF_EXP_PT_0, + I1 => buf_depth_0_buf_depth_0_RSTF_EXP_PT_1, + I2 => buf_depth_0_buf_depth_0_RSTF_EXP_PT_2, + O => buf_depth_0_buf_depth_0_RSTF_EXP_tsimrenamed_net_Q + ); + buf_depth_1_buf_depth_1_RSTF_UIM_1280 : X_BUF + port map ( + I => buf_depth_1_buf_depth_1_RSTF_Q, + O => buf_depth_1_buf_depth_1_RSTF_UIM + ); + buf_depth_1_buf_depth_1_RSTF_Q_1281 : X_BUF + port map ( + I => buf_depth_1_buf_depth_1_RSTF_D, + O => buf_depth_1_buf_depth_1_RSTF_Q + ); + buf_depth_1_buf_depth_1_RSTF_D_1282 : X_XOR2 + port map ( + I0 => buf_depth_1_buf_depth_1_RSTF_D1, + I1 => buf_depth_1_buf_depth_1_RSTF_D2, + O => buf_depth_1_buf_depth_1_RSTF_D + ); + buf_depth_1_buf_depth_1_RSTF_D1_1283 : X_ZERO + port map ( + O => buf_depth_1_buf_depth_1_RSTF_D1 + ); + buf_depth_1_buf_depth_1_RSTF_D2_PT_0_1284 : X_AND2 + port map ( + I0 => RES_IBUF, + I1 => RES_IBUF, + O => buf_depth_1_buf_depth_1_RSTF_D2_PT_0 + ); + buf_depth_1_buf_depth_1_RSTF_D2_PT_1_1285 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => buf_depth(0), + I2 => buf_depth(1), + O => buf_depth_1_buf_depth_1_RSTF_D2_PT_1 + ); + buf_depth_1_buf_depth_1_RSTF_D2_PT_2_1286 : X_AND3 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => NlwInverterSignal_buf_depth_1_buf_depth_1_RSTF_D2_PT_2_IN1, + I2 => NlwInverterSignal_buf_depth_1_buf_depth_1_RSTF_D2_PT_2_IN2, + O => buf_depth_1_buf_depth_1_RSTF_D2_PT_2 + ); + buf_depth_1_buf_depth_1_RSTF_D2_1287 : X_OR3 + port map ( + I0 => buf_depth_1_buf_depth_1_RSTF_D2_PT_0, + I1 => buf_depth_1_buf_depth_1_RSTF_D2_PT_1, + I2 => buf_depth_1_buf_depth_1_RSTF_D2_PT_2, + O => buf_depth_1_buf_depth_1_RSTF_D2 + ); + SHIFT_EN_SHIFT_EN_RSTF_INT_UIM_1288 : X_BUF + port map ( + I => SHIFT_EN_SHIFT_EN_RSTF_INT_Q, + O => SHIFT_EN_SHIFT_EN_RSTF_INT_UIM + ); + SHIFT_EN_SHIFT_EN_RSTF_INT_Q_1289 : X_BUF + port map ( + I => SHIFT_EN_SHIFT_EN_RSTF_INT_D, + O => SHIFT_EN_SHIFT_EN_RSTF_INT_Q + ); + SHIFT_EN_SHIFT_EN_RSTF_INT_D_1290 : X_XOR2 + port map ( + I0 => SHIFT_EN_SHIFT_EN_RSTF_INT_D1, + I1 => SHIFT_EN_SHIFT_EN_RSTF_INT_D2, + O => SHIFT_EN_SHIFT_EN_RSTF_INT_D + ); + SHIFT_EN_SHIFT_EN_RSTF_INT_D1_1291 : X_ZERO + port map ( + O => SHIFT_EN_SHIFT_EN_RSTF_INT_D1 + ); + SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_0_1292 : X_AND3 + port map ( + I0 => NlwInverterSignal_SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_0_IN0, + I1 => state(0), + I2 => NlwInverterSignal_SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_0_IN2, + O => SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_0 + ); + SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_1_1293 : X_AND3 + port map ( + I0 => NlwInverterSignal_SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_1_IN0, + I1 => NlwInverterSignal_SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_1_IN1, + I2 => state(1), + O => SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_1 + ); + SHIFT_EN_SHIFT_EN_RSTF_INT_D2_1294 : X_OR2 + port map ( + I0 => SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_0, + I1 => SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_1, + O => SHIFT_EN_SHIFT_EN_RSTF_INT_D2 + ); + Q_OpTx_FX_DC_19_UIM_1295 : X_BUF + port map ( + I => Q_OpTx_FX_DC_19_Q, + O => Q_OpTx_FX_DC_19_UIM + ); + Q_OpTx_FX_DC_19_Q_1296 : X_BUF + port map ( + I => Q_OpTx_FX_DC_19_D, + O => Q_OpTx_FX_DC_19_Q + ); + Q_OpTx_FX_DC_19_D_1297 : X_XOR2 + port map ( + I0 => Q_OpTx_FX_DC_19_D1, + I1 => Q_OpTx_FX_DC_19_D2, + O => Q_OpTx_FX_DC_19_D + ); + Q_OpTx_FX_DC_19_D1_1298 : X_ZERO + port map ( + O => Q_OpTx_FX_DC_19_D1 + ); + Q_OpTx_FX_DC_19_D2_PT_0_1299 : X_AND2 + port map ( + I0 => DONE_IBUF, + I1 => DONE_IBUF, + O => Q_OpTx_FX_DC_19_D2_PT_0 + ); + Q_OpTx_FX_DC_19_D2_PT_1_1300 : X_AND7 + port map ( + I0 => buf_depth(0), + I1 => NlwInverterSignal_OpTx_FX_DC_19_D2_PT_1_IN1, + I2 => NlwInverterSignal_OpTx_FX_DC_19_D2_PT_1_IN2, + I3 => NlwInverterSignal_OpTx_FX_DC_19_D2_PT_1_IN3, + I4 => NlwInverterSignal_OpTx_FX_DC_19_D2_PT_1_IN4, + I5 => NlwInverterSignal_OpTx_FX_DC_19_D2_PT_1_IN5, + I6 => NlwInverterSignal_OpTx_FX_DC_19_D2_PT_1_IN6, + O => Q_OpTx_FX_DC_19_D2_PT_1 + ); + Q_OpTx_FX_DC_19_D2_1301 : X_OR2 + port map ( + I0 => Q_OpTx_FX_DC_19_D2_PT_0, + I1 => Q_OpTx_FX_DC_19_D2_PT_1, + O => Q_OpTx_FX_DC_19_D2 + ); + next_state_0_next_state_0_RSTF_UIM_1302 : X_BUF + port map ( + I => next_state_0_next_state_0_RSTF_Q, + O => next_state_0_next_state_0_RSTF_UIM + ); + next_state_0_next_state_0_RSTF_Q_1303 : X_BUF + port map ( + I => next_state_0_next_state_0_RSTF_D, + O => next_state_0_next_state_0_RSTF_Q + ); + next_state_0_next_state_0_RSTF_D_1304 : X_XOR2 + port map ( + I0 => next_state_0_next_state_0_RSTF_D1, + I1 => next_state_0_next_state_0_RSTF_D2, + O => next_state_0_next_state_0_RSTF_D + ); + next_state_0_next_state_0_RSTF_D1_1305 : X_ZERO + port map ( + O => next_state_0_next_state_0_RSTF_D1 + ); + next_state_0_next_state_0_RSTF_D2_PT_0_1306 : X_AND2 + port map ( + I0 => NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_0_IN0, + I1 => DONE_IBUF, + O => next_state_0_next_state_0_RSTF_D2_PT_0 + ); + next_state_0_next_state_0_RSTF_D2_PT_1_1307 : X_AND2 + port map ( + I0 => NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_1_IN0, + I1 => state(0), + O => next_state_0_next_state_0_RSTF_D2_PT_1 + ); + next_state_0_next_state_0_RSTF_D2_PT_2_1308 : X_AND2 + port map ( + I0 => NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_2_IN0, + I1 => state(1), + O => next_state_0_next_state_0_RSTF_D2_PT_2 + ); + next_state_0_next_state_0_RSTF_D2_PT_3_1309 : X_AND8 + port map ( + I0 => NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_3_IN0, + I1 => buf_depth(0), + I2 => NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_3_IN2, + I3 => NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_3_IN3, + I4 => NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_3_IN4, + I5 => NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_3_IN5, + I6 => NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_3_IN6, + I7 => NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_3_IN7, + O => next_state_0_next_state_0_RSTF_D2_PT_3 + ); + next_state_0_next_state_0_RSTF_D2_1310 : X_OR4 + port map ( + I0 => next_state_0_next_state_0_RSTF_D2_PT_0, + I1 => next_state_0_next_state_0_RSTF_D2_PT_1, + I2 => next_state_0_next_state_0_RSTF_D2_PT_2, + I3 => next_state_0_next_state_0_RSTF_D2_PT_3, + O => next_state_0_next_state_0_RSTF_D2 + ); + next_state_1_next_state_1_RSTF_UIM_1311 : X_BUF + port map ( + I => next_state_1_next_state_1_RSTF_Q, + O => next_state_1_next_state_1_RSTF_UIM + ); + next_state_1_next_state_1_RSTF_Q_1312 : X_BUF + port map ( + I => next_state_1_next_state_1_RSTF_D, + O => next_state_1_next_state_1_RSTF_Q + ); + next_state_1_next_state_1_RSTF_D_1313 : X_XOR2 + port map ( + I0 => next_state_1_next_state_1_RSTF_D1, + I1 => next_state_1_next_state_1_RSTF_D2, + O => next_state_1_next_state_1_RSTF_D + ); + next_state_1_next_state_1_RSTF_D1_1314 : X_ZERO + port map ( + O => next_state_1_next_state_1_RSTF_D1 + ); + next_state_1_next_state_1_RSTF_D2_PT_0_1315 : X_AND3 + port map ( + I0 => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_0_IN0, + I1 => DONE_IBUF, + I2 => state(1), + O => next_state_1_next_state_1_RSTF_D2_PT_0 + ); + next_state_1_next_state_1_RSTF_D2_PT_1_1316 : X_AND3 + port map ( + I0 => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_1_IN0, + I1 => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_1_IN1, + I2 => state(1), + O => next_state_1_next_state_1_RSTF_D2_PT_1 + ); + next_state_1_next_state_1_RSTF_D2_PT_2_1317 : X_AND3 + port map ( + I0 => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_2_IN0, + I1 => state(0), + I2 => state(1), + O => next_state_1_next_state_1_RSTF_D2_PT_2 + ); + next_state_1_next_state_1_RSTF_D2_PT_3_1318 : X_AND3 + port map ( + I0 => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_3_IN0, + I1 => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_3_IN1, + I2 => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_3_IN2, + O => next_state_1_next_state_1_RSTF_D2_PT_3 + ); + next_state_1_next_state_1_RSTF_D2_PT_4_1319 : X_AND16 + port map ( + I0 => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_4_IN0, + I1 => buf_depth(0), + I2 => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_4_IN2, + I3 => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_4_IN3, + I4 => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_4_IN4, + I5 => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_4_IN5, + I6 => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_4_IN6, + I7 => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_4_IN7, + I8 => state(1), + I9 => Vcc, + I10 => Vcc, + I11 => Vcc, + I12 => Vcc, + I13 => Vcc, + I14 => Vcc, + I15 => Vcc, + O => next_state_1_next_state_1_RSTF_D2_PT_4 + ); + next_state_1_next_state_1_RSTF_D2_1320 : X_OR5 + port map ( + I0 => next_state_1_next_state_1_RSTF_D2_PT_0, + I1 => next_state_1_next_state_1_RSTF_D2_PT_1, + I2 => next_state_1_next_state_1_RSTF_D2_PT_2, + I3 => next_state_1_next_state_1_RSTF_D2_PT_3, + I4 => next_state_1_next_state_1_RSTF_D2_PT_4, + O => next_state_1_next_state_1_RSTF_D2 + ); + EXP18_EXP_1321 : X_BUF + port map ( + I => EXP18_EXP_tsimrenamed_net_Q, + O => EXP18_EXP + ); + EXP18_EXP_PT_0_1322 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP18_EXP_PT_0_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_EXP18_EXP_PT_0_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_EXP18_EXP_PT_0_IN4, + I5 => DIN_1_IBUF, + I6 => NlwInverterSignal_EXP18_EXP_PT_0_IN6, + O => EXP18_EXP_PT_0 + ); + EXP18_EXP_PT_1_1323 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP18_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_EXP18_EXP_PT_1_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_EXP18_EXP_PT_1_IN4, + I5 => NlwInverterSignal_EXP18_EXP_PT_1_IN5, + I6 => REG_0_1, + O => EXP18_EXP_PT_1 + ); + EXP18_EXP_tsimrenamed_net_Q_1324 : X_OR2 + port map ( + I0 => EXP18_EXP_PT_0, + I1 => EXP18_EXP_PT_1, + O => EXP18_EXP_tsimrenamed_net_Q + ); + EXP19_EXP_1325 : X_BUF + port map ( + I => EXP19_EXP_tsimrenamed_net_Q, + O => EXP19_EXP + ); + EXP19_EXP_PT_0_1326 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP19_EXP_PT_0_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_EXP19_EXP_PT_0_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_EXP19_EXP_PT_0_IN4, + I5 => DIN_5_IBUF, + I6 => NlwInverterSignal_EXP19_EXP_PT_0_IN6, + O => EXP19_EXP_PT_0 + ); + EXP19_EXP_PT_1_1327 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP19_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_EXP19_EXP_PT_1_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_EXP19_EXP_PT_1_IN4, + I5 => NlwInverterSignal_EXP19_EXP_PT_1_IN5, + I6 => REG_0_5, + O => EXP19_EXP_PT_1 + ); + EXP19_EXP_tsimrenamed_net_Q_1328 : X_OR2 + port map ( + I0 => EXP19_EXP_PT_0, + I1 => EXP19_EXP_PT_1, + O => EXP19_EXP_tsimrenamed_net_Q + ); + EXP20_EXP_1329 : X_BUF + port map ( + I => EXP20_EXP_tsimrenamed_net_Q, + O => EXP20_EXP + ); + EXP20_EXP_tsimrenamed_net_Q_1330 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP20_EXP_tsimrenamed_net_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_EXP20_EXP_tsimrenamed_net_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_EXP20_EXP_tsimrenamed_net_IN4, + I5 => NlwInverterSignal_EXP20_EXP_tsimrenamed_net_IN5, + I6 => REG_0_6, + O => EXP20_EXP_tsimrenamed_net_Q + ); + EXP21_EXP_1331 : X_BUF + port map ( + I => EXP21_EXP_tsimrenamed_net_Q, + O => EXP21_EXP + ); + EXP21_EXP_tsimrenamed_net_Q_1332 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP21_EXP_tsimrenamed_net_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_EXP21_EXP_tsimrenamed_net_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_EXP21_EXP_tsimrenamed_net_IN4, + I5 => DIN_6_IBUF, + I6 => NlwInverterSignal_EXP21_EXP_tsimrenamed_net_IN6, + O => EXP21_EXP_tsimrenamed_net_Q + ); + EXP22_EXP_1333 : X_BUF + port map ( + I => EXP22_EXP_tsimrenamed_net_Q, + O => EXP22_EXP + ); + EXP22_EXP_PT_0_1334 : X_AND5 + port map ( + I0 => NlwInverterSignal_EXP22_EXP_PT_0_IN0, + I1 => NlwInverterSignal_EXP22_EXP_PT_0_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_EXP22_EXP_PT_0_IN3, + I4 => REG_0_0, + O => EXP22_EXP_PT_0 + ); + EXP22_EXP_PT_1_1335 : X_AND6 + port map ( + I0 => NlwInverterSignal_EXP22_EXP_PT_1_IN0, + I1 => NlwInverterSignal_EXP22_EXP_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_EXP22_EXP_PT_1_IN3, + I4 => NlwInverterSignal_EXP22_EXP_PT_1_IN4, + I5 => REG_0_0, + O => EXP22_EXP_PT_1 + ); + EXP22_EXP_PT_2_1336 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP22_EXP_PT_2_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_EXP22_EXP_PT_2_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_EXP22_EXP_PT_2_IN4, + I5 => DIN_0_IBUF, + I6 => NlwInverterSignal_EXP22_EXP_PT_2_IN6, + O => EXP22_EXP_PT_2 + ); + EXP22_EXP_tsimrenamed_net_Q_1337 : X_OR3 + port map ( + I0 => EXP22_EXP_PT_0, + I1 => EXP22_EXP_PT_1, + I2 => EXP22_EXP_PT_2, + O => EXP22_EXP_tsimrenamed_net_Q + ); + EXP23_EXP_1338 : X_BUF + port map ( + I => EXP23_EXP_tsimrenamed_net_Q, + O => EXP23_EXP + ); + EXP23_EXP_PT_0_1339 : X_AND6 + port map ( + I0 => NlwInverterSignal_EXP23_EXP_PT_0_IN0, + I1 => NlwInverterSignal_EXP23_EXP_PT_0_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_EXP23_EXP_PT_0_IN3, + I4 => REG_0_2, + I5 => NlwInverterSignal_EXP23_EXP_PT_0_IN5, + O => EXP23_EXP_PT_0 + ); + EXP23_EXP_PT_1_1340 : X_AND6 + port map ( + I0 => NlwInverterSignal_EXP23_EXP_PT_1_IN0, + I1 => NlwInverterSignal_EXP23_EXP_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_EXP23_EXP_PT_1_IN3, + I4 => NlwInverterSignal_EXP23_EXP_PT_1_IN4, + I5 => REG_0_3, + O => EXP23_EXP_PT_1 + ); + EXP23_EXP_PT_2_1341 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP23_EXP_PT_2_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_EXP23_EXP_PT_2_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_EXP23_EXP_PT_2_IN4, + I5 => DIN_3_IBUF, + I6 => NlwInverterSignal_EXP23_EXP_PT_2_IN6, + O => EXP23_EXP_PT_2 + ); + EXP23_EXP_PT_3_1342 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP23_EXP_PT_3_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_EXP23_EXP_PT_3_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_EXP23_EXP_PT_3_IN4, + I5 => NlwInverterSignal_EXP23_EXP_PT_3_IN5, + I6 => REG_0_3, + O => EXP23_EXP_PT_3 + ); + EXP23_EXP_tsimrenamed_net_Q_1343 : X_OR4 + port map ( + I0 => EXP23_EXP_PT_0, + I1 => EXP23_EXP_PT_1, + I2 => EXP23_EXP_PT_2, + I3 => EXP23_EXP_PT_3, + O => EXP23_EXP_tsimrenamed_net_Q + ); + EXP24_EXP_1344 : X_BUF + port map ( + I => EXP24_EXP_tsimrenamed_net_Q, + O => EXP24_EXP + ); + EXP24_EXP_PT_0_1345 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP24_EXP_PT_0_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_EXP24_EXP_PT_0_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_EXP24_EXP_PT_0_IN4, + I5 => DIN_31_IBUF, + I6 => NlwInverterSignal_EXP24_EXP_PT_0_IN6, + O => EXP24_EXP_PT_0 + ); + EXP24_EXP_PT_1_1346 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP24_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_EXP24_EXP_PT_1_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_EXP24_EXP_PT_1_IN4, + I5 => NlwInverterSignal_EXP24_EXP_PT_1_IN5, + I6 => REG_0_31, + O => EXP24_EXP_PT_1 + ); + EXP24_EXP_tsimrenamed_net_Q_1347 : X_OR2 + port map ( + I0 => EXP24_EXP_PT_0, + I1 => EXP24_EXP_PT_1, + O => EXP24_EXP_tsimrenamed_net_Q + ); + EXP25_EXP_1348 : X_BUF + port map ( + I => EXP25_EXP_tsimrenamed_net_Q, + O => EXP25_EXP + ); + EXP25_EXP_PT_0_1349 : X_AND6 + port map ( + I0 => NlwInverterSignal_EXP25_EXP_PT_0_IN0, + I1 => NlwInverterSignal_EXP25_EXP_PT_0_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_EXP25_EXP_PT_0_IN3, + I4 => REG_0_29, + I5 => NlwInverterSignal_EXP25_EXP_PT_0_IN5, + O => EXP25_EXP_PT_0 + ); + EXP25_EXP_PT_1_1350 : X_AND6 + port map ( + I0 => NlwInverterSignal_EXP25_EXP_PT_1_IN0, + I1 => NlwInverterSignal_EXP25_EXP_PT_1_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_EXP25_EXP_PT_1_IN3, + I4 => NlwInverterSignal_EXP25_EXP_PT_1_IN4, + I5 => REG_0_30, + O => EXP25_EXP_PT_1 + ); + EXP25_EXP_PT_2_1351 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP25_EXP_PT_2_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_EXP25_EXP_PT_2_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_EXP25_EXP_PT_2_IN4, + I5 => DIN_30_IBUF, + I6 => NlwInverterSignal_EXP25_EXP_PT_2_IN6, + O => EXP25_EXP_PT_2 + ); + EXP25_EXP_PT_3_1352 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP25_EXP_PT_3_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_EXP25_EXP_PT_3_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_EXP25_EXP_PT_3_IN4, + I5 => NlwInverterSignal_EXP25_EXP_PT_3_IN5, + I6 => REG_0_30, + O => EXP25_EXP_PT_3 + ); + EXP25_EXP_tsimrenamed_net_Q_1353 : X_OR4 + port map ( + I0 => EXP25_EXP_PT_0, + I1 => EXP25_EXP_PT_1, + I2 => EXP25_EXP_PT_2, + I3 => EXP25_EXP_PT_3, + O => EXP25_EXP_tsimrenamed_net_Q + ); + EXP26_EXP_1354 : X_BUF + port map ( + I => EXP26_EXP_tsimrenamed_net_Q, + O => EXP26_EXP + ); + EXP26_EXP_PT_0_1355 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP26_EXP_PT_0_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_EXP26_EXP_PT_0_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_EXP26_EXP_PT_0_IN4, + I5 => DIN_28_IBUF, + I6 => NlwInverterSignal_EXP26_EXP_PT_0_IN6, + O => EXP26_EXP_PT_0 + ); + EXP26_EXP_PT_1_1356 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP26_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_EXP26_EXP_PT_1_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_EXP26_EXP_PT_1_IN4, + I5 => NlwInverterSignal_EXP26_EXP_PT_1_IN5, + I6 => REG_0_28, + O => EXP26_EXP_PT_1 + ); + EXP26_EXP_tsimrenamed_net_Q_1357 : X_OR2 + port map ( + I0 => EXP26_EXP_PT_0, + I1 => EXP26_EXP_PT_1, + O => EXP26_EXP_tsimrenamed_net_Q + ); + EXP27_EXP_1358 : X_BUF + port map ( + I => EXP27_EXP_tsimrenamed_net_Q, + O => EXP27_EXP + ); + EXP27_EXP_PT_0_1359 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP27_EXP_PT_0_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => DIN_31_IBUF, + I6 => NlwInverterSignal_EXP27_EXP_PT_0_IN6, + O => EXP27_EXP_PT_0 + ); + EXP27_EXP_PT_1_1360 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP27_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => NlwInverterSignal_EXP27_EXP_PT_1_IN5, + I6 => REG_1_31, + O => EXP27_EXP_PT_1 + ); + EXP27_EXP_tsimrenamed_net_Q_1361 : X_OR2 + port map ( + I0 => EXP27_EXP_PT_0, + I1 => EXP27_EXP_PT_1, + O => EXP27_EXP_tsimrenamed_net_Q + ); + EXP28_EXP_1362 : X_BUF + port map ( + I => EXP28_EXP_tsimrenamed_net_Q, + O => EXP28_EXP + ); + EXP28_EXP_PT_0_1363 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP28_EXP_PT_0_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => DIN_29_IBUF, + I6 => NlwInverterSignal_EXP28_EXP_PT_0_IN6, + O => EXP28_EXP_PT_0 + ); + EXP28_EXP_PT_1_1364 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP28_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => NlwInverterSignal_EXP28_EXP_PT_1_IN5, + I6 => REG_1_29, + O => EXP28_EXP_PT_1 + ); + EXP28_EXP_tsimrenamed_net_Q_1365 : X_OR2 + port map ( + I0 => EXP28_EXP_PT_0, + I1 => EXP28_EXP_PT_1, + O => EXP28_EXP_tsimrenamed_net_Q + ); + EXP29_EXP_1366 : X_BUF + port map ( + I => EXP29_EXP_tsimrenamed_net_Q, + O => EXP29_EXP + ); + EXP29_EXP_PT_0_1367 : X_AND6 + port map ( + I0 => NlwInverterSignal_EXP29_EXP_PT_0_IN0, + I1 => NlwInverterSignal_EXP29_EXP_PT_0_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_EXP29_EXP_PT_0_IN3, + I4 => REG_0_16, + I5 => NlwInverterSignal_EXP29_EXP_PT_0_IN5, + O => EXP29_EXP_PT_0 + ); + EXP29_EXP_PT_1_1368 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP29_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_EXP29_EXP_PT_1_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_EXP29_EXP_PT_1_IN4, + I5 => DIN_17_IBUF, + I6 => NlwInverterSignal_EXP29_EXP_PT_1_IN6, + O => EXP29_EXP_PT_1 + ); + EXP29_EXP_PT_2_1369 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP29_EXP_PT_2_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_EXP29_EXP_PT_2_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_EXP29_EXP_PT_2_IN4, + I5 => NlwInverterSignal_EXP29_EXP_PT_2_IN5, + I6 => REG_0_17, + O => EXP29_EXP_PT_2 + ); + EXP29_EXP_tsimrenamed_net_Q_1370 : X_OR3 + port map ( + I0 => EXP29_EXP_PT_0, + I1 => EXP29_EXP_PT_1, + I2 => EXP29_EXP_PT_2, + O => EXP29_EXP_tsimrenamed_net_Q + ); + EXP30_EXP_1371 : X_BUF + port map ( + I => EXP30_EXP_tsimrenamed_net_Q, + O => EXP30_EXP + ); + EXP30_EXP_PT_0_1372 : X_AND6 + port map ( + I0 => NlwInverterSignal_EXP30_EXP_PT_0_IN0, + I1 => NlwInverterSignal_EXP30_EXP_PT_0_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_EXP30_EXP_PT_0_IN3, + I4 => REG_0_14, + I5 => NlwInverterSignal_EXP30_EXP_PT_0_IN5, + O => EXP30_EXP_PT_0 + ); + EXP30_EXP_PT_1_1373 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP30_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_EXP30_EXP_PT_1_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_EXP30_EXP_PT_1_IN4, + I5 => DIN_15_IBUF, + I6 => NlwInverterSignal_EXP30_EXP_PT_1_IN6, + O => EXP30_EXP_PT_1 + ); + EXP30_EXP_PT_2_1374 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP30_EXP_PT_2_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_EXP30_EXP_PT_2_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_EXP30_EXP_PT_2_IN4, + I5 => NlwInverterSignal_EXP30_EXP_PT_2_IN5, + I6 => REG_0_15, + O => EXP30_EXP_PT_2 + ); + EXP30_EXP_tsimrenamed_net_Q_1375 : X_OR3 + port map ( + I0 => EXP30_EXP_PT_0, + I1 => EXP30_EXP_PT_1, + I2 => EXP30_EXP_PT_2, + O => EXP30_EXP_tsimrenamed_net_Q + ); + EXP31_EXP_1376 : X_BUF + port map ( + I => EXP31_EXP_tsimrenamed_net_Q, + O => EXP31_EXP + ); + EXP31_EXP_PT_0_1377 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP31_EXP_PT_0_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_EXP31_EXP_PT_0_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_EXP31_EXP_PT_0_IN4, + I5 => DIN_20_IBUF, + I6 => NlwInverterSignal_EXP31_EXP_PT_0_IN6, + O => EXP31_EXP_PT_0 + ); + EXP31_EXP_PT_1_1378 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP31_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_EXP31_EXP_PT_1_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_EXP31_EXP_PT_1_IN4, + I5 => NlwInverterSignal_EXP31_EXP_PT_1_IN5, + I6 => REG_0_20, + O => EXP31_EXP_PT_1 + ); + EXP31_EXP_tsimrenamed_net_Q_1379 : X_OR2 + port map ( + I0 => EXP31_EXP_PT_0, + I1 => EXP31_EXP_PT_1, + O => EXP31_EXP_tsimrenamed_net_Q + ); + EXP32_EXP_1380 : X_BUF + port map ( + I => EXP32_EXP_tsimrenamed_net_Q, + O => EXP32_EXP + ); + EXP32_EXP_PT_0_1381 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP32_EXP_PT_0_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_EXP32_EXP_PT_0_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_EXP32_EXP_PT_0_IN4, + I5 => DIN_18_IBUF, + I6 => NlwInverterSignal_EXP32_EXP_PT_0_IN6, + O => EXP32_EXP_PT_0 + ); + EXP32_EXP_PT_1_1382 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP32_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_EXP32_EXP_PT_1_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_EXP32_EXP_PT_1_IN4, + I5 => NlwInverterSignal_EXP32_EXP_PT_1_IN5, + I6 => REG_0_18, + O => EXP32_EXP_PT_1 + ); + EXP32_EXP_tsimrenamed_net_Q_1383 : X_OR2 + port map ( + I0 => EXP32_EXP_PT_0, + I1 => EXP32_EXP_PT_1, + O => EXP32_EXP_tsimrenamed_net_Q + ); + EXP33_EXP_1384 : X_BUF + port map ( + I => EXP33_EXP_tsimrenamed_net_Q, + O => EXP33_EXP + ); + EXP33_EXP_PT_0_1385 : X_AND6 + port map ( + I0 => NlwInverterSignal_EXP33_EXP_PT_0_IN0, + I1 => NlwInverterSignal_EXP33_EXP_PT_0_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_EXP33_EXP_PT_0_IN3, + I4 => REG_0_22, + I5 => NlwInverterSignal_EXP33_EXP_PT_0_IN5, + O => EXP33_EXP_PT_0 + ); + EXP33_EXP_PT_1_1386 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP33_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_EXP33_EXP_PT_1_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_EXP33_EXP_PT_1_IN4, + I5 => DIN_23_IBUF, + I6 => NlwInverterSignal_EXP33_EXP_PT_1_IN6, + O => EXP33_EXP_PT_1 + ); + EXP33_EXP_PT_2_1387 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP33_EXP_PT_2_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_EXP33_EXP_PT_2_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_EXP33_EXP_PT_2_IN4, + I5 => NlwInverterSignal_EXP33_EXP_PT_2_IN5, + I6 => REG_0_23, + O => EXP33_EXP_PT_2 + ); + EXP33_EXP_tsimrenamed_net_Q_1388 : X_OR3 + port map ( + I0 => EXP33_EXP_PT_0, + I1 => EXP33_EXP_PT_1, + I2 => EXP33_EXP_PT_2, + O => EXP33_EXP_tsimrenamed_net_Q + ); + EXP34_EXP_1389 : X_BUF + port map ( + I => EXP34_EXP_tsimrenamed_net_Q, + O => EXP34_EXP + ); + EXP34_EXP_PT_0_1390 : X_AND6 + port map ( + I0 => NlwInverterSignal_EXP34_EXP_PT_0_IN0, + I1 => NlwInverterSignal_EXP34_EXP_PT_0_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_EXP34_EXP_PT_0_IN3, + I4 => REG_0_20, + I5 => NlwInverterSignal_EXP34_EXP_PT_0_IN5, + O => EXP34_EXP_PT_0 + ); + EXP34_EXP_PT_1_1391 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP34_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_EXP34_EXP_PT_1_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_EXP34_EXP_PT_1_IN4, + I5 => DIN_21_IBUF, + I6 => NlwInverterSignal_EXP34_EXP_PT_1_IN6, + O => EXP34_EXP_PT_1 + ); + EXP34_EXP_PT_2_1392 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP34_EXP_PT_2_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_EXP34_EXP_PT_2_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_EXP34_EXP_PT_2_IN4, + I5 => NlwInverterSignal_EXP34_EXP_PT_2_IN5, + I6 => REG_0_21, + O => EXP34_EXP_PT_2 + ); + EXP34_EXP_tsimrenamed_net_Q_1393 : X_OR3 + port map ( + I0 => EXP34_EXP_PT_0, + I1 => EXP34_EXP_PT_1, + I2 => EXP34_EXP_PT_2, + O => EXP34_EXP_tsimrenamed_net_Q + ); + EXP35_EXP_1394 : X_BUF + port map ( + I => EXP35_EXP_tsimrenamed_net_Q, + O => EXP35_EXP + ); + EXP35_EXP_PT_0_1395 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP35_EXP_PT_0_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_EXP35_EXP_PT_0_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_EXP35_EXP_PT_0_IN4, + I5 => DIN_26_IBUF, + I6 => NlwInverterSignal_EXP35_EXP_PT_0_IN6, + O => EXP35_EXP_PT_0 + ); + EXP35_EXP_PT_1_1396 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP35_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_EXP35_EXP_PT_1_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_EXP35_EXP_PT_1_IN4, + I5 => NlwInverterSignal_EXP35_EXP_PT_1_IN5, + I6 => REG_0_26, + O => EXP35_EXP_PT_1 + ); + EXP35_EXP_tsimrenamed_net_Q_1397 : X_OR2 + port map ( + I0 => EXP35_EXP_PT_0, + I1 => EXP35_EXP_PT_1, + O => EXP35_EXP_tsimrenamed_net_Q + ); + EXP36_EXP_1398 : X_BUF + port map ( + I => EXP36_EXP_tsimrenamed_net_Q, + O => EXP36_EXP + ); + EXP36_EXP_PT_0_1399 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP36_EXP_PT_0_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_EXP36_EXP_PT_0_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_EXP36_EXP_PT_0_IN4, + I5 => DIN_24_IBUF, + I6 => NlwInverterSignal_EXP36_EXP_PT_0_IN6, + O => EXP36_EXP_PT_0 + ); + EXP36_EXP_PT_1_1400 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP36_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_EXP36_EXP_PT_1_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_EXP36_EXP_PT_1_IN4, + I5 => NlwInverterSignal_EXP36_EXP_PT_1_IN5, + I6 => REG_0_24, + O => EXP36_EXP_PT_1 + ); + EXP36_EXP_tsimrenamed_net_Q_1401 : X_OR2 + port map ( + I0 => EXP36_EXP_PT_0, + I1 => EXP36_EXP_PT_1, + O => EXP36_EXP_tsimrenamed_net_Q + ); + EXP37_EXP_1402 : X_BUF + port map ( + I => EXP37_EXP_tsimrenamed_net_Q, + O => EXP37_EXP + ); + EXP37_EXP_PT_0_1403 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP37_EXP_PT_0_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => DIN_27_IBUF, + I6 => NlwInverterSignal_EXP37_EXP_PT_0_IN6, + O => EXP37_EXP_PT_0 + ); + EXP37_EXP_PT_1_1404 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP37_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => NlwInverterSignal_EXP37_EXP_PT_1_IN5, + I6 => REG_1_27, + O => EXP37_EXP_PT_1 + ); + EXP37_EXP_tsimrenamed_net_Q_1405 : X_OR2 + port map ( + I0 => EXP37_EXP_PT_0, + I1 => EXP37_EXP_PT_1, + O => EXP37_EXP_tsimrenamed_net_Q + ); + EXP38_EXP_1406 : X_BUF + port map ( + I => EXP38_EXP_tsimrenamed_net_Q, + O => EXP38_EXP + ); + EXP38_EXP_PT_0_1407 : X_AND6 + port map ( + I0 => NlwInverterSignal_EXP38_EXP_PT_0_IN0, + I1 => NlwInverterSignal_EXP38_EXP_PT_0_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => REG_1_23, + I5 => NlwInverterSignal_EXP38_EXP_PT_0_IN5, + O => EXP38_EXP_PT_0 + ); + EXP38_EXP_PT_1_1408 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP38_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => DIN_24_IBUF, + I6 => NlwInverterSignal_EXP38_EXP_PT_1_IN6, + O => EXP38_EXP_PT_1 + ); + EXP38_EXP_PT_2_1409 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP38_EXP_PT_2_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => NlwInverterSignal_EXP38_EXP_PT_2_IN5, + I6 => REG_1_24, + O => EXP38_EXP_PT_2 + ); + EXP38_EXP_tsimrenamed_net_Q_1410 : X_OR3 + port map ( + I0 => EXP38_EXP_PT_0, + I1 => EXP38_EXP_PT_1, + I2 => EXP38_EXP_PT_2, + O => EXP38_EXP_tsimrenamed_net_Q + ); + EXP39_EXP_1411 : X_BUF + port map ( + I => EXP39_EXP_tsimrenamed_net_Q, + O => EXP39_EXP + ); + EXP39_EXP_PT_0_1412 : X_AND6 + port map ( + I0 => NlwInverterSignal_EXP39_EXP_PT_0_IN0, + I1 => NlwInverterSignal_EXP39_EXP_PT_0_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_EXP39_EXP_PT_0_IN3, + I4 => REG_0_26, + I5 => NlwInverterSignal_EXP39_EXP_PT_0_IN5, + O => EXP39_EXP_PT_0 + ); + EXP39_EXP_PT_1_1413 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP39_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_EXP39_EXP_PT_1_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_EXP39_EXP_PT_1_IN4, + I5 => DIN_27_IBUF, + I6 => NlwInverterSignal_EXP39_EXP_PT_1_IN6, + O => EXP39_EXP_PT_1 + ); + EXP39_EXP_PT_2_1414 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP39_EXP_PT_2_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_EXP39_EXP_PT_2_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_EXP39_EXP_PT_2_IN4, + I5 => NlwInverterSignal_EXP39_EXP_PT_2_IN5, + I6 => REG_0_27, + O => EXP39_EXP_PT_2 + ); + EXP39_EXP_tsimrenamed_net_Q_1415 : X_OR3 + port map ( + I0 => EXP39_EXP_PT_0, + I1 => EXP39_EXP_PT_1, + I2 => EXP39_EXP_PT_2, + O => EXP39_EXP_tsimrenamed_net_Q + ); + EXP40_EXP_1416 : X_BUF + port map ( + I => EXP40_EXP_tsimrenamed_net_Q, + O => EXP40_EXP + ); + EXP40_EXP_PT_0_1417 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP40_EXP_PT_0_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => DIN_26_IBUF, + I6 => NlwInverterSignal_EXP40_EXP_PT_0_IN6, + O => EXP40_EXP_PT_0 + ); + EXP40_EXP_PT_1_1418 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP40_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => NlwInverterSignal_EXP40_EXP_PT_1_IN5, + I6 => REG_1_26, + O => EXP40_EXP_PT_1 + ); + EXP40_EXP_tsimrenamed_net_Q_1419 : X_OR2 + port map ( + I0 => EXP40_EXP_PT_0, + I1 => EXP40_EXP_PT_1, + O => EXP40_EXP_tsimrenamed_net_Q + ); + EXP41_EXP_1420 : X_BUF + port map ( + I => EXP41_EXP_tsimrenamed_net_Q, + O => EXP41_EXP + ); + EXP41_EXP_PT_0_1421 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP41_EXP_PT_0_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => DIN_25_IBUF, + I6 => NlwInverterSignal_EXP41_EXP_PT_0_IN6, + O => EXP41_EXP_PT_0 + ); + EXP41_EXP_PT_1_1422 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP41_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => NlwInverterSignal_EXP41_EXP_PT_1_IN5, + I6 => REG_1_25, + O => EXP41_EXP_PT_1 + ); + EXP41_EXP_tsimrenamed_net_Q_1423 : X_OR2 + port map ( + I0 => EXP41_EXP_PT_0, + I1 => EXP41_EXP_PT_1, + O => EXP41_EXP_tsimrenamed_net_Q + ); + EXP42_EXP_1424 : X_BUF + port map ( + I => EXP42_EXP_tsimrenamed_net_Q, + O => EXP42_EXP + ); + EXP42_EXP_PT_0_1425 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP42_EXP_PT_0_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => DIN_7_IBUF, + I6 => NlwInverterSignal_EXP42_EXP_PT_0_IN6, + O => EXP42_EXP_PT_0 + ); + EXP42_EXP_PT_1_1426 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP42_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => NlwInverterSignal_EXP42_EXP_PT_1_IN5, + I6 => REG_1_7, + O => EXP42_EXP_PT_1 + ); + EXP42_EXP_tsimrenamed_net_Q_1427 : X_OR2 + port map ( + I0 => EXP42_EXP_PT_0, + I1 => EXP42_EXP_PT_1, + O => EXP42_EXP_tsimrenamed_net_Q + ); + EXP43_EXP_1428 : X_BUF + port map ( + I => EXP43_EXP_tsimrenamed_net_Q, + O => EXP43_EXP + ); + EXP43_EXP_PT_0_1429 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP43_EXP_PT_0_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => DIN_10_IBUF, + I6 => NlwInverterSignal_EXP43_EXP_PT_0_IN6, + O => EXP43_EXP_PT_0 + ); + EXP43_EXP_PT_1_1430 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP43_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => NlwInverterSignal_EXP43_EXP_PT_1_IN5, + I6 => REG_1_10, + O => EXP43_EXP_PT_1 + ); + EXP43_EXP_tsimrenamed_net_Q_1431 : X_OR2 + port map ( + I0 => EXP43_EXP_PT_0, + I1 => EXP43_EXP_PT_1, + O => EXP43_EXP_tsimrenamed_net_Q + ); + EXP44_EXP_1432 : X_BUF + port map ( + I => EXP44_EXP_tsimrenamed_net_Q, + O => EXP44_EXP + ); + EXP44_EXP_PT_0_1433 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP44_EXP_PT_0_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => DIN_9_IBUF, + I6 => NlwInverterSignal_EXP44_EXP_PT_0_IN6, + O => EXP44_EXP_PT_0 + ); + EXP44_EXP_PT_1_1434 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP44_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => NlwInverterSignal_EXP44_EXP_PT_1_IN5, + I6 => REG_1_9, + O => EXP44_EXP_PT_1 + ); + EXP44_EXP_tsimrenamed_net_Q_1435 : X_OR2 + port map ( + I0 => EXP44_EXP_PT_0, + I1 => EXP44_EXP_PT_1, + O => EXP44_EXP_tsimrenamed_net_Q + ); + EXP45_EXP_1436 : X_BUF + port map ( + I => EXP45_EXP_tsimrenamed_net_Q, + O => EXP45_EXP + ); + EXP45_EXP_PT_0_1437 : X_AND6 + port map ( + I0 => NlwInverterSignal_EXP45_EXP_PT_0_IN0, + I1 => NlwInverterSignal_EXP45_EXP_PT_0_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_EXP45_EXP_PT_0_IN3, + I4 => NlwInverterSignal_EXP45_EXP_PT_0_IN4, + I5 => REG_0_8, + O => EXP45_EXP_PT_0 + ); + EXP45_EXP_PT_1_1438 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP45_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_EXP45_EXP_PT_1_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_EXP45_EXP_PT_1_IN4, + I5 => REG_0_9, + I6 => NlwInverterSignal_EXP45_EXP_PT_1_IN6, + O => EXP45_EXP_PT_1 + ); + EXP45_EXP_PT_2_1439 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP45_EXP_PT_2_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_EXP45_EXP_PT_2_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_EXP45_EXP_PT_2_IN4, + I5 => NlwInverterSignal_EXP45_EXP_PT_2_IN5, + I6 => DIN_9_IBUF, + O => EXP45_EXP_PT_2 + ); + EXP45_EXP_tsimrenamed_net_Q_1440 : X_OR3 + port map ( + I0 => EXP45_EXP_PT_0, + I1 => EXP45_EXP_PT_1, + I2 => EXP45_EXP_PT_2, + O => EXP45_EXP_tsimrenamed_net_Q + ); + EXP46_EXP_1441 : X_BUF + port map ( + I => EXP46_EXP_tsimrenamed_net_Q, + O => EXP46_EXP + ); + EXP46_EXP_PT_0_1442 : X_AND6 + port map ( + I0 => NlwInverterSignal_EXP46_EXP_PT_0_IN0, + I1 => NlwInverterSignal_EXP46_EXP_PT_0_IN1, + I2 => SHIFT_EN, + I3 => NlwInverterSignal_EXP46_EXP_PT_0_IN3, + I4 => REG_0_6, + I5 => NlwInverterSignal_EXP46_EXP_PT_0_IN5, + O => EXP46_EXP_PT_0 + ); + EXP46_EXP_PT_1_1443 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP46_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_EXP46_EXP_PT_1_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_EXP46_EXP_PT_1_IN4, + I5 => DIN_7_IBUF, + I6 => NlwInverterSignal_EXP46_EXP_PT_1_IN6, + O => EXP46_EXP_PT_1 + ); + EXP46_EXP_PT_2_1444 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP46_EXP_PT_2_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_EXP46_EXP_PT_2_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_EXP46_EXP_PT_2_IN4, + I5 => NlwInverterSignal_EXP46_EXP_PT_2_IN5, + I6 => REG_0_7, + O => EXP46_EXP_PT_2 + ); + EXP46_EXP_tsimrenamed_net_Q_1445 : X_OR3 + port map ( + I0 => EXP46_EXP_PT_0, + I1 => EXP46_EXP_PT_1, + I2 => EXP46_EXP_PT_2, + O => EXP46_EXP_tsimrenamed_net_Q + ); + EXP47_EXP_1446 : X_BUF + port map ( + I => EXP47_EXP_tsimrenamed_net_Q, + O => EXP47_EXP + ); + EXP47_EXP_PT_0_1447 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP47_EXP_PT_0_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => DIN_8_IBUF, + I6 => NlwInverterSignal_EXP47_EXP_PT_0_IN6, + O => EXP47_EXP_PT_0 + ); + EXP47_EXP_PT_1_1448 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP47_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => NlwInverterSignal_EXP47_EXP_PT_1_IN5, + I6 => REG_1_8, + O => EXP47_EXP_PT_1 + ); + EXP47_EXP_tsimrenamed_net_Q_1449 : X_OR2 + port map ( + I0 => EXP47_EXP_PT_0, + I1 => EXP47_EXP_PT_1, + O => EXP47_EXP_tsimrenamed_net_Q + ); + EXP48_EXP_1450 : X_BUF + port map ( + I => EXP48_EXP_tsimrenamed_net_Q, + O => EXP48_EXP + ); + EXP48_EXP_PT_0_1451 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP48_EXP_PT_0_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => DIN_1_IBUF, + I6 => NlwInverterSignal_EXP48_EXP_PT_0_IN6, + O => EXP48_EXP_PT_0 + ); + EXP48_EXP_PT_1_1452 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP48_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => NlwInverterSignal_EXP48_EXP_PT_1_IN5, + I6 => REG_1_1, + O => EXP48_EXP_PT_1 + ); + EXP48_EXP_tsimrenamed_net_Q_1453 : X_OR2 + port map ( + I0 => EXP48_EXP_PT_0, + I1 => EXP48_EXP_PT_1, + O => EXP48_EXP_tsimrenamed_net_Q + ); + EXP49_EXP_1454 : X_BUF + port map ( + I => EXP49_EXP_tsimrenamed_net_Q, + O => EXP49_EXP + ); + EXP49_EXP_PT_0_1455 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP49_EXP_PT_0_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => DIN_5_IBUF, + I6 => NlwInverterSignal_EXP49_EXP_PT_0_IN6, + O => EXP49_EXP_PT_0 + ); + EXP49_EXP_PT_1_1456 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP49_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => NlwInverterSignal_EXP49_EXP_PT_1_IN5, + I6 => REG_1_5, + O => EXP49_EXP_PT_1 + ); + EXP49_EXP_tsimrenamed_net_Q_1457 : X_OR2 + port map ( + I0 => EXP49_EXP_PT_0, + I1 => EXP49_EXP_PT_1, + O => EXP49_EXP_tsimrenamed_net_Q + ); + EXP50_EXP_1458 : X_BUF + port map ( + I => EXP50_EXP_tsimrenamed_net_Q, + O => EXP50_EXP + ); + EXP50_EXP_tsimrenamed_net_Q_1459 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP50_EXP_tsimrenamed_net_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => NlwInverterSignal_EXP50_EXP_tsimrenamed_net_IN5, + I6 => REG_1_6, + O => EXP50_EXP_tsimrenamed_net_Q + ); + EXP51_EXP_1460 : X_BUF + port map ( + I => EXP51_EXP_tsimrenamed_net_Q, + O => EXP51_EXP + ); + EXP51_EXP_tsimrenamed_net_Q_1461 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP51_EXP_tsimrenamed_net_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => DIN_6_IBUF, + I6 => NlwInverterSignal_EXP51_EXP_tsimrenamed_net_IN6, + O => EXP51_EXP_tsimrenamed_net_Q + ); + EXP52_EXP_1462 : X_BUF + port map ( + I => EXP52_EXP_tsimrenamed_net_Q, + O => EXP52_EXP + ); + EXP52_EXP_PT_0_1463 : X_AND5 + port map ( + I0 => NlwInverterSignal_EXP52_EXP_PT_0_IN0, + I1 => NlwInverterSignal_EXP52_EXP_PT_0_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => REG_1_0, + O => EXP52_EXP_PT_0 + ); + EXP52_EXP_PT_1_1464 : X_AND6 + port map ( + I0 => NlwInverterSignal_EXP52_EXP_PT_1_IN0, + I1 => writeBufId(0), + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => NlwInverterSignal_EXP52_EXP_PT_1_IN4, + I5 => REG_1_0, + O => EXP52_EXP_PT_1 + ); + EXP52_EXP_PT_2_1465 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP52_EXP_PT_2_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => DIN_0_IBUF, + I6 => NlwInverterSignal_EXP52_EXP_PT_2_IN6, + O => EXP52_EXP_PT_2 + ); + EXP52_EXP_tsimrenamed_net_Q_1466 : X_OR3 + port map ( + I0 => EXP52_EXP_PT_0, + I1 => EXP52_EXP_PT_1, + I2 => EXP52_EXP_PT_2, + O => EXP52_EXP_tsimrenamed_net_Q + ); + EXP53_EXP_1467 : X_BUF + port map ( + I => EXP53_EXP_tsimrenamed_net_Q, + O => EXP53_EXP + ); + EXP53_EXP_PT_0_1468 : X_AND6 + port map ( + I0 => NlwInverterSignal_EXP53_EXP_PT_0_IN0, + I1 => NlwInverterSignal_EXP53_EXP_PT_0_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => REG_1_2, + I5 => NlwInverterSignal_EXP53_EXP_PT_0_IN5, + O => EXP53_EXP_PT_0 + ); + EXP53_EXP_PT_1_1469 : X_AND6 + port map ( + I0 => NlwInverterSignal_EXP53_EXP_PT_1_IN0, + I1 => NlwInverterSignal_EXP53_EXP_PT_1_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => NlwInverterSignal_EXP53_EXP_PT_1_IN4, + I5 => REG_1_3, + O => EXP53_EXP_PT_1 + ); + EXP53_EXP_PT_2_1470 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP53_EXP_PT_2_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => DIN_3_IBUF, + I6 => NlwInverterSignal_EXP53_EXP_PT_2_IN6, + O => EXP53_EXP_PT_2 + ); + EXP53_EXP_PT_3_1471 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP53_EXP_PT_3_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => NlwInverterSignal_EXP53_EXP_PT_3_IN5, + I6 => REG_1_3, + O => EXP53_EXP_PT_3 + ); + EXP53_EXP_tsimrenamed_net_Q_1472 : X_OR4 + port map ( + I0 => EXP53_EXP_PT_0, + I1 => EXP53_EXP_PT_1, + I2 => EXP53_EXP_PT_2, + I3 => EXP53_EXP_PT_3, + O => EXP53_EXP_tsimrenamed_net_Q + ); + EXP54_EXP_1473 : X_BUF + port map ( + I => EXP54_EXP_tsimrenamed_net_Q, + O => EXP54_EXP + ); + EXP54_EXP_PT_0_1474 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP54_EXP_PT_0_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => DIN_16_IBUF, + I6 => NlwInverterSignal_EXP54_EXP_PT_0_IN6, + O => EXP54_EXP_PT_0 + ); + EXP54_EXP_PT_1_1475 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP54_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => NlwInverterSignal_EXP54_EXP_PT_1_IN5, + I6 => REG_1_16, + O => EXP54_EXP_PT_1 + ); + EXP54_EXP_tsimrenamed_net_Q_1476 : X_OR2 + port map ( + I0 => EXP54_EXP_PT_0, + I1 => EXP54_EXP_PT_1, + O => EXP54_EXP_tsimrenamed_net_Q + ); + EXP55_EXP_1477 : X_BUF + port map ( + I => EXP55_EXP_tsimrenamed_net_Q, + O => EXP55_EXP + ); + EXP55_EXP_PT_0_1478 : X_AND6 + port map ( + I0 => NlwInverterSignal_EXP55_EXP_PT_0_IN0, + I1 => NlwInverterSignal_EXP55_EXP_PT_0_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => REG_1_12, + I5 => NlwInverterSignal_EXP55_EXP_PT_0_IN5, + O => EXP55_EXP_PT_0 + ); + EXP55_EXP_PT_1_1479 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP55_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => DIN_13_IBUF, + I6 => NlwInverterSignal_EXP55_EXP_PT_1_IN6, + O => EXP55_EXP_PT_1 + ); + EXP55_EXP_PT_2_1480 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP55_EXP_PT_2_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => NlwInverterSignal_EXP55_EXP_PT_2_IN5, + I6 => REG_1_13, + O => EXP55_EXP_PT_2 + ); + EXP55_EXP_tsimrenamed_net_Q_1481 : X_OR3 + port map ( + I0 => EXP55_EXP_PT_0, + I1 => EXP55_EXP_PT_1, + I2 => EXP55_EXP_PT_2, + O => EXP55_EXP_tsimrenamed_net_Q + ); + EXP56_EXP_1482 : X_BUF + port map ( + I => EXP56_EXP_tsimrenamed_net_Q, + O => EXP56_EXP + ); + EXP56_EXP_PT_0_1483 : X_AND6 + port map ( + I0 => NlwInverterSignal_EXP56_EXP_PT_0_IN0, + I1 => NlwInverterSignal_EXP56_EXP_PT_0_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => REG_1_10, + I5 => NlwInverterSignal_EXP56_EXP_PT_0_IN5, + O => EXP56_EXP_PT_0 + ); + EXP56_EXP_PT_1_1484 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP56_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => DIN_11_IBUF, + I6 => NlwInverterSignal_EXP56_EXP_PT_1_IN6, + O => EXP56_EXP_PT_1 + ); + EXP56_EXP_PT_2_1485 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP56_EXP_PT_2_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => NlwInverterSignal_EXP56_EXP_PT_2_IN5, + I6 => REG_1_11, + O => EXP56_EXP_PT_2 + ); + EXP56_EXP_tsimrenamed_net_Q_1486 : X_OR3 + port map ( + I0 => EXP56_EXP_PT_0, + I1 => EXP56_EXP_PT_1, + I2 => EXP56_EXP_PT_2, + O => EXP56_EXP_tsimrenamed_net_Q + ); + EXP57_EXP_1487 : X_BUF + port map ( + I => EXP57_EXP_tsimrenamed_net_Q, + O => EXP57_EXP + ); + EXP57_EXP_PT_0_1488 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP57_EXP_PT_0_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => DIN_15_IBUF, + I6 => NlwInverterSignal_EXP57_EXP_PT_0_IN6, + O => EXP57_EXP_PT_0 + ); + EXP57_EXP_PT_1_1489 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP57_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => NlwInverterSignal_EXP57_EXP_PT_1_IN5, + I6 => REG_1_15, + O => EXP57_EXP_PT_1 + ); + EXP57_EXP_tsimrenamed_net_Q_1490 : X_OR2 + port map ( + I0 => EXP57_EXP_PT_0, + I1 => EXP57_EXP_PT_1, + O => EXP57_EXP_tsimrenamed_net_Q + ); + EXP58_EXP_1491 : X_BUF + port map ( + I => EXP58_EXP_tsimrenamed_net_Q, + O => EXP58_EXP + ); + EXP58_EXP_PT_0_1492 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP58_EXP_PT_0_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => DIN_14_IBUF, + I6 => NlwInverterSignal_EXP58_EXP_PT_0_IN6, + O => EXP58_EXP_PT_0 + ); + EXP58_EXP_PT_1_1493 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP58_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => NlwInverterSignal_EXP58_EXP_PT_1_IN5, + I6 => REG_1_14, + O => EXP58_EXP_PT_1 + ); + EXP58_EXP_tsimrenamed_net_Q_1494 : X_OR2 + port map ( + I0 => EXP58_EXP_PT_0, + I1 => EXP58_EXP_PT_1, + O => EXP58_EXP_tsimrenamed_net_Q + ); + EXP59_EXP_1495 : X_BUF + port map ( + I => EXP59_EXP_tsimrenamed_net_Q, + O => EXP59_EXP + ); + EXP59_EXP_PT_0_1496 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP59_EXP_PT_0_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => DIN_22_IBUF, + I6 => NlwInverterSignal_EXP59_EXP_PT_0_IN6, + O => EXP59_EXP_PT_0 + ); + EXP59_EXP_PT_1_1497 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP59_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => NlwInverterSignal_EXP59_EXP_PT_1_IN5, + I6 => REG_1_22, + O => EXP59_EXP_PT_1 + ); + EXP59_EXP_tsimrenamed_net_Q_1498 : X_OR2 + port map ( + I0 => EXP59_EXP_PT_0, + I1 => EXP59_EXP_PT_1, + O => EXP59_EXP_tsimrenamed_net_Q + ); + EXP60_EXP_1499 : X_BUF + port map ( + I => EXP60_EXP_tsimrenamed_net_Q, + O => EXP60_EXP + ); + EXP60_EXP_PT_0_1500 : X_AND6 + port map ( + I0 => NlwInverterSignal_EXP60_EXP_PT_0_IN0, + I1 => NlwInverterSignal_EXP60_EXP_PT_0_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => REG_1_18, + I5 => NlwInverterSignal_EXP60_EXP_PT_0_IN5, + O => EXP60_EXP_PT_0 + ); + EXP60_EXP_PT_1_1501 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP60_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => DIN_19_IBUF, + I6 => NlwInverterSignal_EXP60_EXP_PT_1_IN6, + O => EXP60_EXP_PT_1 + ); + EXP60_EXP_PT_2_1502 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP60_EXP_PT_2_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => NlwInverterSignal_EXP60_EXP_PT_2_IN5, + I6 => REG_1_19, + O => EXP60_EXP_PT_2 + ); + EXP60_EXP_tsimrenamed_net_Q_1503 : X_OR3 + port map ( + I0 => EXP60_EXP_PT_0, + I1 => EXP60_EXP_PT_1, + I2 => EXP60_EXP_PT_2, + O => EXP60_EXP_tsimrenamed_net_Q + ); + EXP61_EXP_1504 : X_BUF + port map ( + I => EXP61_EXP_tsimrenamed_net_Q, + O => EXP61_EXP + ); + EXP61_EXP_PT_0_1505 : X_AND6 + port map ( + I0 => NlwInverterSignal_EXP61_EXP_PT_0_IN0, + I1 => NlwInverterSignal_EXP61_EXP_PT_0_IN1, + I2 => SHIFT_EN, + I3 => readBufId(0), + I4 => REG_1_16, + I5 => NlwInverterSignal_EXP61_EXP_PT_0_IN5, + O => EXP61_EXP_PT_0 + ); + EXP61_EXP_PT_1_1506 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP61_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => DIN_17_IBUF, + I6 => NlwInverterSignal_EXP61_EXP_PT_1_IN6, + O => EXP61_EXP_PT_1 + ); + EXP61_EXP_PT_2_1507 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP61_EXP_PT_2_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => NlwInverterSignal_EXP61_EXP_PT_2_IN5, + I6 => REG_1_17, + O => EXP61_EXP_PT_2 + ); + EXP61_EXP_tsimrenamed_net_Q_1508 : X_OR3 + port map ( + I0 => EXP61_EXP_PT_0, + I1 => EXP61_EXP_PT_1, + I2 => EXP61_EXP_PT_2, + O => EXP61_EXP_tsimrenamed_net_Q + ); + EXP62_EXP_1509 : X_BUF + port map ( + I => EXP62_EXP_tsimrenamed_net_Q, + O => EXP62_EXP + ); + EXP62_EXP_PT_0_1510 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP62_EXP_PT_0_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => DIN_21_IBUF, + I6 => NlwInverterSignal_EXP62_EXP_PT_0_IN6, + O => EXP62_EXP_PT_0 + ); + EXP62_EXP_PT_1_1511 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP62_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => NlwInverterSignal_EXP62_EXP_PT_1_IN5, + I6 => REG_1_21, + O => EXP62_EXP_PT_1 + ); + EXP62_EXP_tsimrenamed_net_Q_1512 : X_OR2 + port map ( + I0 => EXP62_EXP_PT_0, + I1 => EXP62_EXP_PT_1, + O => EXP62_EXP_tsimrenamed_net_Q + ); + EXP63_EXP_1513 : X_BUF + port map ( + I => EXP63_EXP_tsimrenamed_net_Q, + O => EXP63_EXP + ); + EXP63_EXP_PT_0_1514 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP63_EXP_PT_0_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => DIN_20_IBUF, + I6 => NlwInverterSignal_EXP63_EXP_PT_0_IN6, + O => EXP63_EXP_PT_0 + ); + EXP63_EXP_PT_1_1515 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP63_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => NlwInverterSignal_EXP63_EXP_PT_1_IN5, + I6 => REG_1_20, + O => EXP63_EXP_PT_1 + ); + EXP63_EXP_tsimrenamed_net_Q_1516 : X_OR2 + port map ( + I0 => EXP63_EXP_PT_0, + I1 => EXP63_EXP_PT_1, + O => EXP63_EXP_tsimrenamed_net_Q + ); + EXP64_EXP_1517 : X_BUF + port map ( + I => EXP64_EXP_tsimrenamed_net_Q, + O => EXP64_EXP + ); + EXP64_EXP_PT_0_1518 : X_AND3 + port map ( + I0 => NlwInverterSignal_EXP64_EXP_PT_0_IN0, + I1 => NlwInverterSignal_EXP64_EXP_PT_0_IN1, + I2 => state(1), + O => EXP64_EXP_PT_0 + ); + EXP64_EXP_PT_1_1519 : X_AND3 + port map ( + I0 => NlwInverterSignal_EXP64_EXP_PT_1_IN0, + I1 => state(0), + I2 => state(1), + O => EXP64_EXP_PT_1 + ); + EXP64_EXP_tsimrenamed_net_Q_1520 : X_OR2 + port map ( + I0 => EXP64_EXP_PT_0, + I1 => EXP64_EXP_PT_1, + O => EXP64_EXP_tsimrenamed_net_Q + ); + EXP65_EXP_1521 : X_BUF + port map ( + I => EXP65_EXP_tsimrenamed_net_Q, + O => EXP65_EXP + ); + EXP65_EXP_PT_0_1522 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP65_EXP_PT_0_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_EXP65_EXP_PT_0_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_EXP65_EXP_PT_0_IN4, + I5 => DIN_10_IBUF, + I6 => NlwInverterSignal_EXP65_EXP_PT_0_IN6, + O => EXP65_EXP_PT_0 + ); + EXP65_EXP_PT_1_1523 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP65_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_EXP65_EXP_PT_1_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_EXP65_EXP_PT_1_IN4, + I5 => NlwInverterSignal_EXP65_EXP_PT_1_IN5, + I6 => REG_0_10, + O => EXP65_EXP_PT_1 + ); + EXP65_EXP_tsimrenamed_net_Q_1524 : X_OR2 + port map ( + I0 => EXP65_EXP_PT_0, + I1 => EXP65_EXP_PT_1, + O => EXP65_EXP_tsimrenamed_net_Q + ); + EXP66_EXP_1525 : X_BUF + port map ( + I => EXP66_EXP_tsimrenamed_net_Q, + O => EXP66_EXP + ); + EXP66_EXP_PT_0_1526 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP66_EXP_PT_0_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_EXP66_EXP_PT_0_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_EXP66_EXP_PT_0_IN4, + I5 => DIN_14_IBUF, + I6 => NlwInverterSignal_EXP66_EXP_PT_0_IN6, + O => EXP66_EXP_PT_0 + ); + EXP66_EXP_PT_1_1527 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP66_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => NlwInverterSignal_EXP66_EXP_PT_1_IN2, + I3 => SHIFT_EN, + I4 => NlwInverterSignal_EXP66_EXP_PT_1_IN4, + I5 => NlwInverterSignal_EXP66_EXP_PT_1_IN5, + I6 => REG_0_14, + O => EXP66_EXP_PT_1 + ); + EXP66_EXP_tsimrenamed_net_Q_1528 : X_OR2 + port map ( + I0 => EXP66_EXP_PT_0, + I1 => EXP66_EXP_PT_1, + O => EXP66_EXP_tsimrenamed_net_Q + ); + EXP67_EXP_1529 : X_BUF + port map ( + I => EXP67_EXP_tsimrenamed_net_Q, + O => EXP67_EXP + ); + EXP67_EXP_PT_0_1530 : X_AND2 + port map ( + I0 => LOAD_PRESCALER_IBUF, + I1 => count(0), + O => EXP67_EXP_PT_0 + ); + EXP67_EXP_PT_1_1531 : X_AND3 + port map ( + I0 => NlwInverterSignal_EXP67_EXP_PT_1_IN0, + I1 => NlwInverterSignal_EXP67_EXP_PT_1_IN1, + I2 => NlwInverterSignal_EXP67_EXP_PT_1_IN2, + O => EXP67_EXP_PT_1 + ); + EXP67_EXP_tsimrenamed_net_Q_1532 : X_OR2 + port map ( + I0 => EXP67_EXP_PT_0, + I1 => EXP67_EXP_PT_1, + O => EXP67_EXP_tsimrenamed_net_Q + ); + EXP68_EXP_1533 : X_BUF + port map ( + I => EXP68_EXP_tsimrenamed_net_Q, + O => EXP68_EXP + ); + EXP68_EXP_PT_0_1534 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP68_EXP_PT_0_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => DIN_28_IBUF, + I6 => NlwInverterSignal_EXP68_EXP_PT_0_IN6, + O => EXP68_EXP_PT_0 + ); + EXP68_EXP_PT_1_1535 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP68_EXP_PT_1_IN0, + I1 => LOAD_SREG_IBUF, + I2 => writeBufId(0), + I3 => SHIFT_EN, + I4 => readBufId(0), + I5 => NlwInverterSignal_EXP68_EXP_PT_1_IN5, + I6 => REG_1_28, + O => EXP68_EXP_PT_1 + ); + EXP68_EXP_tsimrenamed_net_Q_1536 : X_OR2 + port map ( + I0 => EXP68_EXP_PT_0, + I1 => EXP68_EXP_PT_1, + O => EXP68_EXP_tsimrenamed_net_Q + ); + EXP69_EXP_1537 : X_BUF + port map ( + I => EXP69_EXP_tsimrenamed_net_Q, + O => EXP69_EXP + ); + EXP69_EXP_PT_0_1538 : X_AND2 + port map ( + I0 => LOAD_SREG_IBUF, + I1 => LOAD_SREG_IBUF, + O => EXP69_EXP_PT_0 + ); + EXP69_EXP_PT_1_1539 : X_AND7 + port map ( + I0 => NlwInverterSignal_EXP69_EXP_PT_1_IN0, + I1 => NlwInverterSignal_EXP69_EXP_PT_1_IN1, + I2 => NlwInverterSignal_EXP69_EXP_PT_1_IN2, + I3 => NlwInverterSignal_EXP69_EXP_PT_1_IN3, + I4 => NlwInverterSignal_EXP69_EXP_PT_1_IN4, + I5 => NlwInverterSignal_EXP69_EXP_PT_1_IN5, + I6 => NlwInverterSignal_EXP69_EXP_PT_1_IN6, + O => EXP69_EXP_PT_1 + ); + EXP69_EXP_tsimrenamed_net_Q_1540 : X_OR2 + port map ( + I0 => EXP69_EXP_PT_0, + I1 => EXP69_EXP_PT_1, + O => EXP69_EXP_tsimrenamed_net_Q + ); + NlwInverterBlock_SCLK_CE_IN0 : X_INV + port map ( + I => LOAD_PRESCALER_IBUF, + O => NlwInverterSignal_SCLK_CE_IN0 + ); + NlwInverterBlock_SCLK_CE_IN2 : X_INV + port map ( + I => count(4), + O => NlwInverterSignal_SCLK_CE_IN2 + ); + NlwInverterBlock_SCLK_CE_IN3 : X_INV + port map ( + I => count(1), + O => NlwInverterSignal_SCLK_CE_IN3 + ); + NlwInverterBlock_SCLK_CE_IN4 : X_INV + port map ( + I => count(2), + O => NlwInverterSignal_SCLK_CE_IN4 + ); + NlwInverterBlock_SCLK_CE_IN5 : X_INV + port map ( + I => count(3), + O => NlwInverterSignal_SCLK_CE_IN5 + ); + NlwInverterBlock_SCLK_CE_IN6 : X_INV + port map ( + I => count(5), + O => NlwInverterSignal_SCLK_CE_IN6 + ); + NlwInverterBlock_readBufId_0_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_readBufId_0_CLKF_IN0 + ); + NlwInverterBlock_readBufId_0_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_readBufId_0_CLKF_IN1 + ); + NlwInverterBlock_readBufId_0_CE_IN0 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_readBufId_0_CE_IN0 + ); + NlwInverterBlock_readBufId_0_CE_IN1 : X_INV + port map ( + I => SHIFT_CNT(0), + O => NlwInverterSignal_readBufId_0_CE_IN1 + ); + NlwInverterBlock_readBufId_0_CE_IN2 : X_INV + port map ( + I => SHIFT_CNT(1), + O => NlwInverterSignal_readBufId_0_CE_IN2 + ); + NlwInverterBlock_readBufId_0_CE_IN3 : X_INV + port map ( + I => SHIFT_CNT(2), + O => NlwInverterSignal_readBufId_0_CE_IN3 + ); + NlwInverterBlock_readBufId_0_CE_IN4 : X_INV + port map ( + I => SHIFT_CNT(3), + O => NlwInverterSignal_readBufId_0_CE_IN4 + ); + NlwInverterBlock_readBufId_0_CE_IN5 : X_INV + port map ( + I => SHIFT_CNT(4), + O => NlwInverterSignal_readBufId_0_CE_IN5 + ); + NlwInverterBlock_buf_depth_0_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => buf_depth_0_RSTF, + O => NlwInverterSignal_buf_depth_0_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_buf_depth_0_D2_PT_0_IN1 : X_INV + port map ( + I => SHIFT_CNT(0), + O => NlwInverterSignal_buf_depth_0_D2_PT_0_IN1 + ); + NlwInverterBlock_buf_depth_0_D2_PT_0_IN2 : X_INV + port map ( + I => SHIFT_CNT(1), + O => NlwInverterSignal_buf_depth_0_D2_PT_0_IN2 + ); + NlwInverterBlock_buf_depth_0_D2_PT_0_IN3 : X_INV + port map ( + I => SHIFT_CNT(2), + O => NlwInverterSignal_buf_depth_0_D2_PT_0_IN3 + ); + NlwInverterBlock_buf_depth_0_D2_PT_0_IN4 : X_INV + port map ( + I => SHIFT_CNT(3), + O => NlwInverterSignal_buf_depth_0_D2_PT_0_IN4 + ); + NlwInverterBlock_buf_depth_0_D2_PT_0_IN5 : X_INV + port map ( + I => SHIFT_CNT(4), + O => NlwInverterSignal_buf_depth_0_D2_PT_0_IN5 + ); + NlwInverterBlock_buf_depth_0_D2_PT_1_IN0 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_buf_depth_0_D2_PT_1_IN0 + ); + NlwInverterBlock_buf_depth_0_D2_PT_1_IN2 : X_INV + port map ( + I => SHIFT_CNT(0), + O => NlwInverterSignal_buf_depth_0_D2_PT_1_IN2 + ); + NlwInverterBlock_buf_depth_0_D2_PT_1_IN3 : X_INV + port map ( + I => SHIFT_CNT(1), + O => NlwInverterSignal_buf_depth_0_D2_PT_1_IN3 + ); + NlwInverterBlock_buf_depth_0_D2_PT_1_IN4 : X_INV + port map ( + I => SHIFT_CNT(2), + O => NlwInverterSignal_buf_depth_0_D2_PT_1_IN4 + ); + NlwInverterBlock_buf_depth_0_D2_PT_1_IN5 : X_INV + port map ( + I => SHIFT_CNT(3), + O => NlwInverterSignal_buf_depth_0_D2_PT_1_IN5 + ); + NlwInverterBlock_buf_depth_0_D2_PT_1_IN6 : X_INV + port map ( + I => SHIFT_CNT(4), + O => NlwInverterSignal_buf_depth_0_D2_PT_1_IN6 + ); + NlwInverterBlock_buf_depth_0_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_buf_depth_0_CLKF_IN0 + ); + NlwInverterBlock_buf_depth_0_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_buf_depth_0_CLKF_IN1 + ); + NlwInverterBlock_buf_depth_0_SETF_IN1 : X_INV + port map ( + I => buf_depth(0), + O => NlwInverterSignal_buf_depth_0_SETF_IN1 + ); + NlwInverterBlock_buf_depth_0_SETF_IN2 : X_INV + port map ( + I => buf_depth(1), + O => NlwInverterSignal_buf_depth_0_SETF_IN2 + ); + NlwInverterBlock_buf_depth_1_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => buf_depth_1_RSTF, + O => NlwInverterSignal_buf_depth_1_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_buf_depth_1_D2_PT_0_IN2 : X_INV + port map ( + I => SHIFT_CNT(0), + O => NlwInverterSignal_buf_depth_1_D2_PT_0_IN2 + ); + NlwInverterBlock_buf_depth_1_D2_PT_0_IN3 : X_INV + port map ( + I => SHIFT_CNT(1), + O => NlwInverterSignal_buf_depth_1_D2_PT_0_IN3 + ); + NlwInverterBlock_buf_depth_1_D2_PT_0_IN4 : X_INV + port map ( + I => SHIFT_CNT(2), + O => NlwInverterSignal_buf_depth_1_D2_PT_0_IN4 + ); + NlwInverterBlock_buf_depth_1_D2_PT_0_IN5 : X_INV + port map ( + I => SHIFT_CNT(3), + O => NlwInverterSignal_buf_depth_1_D2_PT_0_IN5 + ); + NlwInverterBlock_buf_depth_1_D2_PT_0_IN6 : X_INV + port map ( + I => SHIFT_CNT(4), + O => NlwInverterSignal_buf_depth_1_D2_PT_0_IN6 + ); + NlwInverterBlock_buf_depth_1_D2_PT_1_IN0 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_buf_depth_1_D2_PT_1_IN0 + ); + NlwInverterBlock_buf_depth_1_D2_PT_1_IN1 : X_INV + port map ( + I => buf_depth(0), + O => NlwInverterSignal_buf_depth_1_D2_PT_1_IN1 + ); + NlwInverterBlock_buf_depth_1_D2_PT_1_IN3 : X_INV + port map ( + I => SHIFT_CNT(0), + O => NlwInverterSignal_buf_depth_1_D2_PT_1_IN3 + ); + NlwInverterBlock_buf_depth_1_D2_PT_1_IN4 : X_INV + port map ( + I => SHIFT_CNT(1), + O => NlwInverterSignal_buf_depth_1_D2_PT_1_IN4 + ); + NlwInverterBlock_buf_depth_1_D2_PT_1_IN5 : X_INV + port map ( + I => SHIFT_CNT(2), + O => NlwInverterSignal_buf_depth_1_D2_PT_1_IN5 + ); + NlwInverterBlock_buf_depth_1_D2_PT_1_IN6 : X_INV + port map ( + I => SHIFT_CNT(3), + O => NlwInverterSignal_buf_depth_1_D2_PT_1_IN6 + ); + NlwInverterBlock_buf_depth_1_D2_PT_1_IN7 : X_INV + port map ( + I => SHIFT_CNT(4), + O => NlwInverterSignal_buf_depth_1_D2_PT_1_IN7 + ); + NlwInverterBlock_buf_depth_1_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_buf_depth_1_CLKF_IN0 + ); + NlwInverterBlock_buf_depth_1_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_buf_depth_1_CLKF_IN1 + ); + NlwInverterBlock_buf_depth_1_SETF_IN2 : X_INV + port map ( + I => buf_depth(1), + O => NlwInverterSignal_buf_depth_1_SETF_IN2 + ); + NlwInverterBlock_SHIFT_CNT_0_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => SHIFT_CNT_0_RSTF, + O => NlwInverterSignal_SHIFT_CNT_0_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_SHIFT_CNT_0_D_IN0 : X_INV + port map ( + I => SHIFT_CNT_0_D1, + O => NlwInverterSignal_SHIFT_CNT_0_D_IN0 + ); + NlwInverterBlock_SHIFT_CNT_0_D2_PT_0_IN0 : X_INV + port map ( + I => SHIFT_EN, + O => NlwInverterSignal_SHIFT_CNT_0_D2_PT_0_IN0 + ); + NlwInverterBlock_SHIFT_CNT_0_D2_PT_0_IN1 : X_INV + port map ( + I => SHIFT_EN, + O => NlwInverterSignal_SHIFT_CNT_0_D2_PT_0_IN1 + ); + NlwInverterBlock_SHIFT_CNT_0_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_SHIFT_CNT_0_CLKF_IN0 + ); + NlwInverterBlock_SHIFT_CNT_0_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_SHIFT_CNT_0_CLKF_IN1 + ); + NlwInverterBlock_SHIFT_CNT_0_SETF_IN1 : X_INV + port map ( + I => SHIFT_EN, + O => NlwInverterSignal_SHIFT_CNT_0_SETF_IN1 + ); + NlwInverterBlock_SHIFT_CNT_0_EXP_tsimrenamed_net_IN0 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_SHIFT_CNT_0_EXP_tsimrenamed_net_IN0 + ); + NlwInverterBlock_SHIFT_CNT_0_EXP_tsimrenamed_net_IN1 : X_INV + port map ( + I => SHIFT_CNT(0), + O => NlwInverterSignal_SHIFT_CNT_0_EXP_tsimrenamed_net_IN1 + ); + NlwInverterBlock_SHIFT_CNT_0_EXP_tsimrenamed_net_IN2 : X_INV + port map ( + I => SHIFT_CNT(1), + O => NlwInverterSignal_SHIFT_CNT_0_EXP_tsimrenamed_net_IN2 + ); + NlwInverterBlock_SHIFT_CNT_0_EXP_tsimrenamed_net_IN3 : X_INV + port map ( + I => SHIFT_CNT(2), + O => NlwInverterSignal_SHIFT_CNT_0_EXP_tsimrenamed_net_IN3 + ); + NlwInverterBlock_SHIFT_CNT_0_EXP_tsimrenamed_net_IN4 : X_INV + port map ( + I => SHIFT_CNT(3), + O => NlwInverterSignal_SHIFT_CNT_0_EXP_tsimrenamed_net_IN4 + ); + NlwInverterBlock_count_0_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => count_0_RSTF, + O => NlwInverterSignal_count_0_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_count_0_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_PRESCALER_IBUF, + O => NlwInverterSignal_count_0_D2_PT_1_IN1 + ); + NlwInverterBlock_count_0_D2_PT_2_IN0 : X_INV + port map ( + I => LOAD_PRESCALER_IBUF, + O => NlwInverterSignal_count_0_D2_PT_2_IN0 + ); + NlwInverterBlock_count_0_D2_PT_2_IN1 : X_INV + port map ( + I => count(4), + O => NlwInverterSignal_count_0_D2_PT_2_IN1 + ); + NlwInverterBlock_count_0_D2_PT_2_IN2 : X_INV + port map ( + I => count(1), + O => NlwInverterSignal_count_0_D2_PT_2_IN2 + ); + NlwInverterBlock_count_0_D2_PT_2_IN3 : X_INV + port map ( + I => count(2), + O => NlwInverterSignal_count_0_D2_PT_2_IN3 + ); + NlwInverterBlock_count_0_D2_PT_2_IN4 : X_INV + port map ( + I => count(3), + O => NlwInverterSignal_count_0_D2_PT_2_IN4 + ); + NlwInverterBlock_count_0_D2_PT_2_IN5 : X_INV + port map ( + I => count(5), + O => NlwInverterSignal_count_0_D2_PT_2_IN5 + ); + NlwInverterBlock_count_0_RSTF_IN1 : X_INV + port map ( + I => CLK_SCALE(0), + O => NlwInverterSignal_count_0_RSTF_IN1 + ); + NlwInverterBlock_count_0_EXP_tsimrenamed_net_IN1 : X_INV + port map ( + I => LOAD_PRESCALER_IBUF, + O => NlwInverterSignal_count_0_EXP_tsimrenamed_net_IN1 + ); + NlwInverterBlock_count_0_EXP_tsimrenamed_net_IN3 : X_INV + port map ( + I => CLK_SCALE(2), + O => NlwInverterSignal_count_0_EXP_tsimrenamed_net_IN3 + ); + NlwInverterBlock_count_4_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => count_4_RSTF, + O => NlwInverterSignal_count_4_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_count_4_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_count_4_D2_PT_1_IN0 + ); + NlwInverterBlock_count_4_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_PRESCALER_IBUF, + O => NlwInverterSignal_count_4_D2_PT_1_IN1 + ); + NlwInverterBlock_count_4_D2_PT_1_IN2 : X_INV + port map ( + I => count(0), + O => NlwInverterSignal_count_4_D2_PT_1_IN2 + ); + NlwInverterBlock_count_4_D2_PT_1_IN3 : X_INV + port map ( + I => count(1), + O => NlwInverterSignal_count_4_D2_PT_1_IN3 + ); + NlwInverterBlock_count_4_D2_PT_1_IN4 : X_INV + port map ( + I => count(2), + O => NlwInverterSignal_count_4_D2_PT_1_IN4 + ); + NlwInverterBlock_count_4_D2_PT_1_IN5 : X_INV + port map ( + I => count(3), + O => NlwInverterSignal_count_4_D2_PT_1_IN5 + ); + NlwInverterBlock_count_4_D2_PT_2_IN0 : X_INV + port map ( + I => LOAD_PRESCALER_IBUF, + O => NlwInverterSignal_count_4_D2_PT_2_IN0 + ); + NlwInverterBlock_count_4_D2_PT_2_IN1 : X_INV + port map ( + I => count(4), + O => NlwInverterSignal_count_4_D2_PT_2_IN1 + ); + NlwInverterBlock_count_4_D2_PT_2_IN2 : X_INV + port map ( + I => count(1), + O => NlwInverterSignal_count_4_D2_PT_2_IN2 + ); + NlwInverterBlock_count_4_D2_PT_2_IN3 : X_INV + port map ( + I => count(2), + O => NlwInverterSignal_count_4_D2_PT_2_IN3 + ); + NlwInverterBlock_count_4_D2_PT_2_IN4 : X_INV + port map ( + I => count(3), + O => NlwInverterSignal_count_4_D2_PT_2_IN4 + ); + NlwInverterBlock_count_4_D2_PT_2_IN5 : X_INV + port map ( + I => count(5), + O => NlwInverterSignal_count_4_D2_PT_2_IN5 + ); + NlwInverterBlock_count_4_RSTF_IN1 : X_INV + port map ( + I => CLK_SCALE(4), + O => NlwInverterSignal_count_4_RSTF_IN1 + ); + NlwInverterBlock_count_4_EXP_tsimrenamed_net_IN1 : X_INV + port map ( + I => LOAD_PRESCALER_IBUF, + O => NlwInverterSignal_count_4_EXP_tsimrenamed_net_IN1 + ); + NlwInverterBlock_count_4_EXP_tsimrenamed_net_IN3 : X_INV + port map ( + I => CLK_SCALE(3), + O => NlwInverterSignal_count_4_EXP_tsimrenamed_net_IN3 + ); + NlwInverterBlock_SHIFT_CNT_1_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => SHIFT_CNT_1_RSTF, + O => NlwInverterSignal_SHIFT_CNT_1_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_SHIFT_CNT_1_D_IN0 : X_INV + port map ( + I => SHIFT_CNT_1_D1, + O => NlwInverterSignal_SHIFT_CNT_1_D_IN0 + ); + NlwInverterBlock_SHIFT_CNT_1_D2_PT_1_IN0 : X_INV + port map ( + I => SHIFT_EN, + O => NlwInverterSignal_SHIFT_CNT_1_D2_PT_1_IN0 + ); + NlwInverterBlock_SHIFT_CNT_1_D2_PT_1_IN1 : X_INV + port map ( + I => SHIFT_EN, + O => NlwInverterSignal_SHIFT_CNT_1_D2_PT_1_IN1 + ); + NlwInverterBlock_SHIFT_CNT_1_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_SHIFT_CNT_1_CLKF_IN0 + ); + NlwInverterBlock_SHIFT_CNT_1_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_SHIFT_CNT_1_CLKF_IN1 + ); + NlwInverterBlock_SHIFT_CNT_1_SETF_IN1 : X_INV + port map ( + I => SHIFT_EN, + O => NlwInverterSignal_SHIFT_CNT_1_SETF_IN1 + ); + NlwInverterBlock_SHIFT_CNT_2_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => SHIFT_CNT_2_RSTF, + O => NlwInverterSignal_SHIFT_CNT_2_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_SHIFT_CNT_2_D_IN0 : X_INV + port map ( + I => SHIFT_CNT_2_D1, + O => NlwInverterSignal_SHIFT_CNT_2_D_IN0 + ); + NlwInverterBlock_SHIFT_CNT_2_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_SHIFT_CNT_2_CLKF_IN0 + ); + NlwInverterBlock_SHIFT_CNT_2_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_SHIFT_CNT_2_CLKF_IN1 + ); + NlwInverterBlock_SHIFT_CNT_2_SETF_IN1 : X_INV + port map ( + I => SHIFT_EN, + O => NlwInverterSignal_SHIFT_CNT_2_SETF_IN1 + ); + NlwInverterBlock_SHIFT_CNT_2_EXP_tsimrenamed_net_IN0 : X_INV + port map ( + I => buf_depth(0), + O => NlwInverterSignal_SHIFT_CNT_2_EXP_tsimrenamed_net_IN0 + ); + NlwInverterBlock_SHIFT_CNT_2_EXP_tsimrenamed_net_IN1 : X_INV + port map ( + I => buf_depth(1), + O => NlwInverterSignal_SHIFT_CNT_2_EXP_tsimrenamed_net_IN1 + ); + NlwInverterBlock_SHIFT_CNT_2_EXP_tsimrenamed_net_IN2 : X_INV + port map ( + I => SHIFT_CNT(1), + O => NlwInverterSignal_SHIFT_CNT_2_EXP_tsimrenamed_net_IN2 + ); + NlwInverterBlock_SHIFT_CNT_2_EXP_tsimrenamed_net_IN3 : X_INV + port map ( + I => SHIFT_CNT(2), + O => NlwInverterSignal_SHIFT_CNT_2_EXP_tsimrenamed_net_IN3 + ); + NlwInverterBlock_SHIFT_CNT_2_EXP_tsimrenamed_net_IN4 : X_INV + port map ( + I => SHIFT_CNT(3), + O => NlwInverterSignal_SHIFT_CNT_2_EXP_tsimrenamed_net_IN4 + ); + NlwInverterBlock_SHIFT_CNT_2_EXP_tsimrenamed_net_IN5 : X_INV + port map ( + I => SHIFT_CNT(4), + O => NlwInverterSignal_SHIFT_CNT_2_EXP_tsimrenamed_net_IN5 + ); + NlwInverterBlock_SHIFT_CNT_3_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => SHIFT_CNT_3_RSTF, + O => NlwInverterSignal_SHIFT_CNT_3_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_SHIFT_CNT_3_D2_PT_1_IN0 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_SHIFT_CNT_3_D2_PT_1_IN0 + ); + NlwInverterBlock_SHIFT_CNT_3_D2_PT_1_IN1 : X_INV + port map ( + I => SHIFT_CNT(0), + O => NlwInverterSignal_SHIFT_CNT_3_D2_PT_1_IN1 + ); + NlwInverterBlock_SHIFT_CNT_3_D2_PT_1_IN2 : X_INV + port map ( + I => SHIFT_CNT(1), + O => NlwInverterSignal_SHIFT_CNT_3_D2_PT_1_IN2 + ); + NlwInverterBlock_SHIFT_CNT_3_D2_PT_1_IN3 : X_INV + port map ( + I => SHIFT_CNT(2), + O => NlwInverterSignal_SHIFT_CNT_3_D2_PT_1_IN3 + ); + NlwInverterBlock_SHIFT_CNT_3_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_SHIFT_CNT_3_CLKF_IN0 + ); + NlwInverterBlock_SHIFT_CNT_3_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_SHIFT_CNT_3_CLKF_IN1 + ); + NlwInverterBlock_SHIFT_CNT_3_SETF_IN1 : X_INV + port map ( + I => SHIFT_EN, + O => NlwInverterSignal_SHIFT_CNT_3_SETF_IN1 + ); + NlwInverterBlock_count_1_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => count_1_RSTF, + O => NlwInverterSignal_count_1_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_count_1_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_count_1_D2_PT_1_IN0 + ); + NlwInverterBlock_count_1_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_PRESCALER_IBUF, + O => NlwInverterSignal_count_1_D2_PT_1_IN1 + ); + NlwInverterBlock_count_1_D2_PT_1_IN2 : X_INV + port map ( + I => count(0), + O => NlwInverterSignal_count_1_D2_PT_1_IN2 + ); + NlwInverterBlock_count_1_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_PRESCALER_IBUF, + O => NlwInverterSignal_count_1_D2_PT_2_IN1 + ); + NlwInverterBlock_count_1_D2_PT_2_IN2 : X_INV + port map ( + I => count(1), + O => NlwInverterSignal_count_1_D2_PT_2_IN2 + ); + NlwInverterBlock_count_1_D2_PT_3_IN0 : X_INV + port map ( + I => LOAD_PRESCALER_IBUF, + O => NlwInverterSignal_count_1_D2_PT_3_IN0 + ); + NlwInverterBlock_count_1_D2_PT_3_IN1 : X_INV + port map ( + I => count(4), + O => NlwInverterSignal_count_1_D2_PT_3_IN1 + ); + NlwInverterBlock_count_1_D2_PT_3_IN2 : X_INV + port map ( + I => count(1), + O => NlwInverterSignal_count_1_D2_PT_3_IN2 + ); + NlwInverterBlock_count_1_D2_PT_3_IN3 : X_INV + port map ( + I => count(2), + O => NlwInverterSignal_count_1_D2_PT_3_IN3 + ); + NlwInverterBlock_count_1_D2_PT_3_IN4 : X_INV + port map ( + I => count(3), + O => NlwInverterSignal_count_1_D2_PT_3_IN4 + ); + NlwInverterBlock_count_1_D2_PT_3_IN5 : X_INV + port map ( + I => count(5), + O => NlwInverterSignal_count_1_D2_PT_3_IN5 + ); + NlwInverterBlock_count_1_RSTF_IN1 : X_INV + port map ( + I => CLK_SCALE(1), + O => NlwInverterSignal_count_1_RSTF_IN1 + ); + NlwInverterBlock_count_2_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => count_2_RSTF, + O => NlwInverterSignal_count_2_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_count_2_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_PRESCALER_IBUF, + O => NlwInverterSignal_count_2_D2_PT_1_IN1 + ); + NlwInverterBlock_count_2_D2_PT_1_IN2 : X_INV + port map ( + I => count(2), + O => NlwInverterSignal_count_2_D2_PT_1_IN2 + ); + NlwInverterBlock_count_2_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_count_2_D2_PT_2_IN0 + ); + NlwInverterBlock_count_2_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_PRESCALER_IBUF, + O => NlwInverterSignal_count_2_D2_PT_2_IN1 + ); + NlwInverterBlock_count_2_D2_PT_2_IN2 : X_INV + port map ( + I => count(0), + O => NlwInverterSignal_count_2_D2_PT_2_IN2 + ); + NlwInverterBlock_count_2_D2_PT_2_IN3 : X_INV + port map ( + I => count(1), + O => NlwInverterSignal_count_2_D2_PT_2_IN3 + ); + NlwInverterBlock_count_2_D2_PT_3_IN0 : X_INV + port map ( + I => LOAD_PRESCALER_IBUF, + O => NlwInverterSignal_count_2_D2_PT_3_IN0 + ); + NlwInverterBlock_count_2_D2_PT_3_IN1 : X_INV + port map ( + I => count(4), + O => NlwInverterSignal_count_2_D2_PT_3_IN1 + ); + NlwInverterBlock_count_2_D2_PT_3_IN2 : X_INV + port map ( + I => count(1), + O => NlwInverterSignal_count_2_D2_PT_3_IN2 + ); + NlwInverterBlock_count_2_D2_PT_3_IN3 : X_INV + port map ( + I => count(2), + O => NlwInverterSignal_count_2_D2_PT_3_IN3 + ); + NlwInverterBlock_count_2_D2_PT_3_IN4 : X_INV + port map ( + I => count(3), + O => NlwInverterSignal_count_2_D2_PT_3_IN4 + ); + NlwInverterBlock_count_2_D2_PT_3_IN5 : X_INV + port map ( + I => count(5), + O => NlwInverterSignal_count_2_D2_PT_3_IN5 + ); + NlwInverterBlock_count_2_RSTF_IN1 : X_INV + port map ( + I => CLK_SCALE(2), + O => NlwInverterSignal_count_2_RSTF_IN1 + ); + NlwInverterBlock_count_3_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => count_3_RSTF, + O => NlwInverterSignal_count_3_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_count_3_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_PRESCALER_IBUF, + O => NlwInverterSignal_count_3_D2_PT_1_IN1 + ); + NlwInverterBlock_count_3_D2_PT_1_IN2 : X_INV + port map ( + I => count(3), + O => NlwInverterSignal_count_3_D2_PT_1_IN2 + ); + NlwInverterBlock_count_3_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_count_3_D2_PT_2_IN0 + ); + NlwInverterBlock_count_3_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_PRESCALER_IBUF, + O => NlwInverterSignal_count_3_D2_PT_2_IN1 + ); + NlwInverterBlock_count_3_D2_PT_2_IN2 : X_INV + port map ( + I => count(0), + O => NlwInverterSignal_count_3_D2_PT_2_IN2 + ); + NlwInverterBlock_count_3_D2_PT_2_IN3 : X_INV + port map ( + I => count(1), + O => NlwInverterSignal_count_3_D2_PT_2_IN3 + ); + NlwInverterBlock_count_3_D2_PT_2_IN4 : X_INV + port map ( + I => count(2), + O => NlwInverterSignal_count_3_D2_PT_2_IN4 + ); + NlwInverterBlock_count_3_D2_PT_3_IN0 : X_INV + port map ( + I => LOAD_PRESCALER_IBUF, + O => NlwInverterSignal_count_3_D2_PT_3_IN0 + ); + NlwInverterBlock_count_3_D2_PT_3_IN1 : X_INV + port map ( + I => count(4), + O => NlwInverterSignal_count_3_D2_PT_3_IN1 + ); + NlwInverterBlock_count_3_D2_PT_3_IN2 : X_INV + port map ( + I => count(1), + O => NlwInverterSignal_count_3_D2_PT_3_IN2 + ); + NlwInverterBlock_count_3_D2_PT_3_IN3 : X_INV + port map ( + I => count(2), + O => NlwInverterSignal_count_3_D2_PT_3_IN3 + ); + NlwInverterBlock_count_3_D2_PT_3_IN4 : X_INV + port map ( + I => count(3), + O => NlwInverterSignal_count_3_D2_PT_3_IN4 + ); + NlwInverterBlock_count_3_D2_PT_3_IN5 : X_INV + port map ( + I => count(5), + O => NlwInverterSignal_count_3_D2_PT_3_IN5 + ); + NlwInverterBlock_count_3_RSTF_IN1 : X_INV + port map ( + I => CLK_SCALE(3), + O => NlwInverterSignal_count_3_RSTF_IN1 + ); + NlwInverterBlock_SHIFT_CNT_4_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => SHIFT_CNT_4_RSTF, + O => NlwInverterSignal_SHIFT_CNT_4_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_SHIFT_CNT_4_D2_PT_1_IN0 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_SHIFT_CNT_4_D2_PT_1_IN0 + ); + NlwInverterBlock_SHIFT_CNT_4_D2_PT_1_IN2 : X_INV + port map ( + I => SHIFT_CNT(0), + O => NlwInverterSignal_SHIFT_CNT_4_D2_PT_1_IN2 + ); + NlwInverterBlock_SHIFT_CNT_4_D2_PT_1_IN3 : X_INV + port map ( + I => SHIFT_CNT(1), + O => NlwInverterSignal_SHIFT_CNT_4_D2_PT_1_IN3 + ); + NlwInverterBlock_SHIFT_CNT_4_D2_PT_1_IN4 : X_INV + port map ( + I => SHIFT_CNT(2), + O => NlwInverterSignal_SHIFT_CNT_4_D2_PT_1_IN4 + ); + NlwInverterBlock_SHIFT_CNT_4_D2_PT_1_IN5 : X_INV + port map ( + I => SHIFT_CNT(3), + O => NlwInverterSignal_SHIFT_CNT_4_D2_PT_1_IN5 + ); + NlwInverterBlock_SHIFT_CNT_4_D2_PT_2_IN0 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_SHIFT_CNT_4_D2_PT_2_IN0 + ); + NlwInverterBlock_SHIFT_CNT_4_D2_PT_2_IN2 : X_INV + port map ( + I => SHIFT_CNT(0), + O => NlwInverterSignal_SHIFT_CNT_4_D2_PT_2_IN2 + ); + NlwInverterBlock_SHIFT_CNT_4_D2_PT_2_IN3 : X_INV + port map ( + I => SHIFT_CNT(1), + O => NlwInverterSignal_SHIFT_CNT_4_D2_PT_2_IN3 + ); + NlwInverterBlock_SHIFT_CNT_4_D2_PT_2_IN4 : X_INV + port map ( + I => SHIFT_CNT(2), + O => NlwInverterSignal_SHIFT_CNT_4_D2_PT_2_IN4 + ); + NlwInverterBlock_SHIFT_CNT_4_D2_PT_2_IN5 : X_INV + port map ( + I => SHIFT_CNT(3), + O => NlwInverterSignal_SHIFT_CNT_4_D2_PT_2_IN5 + ); + NlwInverterBlock_SHIFT_CNT_4_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_SHIFT_CNT_4_CLKF_IN0 + ); + NlwInverterBlock_SHIFT_CNT_4_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_SHIFT_CNT_4_CLKF_IN1 + ); + NlwInverterBlock_SHIFT_CNT_4_SETF_IN1 : X_INV + port map ( + I => SHIFT_EN, + O => NlwInverterSignal_SHIFT_CNT_4_SETF_IN1 + ); + NlwInverterBlock_count_5_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => count_5_RSTF, + O => NlwInverterSignal_count_5_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_count_5_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_PRESCALER_IBUF, + O => NlwInverterSignal_count_5_D2_PT_1_IN1 + ); + NlwInverterBlock_count_5_D2_PT_1_IN3 : X_INV + port map ( + I => CLK_SCALE(5), + O => NlwInverterSignal_count_5_D2_PT_1_IN3 + ); + NlwInverterBlock_count_5_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_PRESCALER_IBUF, + O => NlwInverterSignal_count_5_D2_PT_2_IN1 + ); + NlwInverterBlock_count_5_D2_PT_2_IN2 : X_INV + port map ( + I => count(5), + O => NlwInverterSignal_count_5_D2_PT_2_IN2 + ); + NlwInverterBlock_count_5_RSTF_IN1 : X_INV + port map ( + I => CLK_SCALE(5), + O => NlwInverterSignal_count_5_RSTF_IN1 + ); + NlwInverterBlock_count_5_EXP_tsimrenamed_net_IN0 : X_INV + port map ( + I => LOAD_PRESCALER_IBUF, + O => NlwInverterSignal_count_5_EXP_tsimrenamed_net_IN0 + ); + NlwInverterBlock_writeBufId_0_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_writeBufId_0_CLKF_IN0 + ); + NlwInverterBlock_writeBufId_0_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_writeBufId_0_CLKF_IN1 + ); + NlwInverterBlock_writeBufId_0_CE_IN0 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_writeBufId_0_CE_IN0 + ); + NlwInverterBlock_writeBufId_0_CE_IN1 : X_INV + port map ( + I => SHIFT_CNT(0), + O => NlwInverterSignal_writeBufId_0_CE_IN1 + ); + NlwInverterBlock_writeBufId_0_CE_IN2 : X_INV + port map ( + I => SHIFT_CNT(1), + O => NlwInverterSignal_writeBufId_0_CE_IN2 + ); + NlwInverterBlock_writeBufId_0_CE_IN3 : X_INV + port map ( + I => SHIFT_CNT(2), + O => NlwInverterSignal_writeBufId_0_CE_IN3 + ); + NlwInverterBlock_writeBufId_0_CE_IN4 : X_INV + port map ( + I => SHIFT_CNT(3), + O => NlwInverterSignal_writeBufId_0_CE_IN4 + ); + NlwInverterBlock_writeBufId_0_CE_IN5 : X_INV + port map ( + I => SHIFT_CNT(4), + O => NlwInverterSignal_writeBufId_0_CE_IN5 + ); + NlwInverterBlock_CLK_SCALE_0_EXP_PT_0_IN1 : X_INV + port map ( + I => LOAD_PRESCALER_IBUF, + O => NlwInverterSignal_CLK_SCALE_0_EXP_PT_0_IN1 + ); + NlwInverterBlock_CLK_SCALE_0_EXP_PT_0_IN3 : X_INV + port map ( + I => CLK_SCALE(4), + O => NlwInverterSignal_CLK_SCALE_0_EXP_PT_0_IN3 + ); + NlwInverterBlock_CLK_SCALE_0_EXP_PT_1_IN1 : X_INV + port map ( + I => LOAD_PRESCALER_IBUF, + O => NlwInverterSignal_CLK_SCALE_0_EXP_PT_1_IN1 + ); + NlwInverterBlock_CLK_SCALE_0_EXP_PT_1_IN2 : X_INV + port map ( + I => count(4), + O => NlwInverterSignal_CLK_SCALE_0_EXP_PT_1_IN2 + ); + NlwInverterBlock_REG_0_0_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_0_0_RSTF, + O => NlwInverterSignal_REG_0_0_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_0_0_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_0_CLKF_IN0 + ); + NlwInverterBlock_REG_0_0_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_0_CLKF_IN1 + ); + NlwInverterBlock_REG_0_0_SETF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_0_SETF_IN1 + ); + NlwInverterBlock_REG_0_0_RSTF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_0_RSTF_IN1 + ); + NlwInverterBlock_REG_0_0_RSTF_IN2 : X_INV + port map ( + I => DIN_0_IBUF, + O => NlwInverterSignal_REG_0_0_RSTF_IN2 + ); + NlwInverterBlock_REG_0_0_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_0_EXP_PT_0_IN0 + ); + NlwInverterBlock_REG_0_0_EXP_PT_0_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_0_EXP_PT_0_IN2 + ); + NlwInverterBlock_REG_0_0_EXP_PT_0_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_0_EXP_PT_0_IN4 + ); + NlwInverterBlock_REG_0_0_EXP_PT_0_IN6 : X_INV + port map ( + I => DIN_4_IBUF, + O => NlwInverterSignal_REG_0_0_EXP_PT_0_IN6 + ); + NlwInverterBlock_REG_0_0_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_0_EXP_PT_1_IN0 + ); + NlwInverterBlock_REG_0_0_EXP_PT_1_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_0_EXP_PT_1_IN2 + ); + NlwInverterBlock_REG_0_0_EXP_PT_1_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_0_EXP_PT_1_IN4 + ); + NlwInverterBlock_REG_0_0_EXP_PT_1_IN5 : X_INV + port map ( + I => REG_0_4, + O => NlwInverterSignal_REG_0_0_EXP_PT_1_IN5 + ); + NlwInverterBlock_REG_0_1_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_0_1_RSTF, + O => NlwInverterSignal_REG_0_1_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_0_1_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_1_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_0_1_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_1_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_0_1_D2_PT_1_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_1_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_0_1_D2_PT_1_IN5 : X_INV + port map ( + I => REG_0_1, + O => NlwInverterSignal_REG_0_1_D2_PT_1_IN5 + ); + NlwInverterBlock_REG_0_1_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_1_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_0_1_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_1_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_0_1_D2_PT_2_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_1_D2_PT_2_IN3 + ); + NlwInverterBlock_REG_0_1_D2_PT_2_IN4 : X_INV + port map ( + I => REG_0_0, + O => NlwInverterSignal_REG_0_1_D2_PT_2_IN4 + ); + NlwInverterBlock_REG_0_1_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_1_CLKF_IN0 + ); + NlwInverterBlock_REG_0_1_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_1_CLKF_IN1 + ); + NlwInverterBlock_REG_0_1_SETF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_1_SETF_IN1 + ); + NlwInverterBlock_REG_0_1_RSTF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_1_RSTF_IN1 + ); + NlwInverterBlock_REG_0_1_RSTF_IN2 : X_INV + port map ( + I => DIN_1_IBUF, + O => NlwInverterSignal_REG_0_1_RSTF_IN2 + ); + NlwInverterBlock_REG_0_10_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_0_10_RSTF, + O => NlwInverterSignal_REG_0_10_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_0_10_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_10_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_0_10_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_10_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_0_10_D2_PT_1_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_10_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_0_10_D2_PT_1_IN5 : X_INV + port map ( + I => REG_0_9, + O => NlwInverterSignal_REG_0_10_D2_PT_1_IN5 + ); + NlwInverterBlock_REG_0_10_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_10_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_0_10_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_10_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_0_10_D2_PT_2_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_10_D2_PT_2_IN3 + ); + NlwInverterBlock_REG_0_10_D2_PT_2_IN4 : X_INV + port map ( + I => REG_0_10, + O => NlwInverterSignal_REG_0_10_D2_PT_2_IN4 + ); + NlwInverterBlock_REG_0_10_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_10_CLKF_IN0 + ); + NlwInverterBlock_REG_0_10_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_10_CLKF_IN1 + ); + NlwInverterBlock_REG_0_10_SETF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_10_SETF_IN1 + ); + NlwInverterBlock_REG_0_10_RSTF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_10_RSTF_IN1 + ); + NlwInverterBlock_REG_0_10_RSTF_IN2 : X_INV + port map ( + I => DIN_10_IBUF, + O => NlwInverterSignal_REG_0_10_RSTF_IN2 + ); + NlwInverterBlock_REG_0_11_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_0_11_RSTF, + O => NlwInverterSignal_REG_0_11_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_0_11_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_11_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_0_11_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_11_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_0_11_D2_PT_1_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_11_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_0_11_D2_PT_1_IN5 : X_INV + port map ( + I => REG_0_11, + O => NlwInverterSignal_REG_0_11_D2_PT_1_IN5 + ); + NlwInverterBlock_REG_0_11_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_11_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_0_11_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_11_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_0_11_D2_PT_2_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_11_D2_PT_2_IN3 + ); + NlwInverterBlock_REG_0_11_D2_PT_2_IN4 : X_INV + port map ( + I => REG_0_10, + O => NlwInverterSignal_REG_0_11_D2_PT_2_IN4 + ); + NlwInverterBlock_REG_0_11_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_11_CLKF_IN0 + ); + NlwInverterBlock_REG_0_11_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_11_CLKF_IN1 + ); + NlwInverterBlock_REG_0_11_SETF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_11_SETF_IN1 + ); + NlwInverterBlock_REG_0_11_RSTF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_11_RSTF_IN1 + ); + NlwInverterBlock_REG_0_11_RSTF_IN2 : X_INV + port map ( + I => DIN_11_IBUF, + O => NlwInverterSignal_REG_0_11_RSTF_IN2 + ); + NlwInverterBlock_REG_0_12_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_0_12_RSTF, + O => NlwInverterSignal_REG_0_12_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_0_12_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_12_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_0_12_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_12_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_0_12_D2_PT_1_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_12_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_0_12_D2_PT_1_IN5 : X_INV + port map ( + I => REG_0_12, + O => NlwInverterSignal_REG_0_12_D2_PT_1_IN5 + ); + NlwInverterBlock_REG_0_12_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_12_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_0_12_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_12_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_0_12_D2_PT_2_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_12_D2_PT_2_IN3 + ); + NlwInverterBlock_REG_0_12_D2_PT_2_IN4 : X_INV + port map ( + I => REG_0_11, + O => NlwInverterSignal_REG_0_12_D2_PT_2_IN4 + ); + NlwInverterBlock_REG_0_12_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_12_CLKF_IN0 + ); + NlwInverterBlock_REG_0_12_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_12_CLKF_IN1 + ); + NlwInverterBlock_REG_0_12_SETF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_12_SETF_IN1 + ); + NlwInverterBlock_REG_0_12_RSTF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_12_RSTF_IN1 + ); + NlwInverterBlock_REG_0_12_RSTF_IN2 : X_INV + port map ( + I => DIN_12_IBUF, + O => NlwInverterSignal_REG_0_12_RSTF_IN2 + ); + NlwInverterBlock_REG_0_13_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_0_13_RSTF, + O => NlwInverterSignal_REG_0_13_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_0_13_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_13_CLKF_IN0 + ); + NlwInverterBlock_REG_0_13_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_13_CLKF_IN1 + ); + NlwInverterBlock_REG_0_13_SETF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_13_SETF_IN1 + ); + NlwInverterBlock_REG_0_13_RSTF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_13_RSTF_IN1 + ); + NlwInverterBlock_REG_0_13_RSTF_IN2 : X_INV + port map ( + I => DIN_13_IBUF, + O => NlwInverterSignal_REG_0_13_RSTF_IN2 + ); + NlwInverterBlock_REG_0_13_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_13_EXP_PT_0_IN0 + ); + NlwInverterBlock_REG_0_13_EXP_PT_0_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_13_EXP_PT_0_IN2 + ); + NlwInverterBlock_REG_0_13_EXP_PT_0_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_13_EXP_PT_0_IN4 + ); + NlwInverterBlock_REG_0_13_EXP_PT_0_IN6 : X_INV + port map ( + I => REG_0_12, + O => NlwInverterSignal_REG_0_13_EXP_PT_0_IN6 + ); + NlwInverterBlock_REG_0_13_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_13_EXP_PT_1_IN0 + ); + NlwInverterBlock_REG_0_13_EXP_PT_1_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_13_EXP_PT_1_IN2 + ); + NlwInverterBlock_REG_0_13_EXP_PT_1_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_13_EXP_PT_1_IN4 + ); + NlwInverterBlock_REG_0_13_EXP_PT_1_IN5 : X_INV + port map ( + I => DIN_12_IBUF, + O => NlwInverterSignal_REG_0_13_EXP_PT_1_IN5 + ); + NlwInverterBlock_REG_0_14_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_0_14_RSTF, + O => NlwInverterSignal_REG_0_14_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_0_14_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_14_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_0_14_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_14_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_0_14_D2_PT_1_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_14_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_0_14_D2_PT_1_IN5 : X_INV + port map ( + I => REG_0_14, + O => NlwInverterSignal_REG_0_14_D2_PT_1_IN5 + ); + NlwInverterBlock_REG_0_14_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_14_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_0_14_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_14_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_0_14_D2_PT_2_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_14_D2_PT_2_IN3 + ); + NlwInverterBlock_REG_0_14_D2_PT_2_IN4 : X_INV + port map ( + I => REG_0_13, + O => NlwInverterSignal_REG_0_14_D2_PT_2_IN4 + ); + NlwInverterBlock_REG_0_14_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_14_CLKF_IN0 + ); + NlwInverterBlock_REG_0_14_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_14_CLKF_IN1 + ); + NlwInverterBlock_REG_0_14_SETF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_14_SETF_IN1 + ); + NlwInverterBlock_REG_0_14_RSTF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_14_RSTF_IN1 + ); + NlwInverterBlock_REG_0_14_RSTF_IN2 : X_INV + port map ( + I => DIN_14_IBUF, + O => NlwInverterSignal_REG_0_14_RSTF_IN2 + ); + NlwInverterBlock_REG_0_15_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_0_15_RSTF, + O => NlwInverterSignal_REG_0_15_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_0_15_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_15_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_0_15_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_15_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_0_15_D2_PT_1_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_15_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_0_15_D2_PT_1_IN4 : X_INV + port map ( + I => REG_0_14, + O => NlwInverterSignal_REG_0_15_D2_PT_1_IN4 + ); + NlwInverterBlock_REG_0_15_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_15_CLKF_IN0 + ); + NlwInverterBlock_REG_0_15_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_15_CLKF_IN1 + ); + NlwInverterBlock_REG_0_15_SETF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_15_SETF_IN1 + ); + NlwInverterBlock_REG_0_15_RSTF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_15_RSTF_IN1 + ); + NlwInverterBlock_REG_0_15_RSTF_IN2 : X_INV + port map ( + I => DIN_15_IBUF, + O => NlwInverterSignal_REG_0_15_RSTF_IN2 + ); + NlwInverterBlock_REG_0_15_EXP_tsimrenamed_net_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_15_EXP_tsimrenamed_net_IN0 + ); + NlwInverterBlock_REG_0_15_EXP_tsimrenamed_net_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_15_EXP_tsimrenamed_net_IN2 + ); + NlwInverterBlock_REG_0_15_EXP_tsimrenamed_net_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_15_EXP_tsimrenamed_net_IN4 + ); + NlwInverterBlock_REG_0_15_EXP_tsimrenamed_net_IN5 : X_INV + port map ( + I => REG_0_16, + O => NlwInverterSignal_REG_0_15_EXP_tsimrenamed_net_IN5 + ); + NlwInverterBlock_REG_0_16_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_0_16_RSTF, + O => NlwInverterSignal_REG_0_16_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_0_16_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_16_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_0_16_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_16_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_0_16_D2_PT_2_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_16_D2_PT_2_IN3 + ); + NlwInverterBlock_REG_0_16_D2_PT_2_IN5 : X_INV + port map ( + I => REG_0_16, + O => NlwInverterSignal_REG_0_16_D2_PT_2_IN5 + ); + NlwInverterBlock_REG_0_16_D2_PT_3_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_16_D2_PT_3_IN0 + ); + NlwInverterBlock_REG_0_16_D2_PT_3_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_16_D2_PT_3_IN1 + ); + NlwInverterBlock_REG_0_16_D2_PT_3_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_16_D2_PT_3_IN3 + ); + NlwInverterBlock_REG_0_16_D2_PT_3_IN4 : X_INV + port map ( + I => REG_0_15, + O => NlwInverterSignal_REG_0_16_D2_PT_3_IN4 + ); + NlwInverterBlock_REG_0_16_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_16_CLKF_IN0 + ); + NlwInverterBlock_REG_0_16_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_16_CLKF_IN1 + ); + NlwInverterBlock_REG_0_16_SETF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_16_SETF_IN1 + ); + NlwInverterBlock_REG_0_16_RSTF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_16_RSTF_IN1 + ); + NlwInverterBlock_REG_0_16_RSTF_IN2 : X_INV + port map ( + I => DIN_16_IBUF, + O => NlwInverterSignal_REG_0_16_RSTF_IN2 + ); + NlwInverterBlock_REG_0_17_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_0_17_RSTF, + O => NlwInverterSignal_REG_0_17_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_0_17_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_17_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_0_17_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_17_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_0_17_D2_PT_1_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_17_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_0_17_D2_PT_1_IN4 : X_INV + port map ( + I => REG_0_16, + O => NlwInverterSignal_REG_0_17_D2_PT_1_IN4 + ); + NlwInverterBlock_REG_0_17_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_17_CLKF_IN0 + ); + NlwInverterBlock_REG_0_17_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_17_CLKF_IN1 + ); + NlwInverterBlock_REG_0_17_SETF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_17_SETF_IN1 + ); + NlwInverterBlock_REG_0_17_RSTF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_17_RSTF_IN1 + ); + NlwInverterBlock_REG_0_17_RSTF_IN2 : X_INV + port map ( + I => DIN_17_IBUF, + O => NlwInverterSignal_REG_0_17_RSTF_IN2 + ); + NlwInverterBlock_REG_0_17_EXP_tsimrenamed_net_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_17_EXP_tsimrenamed_net_IN0 + ); + NlwInverterBlock_REG_0_17_EXP_tsimrenamed_net_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_17_EXP_tsimrenamed_net_IN2 + ); + NlwInverterBlock_REG_0_17_EXP_tsimrenamed_net_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_17_EXP_tsimrenamed_net_IN4 + ); + NlwInverterBlock_REG_0_17_EXP_tsimrenamed_net_IN6 : X_INV + port map ( + I => DIN_16_IBUF, + O => NlwInverterSignal_REG_0_17_EXP_tsimrenamed_net_IN6 + ); + NlwInverterBlock_REG_0_18_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_0_18_RSTF, + O => NlwInverterSignal_REG_0_18_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_0_18_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_18_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_0_18_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_18_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_0_18_D2_PT_1_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_18_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_0_18_D2_PT_1_IN5 : X_INV + port map ( + I => REG_0_18, + O => NlwInverterSignal_REG_0_18_D2_PT_1_IN5 + ); + NlwInverterBlock_REG_0_18_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_18_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_0_18_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_18_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_0_18_D2_PT_2_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_18_D2_PT_2_IN3 + ); + NlwInverterBlock_REG_0_18_D2_PT_2_IN4 : X_INV + port map ( + I => REG_0_17, + O => NlwInverterSignal_REG_0_18_D2_PT_2_IN4 + ); + NlwInverterBlock_REG_0_18_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_18_CLKF_IN0 + ); + NlwInverterBlock_REG_0_18_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_18_CLKF_IN1 + ); + NlwInverterBlock_REG_0_18_SETF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_18_SETF_IN1 + ); + NlwInverterBlock_REG_0_18_RSTF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_18_RSTF_IN1 + ); + NlwInverterBlock_REG_0_18_RSTF_IN2 : X_INV + port map ( + I => DIN_18_IBUF, + O => NlwInverterSignal_REG_0_18_RSTF_IN2 + ); + NlwInverterBlock_REG_0_19_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_0_19_RSTF, + O => NlwInverterSignal_REG_0_19_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_0_19_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_19_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_0_19_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_19_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_0_19_D2_PT_1_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_19_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_0_19_D2_PT_1_IN5 : X_INV + port map ( + I => REG_0_19, + O => NlwInverterSignal_REG_0_19_D2_PT_1_IN5 + ); + NlwInverterBlock_REG_0_19_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_19_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_0_19_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_19_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_0_19_D2_PT_2_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_19_D2_PT_2_IN3 + ); + NlwInverterBlock_REG_0_19_D2_PT_2_IN4 : X_INV + port map ( + I => REG_0_18, + O => NlwInverterSignal_REG_0_19_D2_PT_2_IN4 + ); + NlwInverterBlock_REG_0_19_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_19_CLKF_IN0 + ); + NlwInverterBlock_REG_0_19_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_19_CLKF_IN1 + ); + NlwInverterBlock_REG_0_19_SETF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_19_SETF_IN1 + ); + NlwInverterBlock_REG_0_19_RSTF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_19_RSTF_IN1 + ); + NlwInverterBlock_REG_0_19_RSTF_IN2 : X_INV + port map ( + I => DIN_19_IBUF, + O => NlwInverterSignal_REG_0_19_RSTF_IN2 + ); + NlwInverterBlock_REG_0_2_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_0_2_RSTF, + O => NlwInverterSignal_REG_0_2_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_0_2_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_2_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_0_2_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_2_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_0_2_D2_PT_1_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_2_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_0_2_D2_PT_1_IN5 : X_INV + port map ( + I => REG_0_2, + O => NlwInverterSignal_REG_0_2_D2_PT_1_IN5 + ); + NlwInverterBlock_REG_0_2_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_2_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_0_2_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_2_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_0_2_D2_PT_2_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_2_D2_PT_2_IN3 + ); + NlwInverterBlock_REG_0_2_D2_PT_2_IN4 : X_INV + port map ( + I => REG_0_1, + O => NlwInverterSignal_REG_0_2_D2_PT_2_IN4 + ); + NlwInverterBlock_REG_0_2_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_2_CLKF_IN0 + ); + NlwInverterBlock_REG_0_2_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_2_CLKF_IN1 + ); + NlwInverterBlock_REG_0_2_SETF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_2_SETF_IN1 + ); + NlwInverterBlock_REG_0_2_RSTF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_2_RSTF_IN1 + ); + NlwInverterBlock_REG_0_2_RSTF_IN2 : X_INV + port map ( + I => DIN_2_IBUF, + O => NlwInverterSignal_REG_0_2_RSTF_IN2 + ); + NlwInverterBlock_REG_0_20_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_0_20_RSTF, + O => NlwInverterSignal_REG_0_20_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_0_20_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_20_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_0_20_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_20_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_0_20_D2_PT_1_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_20_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_0_20_D2_PT_1_IN5 : X_INV + port map ( + I => REG_0_20, + O => NlwInverterSignal_REG_0_20_D2_PT_1_IN5 + ); + NlwInverterBlock_REG_0_20_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_20_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_0_20_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_20_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_0_20_D2_PT_2_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_20_D2_PT_2_IN3 + ); + NlwInverterBlock_REG_0_20_D2_PT_2_IN4 : X_INV + port map ( + I => REG_0_19, + O => NlwInverterSignal_REG_0_20_D2_PT_2_IN4 + ); + NlwInverterBlock_REG_0_20_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_20_CLKF_IN0 + ); + NlwInverterBlock_REG_0_20_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_20_CLKF_IN1 + ); + NlwInverterBlock_REG_0_20_SETF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_20_SETF_IN1 + ); + NlwInverterBlock_REG_0_20_RSTF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_20_RSTF_IN1 + ); + NlwInverterBlock_REG_0_20_RSTF_IN2 : X_INV + port map ( + I => DIN_20_IBUF, + O => NlwInverterSignal_REG_0_20_RSTF_IN2 + ); + NlwInverterBlock_REG_0_21_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_0_21_RSTF, + O => NlwInverterSignal_REG_0_21_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_0_21_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_21_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_0_21_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_21_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_0_21_D2_PT_1_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_21_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_0_21_D2_PT_1_IN4 : X_INV + port map ( + I => REG_0_20, + O => NlwInverterSignal_REG_0_21_D2_PT_1_IN4 + ); + NlwInverterBlock_REG_0_21_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_21_CLKF_IN0 + ); + NlwInverterBlock_REG_0_21_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_21_CLKF_IN1 + ); + NlwInverterBlock_REG_0_21_SETF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_21_SETF_IN1 + ); + NlwInverterBlock_REG_0_21_RSTF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_21_RSTF_IN1 + ); + NlwInverterBlock_REG_0_21_RSTF_IN2 : X_INV + port map ( + I => DIN_21_IBUF, + O => NlwInverterSignal_REG_0_21_RSTF_IN2 + ); + NlwInverterBlock_REG_0_21_EXP_tsimrenamed_net_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_21_EXP_tsimrenamed_net_IN0 + ); + NlwInverterBlock_REG_0_21_EXP_tsimrenamed_net_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_21_EXP_tsimrenamed_net_IN2 + ); + NlwInverterBlock_REG_0_21_EXP_tsimrenamed_net_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_21_EXP_tsimrenamed_net_IN4 + ); + NlwInverterBlock_REG_0_21_EXP_tsimrenamed_net_IN5 : X_INV + port map ( + I => REG_0_22, + O => NlwInverterSignal_REG_0_21_EXP_tsimrenamed_net_IN5 + ); + NlwInverterBlock_REG_0_22_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_0_22_RSTF, + O => NlwInverterSignal_REG_0_22_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_0_22_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_22_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_0_22_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_22_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_0_22_D2_PT_2_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_22_D2_PT_2_IN3 + ); + NlwInverterBlock_REG_0_22_D2_PT_2_IN5 : X_INV + port map ( + I => REG_0_22, + O => NlwInverterSignal_REG_0_22_D2_PT_2_IN5 + ); + NlwInverterBlock_REG_0_22_D2_PT_3_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_22_D2_PT_3_IN0 + ); + NlwInverterBlock_REG_0_22_D2_PT_3_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_22_D2_PT_3_IN1 + ); + NlwInverterBlock_REG_0_22_D2_PT_3_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_22_D2_PT_3_IN3 + ); + NlwInverterBlock_REG_0_22_D2_PT_3_IN4 : X_INV + port map ( + I => REG_0_21, + O => NlwInverterSignal_REG_0_22_D2_PT_3_IN4 + ); + NlwInverterBlock_REG_0_22_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_22_CLKF_IN0 + ); + NlwInverterBlock_REG_0_22_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_22_CLKF_IN1 + ); + NlwInverterBlock_REG_0_22_SETF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_22_SETF_IN1 + ); + NlwInverterBlock_REG_0_22_RSTF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_22_RSTF_IN1 + ); + NlwInverterBlock_REG_0_22_RSTF_IN2 : X_INV + port map ( + I => DIN_22_IBUF, + O => NlwInverterSignal_REG_0_22_RSTF_IN2 + ); + NlwInverterBlock_REG_0_23_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_0_23_RSTF, + O => NlwInverterSignal_REG_0_23_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_0_23_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_23_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_0_23_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_23_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_0_23_D2_PT_1_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_23_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_0_23_D2_PT_1_IN4 : X_INV + port map ( + I => REG_0_22, + O => NlwInverterSignal_REG_0_23_D2_PT_1_IN4 + ); + NlwInverterBlock_REG_0_23_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_23_CLKF_IN0 + ); + NlwInverterBlock_REG_0_23_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_23_CLKF_IN1 + ); + NlwInverterBlock_REG_0_23_SETF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_23_SETF_IN1 + ); + NlwInverterBlock_REG_0_23_RSTF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_23_RSTF_IN1 + ); + NlwInverterBlock_REG_0_23_RSTF_IN2 : X_INV + port map ( + I => DIN_23_IBUF, + O => NlwInverterSignal_REG_0_23_RSTF_IN2 + ); + NlwInverterBlock_REG_0_23_EXP_tsimrenamed_net_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_23_EXP_tsimrenamed_net_IN0 + ); + NlwInverterBlock_REG_0_23_EXP_tsimrenamed_net_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_23_EXP_tsimrenamed_net_IN2 + ); + NlwInverterBlock_REG_0_23_EXP_tsimrenamed_net_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_23_EXP_tsimrenamed_net_IN4 + ); + NlwInverterBlock_REG_0_23_EXP_tsimrenamed_net_IN6 : X_INV + port map ( + I => DIN_22_IBUF, + O => NlwInverterSignal_REG_0_23_EXP_tsimrenamed_net_IN6 + ); + NlwInverterBlock_REG_0_24_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_0_24_RSTF, + O => NlwInverterSignal_REG_0_24_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_0_24_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_24_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_0_24_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_24_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_0_24_D2_PT_1_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_24_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_0_24_D2_PT_1_IN5 : X_INV + port map ( + I => REG_0_24, + O => NlwInverterSignal_REG_0_24_D2_PT_1_IN5 + ); + NlwInverterBlock_REG_0_24_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_24_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_0_24_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_24_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_0_24_D2_PT_2_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_24_D2_PT_2_IN3 + ); + NlwInverterBlock_REG_0_24_D2_PT_2_IN4 : X_INV + port map ( + I => REG_0_23, + O => NlwInverterSignal_REG_0_24_D2_PT_2_IN4 + ); + NlwInverterBlock_REG_0_24_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_24_CLKF_IN0 + ); + NlwInverterBlock_REG_0_24_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_24_CLKF_IN1 + ); + NlwInverterBlock_REG_0_24_SETF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_24_SETF_IN1 + ); + NlwInverterBlock_REG_0_24_RSTF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_24_RSTF_IN1 + ); + NlwInverterBlock_REG_0_24_RSTF_IN2 : X_INV + port map ( + I => DIN_24_IBUF, + O => NlwInverterSignal_REG_0_24_RSTF_IN2 + ); + NlwInverterBlock_REG_0_25_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_0_25_RSTF, + O => NlwInverterSignal_REG_0_25_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_0_25_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_25_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_0_25_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_25_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_0_25_D2_PT_1_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_25_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_0_25_D2_PT_1_IN5 : X_INV + port map ( + I => REG_0_25, + O => NlwInverterSignal_REG_0_25_D2_PT_1_IN5 + ); + NlwInverterBlock_REG_0_25_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_25_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_0_25_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_25_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_0_25_D2_PT_2_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_25_D2_PT_2_IN3 + ); + NlwInverterBlock_REG_0_25_D2_PT_2_IN4 : X_INV + port map ( + I => REG_0_24, + O => NlwInverterSignal_REG_0_25_D2_PT_2_IN4 + ); + NlwInverterBlock_REG_0_25_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_25_CLKF_IN0 + ); + NlwInverterBlock_REG_0_25_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_25_CLKF_IN1 + ); + NlwInverterBlock_REG_0_25_SETF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_25_SETF_IN1 + ); + NlwInverterBlock_REG_0_25_RSTF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_25_RSTF_IN1 + ); + NlwInverterBlock_REG_0_25_RSTF_IN2 : X_INV + port map ( + I => DIN_25_IBUF, + O => NlwInverterSignal_REG_0_25_RSTF_IN2 + ); + NlwInverterBlock_REG_0_26_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_0_26_RSTF, + O => NlwInverterSignal_REG_0_26_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_0_26_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_26_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_0_26_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_26_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_0_26_D2_PT_1_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_26_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_0_26_D2_PT_1_IN5 : X_INV + port map ( + I => REG_0_26, + O => NlwInverterSignal_REG_0_26_D2_PT_1_IN5 + ); + NlwInverterBlock_REG_0_26_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_26_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_0_26_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_26_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_0_26_D2_PT_2_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_26_D2_PT_2_IN3 + ); + NlwInverterBlock_REG_0_26_D2_PT_2_IN4 : X_INV + port map ( + I => REG_0_25, + O => NlwInverterSignal_REG_0_26_D2_PT_2_IN4 + ); + NlwInverterBlock_REG_0_26_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_26_CLKF_IN0 + ); + NlwInverterBlock_REG_0_26_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_26_CLKF_IN1 + ); + NlwInverterBlock_REG_0_26_SETF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_26_SETF_IN1 + ); + NlwInverterBlock_REG_0_26_RSTF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_26_RSTF_IN1 + ); + NlwInverterBlock_REG_0_26_RSTF_IN2 : X_INV + port map ( + I => DIN_26_IBUF, + O => NlwInverterSignal_REG_0_26_RSTF_IN2 + ); + NlwInverterBlock_REG_0_27_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_0_27_RSTF, + O => NlwInverterSignal_REG_0_27_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_0_27_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_27_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_0_27_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_27_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_0_27_D2_PT_1_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_27_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_0_27_D2_PT_1_IN4 : X_INV + port map ( + I => REG_0_26, + O => NlwInverterSignal_REG_0_27_D2_PT_1_IN4 + ); + NlwInverterBlock_REG_0_27_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_27_CLKF_IN0 + ); + NlwInverterBlock_REG_0_27_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_27_CLKF_IN1 + ); + NlwInverterBlock_REG_0_27_SETF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_27_SETF_IN1 + ); + NlwInverterBlock_REG_0_27_RSTF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_27_RSTF_IN1 + ); + NlwInverterBlock_REG_0_27_RSTF_IN2 : X_INV + port map ( + I => DIN_27_IBUF, + O => NlwInverterSignal_REG_0_27_RSTF_IN2 + ); + NlwInverterBlock_REG_0_27_EXP_tsimrenamed_net_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_27_EXP_tsimrenamed_net_IN0 + ); + NlwInverterBlock_REG_0_27_EXP_tsimrenamed_net_IN6 : X_INV + port map ( + I => REG_1_23, + O => NlwInverterSignal_REG_0_27_EXP_tsimrenamed_net_IN6 + ); + NlwInverterBlock_REG_0_28_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_0_28_RSTF, + O => NlwInverterSignal_REG_0_28_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_0_28_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_28_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_0_28_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_28_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_0_28_D2_PT_1_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_28_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_0_28_D2_PT_1_IN5 : X_INV + port map ( + I => REG_0_28, + O => NlwInverterSignal_REG_0_28_D2_PT_1_IN5 + ); + NlwInverterBlock_REG_0_28_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_28_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_0_28_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_28_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_0_28_D2_PT_2_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_28_D2_PT_2_IN3 + ); + NlwInverterBlock_REG_0_28_D2_PT_2_IN4 : X_INV + port map ( + I => REG_0_27, + O => NlwInverterSignal_REG_0_28_D2_PT_2_IN4 + ); + NlwInverterBlock_REG_0_28_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_28_CLKF_IN0 + ); + NlwInverterBlock_REG_0_28_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_28_CLKF_IN1 + ); + NlwInverterBlock_REG_0_28_SETF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_28_SETF_IN1 + ); + NlwInverterBlock_REG_0_28_RSTF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_28_RSTF_IN1 + ); + NlwInverterBlock_REG_0_28_RSTF_IN2 : X_INV + port map ( + I => DIN_28_IBUF, + O => NlwInverterSignal_REG_0_28_RSTF_IN2 + ); + NlwInverterBlock_REG_0_29_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_0_29_RSTF, + O => NlwInverterSignal_REG_0_29_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_0_29_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_29_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_0_29_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_29_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_0_29_D2_PT_1_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_29_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_0_29_D2_PT_1_IN5 : X_INV + port map ( + I => REG_0_29, + O => NlwInverterSignal_REG_0_29_D2_PT_1_IN5 + ); + NlwInverterBlock_REG_0_29_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_29_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_0_29_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_29_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_0_29_D2_PT_2_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_29_D2_PT_2_IN3 + ); + NlwInverterBlock_REG_0_29_D2_PT_2_IN4 : X_INV + port map ( + I => REG_0_28, + O => NlwInverterSignal_REG_0_29_D2_PT_2_IN4 + ); + NlwInverterBlock_REG_0_29_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_29_CLKF_IN0 + ); + NlwInverterBlock_REG_0_29_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_29_CLKF_IN1 + ); + NlwInverterBlock_REG_0_29_SETF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_29_SETF_IN1 + ); + NlwInverterBlock_REG_0_29_RSTF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_29_RSTF_IN1 + ); + NlwInverterBlock_REG_0_29_RSTF_IN2 : X_INV + port map ( + I => DIN_29_IBUF, + O => NlwInverterSignal_REG_0_29_RSTF_IN2 + ); + NlwInverterBlock_REG_0_3_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_0_3_RSTF, + O => NlwInverterSignal_REG_0_3_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_0_3_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_3_CLKF_IN0 + ); + NlwInverterBlock_REG_0_3_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_3_CLKF_IN1 + ); + NlwInverterBlock_REG_0_3_SETF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_3_SETF_IN1 + ); + NlwInverterBlock_REG_0_3_RSTF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_3_RSTF_IN1 + ); + NlwInverterBlock_REG_0_3_RSTF_IN2 : X_INV + port map ( + I => DIN_3_IBUF, + O => NlwInverterSignal_REG_0_3_RSTF_IN2 + ); + NlwInverterBlock_REG_0_3_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_3_EXP_PT_0_IN0 + ); + NlwInverterBlock_REG_0_3_EXP_PT_0_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_3_EXP_PT_0_IN2 + ); + NlwInverterBlock_REG_0_3_EXP_PT_0_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_3_EXP_PT_0_IN4 + ); + NlwInverterBlock_REG_0_3_EXP_PT_0_IN6 : X_INV + port map ( + I => REG_0_2, + O => NlwInverterSignal_REG_0_3_EXP_PT_0_IN6 + ); + NlwInverterBlock_REG_0_3_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_3_EXP_PT_1_IN0 + ); + NlwInverterBlock_REG_0_3_EXP_PT_1_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_3_EXP_PT_1_IN2 + ); + NlwInverterBlock_REG_0_3_EXP_PT_1_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_3_EXP_PT_1_IN4 + ); + NlwInverterBlock_REG_0_3_EXP_PT_1_IN5 : X_INV + port map ( + I => DIN_2_IBUF, + O => NlwInverterSignal_REG_0_3_EXP_PT_1_IN5 + ); + NlwInverterBlock_REG_0_30_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_0_30_RSTF, + O => NlwInverterSignal_REG_0_30_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_0_30_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_30_CLKF_IN0 + ); + NlwInverterBlock_REG_0_30_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_30_CLKF_IN1 + ); + NlwInverterBlock_REG_0_30_SETF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_30_SETF_IN1 + ); + NlwInverterBlock_REG_0_30_RSTF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_30_RSTF_IN1 + ); + NlwInverterBlock_REG_0_30_RSTF_IN2 : X_INV + port map ( + I => DIN_30_IBUF, + O => NlwInverterSignal_REG_0_30_RSTF_IN2 + ); + NlwInverterBlock_REG_0_30_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_30_EXP_PT_0_IN0 + ); + NlwInverterBlock_REG_0_30_EXP_PT_0_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_30_EXP_PT_0_IN2 + ); + NlwInverterBlock_REG_0_30_EXP_PT_0_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_30_EXP_PT_0_IN4 + ); + NlwInverterBlock_REG_0_30_EXP_PT_0_IN6 : X_INV + port map ( + I => REG_0_29, + O => NlwInverterSignal_REG_0_30_EXP_PT_0_IN6 + ); + NlwInverterBlock_REG_0_30_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_30_EXP_PT_1_IN0 + ); + NlwInverterBlock_REG_0_30_EXP_PT_1_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_30_EXP_PT_1_IN2 + ); + NlwInverterBlock_REG_0_30_EXP_PT_1_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_30_EXP_PT_1_IN4 + ); + NlwInverterBlock_REG_0_30_EXP_PT_1_IN5 : X_INV + port map ( + I => DIN_29_IBUF, + O => NlwInverterSignal_REG_0_30_EXP_PT_1_IN5 + ); + NlwInverterBlock_REG_0_31_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_0_31_RSTF, + O => NlwInverterSignal_REG_0_31_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_0_31_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_31_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_0_31_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_31_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_0_31_D2_PT_1_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_31_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_0_31_D2_PT_1_IN5 : X_INV + port map ( + I => REG_0_31, + O => NlwInverterSignal_REG_0_31_D2_PT_1_IN5 + ); + NlwInverterBlock_REG_0_31_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_31_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_0_31_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_31_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_0_31_D2_PT_2_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_31_D2_PT_2_IN3 + ); + NlwInverterBlock_REG_0_31_D2_PT_2_IN4 : X_INV + port map ( + I => REG_0_30, + O => NlwInverterSignal_REG_0_31_D2_PT_2_IN4 + ); + NlwInverterBlock_REG_0_31_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_31_CLKF_IN0 + ); + NlwInverterBlock_REG_0_31_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_31_CLKF_IN1 + ); + NlwInverterBlock_REG_0_31_SETF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_31_SETF_IN1 + ); + NlwInverterBlock_REG_0_31_RSTF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_31_RSTF_IN1 + ); + NlwInverterBlock_REG_0_31_RSTF_IN2 : X_INV + port map ( + I => DIN_31_IBUF, + O => NlwInverterSignal_REG_0_31_RSTF_IN2 + ); + NlwInverterBlock_REG_0_4_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_0_4_RSTF, + O => NlwInverterSignal_REG_0_4_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_0_4_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_4_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_0_4_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_4_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_0_4_D2_PT_1_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_4_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_0_4_D2_PT_1_IN5 : X_INV + port map ( + I => REG_0_3, + O => NlwInverterSignal_REG_0_4_D2_PT_1_IN5 + ); + NlwInverterBlock_REG_0_4_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_4_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_0_4_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_4_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_0_4_D2_PT_2_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_4_D2_PT_2_IN3 + ); + NlwInverterBlock_REG_0_4_D2_PT_2_IN4 : X_INV + port map ( + I => REG_0_4, + O => NlwInverterSignal_REG_0_4_D2_PT_2_IN4 + ); + NlwInverterBlock_REG_0_4_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_4_CLKF_IN0 + ); + NlwInverterBlock_REG_0_4_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_4_CLKF_IN1 + ); + NlwInverterBlock_REG_0_4_SETF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_4_SETF_IN1 + ); + NlwInverterBlock_REG_0_4_RSTF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_4_RSTF_IN1 + ); + NlwInverterBlock_REG_0_4_RSTF_IN2 : X_INV + port map ( + I => DIN_4_IBUF, + O => NlwInverterSignal_REG_0_4_RSTF_IN2 + ); + NlwInverterBlock_REG_0_5_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_0_5_RSTF, + O => NlwInverterSignal_REG_0_5_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_0_5_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_5_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_0_5_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_5_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_0_5_D2_PT_1_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_5_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_0_5_D2_PT_1_IN5 : X_INV + port map ( + I => REG_0_5, + O => NlwInverterSignal_REG_0_5_D2_PT_1_IN5 + ); + NlwInverterBlock_REG_0_5_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_5_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_0_5_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_5_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_0_5_D2_PT_2_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_5_D2_PT_2_IN3 + ); + NlwInverterBlock_REG_0_5_D2_PT_2_IN4 : X_INV + port map ( + I => REG_0_4, + O => NlwInverterSignal_REG_0_5_D2_PT_2_IN4 + ); + NlwInverterBlock_REG_0_5_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_5_CLKF_IN0 + ); + NlwInverterBlock_REG_0_5_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_5_CLKF_IN1 + ); + NlwInverterBlock_REG_0_5_SETF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_5_SETF_IN1 + ); + NlwInverterBlock_REG_0_5_RSTF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_5_RSTF_IN1 + ); + NlwInverterBlock_REG_0_5_RSTF_IN2 : X_INV + port map ( + I => DIN_5_IBUF, + O => NlwInverterSignal_REG_0_5_RSTF_IN2 + ); + NlwInverterBlock_REG_0_6_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_0_6_RSTF, + O => NlwInverterSignal_REG_0_6_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_0_6_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_6_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_0_6_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_6_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_0_6_D2_PT_2_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_6_D2_PT_2_IN3 + ); + NlwInverterBlock_REG_0_6_D2_PT_2_IN5 : X_INV + port map ( + I => REG_0_6, + O => NlwInverterSignal_REG_0_6_D2_PT_2_IN5 + ); + NlwInverterBlock_REG_0_6_D2_PT_3_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_6_D2_PT_3_IN0 + ); + NlwInverterBlock_REG_0_6_D2_PT_3_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_6_D2_PT_3_IN1 + ); + NlwInverterBlock_REG_0_6_D2_PT_3_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_6_D2_PT_3_IN3 + ); + NlwInverterBlock_REG_0_6_D2_PT_3_IN4 : X_INV + port map ( + I => REG_0_5, + O => NlwInverterSignal_REG_0_6_D2_PT_3_IN4 + ); + NlwInverterBlock_REG_0_6_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_6_CLKF_IN0 + ); + NlwInverterBlock_REG_0_6_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_6_CLKF_IN1 + ); + NlwInverterBlock_REG_0_6_SETF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_6_SETF_IN1 + ); + NlwInverterBlock_REG_0_6_RSTF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_6_RSTF_IN1 + ); + NlwInverterBlock_REG_0_6_RSTF_IN2 : X_INV + port map ( + I => DIN_6_IBUF, + O => NlwInverterSignal_REG_0_6_RSTF_IN2 + ); + NlwInverterBlock_REG_0_7_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_0_7_RSTF, + O => NlwInverterSignal_REG_0_7_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_0_7_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_7_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_0_7_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_7_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_0_7_D2_PT_1_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_7_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_0_7_D2_PT_1_IN4 : X_INV + port map ( + I => REG_0_6, + O => NlwInverterSignal_REG_0_7_D2_PT_1_IN4 + ); + NlwInverterBlock_REG_0_7_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_7_CLKF_IN0 + ); + NlwInverterBlock_REG_0_7_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_7_CLKF_IN1 + ); + NlwInverterBlock_REG_0_7_SETF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_7_SETF_IN1 + ); + NlwInverterBlock_REG_0_7_RSTF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_7_RSTF_IN1 + ); + NlwInverterBlock_REG_0_7_RSTF_IN2 : X_INV + port map ( + I => DIN_7_IBUF, + O => NlwInverterSignal_REG_0_7_RSTF_IN2 + ); + NlwInverterBlock_REG_0_7_EXP_tsimrenamed_net_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_7_EXP_tsimrenamed_net_IN0 + ); + NlwInverterBlock_REG_0_7_EXP_tsimrenamed_net_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_7_EXP_tsimrenamed_net_IN2 + ); + NlwInverterBlock_REG_0_7_EXP_tsimrenamed_net_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_7_EXP_tsimrenamed_net_IN4 + ); + NlwInverterBlock_REG_0_7_EXP_tsimrenamed_net_IN5 : X_INV + port map ( + I => REG_0_8, + O => NlwInverterSignal_REG_0_7_EXP_tsimrenamed_net_IN5 + ); + NlwInverterBlock_REG_0_8_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_0_8_RSTF, + O => NlwInverterSignal_REG_0_8_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_0_8_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_8_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_0_8_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_8_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_0_8_D2_PT_2_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_8_D2_PT_2_IN3 + ); + NlwInverterBlock_REG_0_8_D2_PT_2_IN5 : X_INV + port map ( + I => REG_0_8, + O => NlwInverterSignal_REG_0_8_D2_PT_2_IN5 + ); + NlwInverterBlock_REG_0_8_D2_PT_3_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_8_D2_PT_3_IN0 + ); + NlwInverterBlock_REG_0_8_D2_PT_3_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_8_D2_PT_3_IN1 + ); + NlwInverterBlock_REG_0_8_D2_PT_3_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_8_D2_PT_3_IN3 + ); + NlwInverterBlock_REG_0_8_D2_PT_3_IN4 : X_INV + port map ( + I => REG_0_7, + O => NlwInverterSignal_REG_0_8_D2_PT_3_IN4 + ); + NlwInverterBlock_REG_0_8_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_8_CLKF_IN0 + ); + NlwInverterBlock_REG_0_8_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_8_CLKF_IN1 + ); + NlwInverterBlock_REG_0_8_SETF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_8_SETF_IN1 + ); + NlwInverterBlock_REG_0_8_RSTF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_8_RSTF_IN1 + ); + NlwInverterBlock_REG_0_8_RSTF_IN2 : X_INV + port map ( + I => DIN_8_IBUF, + O => NlwInverterSignal_REG_0_8_RSTF_IN2 + ); + NlwInverterBlock_REG_0_9_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_0_9_RSTF, + O => NlwInverterSignal_REG_0_9_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_0_9_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_9_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_0_9_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_0_9_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_0_9_D2_PT_1_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_9_D2_PT_1_IN3 + ); + NlwInverterBlock_REG_0_9_D2_PT_1_IN5 : X_INV + port map ( + I => REG_0_8, + O => NlwInverterSignal_REG_0_9_D2_PT_1_IN5 + ); + NlwInverterBlock_REG_0_9_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_9_CLKF_IN0 + ); + NlwInverterBlock_REG_0_9_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_0_9_CLKF_IN1 + ); + NlwInverterBlock_REG_0_9_SETF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_9_SETF_IN1 + ); + NlwInverterBlock_REG_0_9_RSTF_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_9_RSTF_IN1 + ); + NlwInverterBlock_REG_0_9_RSTF_IN2 : X_INV + port map ( + I => DIN_9_IBUF, + O => NlwInverterSignal_REG_0_9_RSTF_IN2 + ); + NlwInverterBlock_REG_0_9_EXP_tsimrenamed_net_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_0_9_EXP_tsimrenamed_net_IN0 + ); + NlwInverterBlock_REG_0_9_EXP_tsimrenamed_net_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_REG_0_9_EXP_tsimrenamed_net_IN2 + ); + NlwInverterBlock_REG_0_9_EXP_tsimrenamed_net_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_REG_0_9_EXP_tsimrenamed_net_IN4 + ); + NlwInverterBlock_REG_0_9_EXP_tsimrenamed_net_IN6 : X_INV + port map ( + I => DIN_8_IBUF, + O => NlwInverterSignal_REG_0_9_EXP_tsimrenamed_net_IN6 + ); + NlwInverterBlock_REG_1_0_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_1_0_RSTF, + O => NlwInverterSignal_REG_1_0_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_1_0_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_0_CLKF_IN0 + ); + NlwInverterBlock_REG_1_0_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_0_CLKF_IN1 + ); + NlwInverterBlock_REG_1_0_RSTF_IN2 : X_INV + port map ( + I => DIN_0_IBUF, + O => NlwInverterSignal_REG_1_0_RSTF_IN2 + ); + NlwInverterBlock_REG_1_0_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_0_EXP_PT_0_IN0 + ); + NlwInverterBlock_REG_1_0_EXP_PT_0_IN6 : X_INV + port map ( + I => REG_1_4, + O => NlwInverterSignal_REG_1_0_EXP_PT_0_IN6 + ); + NlwInverterBlock_REG_1_0_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_0_EXP_PT_1_IN0 + ); + NlwInverterBlock_REG_1_0_EXP_PT_1_IN5 : X_INV + port map ( + I => DIN_4_IBUF, + O => NlwInverterSignal_REG_1_0_EXP_PT_1_IN5 + ); + NlwInverterBlock_REG_1_1_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_1_1_RSTF, + O => NlwInverterSignal_REG_1_1_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_1_1_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_1_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_1_1_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_1_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_1_1_D2_PT_1_IN5 : X_INV + port map ( + I => REG_1_1, + O => NlwInverterSignal_REG_1_1_D2_PT_1_IN5 + ); + NlwInverterBlock_REG_1_1_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_1_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_1_1_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_1_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_1_1_D2_PT_2_IN4 : X_INV + port map ( + I => REG_1_0, + O => NlwInverterSignal_REG_1_1_D2_PT_2_IN4 + ); + NlwInverterBlock_REG_1_1_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_1_CLKF_IN0 + ); + NlwInverterBlock_REG_1_1_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_1_CLKF_IN1 + ); + NlwInverterBlock_REG_1_1_RSTF_IN2 : X_INV + port map ( + I => DIN_1_IBUF, + O => NlwInverterSignal_REG_1_1_RSTF_IN2 + ); + NlwInverterBlock_REG_1_10_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_1_10_RSTF, + O => NlwInverterSignal_REG_1_10_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_1_10_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_10_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_1_10_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_10_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_1_10_D2_PT_1_IN5 : X_INV + port map ( + I => REG_1_9, + O => NlwInverterSignal_REG_1_10_D2_PT_1_IN5 + ); + NlwInverterBlock_REG_1_10_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_10_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_1_10_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_10_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_1_10_D2_PT_2_IN4 : X_INV + port map ( + I => REG_1_10, + O => NlwInverterSignal_REG_1_10_D2_PT_2_IN4 + ); + NlwInverterBlock_REG_1_10_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_10_CLKF_IN0 + ); + NlwInverterBlock_REG_1_10_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_10_CLKF_IN1 + ); + NlwInverterBlock_REG_1_10_RSTF_IN2 : X_INV + port map ( + I => DIN_10_IBUF, + O => NlwInverterSignal_REG_1_10_RSTF_IN2 + ); + NlwInverterBlock_REG_1_11_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_1_11_RSTF, + O => NlwInverterSignal_REG_1_11_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_1_11_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_11_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_1_11_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_11_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_1_11_D2_PT_1_IN4 : X_INV + port map ( + I => REG_1_10, + O => NlwInverterSignal_REG_1_11_D2_PT_1_IN4 + ); + NlwInverterBlock_REG_1_11_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_11_CLKF_IN0 + ); + NlwInverterBlock_REG_1_11_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_11_CLKF_IN1 + ); + NlwInverterBlock_REG_1_11_RSTF_IN2 : X_INV + port map ( + I => DIN_11_IBUF, + O => NlwInverterSignal_REG_1_11_RSTF_IN2 + ); + NlwInverterBlock_REG_1_11_EXP_tsimrenamed_net_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_11_EXP_tsimrenamed_net_IN0 + ); + NlwInverterBlock_REG_1_11_EXP_tsimrenamed_net_IN6 : X_INV + port map ( + I => REG_1_12, + O => NlwInverterSignal_REG_1_11_EXP_tsimrenamed_net_IN6 + ); + NlwInverterBlock_REG_1_12_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_1_12_RSTF, + O => NlwInverterSignal_REG_1_12_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_1_12_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_12_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_1_12_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_12_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_1_12_D2_PT_2_IN5 : X_INV + port map ( + I => REG_1_12, + O => NlwInverterSignal_REG_1_12_D2_PT_2_IN5 + ); + NlwInverterBlock_REG_1_12_D2_PT_3_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_12_D2_PT_3_IN0 + ); + NlwInverterBlock_REG_1_12_D2_PT_3_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_12_D2_PT_3_IN1 + ); + NlwInverterBlock_REG_1_12_D2_PT_3_IN4 : X_INV + port map ( + I => REG_1_11, + O => NlwInverterSignal_REG_1_12_D2_PT_3_IN4 + ); + NlwInverterBlock_REG_1_12_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_12_CLKF_IN0 + ); + NlwInverterBlock_REG_1_12_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_12_CLKF_IN1 + ); + NlwInverterBlock_REG_1_12_RSTF_IN2 : X_INV + port map ( + I => DIN_12_IBUF, + O => NlwInverterSignal_REG_1_12_RSTF_IN2 + ); + NlwInverterBlock_REG_1_13_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_1_13_RSTF, + O => NlwInverterSignal_REG_1_13_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_1_13_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_13_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_1_13_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_13_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_1_13_D2_PT_1_IN4 : X_INV + port map ( + I => REG_1_12, + O => NlwInverterSignal_REG_1_13_D2_PT_1_IN4 + ); + NlwInverterBlock_REG_1_13_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_13_CLKF_IN0 + ); + NlwInverterBlock_REG_1_13_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_13_CLKF_IN1 + ); + NlwInverterBlock_REG_1_13_RSTF_IN2 : X_INV + port map ( + I => DIN_13_IBUF, + O => NlwInverterSignal_REG_1_13_RSTF_IN2 + ); + NlwInverterBlock_REG_1_13_EXP_tsimrenamed_net_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_13_EXP_tsimrenamed_net_IN0 + ); + NlwInverterBlock_REG_1_13_EXP_tsimrenamed_net_IN5 : X_INV + port map ( + I => DIN_12_IBUF, + O => NlwInverterSignal_REG_1_13_EXP_tsimrenamed_net_IN5 + ); + NlwInverterBlock_REG_1_14_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_1_14_RSTF, + O => NlwInverterSignal_REG_1_14_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_1_14_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_14_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_1_14_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_14_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_1_14_D2_PT_1_IN5 : X_INV + port map ( + I => REG_1_14, + O => NlwInverterSignal_REG_1_14_D2_PT_1_IN5 + ); + NlwInverterBlock_REG_1_14_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_14_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_1_14_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_14_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_1_14_D2_PT_2_IN4 : X_INV + port map ( + I => REG_1_13, + O => NlwInverterSignal_REG_1_14_D2_PT_2_IN4 + ); + NlwInverterBlock_REG_1_14_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_14_CLKF_IN0 + ); + NlwInverterBlock_REG_1_14_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_14_CLKF_IN1 + ); + NlwInverterBlock_REG_1_14_RSTF_IN2 : X_INV + port map ( + I => DIN_14_IBUF, + O => NlwInverterSignal_REG_1_14_RSTF_IN2 + ); + NlwInverterBlock_REG_1_15_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_1_15_RSTF, + O => NlwInverterSignal_REG_1_15_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_1_15_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_15_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_1_15_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_15_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_1_15_D2_PT_1_IN5 : X_INV + port map ( + I => REG_1_15, + O => NlwInverterSignal_REG_1_15_D2_PT_1_IN5 + ); + NlwInverterBlock_REG_1_15_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_15_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_1_15_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_15_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_1_15_D2_PT_2_IN4 : X_INV + port map ( + I => REG_1_14, + O => NlwInverterSignal_REG_1_15_D2_PT_2_IN4 + ); + NlwInverterBlock_REG_1_15_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_15_CLKF_IN0 + ); + NlwInverterBlock_REG_1_15_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_15_CLKF_IN1 + ); + NlwInverterBlock_REG_1_15_RSTF_IN2 : X_INV + port map ( + I => DIN_15_IBUF, + O => NlwInverterSignal_REG_1_15_RSTF_IN2 + ); + NlwInverterBlock_REG_1_16_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_1_16_RSTF, + O => NlwInverterSignal_REG_1_16_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_1_16_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_16_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_1_16_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_16_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_1_16_D2_PT_1_IN5 : X_INV + port map ( + I => REG_1_16, + O => NlwInverterSignal_REG_1_16_D2_PT_1_IN5 + ); + NlwInverterBlock_REG_1_16_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_16_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_1_16_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_16_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_1_16_D2_PT_2_IN4 : X_INV + port map ( + I => REG_1_15, + O => NlwInverterSignal_REG_1_16_D2_PT_2_IN4 + ); + NlwInverterBlock_REG_1_16_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_16_CLKF_IN0 + ); + NlwInverterBlock_REG_1_16_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_16_CLKF_IN1 + ); + NlwInverterBlock_REG_1_16_RSTF_IN2 : X_INV + port map ( + I => DIN_16_IBUF, + O => NlwInverterSignal_REG_1_16_RSTF_IN2 + ); + NlwInverterBlock_REG_1_17_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_1_17_RSTF, + O => NlwInverterSignal_REG_1_17_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_1_17_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_17_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_1_17_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_17_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_1_17_D2_PT_1_IN4 : X_INV + port map ( + I => REG_1_16, + O => NlwInverterSignal_REG_1_17_D2_PT_1_IN4 + ); + NlwInverterBlock_REG_1_17_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_17_CLKF_IN0 + ); + NlwInverterBlock_REG_1_17_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_17_CLKF_IN1 + ); + NlwInverterBlock_REG_1_17_RSTF_IN2 : X_INV + port map ( + I => DIN_17_IBUF, + O => NlwInverterSignal_REG_1_17_RSTF_IN2 + ); + NlwInverterBlock_REG_1_17_EXP_tsimrenamed_net_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_17_EXP_tsimrenamed_net_IN0 + ); + NlwInverterBlock_REG_1_17_EXP_tsimrenamed_net_IN6 : X_INV + port map ( + I => REG_1_18, + O => NlwInverterSignal_REG_1_17_EXP_tsimrenamed_net_IN6 + ); + NlwInverterBlock_REG_1_18_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_1_18_RSTF, + O => NlwInverterSignal_REG_1_18_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_1_18_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_18_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_1_18_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_18_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_1_18_D2_PT_2_IN5 : X_INV + port map ( + I => REG_1_18, + O => NlwInverterSignal_REG_1_18_D2_PT_2_IN5 + ); + NlwInverterBlock_REG_1_18_D2_PT_3_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_18_D2_PT_3_IN0 + ); + NlwInverterBlock_REG_1_18_D2_PT_3_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_18_D2_PT_3_IN1 + ); + NlwInverterBlock_REG_1_18_D2_PT_3_IN4 : X_INV + port map ( + I => REG_1_17, + O => NlwInverterSignal_REG_1_18_D2_PT_3_IN4 + ); + NlwInverterBlock_REG_1_18_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_18_CLKF_IN0 + ); + NlwInverterBlock_REG_1_18_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_18_CLKF_IN1 + ); + NlwInverterBlock_REG_1_18_RSTF_IN2 : X_INV + port map ( + I => DIN_18_IBUF, + O => NlwInverterSignal_REG_1_18_RSTF_IN2 + ); + NlwInverterBlock_REG_1_19_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_1_19_RSTF, + O => NlwInverterSignal_REG_1_19_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_1_19_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_19_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_1_19_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_19_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_1_19_D2_PT_1_IN4 : X_INV + port map ( + I => REG_1_18, + O => NlwInverterSignal_REG_1_19_D2_PT_1_IN4 + ); + NlwInverterBlock_REG_1_19_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_19_CLKF_IN0 + ); + NlwInverterBlock_REG_1_19_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_19_CLKF_IN1 + ); + NlwInverterBlock_REG_1_19_RSTF_IN2 : X_INV + port map ( + I => DIN_19_IBUF, + O => NlwInverterSignal_REG_1_19_RSTF_IN2 + ); + NlwInverterBlock_REG_1_19_EXP_tsimrenamed_net_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_19_EXP_tsimrenamed_net_IN0 + ); + NlwInverterBlock_REG_1_19_EXP_tsimrenamed_net_IN5 : X_INV + port map ( + I => DIN_18_IBUF, + O => NlwInverterSignal_REG_1_19_EXP_tsimrenamed_net_IN5 + ); + NlwInverterBlock_REG_1_2_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_1_2_RSTF, + O => NlwInverterSignal_REG_1_2_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_1_2_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_2_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_1_2_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_2_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_1_2_D2_PT_1_IN5 : X_INV + port map ( + I => REG_1_2, + O => NlwInverterSignal_REG_1_2_D2_PT_1_IN5 + ); + NlwInverterBlock_REG_1_2_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_2_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_1_2_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_2_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_1_2_D2_PT_2_IN4 : X_INV + port map ( + I => REG_1_1, + O => NlwInverterSignal_REG_1_2_D2_PT_2_IN4 + ); + NlwInverterBlock_REG_1_2_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_2_CLKF_IN0 + ); + NlwInverterBlock_REG_1_2_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_2_CLKF_IN1 + ); + NlwInverterBlock_REG_1_2_RSTF_IN2 : X_INV + port map ( + I => DIN_2_IBUF, + O => NlwInverterSignal_REG_1_2_RSTF_IN2 + ); + NlwInverterBlock_REG_1_20_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_1_20_RSTF, + O => NlwInverterSignal_REG_1_20_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_1_20_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_20_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_1_20_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_20_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_1_20_D2_PT_1_IN5 : X_INV + port map ( + I => REG_1_20, + O => NlwInverterSignal_REG_1_20_D2_PT_1_IN5 + ); + NlwInverterBlock_REG_1_20_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_20_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_1_20_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_20_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_1_20_D2_PT_2_IN4 : X_INV + port map ( + I => REG_1_19, + O => NlwInverterSignal_REG_1_20_D2_PT_2_IN4 + ); + NlwInverterBlock_REG_1_20_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_20_CLKF_IN0 + ); + NlwInverterBlock_REG_1_20_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_20_CLKF_IN1 + ); + NlwInverterBlock_REG_1_20_RSTF_IN2 : X_INV + port map ( + I => DIN_20_IBUF, + O => NlwInverterSignal_REG_1_20_RSTF_IN2 + ); + NlwInverterBlock_REG_1_21_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_1_21_RSTF, + O => NlwInverterSignal_REG_1_21_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_1_21_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_21_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_1_21_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_21_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_1_21_D2_PT_1_IN5 : X_INV + port map ( + I => REG_1_21, + O => NlwInverterSignal_REG_1_21_D2_PT_1_IN5 + ); + NlwInverterBlock_REG_1_21_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_21_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_1_21_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_21_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_1_21_D2_PT_2_IN4 : X_INV + port map ( + I => REG_1_20, + O => NlwInverterSignal_REG_1_21_D2_PT_2_IN4 + ); + NlwInverterBlock_REG_1_21_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_21_CLKF_IN0 + ); + NlwInverterBlock_REG_1_21_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_21_CLKF_IN1 + ); + NlwInverterBlock_REG_1_21_RSTF_IN2 : X_INV + port map ( + I => DIN_21_IBUF, + O => NlwInverterSignal_REG_1_21_RSTF_IN2 + ); + NlwInverterBlock_REG_1_22_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_1_22_RSTF, + O => NlwInverterSignal_REG_1_22_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_1_22_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_22_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_1_22_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_22_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_1_22_D2_PT_1_IN5 : X_INV + port map ( + I => REG_1_22, + O => NlwInverterSignal_REG_1_22_D2_PT_1_IN5 + ); + NlwInverterBlock_REG_1_22_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_22_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_1_22_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_22_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_1_22_D2_PT_2_IN4 : X_INV + port map ( + I => REG_1_21, + O => NlwInverterSignal_REG_1_22_D2_PT_2_IN4 + ); + NlwInverterBlock_REG_1_22_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_22_CLKF_IN0 + ); + NlwInverterBlock_REG_1_22_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_22_CLKF_IN1 + ); + NlwInverterBlock_REG_1_22_RSTF_IN2 : X_INV + port map ( + I => DIN_22_IBUF, + O => NlwInverterSignal_REG_1_22_RSTF_IN2 + ); + NlwInverterBlock_REG_1_23_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_1_23_RSTF, + O => NlwInverterSignal_REG_1_23_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_1_23_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_23_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_1_23_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_23_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_1_23_D2_PT_2_IN5 : X_INV + port map ( + I => REG_1_22, + O => NlwInverterSignal_REG_1_23_D2_PT_2_IN5 + ); + NlwInverterBlock_REG_1_23_D2_PT_3_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_23_D2_PT_3_IN0 + ); + NlwInverterBlock_REG_1_23_D2_PT_3_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_23_D2_PT_3_IN1 + ); + NlwInverterBlock_REG_1_23_D2_PT_3_IN4 : X_INV + port map ( + I => REG_1_23, + O => NlwInverterSignal_REG_1_23_D2_PT_3_IN4 + ); + NlwInverterBlock_REG_1_23_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_23_CLKF_IN0 + ); + NlwInverterBlock_REG_1_23_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_23_CLKF_IN1 + ); + NlwInverterBlock_REG_1_23_RSTF_IN2 : X_INV + port map ( + I => DIN_23_IBUF, + O => NlwInverterSignal_REG_1_23_RSTF_IN2 + ); + NlwInverterBlock_REG_1_24_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_1_24_RSTF, + O => NlwInverterSignal_REG_1_24_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_1_24_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_24_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_1_24_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_24_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_1_24_D2_PT_1_IN4 : X_INV + port map ( + I => REG_1_23, + O => NlwInverterSignal_REG_1_24_D2_PT_1_IN4 + ); + NlwInverterBlock_REG_1_24_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_24_CLKF_IN0 + ); + NlwInverterBlock_REG_1_24_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_24_CLKF_IN1 + ); + NlwInverterBlock_REG_1_24_RSTF_IN2 : X_INV + port map ( + I => DIN_24_IBUF, + O => NlwInverterSignal_REG_1_24_RSTF_IN2 + ); + NlwInverterBlock_REG_1_24_EXP_tsimrenamed_net_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_24_EXP_tsimrenamed_net_IN0 + ); + NlwInverterBlock_REG_1_24_EXP_tsimrenamed_net_IN5 : X_INV + port map ( + I => DIN_23_IBUF, + O => NlwInverterSignal_REG_1_24_EXP_tsimrenamed_net_IN5 + ); + NlwInverterBlock_REG_1_25_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_1_25_RSTF, + O => NlwInverterSignal_REG_1_25_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_1_25_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_25_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_1_25_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_25_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_1_25_D2_PT_1_IN5 : X_INV + port map ( + I => REG_1_25, + O => NlwInverterSignal_REG_1_25_D2_PT_1_IN5 + ); + NlwInverterBlock_REG_1_25_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_25_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_1_25_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_25_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_1_25_D2_PT_2_IN4 : X_INV + port map ( + I => REG_1_24, + O => NlwInverterSignal_REG_1_25_D2_PT_2_IN4 + ); + NlwInverterBlock_REG_1_25_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_25_CLKF_IN0 + ); + NlwInverterBlock_REG_1_25_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_25_CLKF_IN1 + ); + NlwInverterBlock_REG_1_25_RSTF_IN2 : X_INV + port map ( + I => DIN_25_IBUF, + O => NlwInverterSignal_REG_1_25_RSTF_IN2 + ); + NlwInverterBlock_REG_1_26_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_1_26_RSTF, + O => NlwInverterSignal_REG_1_26_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_1_26_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_26_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_1_26_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_26_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_1_26_D2_PT_1_IN5 : X_INV + port map ( + I => REG_1_26, + O => NlwInverterSignal_REG_1_26_D2_PT_1_IN5 + ); + NlwInverterBlock_REG_1_26_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_26_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_1_26_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_26_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_1_26_D2_PT_2_IN4 : X_INV + port map ( + I => REG_1_25, + O => NlwInverterSignal_REG_1_26_D2_PT_2_IN4 + ); + NlwInverterBlock_REG_1_26_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_26_CLKF_IN0 + ); + NlwInverterBlock_REG_1_26_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_26_CLKF_IN1 + ); + NlwInverterBlock_REG_1_26_RSTF_IN2 : X_INV + port map ( + I => DIN_26_IBUF, + O => NlwInverterSignal_REG_1_26_RSTF_IN2 + ); + NlwInverterBlock_REG_1_27_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_1_27_RSTF, + O => NlwInverterSignal_REG_1_27_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_1_27_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_27_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_1_27_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_27_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_1_27_D2_PT_1_IN5 : X_INV + port map ( + I => REG_1_27, + O => NlwInverterSignal_REG_1_27_D2_PT_1_IN5 + ); + NlwInverterBlock_REG_1_27_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_27_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_1_27_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_27_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_1_27_D2_PT_2_IN4 : X_INV + port map ( + I => REG_1_26, + O => NlwInverterSignal_REG_1_27_D2_PT_2_IN4 + ); + NlwInverterBlock_REG_1_27_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_27_CLKF_IN0 + ); + NlwInverterBlock_REG_1_27_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_27_CLKF_IN1 + ); + NlwInverterBlock_REG_1_27_RSTF_IN2 : X_INV + port map ( + I => DIN_27_IBUF, + O => NlwInverterSignal_REG_1_27_RSTF_IN2 + ); + NlwInverterBlock_REG_1_28_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_1_28_RSTF, + O => NlwInverterSignal_REG_1_28_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_1_28_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_28_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_1_28_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_28_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_1_28_D2_PT_1_IN5 : X_INV + port map ( + I => REG_1_28, + O => NlwInverterSignal_REG_1_28_D2_PT_1_IN5 + ); + NlwInverterBlock_REG_1_28_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_28_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_1_28_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_28_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_1_28_D2_PT_2_IN4 : X_INV + port map ( + I => REG_1_27, + O => NlwInverterSignal_REG_1_28_D2_PT_2_IN4 + ); + NlwInverterBlock_REG_1_28_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_28_CLKF_IN0 + ); + NlwInverterBlock_REG_1_28_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_28_CLKF_IN1 + ); + NlwInverterBlock_REG_1_28_RSTF_IN2 : X_INV + port map ( + I => DIN_28_IBUF, + O => NlwInverterSignal_REG_1_28_RSTF_IN2 + ); + NlwInverterBlock_REG_1_29_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_1_29_RSTF, + O => NlwInverterSignal_REG_1_29_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_1_29_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_29_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_1_29_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_29_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_1_29_D2_PT_1_IN5 : X_INV + port map ( + I => REG_1_29, + O => NlwInverterSignal_REG_1_29_D2_PT_1_IN5 + ); + NlwInverterBlock_REG_1_29_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_29_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_1_29_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_29_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_1_29_D2_PT_2_IN4 : X_INV + port map ( + I => REG_1_28, + O => NlwInverterSignal_REG_1_29_D2_PT_2_IN4 + ); + NlwInverterBlock_REG_1_29_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_29_CLKF_IN0 + ); + NlwInverterBlock_REG_1_29_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_29_CLKF_IN1 + ); + NlwInverterBlock_REG_1_29_RSTF_IN2 : X_INV + port map ( + I => DIN_29_IBUF, + O => NlwInverterSignal_REG_1_29_RSTF_IN2 + ); + NlwInverterBlock_REG_1_3_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_1_3_RSTF, + O => NlwInverterSignal_REG_1_3_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_1_3_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_3_CLKF_IN0 + ); + NlwInverterBlock_REG_1_3_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_3_CLKF_IN1 + ); + NlwInverterBlock_REG_1_3_RSTF_IN2 : X_INV + port map ( + I => DIN_3_IBUF, + O => NlwInverterSignal_REG_1_3_RSTF_IN2 + ); + NlwInverterBlock_REG_1_3_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_3_EXP_PT_0_IN0 + ); + NlwInverterBlock_REG_1_3_EXP_PT_0_IN6 : X_INV + port map ( + I => REG_1_2, + O => NlwInverterSignal_REG_1_3_EXP_PT_0_IN6 + ); + NlwInverterBlock_REG_1_3_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_3_EXP_PT_1_IN0 + ); + NlwInverterBlock_REG_1_3_EXP_PT_1_IN5 : X_INV + port map ( + I => DIN_2_IBUF, + O => NlwInverterSignal_REG_1_3_EXP_PT_1_IN5 + ); + NlwInverterBlock_REG_1_30_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_1_30_RSTF, + O => NlwInverterSignal_REG_1_30_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_1_30_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_30_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_1_30_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_30_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_1_30_D2_PT_1_IN5 : X_INV + port map ( + I => REG_1_30, + O => NlwInverterSignal_REG_1_30_D2_PT_1_IN5 + ); + NlwInverterBlock_REG_1_30_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_30_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_1_30_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_30_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_1_30_D2_PT_2_IN4 : X_INV + port map ( + I => REG_1_29, + O => NlwInverterSignal_REG_1_30_D2_PT_2_IN4 + ); + NlwInverterBlock_REG_1_30_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_30_CLKF_IN0 + ); + NlwInverterBlock_REG_1_30_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_30_CLKF_IN1 + ); + NlwInverterBlock_REG_1_30_RSTF_IN2 : X_INV + port map ( + I => DIN_30_IBUF, + O => NlwInverterSignal_REG_1_30_RSTF_IN2 + ); + NlwInverterBlock_REG_1_31_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_1_31_RSTF, + O => NlwInverterSignal_REG_1_31_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_1_31_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_31_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_1_31_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_31_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_1_31_D2_PT_1_IN5 : X_INV + port map ( + I => REG_1_31, + O => NlwInverterSignal_REG_1_31_D2_PT_1_IN5 + ); + NlwInverterBlock_REG_1_31_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_31_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_1_31_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_31_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_1_31_D2_PT_2_IN4 : X_INV + port map ( + I => REG_1_30, + O => NlwInverterSignal_REG_1_31_D2_PT_2_IN4 + ); + NlwInverterBlock_REG_1_31_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_31_CLKF_IN0 + ); + NlwInverterBlock_REG_1_31_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_31_CLKF_IN1 + ); + NlwInverterBlock_REG_1_31_RSTF_IN2 : X_INV + port map ( + I => DIN_31_IBUF, + O => NlwInverterSignal_REG_1_31_RSTF_IN2 + ); + NlwInverterBlock_REG_1_4_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_1_4_RSTF, + O => NlwInverterSignal_REG_1_4_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_1_4_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_4_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_1_4_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_4_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_1_4_D2_PT_1_IN5 : X_INV + port map ( + I => REG_1_3, + O => NlwInverterSignal_REG_1_4_D2_PT_1_IN5 + ); + NlwInverterBlock_REG_1_4_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_4_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_1_4_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_4_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_1_4_D2_PT_2_IN4 : X_INV + port map ( + I => REG_1_4, + O => NlwInverterSignal_REG_1_4_D2_PT_2_IN4 + ); + NlwInverterBlock_REG_1_4_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_4_CLKF_IN0 + ); + NlwInverterBlock_REG_1_4_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_4_CLKF_IN1 + ); + NlwInverterBlock_REG_1_4_RSTF_IN2 : X_INV + port map ( + I => DIN_4_IBUF, + O => NlwInverterSignal_REG_1_4_RSTF_IN2 + ); + NlwInverterBlock_REG_1_5_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_1_5_RSTF, + O => NlwInverterSignal_REG_1_5_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_1_5_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_5_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_1_5_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_5_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_1_5_D2_PT_1_IN5 : X_INV + port map ( + I => REG_1_5, + O => NlwInverterSignal_REG_1_5_D2_PT_1_IN5 + ); + NlwInverterBlock_REG_1_5_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_5_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_1_5_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_5_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_1_5_D2_PT_2_IN4 : X_INV + port map ( + I => REG_1_4, + O => NlwInverterSignal_REG_1_5_D2_PT_2_IN4 + ); + NlwInverterBlock_REG_1_5_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_5_CLKF_IN0 + ); + NlwInverterBlock_REG_1_5_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_5_CLKF_IN1 + ); + NlwInverterBlock_REG_1_5_RSTF_IN2 : X_INV + port map ( + I => DIN_5_IBUF, + O => NlwInverterSignal_REG_1_5_RSTF_IN2 + ); + NlwInverterBlock_REG_1_6_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_1_6_RSTF, + O => NlwInverterSignal_REG_1_6_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_1_6_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_6_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_1_6_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_6_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_1_6_D2_PT_2_IN5 : X_INV + port map ( + I => REG_1_6, + O => NlwInverterSignal_REG_1_6_D2_PT_2_IN5 + ); + NlwInverterBlock_REG_1_6_D2_PT_3_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_6_D2_PT_3_IN0 + ); + NlwInverterBlock_REG_1_6_D2_PT_3_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_6_D2_PT_3_IN1 + ); + NlwInverterBlock_REG_1_6_D2_PT_3_IN4 : X_INV + port map ( + I => REG_1_5, + O => NlwInverterSignal_REG_1_6_D2_PT_3_IN4 + ); + NlwInverterBlock_REG_1_6_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_6_CLKF_IN0 + ); + NlwInverterBlock_REG_1_6_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_6_CLKF_IN1 + ); + NlwInverterBlock_REG_1_6_RSTF_IN2 : X_INV + port map ( + I => DIN_6_IBUF, + O => NlwInverterSignal_REG_1_6_RSTF_IN2 + ); + NlwInverterBlock_REG_1_7_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_1_7_RSTF, + O => NlwInverterSignal_REG_1_7_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_1_7_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_7_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_1_7_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_7_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_1_7_D2_PT_1_IN5 : X_INV + port map ( + I => REG_1_7, + O => NlwInverterSignal_REG_1_7_D2_PT_1_IN5 + ); + NlwInverterBlock_REG_1_7_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_7_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_1_7_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_7_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_1_7_D2_PT_2_IN4 : X_INV + port map ( + I => REG_1_6, + O => NlwInverterSignal_REG_1_7_D2_PT_2_IN4 + ); + NlwInverterBlock_REG_1_7_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_7_CLKF_IN0 + ); + NlwInverterBlock_REG_1_7_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_7_CLKF_IN1 + ); + NlwInverterBlock_REG_1_7_RSTF_IN2 : X_INV + port map ( + I => DIN_7_IBUF, + O => NlwInverterSignal_REG_1_7_RSTF_IN2 + ); + NlwInverterBlock_REG_1_8_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_1_8_RSTF, + O => NlwInverterSignal_REG_1_8_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_1_8_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_8_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_1_8_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_8_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_1_8_D2_PT_1_IN5 : X_INV + port map ( + I => REG_1_8, + O => NlwInverterSignal_REG_1_8_D2_PT_1_IN5 + ); + NlwInverterBlock_REG_1_8_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_8_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_1_8_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_8_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_1_8_D2_PT_2_IN4 : X_INV + port map ( + I => REG_1_7, + O => NlwInverterSignal_REG_1_8_D2_PT_2_IN4 + ); + NlwInverterBlock_REG_1_8_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_8_CLKF_IN0 + ); + NlwInverterBlock_REG_1_8_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_8_CLKF_IN1 + ); + NlwInverterBlock_REG_1_8_RSTF_IN2 : X_INV + port map ( + I => DIN_8_IBUF, + O => NlwInverterSignal_REG_1_8_RSTF_IN2 + ); + NlwInverterBlock_REG_1_9_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => REG_1_9_RSTF, + O => NlwInverterSignal_REG_1_9_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_REG_1_9_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_9_D2_PT_1_IN0 + ); + NlwInverterBlock_REG_1_9_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_9_D2_PT_1_IN1 + ); + NlwInverterBlock_REG_1_9_D2_PT_1_IN5 : X_INV + port map ( + I => REG_1_8, + O => NlwInverterSignal_REG_1_9_D2_PT_1_IN5 + ); + NlwInverterBlock_REG_1_9_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_REG_1_9_D2_PT_2_IN0 + ); + NlwInverterBlock_REG_1_9_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_REG_1_9_D2_PT_2_IN1 + ); + NlwInverterBlock_REG_1_9_D2_PT_2_IN4 : X_INV + port map ( + I => REG_1_9, + O => NlwInverterSignal_REG_1_9_D2_PT_2_IN4 + ); + NlwInverterBlock_REG_1_9_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_9_CLKF_IN0 + ); + NlwInverterBlock_REG_1_9_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_REG_1_9_CLKF_IN1 + ); + NlwInverterBlock_REG_1_9_RSTF_IN2 : X_INV + port map ( + I => DIN_9_IBUF, + O => NlwInverterSignal_REG_1_9_RSTF_IN2 + ); + NlwInverterBlock_DOUT_OBUFE_D2_PT_1_IN0 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_DOUT_OBUFE_D2_PT_1_IN0 + ); + NlwInverterBlock_DOUT_OBUFE_TRST_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_DOUT_OBUFE_TRST_IN0 + ); + NlwInverterBlock_DOUT_OBUFE_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_DOUT_OBUFE_EXP_PT_0_IN0 + ); + NlwInverterBlock_DOUT_OBUFE_EXP_PT_0_IN6 : X_INV + port map ( + I => REG_1_30, + O => NlwInverterSignal_DOUT_OBUFE_EXP_PT_0_IN6 + ); + NlwInverterBlock_DOUT_OBUFE_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_DOUT_OBUFE_EXP_PT_1_IN0 + ); + NlwInverterBlock_DOUT_OBUFE_EXP_PT_1_IN5 : X_INV + port map ( + I => DIN_30_IBUF, + O => NlwInverterSignal_DOUT_OBUFE_EXP_PT_1_IN5 + ); + NlwInverterBlock_state_0_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_state_0_EXP_PT_0_IN0 + ); + NlwInverterBlock_state_0_EXP_PT_0_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_state_0_EXP_PT_0_IN2 + ); + NlwInverterBlock_state_0_EXP_PT_0_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_state_0_EXP_PT_0_IN4 + ); + NlwInverterBlock_state_0_EXP_PT_0_IN6 : X_INV + port map ( + I => REG_0_19, + O => NlwInverterSignal_state_0_EXP_PT_0_IN6 + ); + NlwInverterBlock_state_0_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_state_0_EXP_PT_1_IN0 + ); + NlwInverterBlock_state_0_EXP_PT_1_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_state_0_EXP_PT_1_IN2 + ); + NlwInverterBlock_state_0_EXP_PT_1_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_state_0_EXP_PT_1_IN4 + ); + NlwInverterBlock_state_0_EXP_PT_1_IN5 : X_INV + port map ( + I => DIN_19_IBUF, + O => NlwInverterSignal_state_0_EXP_PT_1_IN5 + ); + NlwInverterBlock_state_1_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_state_1_EXP_PT_0_IN0 + ); + NlwInverterBlock_state_1_EXP_PT_0_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_state_1_EXP_PT_0_IN2 + ); + NlwInverterBlock_state_1_EXP_PT_0_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_state_1_EXP_PT_0_IN4 + ); + NlwInverterBlock_state_1_EXP_PT_0_IN6 : X_INV + port map ( + I => REG_0_25, + O => NlwInverterSignal_state_1_EXP_PT_0_IN6 + ); + NlwInverterBlock_state_1_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_state_1_EXP_PT_1_IN0 + ); + NlwInverterBlock_state_1_EXP_PT_1_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_state_1_EXP_PT_1_IN2 + ); + NlwInverterBlock_state_1_EXP_PT_1_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_state_1_EXP_PT_1_IN4 + ); + NlwInverterBlock_state_1_EXP_PT_1_IN5 : X_INV + port map ( + I => DIN_25_IBUF, + O => NlwInverterSignal_state_1_EXP_PT_1_IN5 + ); + NlwInverterBlock_CLK_SCALE_1_D2_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_CLK_SCALE_1_D2_PT_0_IN0 + ); + NlwInverterBlock_CLK_SCALE_1_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_CLK_SCALE_1_D2_PT_1_IN0 + ); + NlwInverterBlock_CLK_SCALE_1_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_PRESCALER_IBUF, + O => NlwInverterSignal_CLK_SCALE_1_D2_PT_1_IN1 + ); + NlwInverterBlock_CLK_SCALE_1_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_CLK_SCALE_1_D2_PT_2_IN0 + ); + NlwInverterBlock_CLK_SCALE_1_EXP_tsimrenamed_net_IN1 : X_INV + port map ( + I => LOAD_PRESCALER_IBUF, + O => NlwInverterSignal_CLK_SCALE_1_EXP_tsimrenamed_net_IN1 + ); + NlwInverterBlock_CLK_SCALE_1_EXP_tsimrenamed_net_IN3 : X_INV + port map ( + I => CLK_SCALE(1), + O => NlwInverterSignal_CLK_SCALE_1_EXP_tsimrenamed_net_IN3 + ); + NlwInverterBlock_CLK_SCALE_2_D2_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_CLK_SCALE_2_D2_PT_0_IN0 + ); + NlwInverterBlock_CLK_SCALE_2_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_CLK_SCALE_2_D2_PT_1_IN0 + ); + NlwInverterBlock_CLK_SCALE_2_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_PRESCALER_IBUF, + O => NlwInverterSignal_CLK_SCALE_2_D2_PT_1_IN1 + ); + NlwInverterBlock_CLK_SCALE_2_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_CLK_SCALE_2_D2_PT_2_IN0 + ); + NlwInverterBlock_CLK_SCALE_2_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_CLK_SCALE_2_EXP_PT_0_IN0 + ); + NlwInverterBlock_CLK_SCALE_2_EXP_PT_0_IN1 : X_INV + port map ( + I => LOAD_PRESCALER_IBUF, + O => NlwInverterSignal_CLK_SCALE_2_EXP_PT_0_IN1 + ); + NlwInverterBlock_CLK_SCALE_2_EXP_PT_0_IN2 : X_INV + port map ( + I => count(0), + O => NlwInverterSignal_CLK_SCALE_2_EXP_PT_0_IN2 + ); + NlwInverterBlock_CLK_SCALE_2_EXP_PT_0_IN3 : X_INV + port map ( + I => count(4), + O => NlwInverterSignal_CLK_SCALE_2_EXP_PT_0_IN3 + ); + NlwInverterBlock_CLK_SCALE_2_EXP_PT_0_IN4 : X_INV + port map ( + I => count(1), + O => NlwInverterSignal_CLK_SCALE_2_EXP_PT_0_IN4 + ); + NlwInverterBlock_CLK_SCALE_2_EXP_PT_0_IN5 : X_INV + port map ( + I => count(2), + O => NlwInverterSignal_CLK_SCALE_2_EXP_PT_0_IN5 + ); + NlwInverterBlock_CLK_SCALE_2_EXP_PT_0_IN6 : X_INV + port map ( + I => count(3), + O => NlwInverterSignal_CLK_SCALE_2_EXP_PT_0_IN6 + ); + NlwInverterBlock_CLK_SCALE_2_EXP_PT_1_IN0 : X_INV + port map ( + I => LOAD_PRESCALER_IBUF, + O => NlwInverterSignal_CLK_SCALE_2_EXP_PT_1_IN0 + ); + NlwInverterBlock_CLK_SCALE_2_EXP_PT_1_IN1 : X_INV + port map ( + I => count(4), + O => NlwInverterSignal_CLK_SCALE_2_EXP_PT_1_IN1 + ); + NlwInverterBlock_CLK_SCALE_2_EXP_PT_1_IN2 : X_INV + port map ( + I => count(1), + O => NlwInverterSignal_CLK_SCALE_2_EXP_PT_1_IN2 + ); + NlwInverterBlock_CLK_SCALE_2_EXP_PT_1_IN3 : X_INV + port map ( + I => count(2), + O => NlwInverterSignal_CLK_SCALE_2_EXP_PT_1_IN3 + ); + NlwInverterBlock_CLK_SCALE_2_EXP_PT_1_IN4 : X_INV + port map ( + I => count(3), + O => NlwInverterSignal_CLK_SCALE_2_EXP_PT_1_IN4 + ); + NlwInverterBlock_CLK_SCALE_2_EXP_PT_1_IN5 : X_INV + port map ( + I => count(5), + O => NlwInverterSignal_CLK_SCALE_2_EXP_PT_1_IN5 + ); + NlwInverterBlock_CLK_SCALE_3_D2_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_CLK_SCALE_3_D2_PT_0_IN0 + ); + NlwInverterBlock_CLK_SCALE_3_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_CLK_SCALE_3_D2_PT_1_IN0 + ); + NlwInverterBlock_CLK_SCALE_3_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_PRESCALER_IBUF, + O => NlwInverterSignal_CLK_SCALE_3_D2_PT_1_IN1 + ); + NlwInverterBlock_CLK_SCALE_3_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_CLK_SCALE_3_D2_PT_2_IN0 + ); + NlwInverterBlock_CLK_SCALE_4_D2_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_CLK_SCALE_4_D2_PT_0_IN0 + ); + NlwInverterBlock_CLK_SCALE_4_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_CLK_SCALE_4_D2_PT_1_IN0 + ); + NlwInverterBlock_CLK_SCALE_4_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_PRESCALER_IBUF, + O => NlwInverterSignal_CLK_SCALE_4_D2_PT_1_IN1 + ); + NlwInverterBlock_CLK_SCALE_4_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_CLK_SCALE_4_D2_PT_2_IN0 + ); + NlwInverterBlock_CLK_SCALE_5_D2_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_CLK_SCALE_5_D2_PT_0_IN0 + ); + NlwInverterBlock_CLK_SCALE_5_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_CLK_SCALE_5_D2_PT_1_IN0 + ); + NlwInverterBlock_CLK_SCALE_5_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_PRESCALER_IBUF, + O => NlwInverterSignal_CLK_SCALE_5_D2_PT_1_IN1 + ); + NlwInverterBlock_CLK_SCALE_5_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_CLK_SCALE_5_D2_PT_2_IN0 + ); + NlwInverterBlock_tempID_0_D2_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_tempID_0_D2_PT_0_IN0 + ); + NlwInverterBlock_tempID_0_D2_PT_0_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_tempID_0_D2_PT_0_IN1 + ); + NlwInverterBlock_tempID_0_D2_PT_0_IN3 : X_INV + port map ( + I => SHIFT_CNT(0), + O => NlwInverterSignal_tempID_0_D2_PT_0_IN3 + ); + NlwInverterBlock_tempID_0_D2_PT_0_IN4 : X_INV + port map ( + I => SHIFT_CNT(1), + O => NlwInverterSignal_tempID_0_D2_PT_0_IN4 + ); + NlwInverterBlock_tempID_0_D2_PT_0_IN5 : X_INV + port map ( + I => SHIFT_CNT(2), + O => NlwInverterSignal_tempID_0_D2_PT_0_IN5 + ); + NlwInverterBlock_tempID_0_D2_PT_0_IN6 : X_INV + port map ( + I => SHIFT_CNT(3), + O => NlwInverterSignal_tempID_0_D2_PT_0_IN6 + ); + NlwInverterBlock_tempID_0_D2_PT_0_IN7 : X_INV + port map ( + I => SHIFT_CNT(4), + O => NlwInverterSignal_tempID_0_D2_PT_0_IN7 + ); + NlwInverterBlock_tempID_0_D2_PT_0_IN10 : X_INV + port map ( + I => tempID(0), + O => NlwInverterSignal_tempID_0_D2_PT_0_IN10 + ); + NlwInverterBlock_tempID_0_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_tempID_0_D2_PT_1_IN0 + ); + NlwInverterBlock_tempID_0_D2_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_tempID_0_D2_PT_1_IN1 + ); + NlwInverterBlock_tempID_0_D2_PT_1_IN3 : X_INV + port map ( + I => SHIFT_CNT(0), + O => NlwInverterSignal_tempID_0_D2_PT_1_IN3 + ); + NlwInverterBlock_tempID_0_D2_PT_1_IN4 : X_INV + port map ( + I => SHIFT_CNT(1), + O => NlwInverterSignal_tempID_0_D2_PT_1_IN4 + ); + NlwInverterBlock_tempID_0_D2_PT_1_IN5 : X_INV + port map ( + I => SHIFT_CNT(2), + O => NlwInverterSignal_tempID_0_D2_PT_1_IN5 + ); + NlwInverterBlock_tempID_0_D2_PT_1_IN6 : X_INV + port map ( + I => SHIFT_CNT(3), + O => NlwInverterSignal_tempID_0_D2_PT_1_IN6 + ); + NlwInverterBlock_tempID_0_D2_PT_1_IN7 : X_INV + port map ( + I => SHIFT_CNT(4), + O => NlwInverterSignal_tempID_0_D2_PT_1_IN7 + ); + NlwInverterBlock_tempID_0_D2_PT_1_IN9 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_tempID_0_D2_PT_1_IN9 + ); + NlwInverterBlock_tempID_0_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_tempID_0_D2_PT_2_IN0 + ); + NlwInverterBlock_tempID_0_D2_PT_2_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_tempID_0_D2_PT_2_IN1 + ); + NlwInverterBlock_tempID_0_D2_PT_2_IN3 : X_INV + port map ( + I => SHIFT_CNT(0), + O => NlwInverterSignal_tempID_0_D2_PT_2_IN3 + ); + NlwInverterBlock_tempID_0_D2_PT_2_IN4 : X_INV + port map ( + I => SHIFT_CNT(1), + O => NlwInverterSignal_tempID_0_D2_PT_2_IN4 + ); + NlwInverterBlock_tempID_0_D2_PT_2_IN5 : X_INV + port map ( + I => SHIFT_CNT(2), + O => NlwInverterSignal_tempID_0_D2_PT_2_IN5 + ); + NlwInverterBlock_tempID_0_D2_PT_2_IN6 : X_INV + port map ( + I => SHIFT_CNT(3), + O => NlwInverterSignal_tempID_0_D2_PT_2_IN6 + ); + NlwInverterBlock_tempID_0_D2_PT_2_IN7 : X_INV + port map ( + I => SHIFT_CNT(4), + O => NlwInverterSignal_tempID_0_D2_PT_2_IN7 + ); + NlwInverterBlock_tempID_0_D2_PT_2_IN10 : X_INV + port map ( + I => tempID(0), + O => NlwInverterSignal_tempID_0_D2_PT_2_IN10 + ); + NlwInverterBlock_tempID_0_D2_PT_3_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_tempID_0_D2_PT_3_IN0 + ); + NlwInverterBlock_tempID_0_D2_PT_3_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_tempID_0_D2_PT_3_IN1 + ); + NlwInverterBlock_tempID_0_D2_PT_3_IN3 : X_INV + port map ( + I => SHIFT_CNT(0), + O => NlwInverterSignal_tempID_0_D2_PT_3_IN3 + ); + NlwInverterBlock_tempID_0_D2_PT_3_IN4 : X_INV + port map ( + I => SHIFT_CNT(1), + O => NlwInverterSignal_tempID_0_D2_PT_3_IN4 + ); + NlwInverterBlock_tempID_0_D2_PT_3_IN5 : X_INV + port map ( + I => SHIFT_CNT(2), + O => NlwInverterSignal_tempID_0_D2_PT_3_IN5 + ); + NlwInverterBlock_tempID_0_D2_PT_3_IN6 : X_INV + port map ( + I => SHIFT_CNT(3), + O => NlwInverterSignal_tempID_0_D2_PT_3_IN6 + ); + NlwInverterBlock_tempID_0_D2_PT_3_IN7 : X_INV + port map ( + I => SHIFT_CNT(4), + O => NlwInverterSignal_tempID_0_D2_PT_3_IN7 + ); + NlwInverterBlock_tempID_0_D2_PT_3_IN9 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_tempID_0_D2_PT_3_IN9 + ); + NlwInverterBlock_tempID_0_CLKF_IN0 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_tempID_0_CLKF_IN0 + ); + NlwInverterBlock_tempID_0_CLKF_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_tempID_0_CLKF_IN1 + ); + NlwInverterBlock_BUF_IS_EMPTY_OBUF_D2_IN1 : X_INV + port map ( + I => buf_depth(1), + O => NlwInverterSignal_BUF_IS_EMPTY_OBUF_D2_IN1 + ); + NlwInverterBlock_BUF_IS_EMPTY_OBUF_D2_IN2 : X_INV + port map ( + I => SHIFT_CNT(0), + O => NlwInverterSignal_BUF_IS_EMPTY_OBUF_D2_IN2 + ); + NlwInverterBlock_BUF_IS_EMPTY_OBUF_D2_IN3 : X_INV + port map ( + I => SHIFT_CNT(1), + O => NlwInverterSignal_BUF_IS_EMPTY_OBUF_D2_IN3 + ); + NlwInverterBlock_BUF_IS_EMPTY_OBUF_D2_IN4 : X_INV + port map ( + I => SHIFT_CNT(2), + O => NlwInverterSignal_BUF_IS_EMPTY_OBUF_D2_IN4 + ); + NlwInverterBlock_BUF_IS_EMPTY_OBUF_D2_IN5 : X_INV + port map ( + I => SHIFT_CNT(3), + O => NlwInverterSignal_BUF_IS_EMPTY_OBUF_D2_IN5 + ); + NlwInverterBlock_BUF_IS_EMPTY_OBUF_D2_IN6 : X_INV + port map ( + I => SHIFT_CNT(4), + O => NlwInverterSignal_BUF_IS_EMPTY_OBUF_D2_IN6 + ); + NlwInverterBlock_BUF_IS_EMPTY_OBUF_EXP_PT_2_IN0 : X_INV + port map ( + I => SHIFT_EN, + O => NlwInverterSignal_BUF_IS_EMPTY_OBUF_EXP_PT_2_IN0 + ); + NlwInverterBlock_BUF_IS_EMPTY_OBUF_EXP_PT_2_IN1 : X_INV + port map ( + I => SHIFT_EN, + O => NlwInverterSignal_BUF_IS_EMPTY_OBUF_EXP_PT_2_IN1 + ); + NlwInverterBlock_BUF_IS_EMPTY_OBUF_EXP_PT_3_IN0 : X_INV + port map ( + I => buf_depth(0), + O => NlwInverterSignal_BUF_IS_EMPTY_OBUF_EXP_PT_3_IN0 + ); + NlwInverterBlock_BUF_IS_EMPTY_OBUF_EXP_PT_3_IN1 : X_INV + port map ( + I => buf_depth(1), + O => NlwInverterSignal_BUF_IS_EMPTY_OBUF_EXP_PT_3_IN1 + ); + NlwInverterBlock_BUF_IS_EMPTY_OBUF_EXP_PT_3_IN2 : X_INV + port map ( + I => SHIFT_CNT(2), + O => NlwInverterSignal_BUF_IS_EMPTY_OBUF_EXP_PT_3_IN2 + ); + NlwInverterBlock_BUF_IS_EMPTY_OBUF_EXP_PT_3_IN3 : X_INV + port map ( + I => SHIFT_CNT(3), + O => NlwInverterSignal_BUF_IS_EMPTY_OBUF_EXP_PT_3_IN3 + ); + NlwInverterBlock_BUF_IS_EMPTY_OBUF_EXP_PT_3_IN4 : X_INV + port map ( + I => SHIFT_CNT(4), + O => NlwInverterSignal_BUF_IS_EMPTY_OBUF_EXP_PT_3_IN4 + ); + NlwInverterBlock_SHIFT_EN_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => SHIFT_EN_RSTF, + O => NlwInverterSignal_SHIFT_EN_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_SHIFT_EN_SETF_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_SHIFT_EN_SETF_IN0 + ); + NlwInverterBlock_SHIFT_EN_SETF_IN1 : X_INV + port map ( + I => state(0), + O => NlwInverterSignal_SHIFT_EN_SETF_IN1 + ); + NlwInverterBlock_SHIFT_EN_RSTF_IN0 : X_INV + port map ( + I => SHIFT_EN_SHIFT_EN_RSTF_INT_UIM, + O => NlwInverterSignal_SHIFT_EN_RSTF_IN0 + ); + NlwInverterBlock_SHIFT_EN_RSTF_IN1 : X_INV + port map ( + I => SHIFT_EN_SHIFT_EN_RSTF_INT_UIM, + O => NlwInverterSignal_SHIFT_EN_RSTF_IN1 + ); + NlwInverterBlock_SHIFT_EN_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_SHIFT_EN_EXP_PT_0_IN0 + ); + NlwInverterBlock_SHIFT_EN_EXP_PT_0_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_SHIFT_EN_EXP_PT_0_IN2 + ); + NlwInverterBlock_SHIFT_EN_EXP_PT_0_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_SHIFT_EN_EXP_PT_0_IN4 + ); + NlwInverterBlock_SHIFT_EN_EXP_PT_0_IN6 : X_INV + port map ( + I => REG_0_11, + O => NlwInverterSignal_SHIFT_EN_EXP_PT_0_IN6 + ); + NlwInverterBlock_SHIFT_EN_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_SHIFT_EN_EXP_PT_1_IN0 + ); + NlwInverterBlock_SHIFT_EN_EXP_PT_1_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_SHIFT_EN_EXP_PT_1_IN2 + ); + NlwInverterBlock_SHIFT_EN_EXP_PT_1_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_SHIFT_EN_EXP_PT_1_IN4 + ); + NlwInverterBlock_SHIFT_EN_EXP_PT_1_IN5 : X_INV + port map ( + I => DIN_11_IBUF, + O => NlwInverterSignal_SHIFT_EN_EXP_PT_1_IN5 + ); + NlwInverterBlock_next_state_0_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => next_state_0_RSTF, + O => NlwInverterSignal_next_state_0_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_next_state_0_SETF_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_next_state_0_SETF_IN0 + ); + NlwInverterBlock_next_state_0_SETF_IN1 : X_INV + port map ( + I => state(0), + O => NlwInverterSignal_next_state_0_SETF_IN1 + ); + NlwInverterBlock_next_state_0_SETF_IN2 : X_INV + port map ( + I => state(1), + O => NlwInverterSignal_next_state_0_SETF_IN2 + ); + NlwInverterBlock_next_state_0_SETF_IN3 : X_INV + port map ( + I => Q_OpTx_FX_DC_19_UIM, + O => NlwInverterSignal_next_state_0_SETF_IN3 + ); + NlwInverterBlock_next_state_1_tsimcreated_set_and_noreset_IN0 : X_INV + port map ( + I => next_state_1_RSTF, + O => NlwInverterSignal_next_state_1_tsimcreated_set_and_noreset_IN0 + ); + NlwInverterBlock_next_state_1_SETF_IN1 : X_INV + port map ( + I => next_state_1_next_state_1_RSTF_UIM, + O => NlwInverterSignal_next_state_1_SETF_IN1 + ); + NlwInverterBlock_CCLK_OBUF_D_IN0 : X_INV + port map ( + I => CCLK_OBUF_D1, + O => NlwInverterSignal_CCLK_OBUF_D_IN0 + ); + NlwInverterBlock_CCLK_OBUF_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_CCLK_OBUF_D2_PT_1_IN0 + ); + NlwInverterBlock_CCLK_OBUF_D2_PT_1_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_CCLK_OBUF_D2_PT_1_IN1 + ); + NlwInverterBlock_CCLK_OBUF_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_CCLK_OBUF_EXP_PT_0_IN0 + ); + NlwInverterBlock_CCLK_OBUF_EXP_PT_0_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_CCLK_OBUF_EXP_PT_0_IN1 + ); + NlwInverterBlock_CCLK_OBUF_EXP_PT_0_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_CCLK_OBUF_EXP_PT_0_IN3 + ); + NlwInverterBlock_CCLK_OBUF_EXP_PT_0_IN5 : X_INV + port map ( + I => REG_0_13, + O => NlwInverterSignal_CCLK_OBUF_EXP_PT_0_IN5 + ); + NlwInverterBlock_CCLK_OBUF_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_CCLK_OBUF_EXP_PT_1_IN0 + ); + NlwInverterBlock_CCLK_OBUF_EXP_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_CCLK_OBUF_EXP_PT_1_IN1 + ); + NlwInverterBlock_CCLK_OBUF_EXP_PT_1_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_CCLK_OBUF_EXP_PT_1_IN3 + ); + NlwInverterBlock_CCLK_OBUF_EXP_PT_1_IN4 : X_INV + port map ( + I => REG_0_12, + O => NlwInverterSignal_CCLK_OBUF_EXP_PT_1_IN4 + ); + NlwInverterBlock_CCLK_OBUF_EXP_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_CCLK_OBUF_EXP_PT_2_IN0 + ); + NlwInverterBlock_CCLK_OBUF_EXP_PT_2_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_CCLK_OBUF_EXP_PT_2_IN2 + ); + NlwInverterBlock_CCLK_OBUF_EXP_PT_2_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_CCLK_OBUF_EXP_PT_2_IN4 + ); + NlwInverterBlock_CCLK_OBUF_EXP_PT_2_IN6 : X_INV + port map ( + I => REG_0_13, + O => NlwInverterSignal_CCLK_OBUF_EXP_PT_2_IN6 + ); + NlwInverterBlock_CCLK_OBUF_EXP_PT_3_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_CCLK_OBUF_EXP_PT_3_IN0 + ); + NlwInverterBlock_CCLK_OBUF_EXP_PT_3_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_CCLK_OBUF_EXP_PT_3_IN2 + ); + NlwInverterBlock_CCLK_OBUF_EXP_PT_3_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_CCLK_OBUF_EXP_PT_3_IN4 + ); + NlwInverterBlock_CCLK_OBUF_EXP_PT_3_IN5 : X_INV + port map ( + I => DIN_13_IBUF, + O => NlwInverterSignal_CCLK_OBUF_EXP_PT_3_IN5 + ); + NlwInverterBlock_buf_depth_0_buf_depth_0_RSTF_EXP_PT_0_IN0 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_0_IN0 + ); + NlwInverterBlock_buf_depth_0_buf_depth_0_RSTF_EXP_PT_0_IN2 : X_INV + port map ( + I => SHIFT_CNT(0), + O => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_0_IN2 + ); + NlwInverterBlock_buf_depth_0_buf_depth_0_RSTF_EXP_PT_0_IN3 : X_INV + port map ( + I => SHIFT_CNT(1), + O => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_0_IN3 + ); + NlwInverterBlock_buf_depth_0_buf_depth_0_RSTF_EXP_PT_0_IN4 : X_INV + port map ( + I => SHIFT_CNT(2), + O => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_0_IN4 + ); + NlwInverterBlock_buf_depth_0_buf_depth_0_RSTF_EXP_PT_1_IN0 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_1_IN0 + ); + NlwInverterBlock_buf_depth_0_buf_depth_0_RSTF_EXP_PT_1_IN2 : X_INV + port map ( + I => SHIFT_CNT(0), + O => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_1_IN2 + ); + NlwInverterBlock_buf_depth_0_buf_depth_0_RSTF_EXP_PT_1_IN3 : X_INV + port map ( + I => SHIFT_CNT(1), + O => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_1_IN3 + ); + NlwInverterBlock_buf_depth_0_buf_depth_0_RSTF_EXP_PT_1_IN4 : X_INV + port map ( + I => SHIFT_CNT(2), + O => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_1_IN4 + ); + NlwInverterBlock_buf_depth_0_buf_depth_0_RSTF_EXP_PT_2_IN0 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_2_IN0 + ); + NlwInverterBlock_buf_depth_0_buf_depth_0_RSTF_EXP_PT_2_IN1 : X_INV + port map ( + I => SHIFT_CNT(0), + O => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_2_IN1 + ); + NlwInverterBlock_buf_depth_0_buf_depth_0_RSTF_EXP_PT_2_IN2 : X_INV + port map ( + I => SHIFT_CNT(1), + O => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_2_IN2 + ); + NlwInverterBlock_buf_depth_0_buf_depth_0_RSTF_EXP_PT_2_IN3 : X_INV + port map ( + I => SHIFT_CNT(2), + O => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_2_IN3 + ); + NlwInverterBlock_buf_depth_1_buf_depth_1_RSTF_D2_PT_2_IN1 : X_INV + port map ( + I => buf_depth(0), + O => NlwInverterSignal_buf_depth_1_buf_depth_1_RSTF_D2_PT_2_IN1 + ); + NlwInverterBlock_buf_depth_1_buf_depth_1_RSTF_D2_PT_2_IN2 : X_INV + port map ( + I => buf_depth(1), + O => NlwInverterSignal_buf_depth_1_buf_depth_1_RSTF_D2_PT_2_IN2 + ); + NlwInverterBlock_SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_0_IN0 + ); + NlwInverterBlock_SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_0_IN2 : X_INV + port map ( + I => state(1), + O => NlwInverterSignal_SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_0_IN2 + ); + NlwInverterBlock_SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_1_IN0 + ); + NlwInverterBlock_SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_1_IN1 : X_INV + port map ( + I => state(0), + O => NlwInverterSignal_SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_1_IN1 + ); + NlwInverterBlock_OpTx_FX_DC_19_D2_PT_1_IN1 : X_INV + port map ( + I => buf_depth(1), + O => NlwInverterSignal_OpTx_FX_DC_19_D2_PT_1_IN1 + ); + NlwInverterBlock_OpTx_FX_DC_19_D2_PT_1_IN2 : X_INV + port map ( + I => SHIFT_CNT(0), + O => NlwInverterSignal_OpTx_FX_DC_19_D2_PT_1_IN2 + ); + NlwInverterBlock_OpTx_FX_DC_19_D2_PT_1_IN3 : X_INV + port map ( + I => SHIFT_CNT(1), + O => NlwInverterSignal_OpTx_FX_DC_19_D2_PT_1_IN3 + ); + NlwInverterBlock_OpTx_FX_DC_19_D2_PT_1_IN4 : X_INV + port map ( + I => SHIFT_CNT(2), + O => NlwInverterSignal_OpTx_FX_DC_19_D2_PT_1_IN4 + ); + NlwInverterBlock_OpTx_FX_DC_19_D2_PT_1_IN5 : X_INV + port map ( + I => SHIFT_CNT(3), + O => NlwInverterSignal_OpTx_FX_DC_19_D2_PT_1_IN5 + ); + NlwInverterBlock_OpTx_FX_DC_19_D2_PT_1_IN6 : X_INV + port map ( + I => SHIFT_CNT(4), + O => NlwInverterSignal_OpTx_FX_DC_19_D2_PT_1_IN6 + ); + NlwInverterBlock_next_state_0_next_state_0_RSTF_D2_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_0_IN0 + ); + NlwInverterBlock_next_state_0_next_state_0_RSTF_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_1_IN0 + ); + NlwInverterBlock_next_state_0_next_state_0_RSTF_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_2_IN0 + ); + NlwInverterBlock_next_state_0_next_state_0_RSTF_D2_PT_3_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_3_IN0 + ); + NlwInverterBlock_next_state_0_next_state_0_RSTF_D2_PT_3_IN2 : X_INV + port map ( + I => buf_depth(1), + O => NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_3_IN2 + ); + NlwInverterBlock_next_state_0_next_state_0_RSTF_D2_PT_3_IN3 : X_INV + port map ( + I => SHIFT_CNT(0), + O => NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_3_IN3 + ); + NlwInverterBlock_next_state_0_next_state_0_RSTF_D2_PT_3_IN4 : X_INV + port map ( + I => SHIFT_CNT(1), + O => NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_3_IN4 + ); + NlwInverterBlock_next_state_0_next_state_0_RSTF_D2_PT_3_IN5 : X_INV + port map ( + I => SHIFT_CNT(2), + O => NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_3_IN5 + ); + NlwInverterBlock_next_state_0_next_state_0_RSTF_D2_PT_3_IN6 : X_INV + port map ( + I => SHIFT_CNT(3), + O => NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_3_IN6 + ); + NlwInverterBlock_next_state_0_next_state_0_RSTF_D2_PT_3_IN7 : X_INV + port map ( + I => SHIFT_CNT(4), + O => NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_3_IN7 + ); + NlwInverterBlock_next_state_1_next_state_1_RSTF_D2_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_0_IN0 + ); + NlwInverterBlock_next_state_1_next_state_1_RSTF_D2_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_1_IN0 + ); + NlwInverterBlock_next_state_1_next_state_1_RSTF_D2_PT_1_IN1 : X_INV + port map ( + I => nINIT_B_IBUF, + O => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_1_IN1 + ); + NlwInverterBlock_next_state_1_next_state_1_RSTF_D2_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_2_IN0 + ); + NlwInverterBlock_next_state_1_next_state_1_RSTF_D2_PT_3_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_3_IN0 + ); + NlwInverterBlock_next_state_1_next_state_1_RSTF_D2_PT_3_IN1 : X_INV + port map ( + I => state(0), + O => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_3_IN1 + ); + NlwInverterBlock_next_state_1_next_state_1_RSTF_D2_PT_3_IN2 : X_INV + port map ( + I => state(1), + O => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_3_IN2 + ); + NlwInverterBlock_next_state_1_next_state_1_RSTF_D2_PT_4_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_4_IN0 + ); + NlwInverterBlock_next_state_1_next_state_1_RSTF_D2_PT_4_IN2 : X_INV + port map ( + I => buf_depth(1), + O => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_4_IN2 + ); + NlwInverterBlock_next_state_1_next_state_1_RSTF_D2_PT_4_IN3 : X_INV + port map ( + I => SHIFT_CNT(0), + O => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_4_IN3 + ); + NlwInverterBlock_next_state_1_next_state_1_RSTF_D2_PT_4_IN4 : X_INV + port map ( + I => SHIFT_CNT(1), + O => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_4_IN4 + ); + NlwInverterBlock_next_state_1_next_state_1_RSTF_D2_PT_4_IN5 : X_INV + port map ( + I => SHIFT_CNT(2), + O => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_4_IN5 + ); + NlwInverterBlock_next_state_1_next_state_1_RSTF_D2_PT_4_IN6 : X_INV + port map ( + I => SHIFT_CNT(3), + O => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_4_IN6 + ); + NlwInverterBlock_next_state_1_next_state_1_RSTF_D2_PT_4_IN7 : X_INV + port map ( + I => SHIFT_CNT(4), + O => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_4_IN7 + ); + NlwInverterBlock_EXP18_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP18_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP18_EXP_PT_0_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_EXP18_EXP_PT_0_IN2 + ); + NlwInverterBlock_EXP18_EXP_PT_0_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP18_EXP_PT_0_IN4 + ); + NlwInverterBlock_EXP18_EXP_PT_0_IN6 : X_INV + port map ( + I => REG_0_1, + O => NlwInverterSignal_EXP18_EXP_PT_0_IN6 + ); + NlwInverterBlock_EXP18_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP18_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP18_EXP_PT_1_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_EXP18_EXP_PT_1_IN2 + ); + NlwInverterBlock_EXP18_EXP_PT_1_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP18_EXP_PT_1_IN4 + ); + NlwInverterBlock_EXP18_EXP_PT_1_IN5 : X_INV + port map ( + I => DIN_1_IBUF, + O => NlwInverterSignal_EXP18_EXP_PT_1_IN5 + ); + NlwInverterBlock_EXP19_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP19_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP19_EXP_PT_0_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_EXP19_EXP_PT_0_IN2 + ); + NlwInverterBlock_EXP19_EXP_PT_0_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP19_EXP_PT_0_IN4 + ); + NlwInverterBlock_EXP19_EXP_PT_0_IN6 : X_INV + port map ( + I => REG_0_5, + O => NlwInverterSignal_EXP19_EXP_PT_0_IN6 + ); + NlwInverterBlock_EXP19_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP19_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP19_EXP_PT_1_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_EXP19_EXP_PT_1_IN2 + ); + NlwInverterBlock_EXP19_EXP_PT_1_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP19_EXP_PT_1_IN4 + ); + NlwInverterBlock_EXP19_EXP_PT_1_IN5 : X_INV + port map ( + I => DIN_5_IBUF, + O => NlwInverterSignal_EXP19_EXP_PT_1_IN5 + ); + NlwInverterBlock_EXP20_EXP_tsimrenamed_net_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP20_EXP_tsimrenamed_net_IN0 + ); + NlwInverterBlock_EXP20_EXP_tsimrenamed_net_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_EXP20_EXP_tsimrenamed_net_IN2 + ); + NlwInverterBlock_EXP20_EXP_tsimrenamed_net_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP20_EXP_tsimrenamed_net_IN4 + ); + NlwInverterBlock_EXP20_EXP_tsimrenamed_net_IN5 : X_INV + port map ( + I => DIN_6_IBUF, + O => NlwInverterSignal_EXP20_EXP_tsimrenamed_net_IN5 + ); + NlwInverterBlock_EXP21_EXP_tsimrenamed_net_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP21_EXP_tsimrenamed_net_IN0 + ); + NlwInverterBlock_EXP21_EXP_tsimrenamed_net_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_EXP21_EXP_tsimrenamed_net_IN2 + ); + NlwInverterBlock_EXP21_EXP_tsimrenamed_net_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP21_EXP_tsimrenamed_net_IN4 + ); + NlwInverterBlock_EXP21_EXP_tsimrenamed_net_IN6 : X_INV + port map ( + I => REG_0_6, + O => NlwInverterSignal_EXP21_EXP_tsimrenamed_net_IN6 + ); + NlwInverterBlock_EXP22_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP22_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP22_EXP_PT_0_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_EXP22_EXP_PT_0_IN1 + ); + NlwInverterBlock_EXP22_EXP_PT_0_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP22_EXP_PT_0_IN3 + ); + NlwInverterBlock_EXP22_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP22_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP22_EXP_PT_1_IN1 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_EXP22_EXP_PT_1_IN1 + ); + NlwInverterBlock_EXP22_EXP_PT_1_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP22_EXP_PT_1_IN3 + ); + NlwInverterBlock_EXP22_EXP_PT_1_IN4 : X_INV + port map ( + I => DIN_0_IBUF, + O => NlwInverterSignal_EXP22_EXP_PT_1_IN4 + ); + NlwInverterBlock_EXP22_EXP_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP22_EXP_PT_2_IN0 + ); + NlwInverterBlock_EXP22_EXP_PT_2_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_EXP22_EXP_PT_2_IN2 + ); + NlwInverterBlock_EXP22_EXP_PT_2_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP22_EXP_PT_2_IN4 + ); + NlwInverterBlock_EXP22_EXP_PT_2_IN6 : X_INV + port map ( + I => REG_0_0, + O => NlwInverterSignal_EXP22_EXP_PT_2_IN6 + ); + NlwInverterBlock_EXP23_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP23_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP23_EXP_PT_0_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_EXP23_EXP_PT_0_IN1 + ); + NlwInverterBlock_EXP23_EXP_PT_0_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP23_EXP_PT_0_IN3 + ); + NlwInverterBlock_EXP23_EXP_PT_0_IN5 : X_INV + port map ( + I => REG_0_3, + O => NlwInverterSignal_EXP23_EXP_PT_0_IN5 + ); + NlwInverterBlock_EXP23_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP23_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP23_EXP_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_EXP23_EXP_PT_1_IN1 + ); + NlwInverterBlock_EXP23_EXP_PT_1_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP23_EXP_PT_1_IN3 + ); + NlwInverterBlock_EXP23_EXP_PT_1_IN4 : X_INV + port map ( + I => REG_0_2, + O => NlwInverterSignal_EXP23_EXP_PT_1_IN4 + ); + NlwInverterBlock_EXP23_EXP_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP23_EXP_PT_2_IN0 + ); + NlwInverterBlock_EXP23_EXP_PT_2_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_EXP23_EXP_PT_2_IN2 + ); + NlwInverterBlock_EXP23_EXP_PT_2_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP23_EXP_PT_2_IN4 + ); + NlwInverterBlock_EXP23_EXP_PT_2_IN6 : X_INV + port map ( + I => REG_0_3, + O => NlwInverterSignal_EXP23_EXP_PT_2_IN6 + ); + NlwInverterBlock_EXP23_EXP_PT_3_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP23_EXP_PT_3_IN0 + ); + NlwInverterBlock_EXP23_EXP_PT_3_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_EXP23_EXP_PT_3_IN2 + ); + NlwInverterBlock_EXP23_EXP_PT_3_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP23_EXP_PT_3_IN4 + ); + NlwInverterBlock_EXP23_EXP_PT_3_IN5 : X_INV + port map ( + I => DIN_3_IBUF, + O => NlwInverterSignal_EXP23_EXP_PT_3_IN5 + ); + NlwInverterBlock_EXP24_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP24_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP24_EXP_PT_0_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_EXP24_EXP_PT_0_IN2 + ); + NlwInverterBlock_EXP24_EXP_PT_0_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP24_EXP_PT_0_IN4 + ); + NlwInverterBlock_EXP24_EXP_PT_0_IN6 : X_INV + port map ( + I => REG_0_31, + O => NlwInverterSignal_EXP24_EXP_PT_0_IN6 + ); + NlwInverterBlock_EXP24_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP24_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP24_EXP_PT_1_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_EXP24_EXP_PT_1_IN2 + ); + NlwInverterBlock_EXP24_EXP_PT_1_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP24_EXP_PT_1_IN4 + ); + NlwInverterBlock_EXP24_EXP_PT_1_IN5 : X_INV + port map ( + I => DIN_31_IBUF, + O => NlwInverterSignal_EXP24_EXP_PT_1_IN5 + ); + NlwInverterBlock_EXP25_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP25_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP25_EXP_PT_0_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_EXP25_EXP_PT_0_IN1 + ); + NlwInverterBlock_EXP25_EXP_PT_0_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP25_EXP_PT_0_IN3 + ); + NlwInverterBlock_EXP25_EXP_PT_0_IN5 : X_INV + port map ( + I => REG_0_30, + O => NlwInverterSignal_EXP25_EXP_PT_0_IN5 + ); + NlwInverterBlock_EXP25_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP25_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP25_EXP_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_EXP25_EXP_PT_1_IN1 + ); + NlwInverterBlock_EXP25_EXP_PT_1_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP25_EXP_PT_1_IN3 + ); + NlwInverterBlock_EXP25_EXP_PT_1_IN4 : X_INV + port map ( + I => REG_0_29, + O => NlwInverterSignal_EXP25_EXP_PT_1_IN4 + ); + NlwInverterBlock_EXP25_EXP_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP25_EXP_PT_2_IN0 + ); + NlwInverterBlock_EXP25_EXP_PT_2_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_EXP25_EXP_PT_2_IN2 + ); + NlwInverterBlock_EXP25_EXP_PT_2_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP25_EXP_PT_2_IN4 + ); + NlwInverterBlock_EXP25_EXP_PT_2_IN6 : X_INV + port map ( + I => REG_0_30, + O => NlwInverterSignal_EXP25_EXP_PT_2_IN6 + ); + NlwInverterBlock_EXP25_EXP_PT_3_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP25_EXP_PT_3_IN0 + ); + NlwInverterBlock_EXP25_EXP_PT_3_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_EXP25_EXP_PT_3_IN2 + ); + NlwInverterBlock_EXP25_EXP_PT_3_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP25_EXP_PT_3_IN4 + ); + NlwInverterBlock_EXP25_EXP_PT_3_IN5 : X_INV + port map ( + I => DIN_30_IBUF, + O => NlwInverterSignal_EXP25_EXP_PT_3_IN5 + ); + NlwInverterBlock_EXP26_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP26_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP26_EXP_PT_0_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_EXP26_EXP_PT_0_IN2 + ); + NlwInverterBlock_EXP26_EXP_PT_0_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP26_EXP_PT_0_IN4 + ); + NlwInverterBlock_EXP26_EXP_PT_0_IN6 : X_INV + port map ( + I => REG_0_28, + O => NlwInverterSignal_EXP26_EXP_PT_0_IN6 + ); + NlwInverterBlock_EXP26_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP26_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP26_EXP_PT_1_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_EXP26_EXP_PT_1_IN2 + ); + NlwInverterBlock_EXP26_EXP_PT_1_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP26_EXP_PT_1_IN4 + ); + NlwInverterBlock_EXP26_EXP_PT_1_IN5 : X_INV + port map ( + I => DIN_28_IBUF, + O => NlwInverterSignal_EXP26_EXP_PT_1_IN5 + ); + NlwInverterBlock_EXP27_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP27_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP27_EXP_PT_0_IN6 : X_INV + port map ( + I => REG_1_31, + O => NlwInverterSignal_EXP27_EXP_PT_0_IN6 + ); + NlwInverterBlock_EXP27_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP27_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP27_EXP_PT_1_IN5 : X_INV + port map ( + I => DIN_31_IBUF, + O => NlwInverterSignal_EXP27_EXP_PT_1_IN5 + ); + NlwInverterBlock_EXP28_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP28_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP28_EXP_PT_0_IN6 : X_INV + port map ( + I => REG_1_29, + O => NlwInverterSignal_EXP28_EXP_PT_0_IN6 + ); + NlwInverterBlock_EXP28_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP28_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP28_EXP_PT_1_IN5 : X_INV + port map ( + I => DIN_29_IBUF, + O => NlwInverterSignal_EXP28_EXP_PT_1_IN5 + ); + NlwInverterBlock_EXP29_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP29_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP29_EXP_PT_0_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_EXP29_EXP_PT_0_IN1 + ); + NlwInverterBlock_EXP29_EXP_PT_0_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP29_EXP_PT_0_IN3 + ); + NlwInverterBlock_EXP29_EXP_PT_0_IN5 : X_INV + port map ( + I => REG_0_17, + O => NlwInverterSignal_EXP29_EXP_PT_0_IN5 + ); + NlwInverterBlock_EXP29_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP29_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP29_EXP_PT_1_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_EXP29_EXP_PT_1_IN2 + ); + NlwInverterBlock_EXP29_EXP_PT_1_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP29_EXP_PT_1_IN4 + ); + NlwInverterBlock_EXP29_EXP_PT_1_IN6 : X_INV + port map ( + I => REG_0_17, + O => NlwInverterSignal_EXP29_EXP_PT_1_IN6 + ); + NlwInverterBlock_EXP29_EXP_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP29_EXP_PT_2_IN0 + ); + NlwInverterBlock_EXP29_EXP_PT_2_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_EXP29_EXP_PT_2_IN2 + ); + NlwInverterBlock_EXP29_EXP_PT_2_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP29_EXP_PT_2_IN4 + ); + NlwInverterBlock_EXP29_EXP_PT_2_IN5 : X_INV + port map ( + I => DIN_17_IBUF, + O => NlwInverterSignal_EXP29_EXP_PT_2_IN5 + ); + NlwInverterBlock_EXP30_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP30_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP30_EXP_PT_0_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_EXP30_EXP_PT_0_IN1 + ); + NlwInverterBlock_EXP30_EXP_PT_0_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP30_EXP_PT_0_IN3 + ); + NlwInverterBlock_EXP30_EXP_PT_0_IN5 : X_INV + port map ( + I => REG_0_15, + O => NlwInverterSignal_EXP30_EXP_PT_0_IN5 + ); + NlwInverterBlock_EXP30_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP30_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP30_EXP_PT_1_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_EXP30_EXP_PT_1_IN2 + ); + NlwInverterBlock_EXP30_EXP_PT_1_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP30_EXP_PT_1_IN4 + ); + NlwInverterBlock_EXP30_EXP_PT_1_IN6 : X_INV + port map ( + I => REG_0_15, + O => NlwInverterSignal_EXP30_EXP_PT_1_IN6 + ); + NlwInverterBlock_EXP30_EXP_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP30_EXP_PT_2_IN0 + ); + NlwInverterBlock_EXP30_EXP_PT_2_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_EXP30_EXP_PT_2_IN2 + ); + NlwInverterBlock_EXP30_EXP_PT_2_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP30_EXP_PT_2_IN4 + ); + NlwInverterBlock_EXP30_EXP_PT_2_IN5 : X_INV + port map ( + I => DIN_15_IBUF, + O => NlwInverterSignal_EXP30_EXP_PT_2_IN5 + ); + NlwInverterBlock_EXP31_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP31_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP31_EXP_PT_0_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_EXP31_EXP_PT_0_IN2 + ); + NlwInverterBlock_EXP31_EXP_PT_0_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP31_EXP_PT_0_IN4 + ); + NlwInverterBlock_EXP31_EXP_PT_0_IN6 : X_INV + port map ( + I => REG_0_20, + O => NlwInverterSignal_EXP31_EXP_PT_0_IN6 + ); + NlwInverterBlock_EXP31_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP31_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP31_EXP_PT_1_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_EXP31_EXP_PT_1_IN2 + ); + NlwInverterBlock_EXP31_EXP_PT_1_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP31_EXP_PT_1_IN4 + ); + NlwInverterBlock_EXP31_EXP_PT_1_IN5 : X_INV + port map ( + I => DIN_20_IBUF, + O => NlwInverterSignal_EXP31_EXP_PT_1_IN5 + ); + NlwInverterBlock_EXP32_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP32_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP32_EXP_PT_0_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_EXP32_EXP_PT_0_IN2 + ); + NlwInverterBlock_EXP32_EXP_PT_0_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP32_EXP_PT_0_IN4 + ); + NlwInverterBlock_EXP32_EXP_PT_0_IN6 : X_INV + port map ( + I => REG_0_18, + O => NlwInverterSignal_EXP32_EXP_PT_0_IN6 + ); + NlwInverterBlock_EXP32_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP32_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP32_EXP_PT_1_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_EXP32_EXP_PT_1_IN2 + ); + NlwInverterBlock_EXP32_EXP_PT_1_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP32_EXP_PT_1_IN4 + ); + NlwInverterBlock_EXP32_EXP_PT_1_IN5 : X_INV + port map ( + I => DIN_18_IBUF, + O => NlwInverterSignal_EXP32_EXP_PT_1_IN5 + ); + NlwInverterBlock_EXP33_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP33_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP33_EXP_PT_0_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_EXP33_EXP_PT_0_IN1 + ); + NlwInverterBlock_EXP33_EXP_PT_0_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP33_EXP_PT_0_IN3 + ); + NlwInverterBlock_EXP33_EXP_PT_0_IN5 : X_INV + port map ( + I => REG_0_23, + O => NlwInverterSignal_EXP33_EXP_PT_0_IN5 + ); + NlwInverterBlock_EXP33_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP33_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP33_EXP_PT_1_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_EXP33_EXP_PT_1_IN2 + ); + NlwInverterBlock_EXP33_EXP_PT_1_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP33_EXP_PT_1_IN4 + ); + NlwInverterBlock_EXP33_EXP_PT_1_IN6 : X_INV + port map ( + I => REG_0_23, + O => NlwInverterSignal_EXP33_EXP_PT_1_IN6 + ); + NlwInverterBlock_EXP33_EXP_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP33_EXP_PT_2_IN0 + ); + NlwInverterBlock_EXP33_EXP_PT_2_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_EXP33_EXP_PT_2_IN2 + ); + NlwInverterBlock_EXP33_EXP_PT_2_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP33_EXP_PT_2_IN4 + ); + NlwInverterBlock_EXP33_EXP_PT_2_IN5 : X_INV + port map ( + I => DIN_23_IBUF, + O => NlwInverterSignal_EXP33_EXP_PT_2_IN5 + ); + NlwInverterBlock_EXP34_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP34_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP34_EXP_PT_0_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_EXP34_EXP_PT_0_IN1 + ); + NlwInverterBlock_EXP34_EXP_PT_0_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP34_EXP_PT_0_IN3 + ); + NlwInverterBlock_EXP34_EXP_PT_0_IN5 : X_INV + port map ( + I => REG_0_21, + O => NlwInverterSignal_EXP34_EXP_PT_0_IN5 + ); + NlwInverterBlock_EXP34_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP34_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP34_EXP_PT_1_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_EXP34_EXP_PT_1_IN2 + ); + NlwInverterBlock_EXP34_EXP_PT_1_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP34_EXP_PT_1_IN4 + ); + NlwInverterBlock_EXP34_EXP_PT_1_IN6 : X_INV + port map ( + I => REG_0_21, + O => NlwInverterSignal_EXP34_EXP_PT_1_IN6 + ); + NlwInverterBlock_EXP34_EXP_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP34_EXP_PT_2_IN0 + ); + NlwInverterBlock_EXP34_EXP_PT_2_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_EXP34_EXP_PT_2_IN2 + ); + NlwInverterBlock_EXP34_EXP_PT_2_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP34_EXP_PT_2_IN4 + ); + NlwInverterBlock_EXP34_EXP_PT_2_IN5 : X_INV + port map ( + I => DIN_21_IBUF, + O => NlwInverterSignal_EXP34_EXP_PT_2_IN5 + ); + NlwInverterBlock_EXP35_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP35_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP35_EXP_PT_0_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_EXP35_EXP_PT_0_IN2 + ); + NlwInverterBlock_EXP35_EXP_PT_0_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP35_EXP_PT_0_IN4 + ); + NlwInverterBlock_EXP35_EXP_PT_0_IN6 : X_INV + port map ( + I => REG_0_26, + O => NlwInverterSignal_EXP35_EXP_PT_0_IN6 + ); + NlwInverterBlock_EXP35_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP35_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP35_EXP_PT_1_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_EXP35_EXP_PT_1_IN2 + ); + NlwInverterBlock_EXP35_EXP_PT_1_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP35_EXP_PT_1_IN4 + ); + NlwInverterBlock_EXP35_EXP_PT_1_IN5 : X_INV + port map ( + I => DIN_26_IBUF, + O => NlwInverterSignal_EXP35_EXP_PT_1_IN5 + ); + NlwInverterBlock_EXP36_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP36_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP36_EXP_PT_0_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_EXP36_EXP_PT_0_IN2 + ); + NlwInverterBlock_EXP36_EXP_PT_0_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP36_EXP_PT_0_IN4 + ); + NlwInverterBlock_EXP36_EXP_PT_0_IN6 : X_INV + port map ( + I => REG_0_24, + O => NlwInverterSignal_EXP36_EXP_PT_0_IN6 + ); + NlwInverterBlock_EXP36_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP36_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP36_EXP_PT_1_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_EXP36_EXP_PT_1_IN2 + ); + NlwInverterBlock_EXP36_EXP_PT_1_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP36_EXP_PT_1_IN4 + ); + NlwInverterBlock_EXP36_EXP_PT_1_IN5 : X_INV + port map ( + I => DIN_24_IBUF, + O => NlwInverterSignal_EXP36_EXP_PT_1_IN5 + ); + NlwInverterBlock_EXP37_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP37_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP37_EXP_PT_0_IN6 : X_INV + port map ( + I => REG_1_27, + O => NlwInverterSignal_EXP37_EXP_PT_0_IN6 + ); + NlwInverterBlock_EXP37_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP37_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP37_EXP_PT_1_IN5 : X_INV + port map ( + I => DIN_27_IBUF, + O => NlwInverterSignal_EXP37_EXP_PT_1_IN5 + ); + NlwInverterBlock_EXP38_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP38_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP38_EXP_PT_0_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_EXP38_EXP_PT_0_IN1 + ); + NlwInverterBlock_EXP38_EXP_PT_0_IN5 : X_INV + port map ( + I => REG_1_24, + O => NlwInverterSignal_EXP38_EXP_PT_0_IN5 + ); + NlwInverterBlock_EXP38_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP38_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP38_EXP_PT_1_IN6 : X_INV + port map ( + I => REG_1_24, + O => NlwInverterSignal_EXP38_EXP_PT_1_IN6 + ); + NlwInverterBlock_EXP38_EXP_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP38_EXP_PT_2_IN0 + ); + NlwInverterBlock_EXP38_EXP_PT_2_IN5 : X_INV + port map ( + I => DIN_24_IBUF, + O => NlwInverterSignal_EXP38_EXP_PT_2_IN5 + ); + NlwInverterBlock_EXP39_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP39_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP39_EXP_PT_0_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_EXP39_EXP_PT_0_IN1 + ); + NlwInverterBlock_EXP39_EXP_PT_0_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP39_EXP_PT_0_IN3 + ); + NlwInverterBlock_EXP39_EXP_PT_0_IN5 : X_INV + port map ( + I => REG_0_27, + O => NlwInverterSignal_EXP39_EXP_PT_0_IN5 + ); + NlwInverterBlock_EXP39_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP39_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP39_EXP_PT_1_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_EXP39_EXP_PT_1_IN2 + ); + NlwInverterBlock_EXP39_EXP_PT_1_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP39_EXP_PT_1_IN4 + ); + NlwInverterBlock_EXP39_EXP_PT_1_IN6 : X_INV + port map ( + I => REG_0_27, + O => NlwInverterSignal_EXP39_EXP_PT_1_IN6 + ); + NlwInverterBlock_EXP39_EXP_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP39_EXP_PT_2_IN0 + ); + NlwInverterBlock_EXP39_EXP_PT_2_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_EXP39_EXP_PT_2_IN2 + ); + NlwInverterBlock_EXP39_EXP_PT_2_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP39_EXP_PT_2_IN4 + ); + NlwInverterBlock_EXP39_EXP_PT_2_IN5 : X_INV + port map ( + I => DIN_27_IBUF, + O => NlwInverterSignal_EXP39_EXP_PT_2_IN5 + ); + NlwInverterBlock_EXP40_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP40_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP40_EXP_PT_0_IN6 : X_INV + port map ( + I => REG_1_26, + O => NlwInverterSignal_EXP40_EXP_PT_0_IN6 + ); + NlwInverterBlock_EXP40_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP40_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP40_EXP_PT_1_IN5 : X_INV + port map ( + I => DIN_26_IBUF, + O => NlwInverterSignal_EXP40_EXP_PT_1_IN5 + ); + NlwInverterBlock_EXP41_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP41_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP41_EXP_PT_0_IN6 : X_INV + port map ( + I => REG_1_25, + O => NlwInverterSignal_EXP41_EXP_PT_0_IN6 + ); + NlwInverterBlock_EXP41_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP41_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP41_EXP_PT_1_IN5 : X_INV + port map ( + I => DIN_25_IBUF, + O => NlwInverterSignal_EXP41_EXP_PT_1_IN5 + ); + NlwInverterBlock_EXP42_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP42_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP42_EXP_PT_0_IN6 : X_INV + port map ( + I => REG_1_7, + O => NlwInverterSignal_EXP42_EXP_PT_0_IN6 + ); + NlwInverterBlock_EXP42_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP42_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP42_EXP_PT_1_IN5 : X_INV + port map ( + I => DIN_7_IBUF, + O => NlwInverterSignal_EXP42_EXP_PT_1_IN5 + ); + NlwInverterBlock_EXP43_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP43_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP43_EXP_PT_0_IN6 : X_INV + port map ( + I => REG_1_10, + O => NlwInverterSignal_EXP43_EXP_PT_0_IN6 + ); + NlwInverterBlock_EXP43_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP43_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP43_EXP_PT_1_IN5 : X_INV + port map ( + I => DIN_10_IBUF, + O => NlwInverterSignal_EXP43_EXP_PT_1_IN5 + ); + NlwInverterBlock_EXP44_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP44_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP44_EXP_PT_0_IN6 : X_INV + port map ( + I => REG_1_9, + O => NlwInverterSignal_EXP44_EXP_PT_0_IN6 + ); + NlwInverterBlock_EXP44_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP44_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP44_EXP_PT_1_IN5 : X_INV + port map ( + I => DIN_9_IBUF, + O => NlwInverterSignal_EXP44_EXP_PT_1_IN5 + ); + NlwInverterBlock_EXP45_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP45_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP45_EXP_PT_0_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_EXP45_EXP_PT_0_IN1 + ); + NlwInverterBlock_EXP45_EXP_PT_0_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP45_EXP_PT_0_IN3 + ); + NlwInverterBlock_EXP45_EXP_PT_0_IN4 : X_INV + port map ( + I => REG_0_9, + O => NlwInverterSignal_EXP45_EXP_PT_0_IN4 + ); + NlwInverterBlock_EXP45_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP45_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP45_EXP_PT_1_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_EXP45_EXP_PT_1_IN2 + ); + NlwInverterBlock_EXP45_EXP_PT_1_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP45_EXP_PT_1_IN4 + ); + NlwInverterBlock_EXP45_EXP_PT_1_IN6 : X_INV + port map ( + I => DIN_9_IBUF, + O => NlwInverterSignal_EXP45_EXP_PT_1_IN6 + ); + NlwInverterBlock_EXP45_EXP_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP45_EXP_PT_2_IN0 + ); + NlwInverterBlock_EXP45_EXP_PT_2_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_EXP45_EXP_PT_2_IN2 + ); + NlwInverterBlock_EXP45_EXP_PT_2_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP45_EXP_PT_2_IN4 + ); + NlwInverterBlock_EXP45_EXP_PT_2_IN5 : X_INV + port map ( + I => REG_0_9, + O => NlwInverterSignal_EXP45_EXP_PT_2_IN5 + ); + NlwInverterBlock_EXP46_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP46_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP46_EXP_PT_0_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_EXP46_EXP_PT_0_IN1 + ); + NlwInverterBlock_EXP46_EXP_PT_0_IN3 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP46_EXP_PT_0_IN3 + ); + NlwInverterBlock_EXP46_EXP_PT_0_IN5 : X_INV + port map ( + I => REG_0_7, + O => NlwInverterSignal_EXP46_EXP_PT_0_IN5 + ); + NlwInverterBlock_EXP46_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP46_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP46_EXP_PT_1_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_EXP46_EXP_PT_1_IN2 + ); + NlwInverterBlock_EXP46_EXP_PT_1_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP46_EXP_PT_1_IN4 + ); + NlwInverterBlock_EXP46_EXP_PT_1_IN6 : X_INV + port map ( + I => REG_0_7, + O => NlwInverterSignal_EXP46_EXP_PT_1_IN6 + ); + NlwInverterBlock_EXP46_EXP_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP46_EXP_PT_2_IN0 + ); + NlwInverterBlock_EXP46_EXP_PT_2_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_EXP46_EXP_PT_2_IN2 + ); + NlwInverterBlock_EXP46_EXP_PT_2_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP46_EXP_PT_2_IN4 + ); + NlwInverterBlock_EXP46_EXP_PT_2_IN5 : X_INV + port map ( + I => DIN_7_IBUF, + O => NlwInverterSignal_EXP46_EXP_PT_2_IN5 + ); + NlwInverterBlock_EXP47_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP47_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP47_EXP_PT_0_IN6 : X_INV + port map ( + I => REG_1_8, + O => NlwInverterSignal_EXP47_EXP_PT_0_IN6 + ); + NlwInverterBlock_EXP47_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP47_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP47_EXP_PT_1_IN5 : X_INV + port map ( + I => DIN_8_IBUF, + O => NlwInverterSignal_EXP47_EXP_PT_1_IN5 + ); + NlwInverterBlock_EXP48_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP48_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP48_EXP_PT_0_IN6 : X_INV + port map ( + I => REG_1_1, + O => NlwInverterSignal_EXP48_EXP_PT_0_IN6 + ); + NlwInverterBlock_EXP48_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP48_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP48_EXP_PT_1_IN5 : X_INV + port map ( + I => DIN_1_IBUF, + O => NlwInverterSignal_EXP48_EXP_PT_1_IN5 + ); + NlwInverterBlock_EXP49_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP49_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP49_EXP_PT_0_IN6 : X_INV + port map ( + I => REG_1_5, + O => NlwInverterSignal_EXP49_EXP_PT_0_IN6 + ); + NlwInverterBlock_EXP49_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP49_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP49_EXP_PT_1_IN5 : X_INV + port map ( + I => DIN_5_IBUF, + O => NlwInverterSignal_EXP49_EXP_PT_1_IN5 + ); + NlwInverterBlock_EXP50_EXP_tsimrenamed_net_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP50_EXP_tsimrenamed_net_IN0 + ); + NlwInverterBlock_EXP50_EXP_tsimrenamed_net_IN5 : X_INV + port map ( + I => DIN_6_IBUF, + O => NlwInverterSignal_EXP50_EXP_tsimrenamed_net_IN5 + ); + NlwInverterBlock_EXP51_EXP_tsimrenamed_net_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP51_EXP_tsimrenamed_net_IN0 + ); + NlwInverterBlock_EXP51_EXP_tsimrenamed_net_IN6 : X_INV + port map ( + I => REG_1_6, + O => NlwInverterSignal_EXP51_EXP_tsimrenamed_net_IN6 + ); + NlwInverterBlock_EXP52_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP52_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP52_EXP_PT_0_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_EXP52_EXP_PT_0_IN1 + ); + NlwInverterBlock_EXP52_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP52_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP52_EXP_PT_1_IN4 : X_INV + port map ( + I => DIN_0_IBUF, + O => NlwInverterSignal_EXP52_EXP_PT_1_IN4 + ); + NlwInverterBlock_EXP52_EXP_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP52_EXP_PT_2_IN0 + ); + NlwInverterBlock_EXP52_EXP_PT_2_IN6 : X_INV + port map ( + I => REG_1_0, + O => NlwInverterSignal_EXP52_EXP_PT_2_IN6 + ); + NlwInverterBlock_EXP53_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP53_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP53_EXP_PT_0_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_EXP53_EXP_PT_0_IN1 + ); + NlwInverterBlock_EXP53_EXP_PT_0_IN5 : X_INV + port map ( + I => REG_1_3, + O => NlwInverterSignal_EXP53_EXP_PT_0_IN5 + ); + NlwInverterBlock_EXP53_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP53_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP53_EXP_PT_1_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_EXP53_EXP_PT_1_IN1 + ); + NlwInverterBlock_EXP53_EXP_PT_1_IN4 : X_INV + port map ( + I => REG_1_2, + O => NlwInverterSignal_EXP53_EXP_PT_1_IN4 + ); + NlwInverterBlock_EXP53_EXP_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP53_EXP_PT_2_IN0 + ); + NlwInverterBlock_EXP53_EXP_PT_2_IN6 : X_INV + port map ( + I => REG_1_3, + O => NlwInverterSignal_EXP53_EXP_PT_2_IN6 + ); + NlwInverterBlock_EXP53_EXP_PT_3_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP53_EXP_PT_3_IN0 + ); + NlwInverterBlock_EXP53_EXP_PT_3_IN5 : X_INV + port map ( + I => DIN_3_IBUF, + O => NlwInverterSignal_EXP53_EXP_PT_3_IN5 + ); + NlwInverterBlock_EXP54_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP54_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP54_EXP_PT_0_IN6 : X_INV + port map ( + I => REG_1_16, + O => NlwInverterSignal_EXP54_EXP_PT_0_IN6 + ); + NlwInverterBlock_EXP54_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP54_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP54_EXP_PT_1_IN5 : X_INV + port map ( + I => DIN_16_IBUF, + O => NlwInverterSignal_EXP54_EXP_PT_1_IN5 + ); + NlwInverterBlock_EXP55_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP55_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP55_EXP_PT_0_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_EXP55_EXP_PT_0_IN1 + ); + NlwInverterBlock_EXP55_EXP_PT_0_IN5 : X_INV + port map ( + I => REG_1_13, + O => NlwInverterSignal_EXP55_EXP_PT_0_IN5 + ); + NlwInverterBlock_EXP55_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP55_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP55_EXP_PT_1_IN6 : X_INV + port map ( + I => REG_1_13, + O => NlwInverterSignal_EXP55_EXP_PT_1_IN6 + ); + NlwInverterBlock_EXP55_EXP_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP55_EXP_PT_2_IN0 + ); + NlwInverterBlock_EXP55_EXP_PT_2_IN5 : X_INV + port map ( + I => DIN_13_IBUF, + O => NlwInverterSignal_EXP55_EXP_PT_2_IN5 + ); + NlwInverterBlock_EXP56_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP56_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP56_EXP_PT_0_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_EXP56_EXP_PT_0_IN1 + ); + NlwInverterBlock_EXP56_EXP_PT_0_IN5 : X_INV + port map ( + I => REG_1_11, + O => NlwInverterSignal_EXP56_EXP_PT_0_IN5 + ); + NlwInverterBlock_EXP56_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP56_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP56_EXP_PT_1_IN6 : X_INV + port map ( + I => REG_1_11, + O => NlwInverterSignal_EXP56_EXP_PT_1_IN6 + ); + NlwInverterBlock_EXP56_EXP_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP56_EXP_PT_2_IN0 + ); + NlwInverterBlock_EXP56_EXP_PT_2_IN5 : X_INV + port map ( + I => DIN_11_IBUF, + O => NlwInverterSignal_EXP56_EXP_PT_2_IN5 + ); + NlwInverterBlock_EXP57_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP57_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP57_EXP_PT_0_IN6 : X_INV + port map ( + I => REG_1_15, + O => NlwInverterSignal_EXP57_EXP_PT_0_IN6 + ); + NlwInverterBlock_EXP57_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP57_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP57_EXP_PT_1_IN5 : X_INV + port map ( + I => DIN_15_IBUF, + O => NlwInverterSignal_EXP57_EXP_PT_1_IN5 + ); + NlwInverterBlock_EXP58_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP58_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP58_EXP_PT_0_IN6 : X_INV + port map ( + I => REG_1_14, + O => NlwInverterSignal_EXP58_EXP_PT_0_IN6 + ); + NlwInverterBlock_EXP58_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP58_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP58_EXP_PT_1_IN5 : X_INV + port map ( + I => DIN_14_IBUF, + O => NlwInverterSignal_EXP58_EXP_PT_1_IN5 + ); + NlwInverterBlock_EXP59_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP59_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP59_EXP_PT_0_IN6 : X_INV + port map ( + I => REG_1_22, + O => NlwInverterSignal_EXP59_EXP_PT_0_IN6 + ); + NlwInverterBlock_EXP59_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP59_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP59_EXP_PT_1_IN5 : X_INV + port map ( + I => DIN_22_IBUF, + O => NlwInverterSignal_EXP59_EXP_PT_1_IN5 + ); + NlwInverterBlock_EXP60_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP60_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP60_EXP_PT_0_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_EXP60_EXP_PT_0_IN1 + ); + NlwInverterBlock_EXP60_EXP_PT_0_IN5 : X_INV + port map ( + I => REG_1_19, + O => NlwInverterSignal_EXP60_EXP_PT_0_IN5 + ); + NlwInverterBlock_EXP60_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP60_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP60_EXP_PT_1_IN6 : X_INV + port map ( + I => REG_1_19, + O => NlwInverterSignal_EXP60_EXP_PT_1_IN6 + ); + NlwInverterBlock_EXP60_EXP_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP60_EXP_PT_2_IN0 + ); + NlwInverterBlock_EXP60_EXP_PT_2_IN5 : X_INV + port map ( + I => DIN_19_IBUF, + O => NlwInverterSignal_EXP60_EXP_PT_2_IN5 + ); + NlwInverterBlock_EXP61_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP61_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP61_EXP_PT_0_IN1 : X_INV + port map ( + I => LOAD_SREG_IBUF, + O => NlwInverterSignal_EXP61_EXP_PT_0_IN1 + ); + NlwInverterBlock_EXP61_EXP_PT_0_IN5 : X_INV + port map ( + I => REG_1_17, + O => NlwInverterSignal_EXP61_EXP_PT_0_IN5 + ); + NlwInverterBlock_EXP61_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP61_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP61_EXP_PT_1_IN6 : X_INV + port map ( + I => REG_1_17, + O => NlwInverterSignal_EXP61_EXP_PT_1_IN6 + ); + NlwInverterBlock_EXP61_EXP_PT_2_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP61_EXP_PT_2_IN0 + ); + NlwInverterBlock_EXP61_EXP_PT_2_IN5 : X_INV + port map ( + I => DIN_17_IBUF, + O => NlwInverterSignal_EXP61_EXP_PT_2_IN5 + ); + NlwInverterBlock_EXP62_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP62_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP62_EXP_PT_0_IN6 : X_INV + port map ( + I => REG_1_21, + O => NlwInverterSignal_EXP62_EXP_PT_0_IN6 + ); + NlwInverterBlock_EXP62_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP62_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP62_EXP_PT_1_IN5 : X_INV + port map ( + I => DIN_21_IBUF, + O => NlwInverterSignal_EXP62_EXP_PT_1_IN5 + ); + NlwInverterBlock_EXP63_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP63_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP63_EXP_PT_0_IN6 : X_INV + port map ( + I => REG_1_20, + O => NlwInverterSignal_EXP63_EXP_PT_0_IN6 + ); + NlwInverterBlock_EXP63_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP63_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP63_EXP_PT_1_IN5 : X_INV + port map ( + I => DIN_20_IBUF, + O => NlwInverterSignal_EXP63_EXP_PT_1_IN5 + ); + NlwInverterBlock_EXP64_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP64_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP64_EXP_PT_0_IN1 : X_INV + port map ( + I => SCLK, + O => NlwInverterSignal_EXP64_EXP_PT_0_IN1 + ); + NlwInverterBlock_EXP64_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP64_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP65_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP65_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP65_EXP_PT_0_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_EXP65_EXP_PT_0_IN2 + ); + NlwInverterBlock_EXP65_EXP_PT_0_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP65_EXP_PT_0_IN4 + ); + NlwInverterBlock_EXP65_EXP_PT_0_IN6 : X_INV + port map ( + I => REG_0_10, + O => NlwInverterSignal_EXP65_EXP_PT_0_IN6 + ); + NlwInverterBlock_EXP65_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP65_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP65_EXP_PT_1_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_EXP65_EXP_PT_1_IN2 + ); + NlwInverterBlock_EXP65_EXP_PT_1_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP65_EXP_PT_1_IN4 + ); + NlwInverterBlock_EXP65_EXP_PT_1_IN5 : X_INV + port map ( + I => DIN_10_IBUF, + O => NlwInverterSignal_EXP65_EXP_PT_1_IN5 + ); + NlwInverterBlock_EXP66_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP66_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP66_EXP_PT_0_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_EXP66_EXP_PT_0_IN2 + ); + NlwInverterBlock_EXP66_EXP_PT_0_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP66_EXP_PT_0_IN4 + ); + NlwInverterBlock_EXP66_EXP_PT_0_IN6 : X_INV + port map ( + I => REG_0_14, + O => NlwInverterSignal_EXP66_EXP_PT_0_IN6 + ); + NlwInverterBlock_EXP66_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP66_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP66_EXP_PT_1_IN2 : X_INV + port map ( + I => writeBufId(0), + O => NlwInverterSignal_EXP66_EXP_PT_1_IN2 + ); + NlwInverterBlock_EXP66_EXP_PT_1_IN4 : X_INV + port map ( + I => readBufId(0), + O => NlwInverterSignal_EXP66_EXP_PT_1_IN4 + ); + NlwInverterBlock_EXP66_EXP_PT_1_IN5 : X_INV + port map ( + I => DIN_14_IBUF, + O => NlwInverterSignal_EXP66_EXP_PT_1_IN5 + ); + NlwInverterBlock_EXP67_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP67_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP67_EXP_PT_1_IN1 : X_INV + port map ( + I => LOAD_PRESCALER_IBUF, + O => NlwInverterSignal_EXP67_EXP_PT_1_IN1 + ); + NlwInverterBlock_EXP67_EXP_PT_1_IN2 : X_INV + port map ( + I => count(0), + O => NlwInverterSignal_EXP67_EXP_PT_1_IN2 + ); + NlwInverterBlock_EXP68_EXP_PT_0_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP68_EXP_PT_0_IN0 + ); + NlwInverterBlock_EXP68_EXP_PT_0_IN6 : X_INV + port map ( + I => REG_1_28, + O => NlwInverterSignal_EXP68_EXP_PT_0_IN6 + ); + NlwInverterBlock_EXP68_EXP_PT_1_IN0 : X_INV + port map ( + I => RES_IBUF, + O => NlwInverterSignal_EXP68_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP68_EXP_PT_1_IN5 : X_INV + port map ( + I => DIN_28_IBUF, + O => NlwInverterSignal_EXP68_EXP_PT_1_IN5 + ); + NlwInverterBlock_EXP69_EXP_PT_1_IN0 : X_INV + port map ( + I => buf_depth(0), + O => NlwInverterSignal_EXP69_EXP_PT_1_IN0 + ); + NlwInverterBlock_EXP69_EXP_PT_1_IN1 : X_INV + port map ( + I => buf_depth(1), + O => NlwInverterSignal_EXP69_EXP_PT_1_IN1 + ); + NlwInverterBlock_EXP69_EXP_PT_1_IN2 : X_INV + port map ( + I => SHIFT_CNT(0), + O => NlwInverterSignal_EXP69_EXP_PT_1_IN2 + ); + NlwInverterBlock_EXP69_EXP_PT_1_IN3 : X_INV + port map ( + I => SHIFT_CNT(1), + O => NlwInverterSignal_EXP69_EXP_PT_1_IN3 + ); + NlwInverterBlock_EXP69_EXP_PT_1_IN4 : X_INV + port map ( + I => SHIFT_CNT(2), + O => NlwInverterSignal_EXP69_EXP_PT_1_IN4 + ); + NlwInverterBlock_EXP69_EXP_PT_1_IN5 : X_INV + port map ( + I => SHIFT_CNT(3), + O => NlwInverterSignal_EXP69_EXP_PT_1_IN5 + ); + NlwInverterBlock_EXP69_EXP_PT_1_IN6 : X_INV + port map ( + I => SHIFT_CNT(4), + O => NlwInverterSignal_EXP69_EXP_PT_1_IN6 + ); + NlwBlockROC : X_ROC + generic map (ROC_WIDTH => 100 ns) + port map (O => PRLD); + +end Structure; + diff --git a/projects/Eval_VConfig/wave.do b/projects/Eval_VConfig/wave.do new file mode 100644 index 0000000..56b137e --- /dev/null +++ b/projects/Eval_VConfig/wave.do @@ -0,0 +1,40 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -format Logic /vconfig_tb/uut/res +add wave -noupdate -format Logic /vconfig_tb/uut/ninit_b +add wave -noupdate -format Logic /vconfig_tb/uut/clk +add wave -noupdate -format Logic /vconfig_tb/uut/done +add wave -noupdate -format Logic /vconfig_tb/uut/cclk +add wave -noupdate -format Literal /vconfig_tb/uut/cclk_prescaler +add wave -noupdate -format Logic /vconfig_tb/uut/load_prescaler +add wave -noupdate -format Literal /vconfig_tb/uut/din +add wave -noupdate -format Logic /vconfig_tb/uut/dout +add wave -noupdate -format Logic /vconfig_tb/uut/load_sreg +add wave -noupdate -format Logic /vconfig_tb/uut/buf_is_empty +add wave -noupdate -format Literal /vconfig_tb/uut/reg +add wave -noupdate -format Literal /vconfig_tb/uut/count +add wave -noupdate -format Literal /vconfig_tb/uut/clk_scale +add wave -noupdate -format Literal /vconfig_tb/uut/shift_cnt +add wave -noupdate -format Literal /vconfig_tb/uut/state +add wave -noupdate -format Literal /vconfig_tb/uut/next_state +add wave -noupdate -format Logic /vconfig_tb/uut/sclk +add wave -noupdate -format Logic /vconfig_tb/uut/shift_en +add wave -noupdate -format Literal /vconfig_tb/uut/buf_depth +add wave -noupdate -format Literal /vconfig_tb/uut/tempid +add wave -noupdate -format Literal /vconfig_tb/uut/readbufid +add wave -noupdate -format Literal /vconfig_tb/uut/writebufid +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {2809539 ps} 0} +WaveRestoreZoom {1356698 ps} {12202906 ps} +configure wave -namecolwidth 150 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 diff --git a/projects/eval_dmux/eval_dmux.ise b/projects/eval_dmux/eval_dmux.ise new file mode 100644 index 0000000..88aa4da Binary files /dev/null and b/projects/eval_dmux/eval_dmux.ise differ diff --git a/projects/eval_dmux/main_top.lso b/projects/eval_dmux/main_top.lso new file mode 100644 index 0000000..22de730 --- /dev/null +++ b/projects/eval_dmux/main_top.lso @@ -0,0 +1 @@ +work diff --git a/projects/eval_dmux/main_top.prj b/projects/eval_dmux/main_top.prj new file mode 100644 index 0000000..fda0cbd --- /dev/null +++ b/projects/eval_dmux/main_top.prj @@ -0,0 +1 @@ +vhdl work "main_top.vhdl" diff --git a/projects/eval_dmux/main_top.vhdl b/projects/eval_dmux/main_top.vhdl new file mode 100644 index 0000000..4196dfc --- /dev/null +++ b/projects/eval_dmux/main_top.vhdl @@ -0,0 +1,86 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following lines to use the declarations that are +-- provided for instantiating Xilinx primitive components. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity main_top is + Port ( clk : in std_logic; + resn : in std_logic; + a : in std_logic_vector(31 downto 0); + d : inout std_logic_vector(31 downto 0); + wen : in std_logic; + csn : in std_logic); +end main_top; + +architecture Behavioral of main_top is + +type t_reg is array (31 downto 0) of std_logic ; +signal reg_a, reg_b, reg_c : t_reg; +signal cs_a, cs_b, cs_c, CI, CO : std_logic; +signal dmuxo : std_logic_vector(31 downto 0); +signal mux_ctrl : std_logic_vector (3 downto 0); +signal AA,BB,S31: std_logic_vector(32-1 downto 0); +signal sum : std_logic_vector(32 downto 0); +signal zeros: std_logic_vector(32-1 downto 0) := (others => '0'); + +begin + +mux_ctrl <= a(7 downto 4); + +dmuxo <= std_logic_vector(reg_a) when (mux_ctrl = X"0") else + std_logic_vector(reg_b) when (mux_ctrl = X"1") else + std_logic_vector(reg_c) when (mux_ctrl = X"2") else + X"12345678"; + +cs_a <= '1' when (mux_ctrl = X"0" and csn = '0') else '0'; +cs_b <= '1' when (mux_ctrl = X"1" and csn = '0') else '0'; +cs_c <= '1' when (mux_ctrl = X"2" and csn = '0') else '0'; + +CI <= wen; +AA <= dmuxo when (wen = '1' and csn = '0') else (31 downto 0 => 'Z'); +BB <=a; +d <= S31; + +write_reg_a: process (clk, wen, cs_a, d) +begin + + if clk'event and clk = '0' then + if (wen = '0' and cs_a = '1') then + reg_a <= t_reg(d); + end if; + end if; +end process; + +write_reg_b: process (clk, wen, cs_b, d) +begin + + if clk'event and clk = '0' then + if (wen = '0' and cs_b = '1') then + reg_b <= t_reg(d); + end if; + end if; +end process; + +write_reg_c: process (clk, wen, cs_c, d) +begin + + if clk'event and clk = '0' then + if (wen = '0' and cs_c = '1') then + reg_c <= t_reg(d); + end if; + end if; +end process; + +process (CI, AA, BB, sum) +begin + sum <= ('0' & AA) + ('0' & BB) + (zeros & CI); + S31 <= sum(32-1 downto 0); + CO <= sum(32); + +end process; +end Behavioral; diff --git a/projects/eval_dmux/main_top.xst b/projects/eval_dmux/main_top.xst new file mode 100644 index 0000000..03c8ff7 --- /dev/null +++ b/projects/eval_dmux/main_top.xst @@ -0,0 +1,53 @@ +set -tmpdir ./xst/projnav.tmp +set -xsthdpdir ./xst +run +-ifn main_top.prj +-ifmt mixed +-ofn main_top +-ofmt NGC +-p xc3s50-5-tq144 +-top main_top +-opt_mode Speed +-opt_level 1 +-iuc NO +-lso main_top.lso +-keep_hierarchy NO +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator _ +-bus_delimiter <> +-case maintain +-slice_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style lut +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract YES +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-mux_extract YES +-resource_sharing YES +-mult_style auto +-iobuf YES +-max_fanout 500 +-bufg 8 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-use_clock_enable Yes +-use_sync_set Yes +-use_sync_reset Yes +-iob auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/projects/eval_dmux/main_top_main_top_tb_vhd_tb.fdo b/projects/eval_dmux/main_top_main_top_tb_vhd_tb.fdo new file mode 100644 index 0000000..fa25739 --- /dev/null +++ b/projects/eval_dmux/main_top_main_top_tb_vhd_tb.fdo @@ -0,0 +1,13 @@ +## NOTE: Do not edit this file. +## Autogenerated by ProjNav (creatfdo.tcl) on Wed Jun 02 00:28:35 Westeuropäische Sommerzeit 2004 +## +vlib work +vcom -93 -explicit main_top.vhdl +vcom -93 -explicit main_top_tb.vhd +vsim -t 1ps -lib work main_top_main_top_tb_vhd_tb +do main_top_main_top_tb_vhd_tb.udo +view wave +add wave * +view structure +view signals +run 1000ns diff --git a/projects/eval_dmux/main_top_main_top_tb_vhd_tb.ndo b/projects/eval_dmux/main_top_main_top_tb_vhd_tb.ndo new file mode 100644 index 0000000..b7fa3cd --- /dev/null +++ b/projects/eval_dmux/main_top_main_top_tb_vhd_tb.ndo @@ -0,0 +1,15 @@ +## NOTE: Do not edit this file. +## Auto generated by Project Navigator for VHDL Post-Translate Simulation +## +vlib work +## Compile Post-Translate Model for Module main_top +vcom -87 -explicit main_top_translate.vhd +vcom -93 -explicit main_top_tb.vhd +vsim -t 1ps -lib work main_top_main_top_tb_vhd_tb +do main_top_main_top_tb_vhd_tb.udo +view wave +add wave * +view structure +view signals +run 1000ns +## End diff --git a/projects/eval_dmux/main_top_main_top_tb_vhd_tb.tdo b/projects/eval_dmux/main_top_main_top_tb_vhd_tb.tdo new file mode 100644 index 0000000..042d91d --- /dev/null +++ b/projects/eval_dmux/main_top_main_top_tb_vhd_tb.tdo @@ -0,0 +1,15 @@ +## NOTE: Do not edit this file. +## Auto generated by Project Navigator for VHDL Post-PAR Simulation +## +vlib work +## Compile Post-PAR Model for Module main_top +vcom -87 -explicit main_top_timesim.vhd +vcom -93 -explicit main_top_tb.vhd +vsim -t 1ps -sdfmax /UUT=main_top_timesim.sdf -lib work main_top_main_top_tb_vhd_tb +do main_top_main_top_tb_vhd_tb.udo +view wave +add wave * +view structure +view signals +run 1000ns +## End diff --git a/projects/eval_dmux/main_top_main_top_tb_vhd_tb.udo b/projects/eval_dmux/main_top_main_top_tb_vhd_tb.udo new file mode 100644 index 0000000..9d670db --- /dev/null +++ b/projects/eval_dmux/main_top_main_top_tb_vhd_tb.udo @@ -0,0 +1,4 @@ +-- ProjNav VHDL simulation template: main_top_main_top_tb_vhd_tb.udo +-- You may edit this file after the line that starts with +-- '-- START' to customize your simulation +-- START user-defined simulation commands diff --git a/projects/eval_dmux/main_top_tb.vhd b/projects/eval_dmux/main_top_tb.vhd new file mode 100644 index 0000000..bcfb4aa --- /dev/null +++ b/projects/eval_dmux/main_top_tb.vhd @@ -0,0 +1,134 @@ + +-- VHDL Test Bench Created from source file main_top.vhd -- 00:26:28 06/02/2004 +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY main_top_main_top_tb_vhd_tb IS +END main_top_main_top_tb_vhd_tb; + +ARCHITECTURE behavior OF main_top_main_top_tb_vhd_tb IS + + COMPONENT main_top + PORT( + clk : IN std_logic; + resn : IN std_logic; + a : IN std_logic_vector(31 downto 0); + wen : IN std_logic; + csn : IN std_logic; + d : INOUT std_logic_vector(31 downto 0) + ); + END COMPONENT; + + SIGNAL clk : std_logic; + SIGNAL resn : std_logic; + SIGNAL a : std_logic_vector(31 downto 0); + SIGNAL d : std_logic_vector(31 downto 0); + SIGNAL wen : std_logic; + SIGNAL csn : std_logic; + + constant ClockPeriod : Time := 25 ns; + +BEGIN + + uut: main_top PORT MAP( + clk => clk, + resn => resn, + a => a, + d => d, + wen => wen, + csn => csn + ); + + + clockgen: process + begin + clk <= '1'; + loop + wait for (ClockPeriod / 2); + clk <= not clk; + end loop; + end process; + +-- *** Test Bench - User Defined Section *** + tb : PROCESS + BEGIN + wait for 8*ClockPeriod; + + resn <= '1'; + wait for 4*ClockPeriod; + + wen <= '0'; + + a <= X"00000000"; + wait for 1*ClockPeriod; + d <= X"AAAAAAAA"; + csn <= '0'; + wait for 1*ClockPeriod; + csn <= '1'; + + a <= X"00000010"; + wait for 1*ClockPeriod; + d <= X"BBBBBBBB"; + csn <= '0'; + wait for 1*ClockPeriod; + csn <= '1'; + + a <= X"00000020"; + wait for 1*ClockPeriod; + d <= X"CCCCCCCC"; + csn <= '0'; + wait for 1*ClockPeriod; + csn <= '1'; + + a <= X"00000030"; + wait for 1*ClockPeriod; + d <= X"DDDDDDDD"; + csn <= '0'; + wait for 1*ClockPeriod; + csn <= '1'; + + wait for 8*ClockPeriod; + wen <= '1'; + + a <= X"00000000"; + wait for 1*ClockPeriod; + d <= (31 downto 0 => 'Z'); + csn <= '0'; + wait for 1*ClockPeriod; + csn <= '1'; + + a <= X"00000010"; + wait for 1*ClockPeriod; + d <= (31 downto 0 => 'Z'); + csn <= '0'; + wait for 1*ClockPeriod; + csn <= '1'; + + a <= X"00000020"; + wait for 1*ClockPeriod; + d <= (31 downto 0 => 'Z'); + csn <= '0'; + wait for 1*ClockPeriod; + csn <= '1'; + + a <= X"00000030"; + wait for 1*ClockPeriod; + d <= (31 downto 0 => 'Z'); + csn <= '0'; + wait for 1*ClockPeriod; + csn <= '1'; + + wait; -- will wait forever + END PROCESS; +-- *** End Test Bench - User Defined Section *** + +END; diff --git a/projects/eval_dmux/main_top_timesim.vhd b/projects/eval_dmux/main_top_timesim.vhd new file mode 100644 index 0000000..e0c6528 --- /dev/null +++ b/projects/eval_dmux/main_top_timesim.vhd @@ -0,0 +1,7856 @@ +-- Xilinx Vhdl netlist produced by netgen application (version G.30) +-- Command : -intstyle ise -s 5 -pcf main_top.pcf -ngm main_top.ngm -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim main_top.ncd main_top_timesim.vhd +-- Input file : main_top.ncd +-- Output file : main_top_timesim.vhd +-- Design name : main_top +-- # of Entities : 1 +-- Xilinx : D:/Xilinx +-- Device : 3s50tq144-5 (ADVANCED 1.30 2004-03-12) + +-- This vhdl netlist is a simulation model and uses simulation +-- primitives which may not represent the true implementation of the +-- device, however the netlist is functionally correct and should not +-- be modified. This file cannot be synthesized and should only be used +-- with supported simulation tools. + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library SIMPRIM; +use SIMPRIM.VCOMPONENTS.ALL; +use SIMPRIM.VPACKAGE.ALL; + +entity main_top is + port ( + resn : in STD_LOGIC := 'X'; + wen : in STD_LOGIC := 'X'; + csn : in STD_LOGIC := 'X'; + clk : in STD_LOGIC := 'X'; + d : inout STD_LOGIC_VECTOR ( 31 downto 0 ); + a : in STD_LOGIC_VECTOR ( 31 downto 0 ) + ); +end main_top; + +architecture Structure of main_top is + signal a_4_IBUF : STD_LOGIC; + signal a_7_IBUF : STD_LOGIC; + signal N4792 : STD_LOGIC; + signal N4774 : STD_LOGIC; + signal a_5_IBUF : STD_LOGIC; + signal a_6_IBUF : STD_LOGIC; + signal N4756 : STD_LOGIC; + signal N4754 : STD_LOGIC; + signal N4725 : STD_LOGIC; + signal N2469 : STD_LOGIC; + signal Q_n0001 : STD_LOGIC; + signal Q_n0000 : STD_LOGIC; + signal N4780 : STD_LOGIC; + signal N4778 : STD_LOGIC; + signal N4786 : STD_LOGIC; + signal N4738 : STD_LOGIC; + signal N2377 : STD_LOGIC; + signal N4707 : STD_LOGIC; + signal N4705 : STD_LOGIC; + signal N4719 : STD_LOGIC; + signal csn_IBUF : STD_LOGIC; + signal wen_IBUF : STD_LOGIC; + signal Q_n0002 : STD_LOGIC; + signal N4736 : STD_LOGIC; + signal N4744 : STD_LOGIC; + signal N4742 : STD_LOGIC; + signal N4750 : STD_LOGIC; + signal I3_N174 : STD_LOGIC; + signal clk_BUFGP : STD_LOGIC; + signal N4649 : STD_LOGIC; + signal N4651 : STD_LOGIC; + signal N4653 : STD_LOGIC; + signal N4655 : STD_LOGIC; + signal clk_BUFGP_IBUFG : STD_LOGIC; + signal N4593 : STD_LOGIC; + signal N4603 : STD_LOGIC; + signal N4595 : STD_LOGIC; + signal N4607 : STD_LOGIC; + signal N4597 : STD_LOGIC; + signal N4623 : STD_LOGIC; + signal N4611 : STD_LOGIC; + signal N4599 : STD_LOGIC; + signal N4627 : STD_LOGIC; + signal N4615 : STD_LOGIC; + signal N4601 : STD_LOGIC; + signal N4619 : STD_LOGIC; + signal N4605 : STD_LOGIC; + signal N4621 : STD_LOGIC; + signal N4609 : STD_LOGIC; + signal N4625 : STD_LOGIC; + signal N4613 : STD_LOGIC; + signal N4629 : STD_LOGIC; + signal N4617 : STD_LOGIC; + signal N4631 : STD_LOGIC; + signal N4633 : STD_LOGIC; + signal N4635 : STD_LOGIC; + signal N4637 : STD_LOGIC; + signal N4639 : STD_LOGIC; + signal N4641 : STD_LOGIC; + signal N4643 : STD_LOGIC; + signal N4645 : STD_LOGIC; + signal N4647 : STD_LOGIC; + signal GLOBAL_LOGIC1 : STD_LOGIC; + signal N4816 : STD_LOGIC; + signal N4814 : STD_LOGIC; + signal N4798 : STD_LOGIC; + signal N4713 : STD_LOGIC; + signal N4711 : STD_LOGIC; + signal N4810 : STD_LOGIC; + signal N4808 : STD_LOGIC; + signal N4804 : STD_LOGIC; + signal N4768 : STD_LOGIC; + signal N4732 : STD_LOGIC; + signal N4730 : STD_LOGIC; + signal N4762 : STD_LOGIC; + signal N4802 : STD_LOGIC; + signal N4723 : STD_LOGIC; + signal N4760 : STD_LOGIC; + signal N4790 : STD_LOGIC; + signal N4784 : STD_LOGIC; + signal N4748 : STD_LOGIC; + signal N4766 : STD_LOGIC; + signal N4796 : STD_LOGIC; + signal N4717 : STD_LOGIC; + signal N4772 : STD_LOGIC; + signal GSR : STD_LOGIC; + signal GTS : STD_LOGIC; + signal N4792_F : STD_LOGIC; + signal N4792_G : STD_LOGIC; + signal dmuxo_0_F : STD_LOGIC; + signal dmuxo_0_G : STD_LOGIC; + signal N4725_F : STD_LOGIC; + signal N4725_G : STD_LOGIC; + signal Q_n0001_F : STD_LOGIC; + signal Q_n0001_G : STD_LOGIC; + signal dmuxo_8_F : STD_LOGIC; + signal dmuxo_8_G : STD_LOGIC; + signal N4786_F : STD_LOGIC; + signal N4786_G : STD_LOGIC; + signal N4738_F : STD_LOGIC; + signal N4738_G : STD_LOGIC; + signal dmuxo_13_F : STD_LOGIC; + signal dmuxo_13_G : STD_LOGIC; + signal N4719_F : STD_LOGIC; + signal N4719_G : STD_LOGIC; + signal Q_n0002_F : STD_LOGIC; + signal Q_n0002_G : STD_LOGIC; + signal dmuxo_17_F : STD_LOGIC; + signal dmuxo_17_G : STD_LOGIC; + signal dmuxo_1_F : STD_LOGIC; + signal dmuxo_1_G : STD_LOGIC; + signal N4750_F : STD_LOGIC; + signal N4750_G : STD_LOGIC; + signal d_7_IFF_IFFDMUX : STD_LOGIC; + signal d_7_IFF_ICEINV : STD_LOGIC; + signal d_7_IFF_ICLK1INVNOT : STD_LOGIC; + signal d_7_IFF_IFF1_RST : STD_LOGIC; + signal d_7_ENABLE : STD_LOGIC; + signal d_7_GTS_OR_T : STD_LOGIC; + signal d_7_O : STD_LOGIC; + signal d_7_T : STD_LOGIC; + signal d_7_INBUF : STD_LOGIC; + signal d_8_IFF_IFFDMUX : STD_LOGIC; + signal d_8_IFF_ICEINV : STD_LOGIC; + signal d_8_IFF_ICLK1INVNOT : STD_LOGIC; + signal d_8_ENABLE : STD_LOGIC; + signal d_8_GTS_OR_T : STD_LOGIC; + signal d_8_O : STD_LOGIC; + signal d_8_T : STD_LOGIC; + signal d_8_INBUF : STD_LOGIC; + signal d_9_ENABLE : STD_LOGIC; + signal d_9_GTS_OR_T : STD_LOGIC; + signal d_9_O : STD_LOGIC; + signal d_9_T : STD_LOGIC; + signal d_9_INBUF : STD_LOGIC; + signal d_10_ENABLE : STD_LOGIC; + signal d_10_GTS_OR_T : STD_LOGIC; + signal d_10_O : STD_LOGIC; + signal d_10_T : STD_LOGIC; + signal d_10_INBUF : STD_LOGIC; + signal clk_INBUF : STD_LOGIC; + signal d_11_IFF_IFF1_RST : STD_LOGIC; + signal d_11_IFF_IFFDMUX : STD_LOGIC; + signal d_11_IFF_ICEINV : STD_LOGIC; + signal d_11_IFF_ICLK1INVNOT : STD_LOGIC; + signal d_11_ENABLE : STD_LOGIC; + signal d_11_GTS_OR_T : STD_LOGIC; + signal d_11_O : STD_LOGIC; + signal d_11_T : STD_LOGIC; + signal d_11_INBUF : STD_LOGIC; + signal d_20_IFF_IFF1_RST : STD_LOGIC; + signal d_20_IFF_IFFDMUX : STD_LOGIC; + signal d_20_IFF_ICEINV : STD_LOGIC; + signal d_20_IFF_ICLK1INVNOT : STD_LOGIC; + signal d_20_ENABLE : STD_LOGIC; + signal d_20_GTS_OR_T : STD_LOGIC; + signal d_20_O : STD_LOGIC; + signal d_20_T : STD_LOGIC; + signal d_20_INBUF : STD_LOGIC; + signal d_12_ENABLE : STD_LOGIC; + signal d_12_GTS_OR_T : STD_LOGIC; + signal d_12_O : STD_LOGIC; + signal d_12_T : STD_LOGIC; + signal d_12_INBUF : STD_LOGIC; + signal d_21_ENABLE : STD_LOGIC; + signal d_21_GTS_OR_T : STD_LOGIC; + signal d_21_O : STD_LOGIC; + signal d_21_T : STD_LOGIC; + signal d_21_INBUF : STD_LOGIC; + signal d_13_ENABLE : STD_LOGIC; + signal d_13_GTS_OR_T : STD_LOGIC; + signal d_13_O : STD_LOGIC; + signal d_13_T : STD_LOGIC; + signal d_13_INBUF : STD_LOGIC; + signal d_30_ENABLE : STD_LOGIC; + signal d_30_GTS_OR_T : STD_LOGIC; + signal d_30_O : STD_LOGIC; + signal d_30_T : STD_LOGIC; + signal d_30_INBUF : STD_LOGIC; + signal d_22_ENABLE : STD_LOGIC; + signal d_22_GTS_OR_T : STD_LOGIC; + signal d_22_O : STD_LOGIC; + signal d_22_T : STD_LOGIC; + signal d_22_INBUF : STD_LOGIC; + signal d_14_ENABLE : STD_LOGIC; + signal d_14_GTS_OR_T : STD_LOGIC; + signal d_14_O : STD_LOGIC; + signal d_14_T : STD_LOGIC; + signal d_14_INBUF : STD_LOGIC; + signal d_31_ENABLE : STD_LOGIC; + signal d_31_GTS_OR_T : STD_LOGIC; + signal d_31_O : STD_LOGIC; + signal d_31_T : STD_LOGIC; + signal d_31_INBUF : STD_LOGIC; + signal d_23_ENABLE : STD_LOGIC; + signal d_23_GTS_OR_T : STD_LOGIC; + signal d_23_O : STD_LOGIC; + signal d_23_T : STD_LOGIC; + signal d_23_INBUF : STD_LOGIC; + signal d_15_ENABLE : STD_LOGIC; + signal d_15_GTS_OR_T : STD_LOGIC; + signal d_15_O : STD_LOGIC; + signal d_15_T : STD_LOGIC; + signal d_15_INBUF : STD_LOGIC; + signal d_24_ENABLE : STD_LOGIC; + signal d_24_GTS_OR_T : STD_LOGIC; + signal d_24_O : STD_LOGIC; + signal d_24_T : STD_LOGIC; + signal d_24_INBUF : STD_LOGIC; + signal d_16_ENABLE : STD_LOGIC; + signal d_16_GTS_OR_T : STD_LOGIC; + signal d_16_O : STD_LOGIC; + signal d_16_T : STD_LOGIC; + signal d_16_INBUF : STD_LOGIC; + signal d_25_ENABLE : STD_LOGIC; + signal d_25_GTS_OR_T : STD_LOGIC; + signal d_25_O : STD_LOGIC; + signal d_25_T : STD_LOGIC; + signal d_25_INBUF : STD_LOGIC; + signal d_9_IFF_ICLK1INVNOT : STD_LOGIC; + signal d_9_IFF_ICEINV : STD_LOGIC; + signal d_9_IFF_IFFDMUX : STD_LOGIC; + signal d_8_IFF_IFF1_RST : STD_LOGIC; + signal d_12_IFF_ICLK1INVNOT : STD_LOGIC; + signal d_12_IFF_ICEINV : STD_LOGIC; + signal d_12_IFF_IFFDMUX : STD_LOGIC; + signal d_13_IFF_ICLK1INVNOT : STD_LOGIC; + signal d_13_IFF_ICEINV : STD_LOGIC; + signal d_13_IFF_IFFDMUX : STD_LOGIC; + signal d_22_IFF_ICLK1INVNOT : STD_LOGIC; + signal d_22_IFF_ICEINV : STD_LOGIC; + signal d_22_IFF_IFFDMUX : STD_LOGIC; + signal d_14_IFF_ICLK1INVNOT : STD_LOGIC; + signal d_14_IFF_ICEINV : STD_LOGIC; + signal d_14_IFF_IFFDMUX : STD_LOGIC; + signal d_31_IFF_IFF1_RST : STD_LOGIC; + signal d_31_IFF_ICLK1INVNOT : STD_LOGIC; + signal d_31_IFF_ICEINV : STD_LOGIC; + signal d_31_IFF_IFFDMUX : STD_LOGIC; + signal d_23_IFF_ICLK1INVNOT : STD_LOGIC; + signal d_23_IFF_ICEINV : STD_LOGIC; + signal d_23_IFF_IFFDMUX : STD_LOGIC; + signal d_24_IFF_ICLK1INVNOT : STD_LOGIC; + signal d_24_IFF_ICEINV : STD_LOGIC; + signal d_24_IFF_IFFDMUX : STD_LOGIC; + signal d_25_IFF_ICLK1INVNOT : STD_LOGIC; + signal d_25_IFF_ICEINV : STD_LOGIC; + signal d_25_IFF_IFFDMUX : STD_LOGIC; + signal d_17_ENABLE : STD_LOGIC; + signal d_17_GTS_OR_T : STD_LOGIC; + signal d_17_O : STD_LOGIC; + signal d_17_T : STD_LOGIC; + signal d_17_INBUF : STD_LOGIC; + signal d_26_IFF_IFFDMUX : STD_LOGIC; + signal d_26_IFF_ICEINV : STD_LOGIC; + signal d_26_IFF_ICLK1INVNOT : STD_LOGIC; + signal d_26_ENABLE : STD_LOGIC; + signal d_26_GTS_OR_T : STD_LOGIC; + signal d_26_O : STD_LOGIC; + signal d_26_T : STD_LOGIC; + signal d_26_INBUF : STD_LOGIC; + signal d_18_ENABLE : STD_LOGIC; + signal d_18_GTS_OR_T : STD_LOGIC; + signal d_18_O : STD_LOGIC; + signal d_18_T : STD_LOGIC; + signal d_18_INBUF : STD_LOGIC; + signal d_27_IFF_IFFDMUX : STD_LOGIC; + signal d_27_IFF_ICEINV : STD_LOGIC; + signal d_27_IFF_ICLK1INVNOT : STD_LOGIC; + signal d_27_IFF_IFF1_RST : STD_LOGIC; + signal d_27_ENABLE : STD_LOGIC; + signal d_27_GTS_OR_T : STD_LOGIC; + signal d_27_O : STD_LOGIC; + signal d_27_T : STD_LOGIC; + signal d_27_INBUF : STD_LOGIC; + signal d_19_IFF_IFF1_RST : STD_LOGIC; + signal d_19_IFF_IFFDMUX : STD_LOGIC; + signal d_19_IFF_ICEINV : STD_LOGIC; + signal d_19_IFF_ICLK1INVNOT : STD_LOGIC; + signal d_19_ENABLE : STD_LOGIC; + signal d_19_GTS_OR_T : STD_LOGIC; + signal d_19_O : STD_LOGIC; + signal d_19_T : STD_LOGIC; + signal d_19_INBUF : STD_LOGIC; + signal csn_INBUF : STD_LOGIC; + signal d_28_ENABLE : STD_LOGIC; + signal d_28_GTS_OR_T : STD_LOGIC; + signal d_28_O : STD_LOGIC; + signal d_28_T : STD_LOGIC; + signal d_28_INBUF : STD_LOGIC; + signal d_29_ENABLE : STD_LOGIC; + signal d_29_GTS_OR_T : STD_LOGIC; + signal d_29_O : STD_LOGIC; + signal d_29_T : STD_LOGIC; + signal d_29_INBUF : STD_LOGIC; + signal a_4_INBUF : STD_LOGIC; + signal a_5_INBUF : STD_LOGIC; + signal a_6_INBUF : STD_LOGIC; + signal a_7_INBUF : STD_LOGIC; + signal wen_INBUF : STD_LOGIC; + signal d_0_ENABLE : STD_LOGIC; + signal d_0_GTS_OR_T : STD_LOGIC; + signal d_0_O : STD_LOGIC; + signal d_0_T : STD_LOGIC; + signal d_0_INBUF : STD_LOGIC; + signal d_1_IFF_IFFDMUX : STD_LOGIC; + signal d_1_IFF_ICEINV : STD_LOGIC; + signal d_1_IFF_ICLK1INVNOT : STD_LOGIC; + signal d_1_ENABLE : STD_LOGIC; + signal d_1_GTS_OR_T : STD_LOGIC; + signal d_1_O : STD_LOGIC; + signal d_1_T : STD_LOGIC; + signal d_1_INBUF : STD_LOGIC; + signal d_2_ENABLE : STD_LOGIC; + signal d_2_GTS_OR_T : STD_LOGIC; + signal d_2_O : STD_LOGIC; + signal d_2_T : STD_LOGIC; + signal d_2_INBUF : STD_LOGIC; + signal d_3_IFF_IFFDMUX : STD_LOGIC; + signal d_3_IFF_ICEINV : STD_LOGIC; + signal d_3_IFF_ICLK1INVNOT : STD_LOGIC; + signal d_3_ENABLE : STD_LOGIC; + signal d_3_GTS_OR_T : STD_LOGIC; + signal d_3_O : STD_LOGIC; + signal d_3_T : STD_LOGIC; + signal d_3_INBUF : STD_LOGIC; + signal d_4_ENABLE : STD_LOGIC; + signal d_4_GTS_OR_T : STD_LOGIC; + signal d_4_O : STD_LOGIC; + signal d_4_T : STD_LOGIC; + signal d_4_INBUF : STD_LOGIC; + signal d_5_IFF_IFFDMUX : STD_LOGIC; + signal d_5_IFF_ICEINV : STD_LOGIC; + signal d_5_IFF_ICLK1INVNOT : STD_LOGIC; + signal d_5_ENABLE : STD_LOGIC; + signal d_5_GTS_OR_T : STD_LOGIC; + signal d_5_O : STD_LOGIC; + signal d_5_T : STD_LOGIC; + signal d_5_INBUF : STD_LOGIC; + signal d_6_ENABLE : STD_LOGIC; + signal d_6_GTS_OR_T : STD_LOGIC; + signal d_6_O : STD_LOGIC; + signal d_6_T : STD_LOGIC; + signal d_6_INBUF : STD_LOGIC; + signal clk_BUFGP_BUFG_S_INVNOT : STD_LOGIC; + signal dmuxo_12_F5MUX : STD_LOGIC; + signal N4848 : STD_LOGIC; + signal dmuxo_12_BXINV : STD_LOGIC; + signal N4846 : STD_LOGIC; + signal dmuxo_20_F5MUX : STD_LOGIC; + signal N4833 : STD_LOGIC; + signal dmuxo_20_BXINV : STD_LOGIC; + signal N4831 : STD_LOGIC; + signal dmuxo_21_F5MUX : STD_LOGIC; + signal N4858 : STD_LOGIC; + signal dmuxo_21_BXINV : STD_LOGIC; + signal N4856 : STD_LOGIC; + signal dmuxo_3_F5MUX : STD_LOGIC; + signal N4838 : STD_LOGIC; + signal dmuxo_3_BXINV : STD_LOGIC; + signal N4836 : STD_LOGIC; + signal dmuxo_14_F5MUX : STD_LOGIC; + signal N4883 : STD_LOGIC; + signal dmuxo_14_BXINV : STD_LOGIC; + signal N4881 : STD_LOGIC; + signal dmuxo_4_F5MUX : STD_LOGIC; + signal N4853 : STD_LOGIC; + signal dmuxo_4_BXINV : STD_LOGIC; + signal N4851 : STD_LOGIC; + signal dmuxo_5_F5MUX : STD_LOGIC; + signal N4863 : STD_LOGIC; + signal dmuxo_5_BXINV : STD_LOGIC; + signal N4861 : STD_LOGIC; + signal dmuxo_6_F5MUX : STD_LOGIC; + signal N4873 : STD_LOGIC; + signal dmuxo_6_BXINV : STD_LOGIC; + signal N4871 : STD_LOGIC; + signal dmuxo_25_F5MUX : STD_LOGIC; + signal N4868 : STD_LOGIC; + signal dmuxo_25_BXINV : STD_LOGIC; + signal N4866 : STD_LOGIC; + signal dmuxo_18_F5MUX : STD_LOGIC; + signal N4843 : STD_LOGIC; + signal dmuxo_18_BXINV : STD_LOGIC; + signal N4841 : STD_LOGIC; + signal dmuxo_9_F5MUX : STD_LOGIC; + signal N4828 : STD_LOGIC; + signal dmuxo_9_BXINV : STD_LOGIC; + signal N4826 : STD_LOGIC; + signal dmuxo_28_F5MUX : STD_LOGIC; + signal N4878 : STD_LOGIC; + signal dmuxo_28_BXINV : STD_LOGIC; + signal N4876 : STD_LOGIC; + signal dmuxo_10_F5MUX : STD_LOGIC; + signal N4823 : STD_LOGIC; + signal dmuxo_10_BXINV : STD_LOGIC; + signal N4821 : STD_LOGIC; + signal dmuxo_29_F : STD_LOGIC; + signal dmuxo_29_G : STD_LOGIC; + signal N4798_F : STD_LOGIC; + signal N4798_G : STD_LOGIC; + signal reg_a_11_DXMUX : STD_LOGIC; + signal reg_a_11_DYMUX : STD_LOGIC; + signal reg_a_11_CLKINVNOT : STD_LOGIC; + signal reg_a_11_CEINV : STD_LOGIC; + signal reg_a_21_DXMUX : STD_LOGIC; + signal reg_a_21_DYMUX : STD_LOGIC; + signal reg_a_21_CLKINVNOT : STD_LOGIC; + signal reg_a_21_CEINV : STD_LOGIC; + signal reg_a_13_DXMUX : STD_LOGIC; + signal reg_a_13_DYMUX : STD_LOGIC; + signal reg_a_13_CLKINVNOT : STD_LOGIC; + signal reg_a_13_CEINV : STD_LOGIC; + signal reg_a_30_DYMUX : STD_LOGIC; + signal reg_a_30_CLKINVNOT : STD_LOGIC; + signal reg_a_30_CEINV : STD_LOGIC; + signal reg_a_23_DXMUX : STD_LOGIC; + signal reg_a_23_DYMUX : STD_LOGIC; + signal reg_a_23_CLKINVNOT : STD_LOGIC; + signal reg_a_23_CEINV : STD_LOGIC; + signal reg_a_15_DXMUX : STD_LOGIC; + signal reg_a_15_DYMUX : STD_LOGIC; + signal reg_a_15_CLKINVNOT : STD_LOGIC; + signal reg_a_15_CEINV : STD_LOGIC; + signal reg_a_25_DXMUX : STD_LOGIC; + signal reg_a_25_DYMUX : STD_LOGIC; + signal reg_a_25_CLKINVNOT : STD_LOGIC; + signal reg_a_25_CEINV : STD_LOGIC; + signal reg_a_17_DXMUX : STD_LOGIC; + signal reg_a_17_DYMUX : STD_LOGIC; + signal reg_a_17_CLKINVNOT : STD_LOGIC; + signal reg_a_17_CEINV : STD_LOGIC; + signal dmuxo_30_F : STD_LOGIC; + signal dmuxo_30_G : STD_LOGIC; + signal dmuxo_22_F : STD_LOGIC; + signal dmuxo_22_G : STD_LOGIC; + signal reg_a_27_DXMUX : STD_LOGIC; + signal reg_a_27_DYMUX : STD_LOGIC; + signal reg_a_27_CLKINVNOT : STD_LOGIC; + signal reg_a_27_CEINV : STD_LOGIC; + signal reg_a_19_DXMUX : STD_LOGIC; + signal reg_a_19_DYMUX : STD_LOGIC; + signal reg_a_19_CLKINVNOT : STD_LOGIC; + signal reg_a_19_CEINV : STD_LOGIC; + signal reg_b_11_DXMUX : STD_LOGIC; + signal reg_b_11_DYMUX : STD_LOGIC; + signal reg_b_11_CLKINVNOT : STD_LOGIC; + signal reg_b_11_CEINV : STD_LOGIC; + signal N4804_F : STD_LOGIC; + signal N4804_G : STD_LOGIC; + signal N4768_F : STD_LOGIC; + signal N4768_G : STD_LOGIC; + signal reg_a_29_DXMUX : STD_LOGIC; + signal reg_a_29_DYMUX : STD_LOGIC; + signal reg_a_29_CLKINVNOT : STD_LOGIC; + signal reg_a_29_CEINV : STD_LOGIC; + signal reg_b_21_DXMUX : STD_LOGIC; + signal reg_b_21_DYMUX : STD_LOGIC; + signal reg_b_21_CLKINVNOT : STD_LOGIC; + signal reg_b_21_CEINV : STD_LOGIC; + signal reg_b_13_DXMUX : STD_LOGIC; + signal reg_b_13_DYMUX : STD_LOGIC; + signal reg_b_13_CLKINVNOT : STD_LOGIC; + signal reg_b_13_CEINV : STD_LOGIC; + signal reg_b_31_DXMUX : STD_LOGIC; + signal reg_b_31_DYMUX : STD_LOGIC; + signal reg_b_31_CLKINVNOT : STD_LOGIC; + signal reg_b_31_CEINV : STD_LOGIC; + signal reg_b_23_DXMUX : STD_LOGIC; + signal reg_b_23_DYMUX : STD_LOGIC; + signal reg_b_23_CLKINVNOT : STD_LOGIC; + signal reg_b_23_CEINV : STD_LOGIC; + signal reg_b_15_DXMUX : STD_LOGIC; + signal reg_b_15_DYMUX : STD_LOGIC; + signal reg_b_15_CLKINVNOT : STD_LOGIC; + signal reg_b_15_CEINV : STD_LOGIC; + signal reg_b_25_DXMUX : STD_LOGIC; + signal reg_b_25_DYMUX : STD_LOGIC; + signal reg_b_25_CLKINVNOT : STD_LOGIC; + signal reg_b_25_CEINV : STD_LOGIC; + signal reg_b_17_DXMUX : STD_LOGIC; + signal reg_b_17_DYMUX : STD_LOGIC; + signal reg_b_17_CLKINVNOT : STD_LOGIC; + signal reg_b_17_CEINV : STD_LOGIC; + signal dmuxo_26_F : STD_LOGIC; + signal dmuxo_26_G : STD_LOGIC; + signal reg_b_27_DXMUX : STD_LOGIC; + signal reg_b_27_DYMUX : STD_LOGIC; + signal reg_b_27_CLKINVNOT : STD_LOGIC; + signal reg_b_27_CEINV : STD_LOGIC; + signal reg_b_19_DXMUX : STD_LOGIC; + signal reg_b_19_DYMUX : STD_LOGIC; + signal reg_b_19_CLKINVNOT : STD_LOGIC; + signal reg_b_19_CEINV : STD_LOGIC; + signal N4762_F : STD_LOGIC; + signal N4762_G : STD_LOGIC; + signal dmuxo_2_F : STD_LOGIC; + signal dmuxo_2_G : STD_LOGIC; + signal reg_b_29_DXMUX : STD_LOGIC; + signal reg_b_29_DYMUX : STD_LOGIC; + signal reg_b_29_CLKINVNOT : STD_LOGIC; + signal reg_b_29_CEINV : STD_LOGIC; + signal reg_c_31_DYMUX : STD_LOGIC; + signal reg_c_31_CLKINVNOT : STD_LOGIC; + signal reg_c_31_CEINV : STD_LOGIC; + signal reg_a_1_DXMUX : STD_LOGIC; + signal reg_a_1_DYMUX : STD_LOGIC; + signal reg_a_1_CLKINVNOT : STD_LOGIC; + signal reg_a_1_CEINV : STD_LOGIC; + signal reg_a_3_DXMUX : STD_LOGIC; + signal reg_a_3_DYMUX : STD_LOGIC; + signal reg_a_3_CLKINVNOT : STD_LOGIC; + signal reg_a_3_CEINV : STD_LOGIC; + signal reg_a_5_DXMUX : STD_LOGIC; + signal reg_a_5_DYMUX : STD_LOGIC; + signal reg_a_5_CLKINVNOT : STD_LOGIC; + signal reg_a_5_CEINV : STD_LOGIC; + signal reg_b_1_DXMUX : STD_LOGIC; + signal reg_b_1_DYMUX : STD_LOGIC; + signal reg_b_1_CLKINVNOT : STD_LOGIC; + signal reg_b_1_CEINV : STD_LOGIC; + signal dmuxo_11_F : STD_LOGIC; + signal dmuxo_11_G : STD_LOGIC; + signal reg_a_7_DXMUX : STD_LOGIC; + signal reg_a_7_DYMUX : STD_LOGIC; + signal reg_a_7_CLKINVNOT : STD_LOGIC; + signal reg_a_7_CEINV : STD_LOGIC; + signal reg_b_3_DXMUX : STD_LOGIC; + signal reg_b_3_DYMUX : STD_LOGIC; + signal reg_b_3_CLKINVNOT : STD_LOGIC; + signal reg_b_3_CEINV : STD_LOGIC; + signal reg_a_9_DXMUX : STD_LOGIC; + signal reg_a_9_DYMUX : STD_LOGIC; + signal reg_a_9_CLKINVNOT : STD_LOGIC; + signal reg_a_9_CEINV : STD_LOGIC; + signal reg_b_5_DXMUX : STD_LOGIC; + signal reg_b_5_DYMUX : STD_LOGIC; + signal reg_b_5_CLKINVNOT : STD_LOGIC; + signal reg_b_5_CEINV : STD_LOGIC; + signal reg_b_7_DXMUX : STD_LOGIC; + signal reg_b_7_DYMUX : STD_LOGIC; + signal reg_b_7_CLKINVNOT : STD_LOGIC; + signal reg_b_7_CEINV : STD_LOGIC; + signal dmuxo_15_F : STD_LOGIC; + signal dmuxo_15_G : STD_LOGIC; + signal dmuxo_23_F : STD_LOGIC; + signal dmuxo_23_G : STD_LOGIC; + signal dmuxo_31_F : STD_LOGIC; + signal dmuxo_31_G : STD_LOGIC; + signal reg_b_9_DXMUX : STD_LOGIC; + signal reg_b_9_DYMUX : STD_LOGIC; + signal reg_b_9_CLKINVNOT : STD_LOGIC; + signal reg_b_9_CEINV : STD_LOGIC; + signal I3_N174_G : STD_LOGIC; + signal dmuxo_19_F : STD_LOGIC; + signal dmuxo_19_G : STD_LOGIC; + signal dmuxo_27_F : STD_LOGIC; + signal dmuxo_27_G : STD_LOGIC; + signal dmuxo_7_F : STD_LOGIC; + signal dmuxo_7_G : STD_LOGIC; + signal dmuxo_24_F : STD_LOGIC; + signal dmuxo_24_G : STD_LOGIC; + signal dmuxo_16_F : STD_LOGIC; + signal dmuxo_16_G : STD_LOGIC; + signal d_5_IFF_IFF1_RST : STD_LOGIC; + signal d_6_IFF_ICLK1INVNOT : STD_LOGIC; + signal d_6_IFF_ICEINV : STD_LOGIC; + signal d_6_IFF_IFFDMUX : STD_LOGIC; + signal d_6_IFF_IFF1_RST : STD_LOGIC; + signal d_23_IFF_IFF1_RST : STD_LOGIC; + signal d_15_IFF_IFF1_RST : STD_LOGIC; + signal d_15_IFF_ICLK1INVNOT : STD_LOGIC; + signal d_15_IFF_ICEINV : STD_LOGIC; + signal d_15_IFF_IFFDMUX : STD_LOGIC; + signal d_0_IFF_ICLK1INVNOT : STD_LOGIC; + signal d_0_IFF_ICEINV : STD_LOGIC; + signal d_0_IFF_IFFDMUX : STD_LOGIC; + signal d_0_IFF_IFF1_RST : STD_LOGIC; + signal d_1_IFF_IFF1_RST : STD_LOGIC; + signal d_2_IFF_ICLK1INVNOT : STD_LOGIC; + signal d_2_IFF_ICEINV : STD_LOGIC; + signal d_2_IFF_IFFDMUX : STD_LOGIC; + signal d_2_IFF_IFF1_RST : STD_LOGIC; + signal reg_b_9_FFY_RST : STD_LOGIC; + signal reg_b_9_FFX_RST : STD_LOGIC; + signal d_13_IFF_IFF1_RST : STD_LOGIC; + signal d_30_IFF_IFF1_RST : STD_LOGIC; + signal d_30_IFF_ICLK1INVNOT : STD_LOGIC; + signal d_30_IFF_ICEINV : STD_LOGIC; + signal d_30_IFF_IFFDMUX : STD_LOGIC; + signal d_24_IFF_IFF1_RST : STD_LOGIC; + signal d_16_IFF_ICLK1INVNOT : STD_LOGIC; + signal d_16_IFF_ICEINV : STD_LOGIC; + signal d_16_IFF_IFFDMUX : STD_LOGIC; + signal d_16_IFF_IFF1_RST : STD_LOGIC; + signal d_22_IFF_IFF1_RST : STD_LOGIC; + signal d_14_IFF_IFF1_RST : STD_LOGIC; + signal d_28_IFF_ICLK1INVNOT : STD_LOGIC; + signal d_28_IFF_ICEINV : STD_LOGIC; + signal d_28_IFF_IFFDMUX : STD_LOGIC; + signal d_28_IFF_IFF1_RST : STD_LOGIC; + signal d_29_IFF_IFF1_RST : STD_LOGIC; + signal d_29_IFF_ICLK1INVNOT : STD_LOGIC; + signal d_29_IFF_ICEINV : STD_LOGIC; + signal d_29_IFF_IFFDMUX : STD_LOGIC; + signal d_12_IFF_IFF1_RST : STD_LOGIC; + signal d_21_IFF_IFF1_RST : STD_LOGIC; + signal d_21_IFF_ICLK1INVNOT : STD_LOGIC; + signal d_21_IFF_ICEINV : STD_LOGIC; + signal d_21_IFF_IFFDMUX : STD_LOGIC; + signal d_9_IFF_IFF1_RST : STD_LOGIC; + signal d_10_IFF_IFF1_RST : STD_LOGIC; + signal d_10_IFF_ICLK1INVNOT : STD_LOGIC; + signal d_10_IFF_ICEINV : STD_LOGIC; + signal d_10_IFF_IFFDMUX : STD_LOGIC; + signal d_3_IFF_IFF1_RST : STD_LOGIC; + signal d_4_IFF_ICLK1INVNOT : STD_LOGIC; + signal d_4_IFF_ICEINV : STD_LOGIC; + signal d_4_IFF_IFFDMUX : STD_LOGIC; + signal d_4_IFF_IFF1_RST : STD_LOGIC; + signal reg_a_25_FFY_RST : STD_LOGIC; + signal reg_a_25_FFX_RST : STD_LOGIC; + signal reg_a_17_FFY_RST : STD_LOGIC; + signal reg_a_17_FFX_RST : STD_LOGIC; + signal reg_a_27_FFY_RST : STD_LOGIC; + signal reg_a_11_FFY_RST : STD_LOGIC; + signal reg_a_11_FFX_RST : STD_LOGIC; + signal reg_a_21_FFY_RST : STD_LOGIC; + signal d_26_IFF_IFF1_RST : STD_LOGIC; + signal d_18_IFF_IFF1_RST : STD_LOGIC; + signal d_18_IFF_ICLK1INVNOT : STD_LOGIC; + signal d_18_IFF_ICEINV : STD_LOGIC; + signal d_18_IFF_IFFDMUX : STD_LOGIC; + signal reg_a_5_FFY_RST : STD_LOGIC; + signal reg_a_5_FFX_RST : STD_LOGIC; + signal reg_b_1_FFY_RST : STD_LOGIC; + signal reg_b_1_FFX_RST : STD_LOGIC; + signal reg_a_7_FFY_RST : STD_LOGIC; + signal reg_a_7_FFX_RST : STD_LOGIC; + signal d_25_IFF_IFF1_RST : STD_LOGIC; + signal d_17_IFF_IFF1_RST : STD_LOGIC; + signal d_17_IFF_ICLK1INVNOT : STD_LOGIC; + signal d_17_IFF_ICEINV : STD_LOGIC; + signal d_17_IFF_IFFDMUX : STD_LOGIC; + signal reg_a_29_FFY_RST : STD_LOGIC; + signal reg_a_29_FFX_RST : STD_LOGIC; + signal reg_b_21_FFY_RST : STD_LOGIC; + signal reg_b_21_FFX_RST : STD_LOGIC; + signal reg_b_13_FFY_RST : STD_LOGIC; + signal reg_b_13_FFX_RST : STD_LOGIC; + signal reg_b_31_FFY_RST : STD_LOGIC; + signal reg_b_31_FFX_RST : STD_LOGIC; + signal reg_b_23_FFY_RST : STD_LOGIC; + signal reg_b_23_FFX_RST : STD_LOGIC; + signal reg_b_15_FFY_RST : STD_LOGIC; + signal reg_b_15_FFX_RST : STD_LOGIC; + signal reg_b_25_FFY_RST : STD_LOGIC; + signal reg_b_25_FFX_RST : STD_LOGIC; + signal reg_b_17_FFY_RST : STD_LOGIC; + signal reg_a_27_FFX_RST : STD_LOGIC; + signal reg_a_19_FFY_RST : STD_LOGIC; + signal reg_a_19_FFX_RST : STD_LOGIC; + signal reg_b_11_FFY_RST : STD_LOGIC; + signal reg_b_11_FFX_RST : STD_LOGIC; + signal reg_a_21_FFX_RST : STD_LOGIC; + signal reg_a_13_FFY_RST : STD_LOGIC; + signal reg_a_13_FFX_RST : STD_LOGIC; + signal reg_a_30_FFY_RST : STD_LOGIC; + signal reg_a_23_FFY_RST : STD_LOGIC; + signal reg_a_23_FFX_RST : STD_LOGIC; + signal reg_a_15_FFY_RST : STD_LOGIC; + signal reg_a_15_FFX_RST : STD_LOGIC; + signal reg_b_17_FFX_RST : STD_LOGIC; + signal reg_b_27_FFY_RST : STD_LOGIC; + signal reg_b_27_FFX_RST : STD_LOGIC; + signal reg_b_19_FFY_RST : STD_LOGIC; + signal reg_b_19_FFX_RST : STD_LOGIC; + signal reg_b_29_FFY_RST : STD_LOGIC; + signal reg_b_29_FFX_RST : STD_LOGIC; + signal reg_c_31_FFY_RST : STD_LOGIC; + signal reg_a_1_FFY_RST : STD_LOGIC; + signal reg_a_1_FFX_RST : STD_LOGIC; + signal reg_a_3_FFY_RST : STD_LOGIC; + signal reg_a_3_FFX_RST : STD_LOGIC; + signal reg_b_3_FFY_RST : STD_LOGIC; + signal reg_b_3_FFX_RST : STD_LOGIC; + signal reg_a_9_FFY_RST : STD_LOGIC; + signal reg_a_9_FFX_RST : STD_LOGIC; + signal reg_b_5_FFY_RST : STD_LOGIC; + signal reg_b_5_FFX_RST : STD_LOGIC; + signal reg_b_7_FFY_RST : STD_LOGIC; + signal reg_b_7_FFX_RST : STD_LOGIC; + signal VCC : STD_LOGIC; + signal GND : STD_LOGIC; + signal reg_c : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal reg_b : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal reg_a : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal dmuxo : STD_LOGIC_VECTOR ( 31 downto 0 ); +begin + dmuxo_23_34_SW1 : X_LUT4 + generic map( + INIT => X"FDFD" + ) + port map ( + ADR0 => reg_c(23), + ADR1 => a_4_IBUF, + ADR2 => a_7_IBUF, + ADR3 => VCC, + O => N4792_F + ); + dmuxo_16_34_SW1 : X_LUT4 + generic map( + INIT => X"FCFF" + ) + port map ( + ADR0 => VCC, + ADR1 => a_4_IBUF, + ADR2 => a_7_IBUF, + ADR3 => reg_c(16), + O => N4792_G + ); + N4792_XUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4792_F, + O => N4792 + ); + N4792_YUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4792_G, + O => N4774 + ); + dmuxo_0_34 : X_LUT4 + generic map( + INIT => X"1015" + ) + port map ( + ADR0 => a_6_IBUF, + ADR1 => N4756, + ADR2 => a_5_IBUF, + ADR3 => N4754, + O => dmuxo_0_F + ); + dmuxo_0_34_SW0 : X_LUT4 + generic map( + INIT => X"F2F7" + ) + port map ( + ADR0 => a_4_IBUF, + ADR1 => reg_b(0), + ADR2 => a_7_IBUF, + ADR3 => reg_a(0), + O => dmuxo_0_G + ); + dmuxo_0_XUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_0_F, + O => dmuxo(0) + ); + dmuxo_0_YUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_0_G, + O => N4754 + ); + N4725_XUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4725_F, + O => N4725 + ); + N4725_YUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4725_G, + O => N4756 + ); + Q_n00001 : X_LUT4 + generic map( + INIT => X"0030" + ) + port map ( + ADR0 => VCC, + ADR1 => a_5_IBUF, + ADR2 => N2469, + ADR3 => a_4_IBUF, + O => Q_n0001_G + ); + Q_n0001_XUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0001_F, + O => Q_n0001 + ); + Q_n0001_YUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0001_G, + O => Q_n0000 + ); + dmuxo_11_34_SW1 : X_LUT4 + generic map( + INIT => X"FFDD" + ) + port map ( + ADR0 => reg_c(11), + ADR1 => a_7_IBUF, + ADR2 => VCC, + ADR3 => a_4_IBUF, + O => N4725_F + ); + dmuxo_8_XUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_8_F, + O => dmuxo(8) + ); + dmuxo_8_YUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_8_G, + O => N4778 + ); + dmuxo_8_34_SW1 : X_LUT4 + generic map( + INIT => X"FFF3" + ) + port map ( + ADR0 => VCC, + ADR1 => reg_c(8), + ADR2 => a_7_IBUF, + ADR3 => a_4_IBUF, + O => N4786_G + ); + N4786_XUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4786_F, + O => N4786 + ); + N4786_YUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4786_G, + O => N4780 + ); + N4738_XUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4738_F, + O => N4738 + ); + N4738_YUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4738_G, + O => N2377 + ); + dmuxo_13_XUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_13_F, + O => dmuxo(13) + ); + dmuxo_13_YUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_13_G, + O => N4705 + ); + N4719_XUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4719_F, + O => N4719 + ); + N4719_YUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4719_G, + O => N4707 + ); + Q_n0002_XUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0002_F, + O => Q_n0002 + ); + Q_n0002_YUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0002_G, + O => N2469 + ); + dmuxo_17_34 : X_LUT4 + generic map( + INIT => X"0047" + ) + port map ( + ADR0 => N4738, + ADR1 => a_5_IBUF, + ADR2 => N4736, + ADR3 => a_6_IBUF, + O => dmuxo_17_F + ); + dmuxo_17_XUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_17_F, + O => dmuxo(17) + ); + dmuxo_17_YUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_17_G, + O => N4736 + ); + dmuxo_1_34 : X_LUT4 + generic map( + INIT => X"0047" + ) + port map ( + ADR0 => N4744, + ADR1 => a_5_IBUF, + ADR2 => N4742, + ADR3 => a_6_IBUF, + O => dmuxo_1_F + ); + dmuxo_1_XUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_1_F, + O => dmuxo(1) + ); + dmuxo_1_YUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_1_G, + O => N4742 + ); + dmuxo_19_34_SW1 : X_LUT4 + generic map( + INIT => X"FBFB" + ) + port map ( + ADR0 => a_7_IBUF, + ADR1 => reg_c(19), + ADR2 => a_4_IBUF, + ADR3 => VCC, + O => N4750_F + ); + N4750_XUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4750_F, + O => N4750 + ); + N4750_YUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4750_G, + O => N4744 + ); + d_7_IFF_ICEINV_0 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0002, + O => d_7_IFF_ICEINV + ); + d_7_IFF_ICLK1INV : X_INV + port map ( + I => clk_BUFGP, + O => d_7_IFF_ICLK1INVNOT + ); + d_7_IFF_IMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_7_INBUF, + O => N4649 + ); + d_7_IFF_IFFDMUX_1 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_7_INBUF, + O => d_7_IFF_IFFDMUX + ); + reg_c_7 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => d_7_IFF_IFFDMUX, + CE => d_7_IFF_ICEINV, + CLK => d_7_IFF_ICLK1INVNOT, + SET => GND, + RST => d_7_IFF_IFF1_RST, + O => reg_c(7) + ); + d_7_IFF_IFF1_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => d_7_IFF_IFF1_RST + ); + d_7_IOBUF_OBUFT : X_TRI_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_7_O, + CTL => d_7_ENABLE, + O => d(7) + ); + d_7_ENABLEINV : X_INV + port map ( + I => d_7_GTS_OR_T, + O => d_7_ENABLE + ); + d_7_GTS_OR_T_2 : X_OR2 + port map ( + I0 => GTS, + I1 => d_7_T, + O => d_7_GTS_OR_T + ); + d_7_IOBUF_IBUF : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d(7), + O => d_7_INBUF + ); + d_8_IFF_ICEINV_3 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0002, + O => d_8_IFF_ICEINV + ); + d_8_IFF_ICLK1INV : X_INV + port map ( + I => clk_BUFGP, + O => d_8_IFF_ICLK1INVNOT + ); + d_8_IFF_IMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_8_INBUF, + O => N4651 + ); + d_8_IFF_IFFDMUX_4 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_8_INBUF, + O => d_8_IFF_IFFDMUX + ); + d_8_IOBUF_OBUFT : X_TRI_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_8_O, + CTL => d_8_ENABLE, + O => d(8) + ); + d_8_ENABLEINV : X_INV + port map ( + I => d_8_GTS_OR_T, + O => d_8_ENABLE + ); + d_8_GTS_OR_T_5 : X_OR2 + port map ( + I0 => GTS, + I1 => d_8_T, + O => d_8_GTS_OR_T + ); + d_8_IOBUF_IBUF : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d(8), + O => d_8_INBUF + ); + d_9_IOBUF_OBUFT : X_TRI_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_9_O, + CTL => d_9_ENABLE, + O => d(9) + ); + d_9_ENABLEINV : X_INV + port map ( + I => d_9_GTS_OR_T, + O => d_9_ENABLE + ); + d_9_GTS_OR_T_6 : X_OR2 + port map ( + I0 => GTS, + I1 => d_9_T, + O => d_9_GTS_OR_T + ); + d_9_IOBUF_IBUF : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d(9), + O => d_9_INBUF + ); + d_10_IOBUF_OBUFT : X_TRI_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_10_O, + CTL => d_10_ENABLE, + O => d(10) + ); + d_10_ENABLEINV : X_INV + port map ( + I => d_10_GTS_OR_T, + O => d_10_ENABLE + ); + d_10_GTS_OR_T_7 : X_OR2 + port map ( + I0 => GTS, + I1 => d_10_T, + O => d_10_GTS_OR_T + ); + d_10_IOBUF_IBUF : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d(10), + O => d_10_INBUF + ); + clk_BUFGP_IBUFG_8 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => clk, + O => clk_INBUF + ); + d_11_IFF_IFF1_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => d_11_IFF_IFF1_RST + ); + reg_c_11 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => d_11_IFF_IFFDMUX, + CE => d_11_IFF_ICEINV, + CLK => d_11_IFF_ICLK1INVNOT, + SET => GND, + RST => d_11_IFF_IFF1_RST, + O => reg_c(11) + ); + d_11_IFF_ICEINV_9 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0002, + O => d_11_IFF_ICEINV + ); + d_11_IFF_ICLK1INV : X_INV + port map ( + I => clk_BUFGP, + O => d_11_IFF_ICLK1INVNOT + ); + d_11_IFF_IMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_11_INBUF, + O => N4593 + ); + d_11_IFF_IFFDMUX_10 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_11_INBUF, + O => d_11_IFF_IFFDMUX + ); + d_11_IOBUF_OBUFT : X_TRI_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_11_O, + CTL => d_11_ENABLE, + O => d(11) + ); + d_11_ENABLEINV : X_INV + port map ( + I => d_11_GTS_OR_T, + O => d_11_ENABLE + ); + d_11_GTS_OR_T_11 : X_OR2 + port map ( + I0 => GTS, + I1 => d_11_T, + O => d_11_GTS_OR_T + ); + d_11_IOBUF_IBUF : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d(11), + O => d_11_INBUF + ); + d_20_IFF_IFF1_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => d_20_IFF_IFF1_RST + ); + reg_c_20 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => d_20_IFF_IFFDMUX, + CE => d_20_IFF_ICEINV, + CLK => d_20_IFF_ICLK1INVNOT, + SET => GND, + RST => d_20_IFF_IFF1_RST, + O => reg_c(20) + ); + d_20_IFF_ICEINV_12 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0002, + O => d_20_IFF_ICEINV + ); + d_20_IFF_ICLK1INV : X_INV + port map ( + I => clk_BUFGP, + O => d_20_IFF_ICLK1INVNOT + ); + d_20_IFF_IMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_20_INBUF, + O => N4603 + ); + d_20_IFF_IFFDMUX_13 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_20_INBUF, + O => d_20_IFF_IFFDMUX + ); + d_20_IOBUF_OBUFT : X_TRI_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_20_O, + CTL => d_20_ENABLE, + O => d(20) + ); + d_20_ENABLEINV : X_INV + port map ( + I => d_20_GTS_OR_T, + O => d_20_ENABLE + ); + d_20_GTS_OR_T_14 : X_OR2 + port map ( + I0 => GTS, + I1 => d_20_T, + O => d_20_GTS_OR_T + ); + d_20_IOBUF_IBUF : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d(20), + O => d_20_INBUF + ); + dmuxo_8_34_SW0 : X_LUT4 + generic map( + INIT => X"CDFD" + ) + port map ( + ADR0 => reg_a(8), + ADR1 => a_7_IBUF, + ADR2 => a_4_IBUF, + ADR3 => reg_b(8), + O => dmuxo_8_G + ); + d_12_IOBUF_OBUFT : X_TRI_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_12_O, + CTL => d_12_ENABLE, + O => d(12) + ); + d_12_ENABLEINV : X_INV + port map ( + I => d_12_GTS_OR_T, + O => d_12_ENABLE + ); + d_12_GTS_OR_T_15 : X_OR2 + port map ( + I0 => GTS, + I1 => d_12_T, + O => d_12_GTS_OR_T + ); + d_12_IOBUF_IBUF : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d(12), + O => d_12_INBUF + ); + Q_n00011 : X_LUT4 + generic map( + INIT => X"3000" + ) + port map ( + ADR0 => VCC, + ADR1 => a_5_IBUF, + ADR2 => N2469, + ADR3 => a_4_IBUF, + O => Q_n0001_F + ); + d_21_IOBUF_OBUFT : X_TRI_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_21_O, + CTL => d_21_ENABLE, + O => d(21) + ); + d_21_ENABLEINV : X_INV + port map ( + I => d_21_GTS_OR_T, + O => d_21_ENABLE + ); + d_21_GTS_OR_T_16 : X_OR2 + port map ( + I0 => GTS, + I1 => d_21_T, + O => d_21_GTS_OR_T + ); + d_21_IOBUF_IBUF : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d(21), + O => d_21_INBUF + ); + d_13_IOBUF_OBUFT : X_TRI_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_13_O, + CTL => d_13_ENABLE, + O => d(13) + ); + d_13_ENABLEINV : X_INV + port map ( + I => d_13_GTS_OR_T, + O => d_13_ENABLE + ); + d_13_GTS_OR_T_17 : X_OR2 + port map ( + I0 => GTS, + I1 => d_13_T, + O => d_13_GTS_OR_T + ); + d_13_IOBUF_IBUF : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d(13), + O => d_13_INBUF + ); + d_30_IOBUF_OBUFT : X_TRI_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_30_O, + CTL => d_30_ENABLE, + O => d(30) + ); + d_30_ENABLEINV : X_INV + port map ( + I => d_30_GTS_OR_T, + O => d_30_ENABLE + ); + d_30_GTS_OR_T_18 : X_OR2 + port map ( + I0 => GTS, + I1 => d_30_T, + O => d_30_GTS_OR_T + ); + d_30_IOBUF_IBUF : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d(30), + O => d_30_INBUF + ); + d_22_IOBUF_OBUFT : X_TRI_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_22_O, + CTL => d_22_ENABLE, + O => d(22) + ); + d_22_ENABLEINV : X_INV + port map ( + I => d_22_GTS_OR_T, + O => d_22_ENABLE + ); + d_22_GTS_OR_T_19 : X_OR2 + port map ( + I0 => GTS, + I1 => d_22_T, + O => d_22_GTS_OR_T + ); + d_22_IOBUF_IBUF : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d(22), + O => d_22_INBUF + ); + d_14_IOBUF_OBUFT : X_TRI_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_14_O, + CTL => d_14_ENABLE, + O => d(14) + ); + d_14_ENABLEINV : X_INV + port map ( + I => d_14_GTS_OR_T, + O => d_14_ENABLE + ); + d_14_GTS_OR_T_20 : X_OR2 + port map ( + I0 => GTS, + I1 => d_14_T, + O => d_14_GTS_OR_T + ); + d_14_IOBUF_IBUF : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d(14), + O => d_14_INBUF + ); + d_31_IOBUF_OBUFT : X_TRI_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_31_O, + CTL => d_31_ENABLE, + O => d(31) + ); + d_31_ENABLEINV : X_INV + port map ( + I => d_31_GTS_OR_T, + O => d_31_ENABLE + ); + d_31_GTS_OR_T_21 : X_OR2 + port map ( + I0 => GTS, + I1 => d_31_T, + O => d_31_GTS_OR_T + ); + d_31_IOBUF_IBUF : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d(31), + O => d_31_INBUF + ); + d_23_IOBUF_OBUFT : X_TRI_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_23_O, + CTL => d_23_ENABLE, + O => d(23) + ); + d_23_ENABLEINV : X_INV + port map ( + I => d_23_GTS_OR_T, + O => d_23_ENABLE + ); + d_23_GTS_OR_T_22 : X_OR2 + port map ( + I0 => GTS, + I1 => d_23_T, + O => d_23_GTS_OR_T + ); + d_23_IOBUF_IBUF : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d(23), + O => d_23_INBUF + ); + d_15_IOBUF_OBUFT : X_TRI_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_15_O, + CTL => d_15_ENABLE, + O => d(15) + ); + d_15_ENABLEINV : X_INV + port map ( + I => d_15_GTS_OR_T, + O => d_15_ENABLE + ); + d_15_GTS_OR_T_23 : X_OR2 + port map ( + I0 => GTS, + I1 => d_15_T, + O => d_15_GTS_OR_T + ); + d_15_IOBUF_IBUF : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d(15), + O => d_15_INBUF + ); + d_24_IOBUF_OBUFT : X_TRI_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_24_O, + CTL => d_24_ENABLE, + O => d(24) + ); + d_24_ENABLEINV : X_INV + port map ( + I => d_24_GTS_OR_T, + O => d_24_ENABLE + ); + d_24_GTS_OR_T_24 : X_OR2 + port map ( + I0 => GTS, + I1 => d_24_T, + O => d_24_GTS_OR_T + ); + d_24_IOBUF_IBUF : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d(24), + O => d_24_INBUF + ); + d_16_IOBUF_OBUFT : X_TRI_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_16_O, + CTL => d_16_ENABLE, + O => d(16) + ); + d_16_ENABLEINV : X_INV + port map ( + I => d_16_GTS_OR_T, + O => d_16_ENABLE + ); + d_16_GTS_OR_T_25 : X_OR2 + port map ( + I0 => GTS, + I1 => d_16_T, + O => d_16_GTS_OR_T + ); + d_16_IOBUF_IBUF : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d(16), + O => d_16_INBUF + ); + d_25_IOBUF_OBUFT : X_TRI_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_25_O, + CTL => d_25_ENABLE, + O => d(25) + ); + d_25_ENABLEINV : X_INV + port map ( + I => d_25_GTS_OR_T, + O => d_25_ENABLE + ); + d_25_GTS_OR_T_26 : X_OR2 + port map ( + I0 => GTS, + I1 => d_25_T, + O => d_25_GTS_OR_T + ); + d_25_IOBUF_IBUF : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d(25), + O => d_25_INBUF + ); + dmuxo_0_34_SW1 : X_LUT4 + generic map( + INIT => X"FFCF" + ) + port map ( + ADR0 => VCC, + ADR1 => a_7_IBUF, + ADR2 => reg_c(0), + ADR3 => a_4_IBUF, + O => N4725_G + ); + Ker23751 : X_LUT4 + generic map( + INIT => X"FAFA" + ) + port map ( + ADR0 => a_6_IBUF, + ADR1 => VCC, + ADR2 => a_7_IBUF, + ADR3 => VCC, + O => N4738_G + ); + Ker24671 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => a_6_IBUF, + ADR1 => wen_IBUF, + ADR2 => csn_IBUF, + ADR3 => a_7_IBUF, + O => Q_n0002_G + ); + dmuxo_13_34_SW1 : X_LUT4 + generic map( + INIT => X"FFCF" + ) + port map ( + ADR0 => VCC, + ADR1 => a_4_IBUF, + ADR2 => reg_c(13), + ADR3 => a_7_IBUF, + O => N4719_G + ); + dmuxo_17_34_SW0 : X_LUT4 + generic map( + INIT => X"FF1D" + ) + port map ( + ADR0 => reg_a(17), + ADR1 => a_4_IBUF, + ADR2 => reg_b(17), + ADR3 => a_7_IBUF, + O => dmuxo_17_G + ); + dmuxo_1_34_SW0 : X_LUT4 + generic map( + INIT => X"FF1D" + ) + port map ( + ADR0 => reg_a(1), + ADR1 => a_4_IBUF, + ADR2 => reg_b(1), + ADR3 => a_7_IBUF, + O => dmuxo_1_G + ); + dmuxo_1_34_SW1 : X_LUT4 + generic map( + INIT => X"FBFB" + ) + port map ( + ADR0 => a_7_IBUF, + ADR1 => reg_c(1), + ADR2 => a_4_IBUF, + ADR3 => VCC, + O => N4750_G + ); + d_9_IFF_IFFDMUX_27 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_9_INBUF, + O => d_9_IFF_IFFDMUX + ); + d_9_IFF_IMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_9_INBUF, + O => N4653 + ); + d_9_IFF_ICLK1INV : X_INV + port map ( + I => clk_BUFGP, + O => d_9_IFF_ICLK1INVNOT + ); + d_9_IFF_ICEINV_28 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0002, + O => d_9_IFF_ICEINV + ); + reg_c_8 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => d_8_IFF_IFFDMUX, + CE => d_8_IFF_ICEINV, + CLK => d_8_IFF_ICLK1INVNOT, + SET => GND, + RST => d_8_IFF_IFF1_RST, + O => reg_c(8) + ); + d_8_IFF_IFF1_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => d_8_IFF_IFF1_RST + ); + d_12_IFF_IFFDMUX_29 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_12_INBUF, + O => d_12_IFF_IFFDMUX + ); + d_12_IFF_IMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_12_INBUF, + O => N4595 + ); + d_12_IFF_ICLK1INV : X_INV + port map ( + I => clk_BUFGP, + O => d_12_IFF_ICLK1INVNOT + ); + d_12_IFF_ICEINV_30 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0002, + O => d_12_IFF_ICEINV + ); + d_13_IFF_IFFDMUX_31 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_13_INBUF, + O => d_13_IFF_IFFDMUX + ); + d_13_IFF_IMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_13_INBUF, + O => N4597 + ); + d_13_IFF_ICLK1INV : X_INV + port map ( + I => clk_BUFGP, + O => d_13_IFF_ICLK1INVNOT + ); + d_13_IFF_ICEINV_32 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0002, + O => d_13_IFF_ICEINV + ); + d_22_IFF_IFFDMUX_33 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_22_INBUF, + O => d_22_IFF_IFFDMUX + ); + d_22_IFF_IMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_22_INBUF, + O => N4611 + ); + d_22_IFF_ICLK1INV : X_INV + port map ( + I => clk_BUFGP, + O => d_22_IFF_ICLK1INVNOT + ); + d_22_IFF_ICEINV_34 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0002, + O => d_22_IFF_ICEINV + ); + d_14_IFF_IFFDMUX_35 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_14_INBUF, + O => d_14_IFF_IFFDMUX + ); + d_14_IFF_IMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_14_INBUF, + O => N4599 + ); + d_14_IFF_ICLK1INV : X_INV + port map ( + I => clk_BUFGP, + O => d_14_IFF_ICLK1INVNOT + ); + d_14_IFF_ICEINV_36 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0002, + O => d_14_IFF_ICEINV + ); + d_31_IFF_IFF1_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => d_31_IFF_IFF1_RST + ); + reg_a_31 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => d_31_IFF_IFFDMUX, + CE => d_31_IFF_ICEINV, + CLK => d_31_IFF_ICLK1INVNOT, + SET => GND, + RST => d_31_IFF_IFF1_RST, + O => reg_a(31) + ); + d_31_IFF_IFFDMUX_37 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_31_INBUF, + O => d_31_IFF_IFFDMUX + ); + d_31_IFF_IMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_31_INBUF, + O => N4627 + ); + d_31_IFF_ICLK1INV : X_INV + port map ( + I => clk_BUFGP, + O => d_31_IFF_ICLK1INVNOT + ); + d_31_IFF_ICEINV_38 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0000, + O => d_31_IFF_ICEINV + ); + d_23_IFF_IFFDMUX_39 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_23_INBUF, + O => d_23_IFF_IFFDMUX + ); + d_23_IFF_IMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_23_INBUF, + O => N4615 + ); + d_23_IFF_ICLK1INV : X_INV + port map ( + I => clk_BUFGP, + O => d_23_IFF_ICLK1INVNOT + ); + d_23_IFF_ICEINV_40 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0002, + O => d_23_IFF_ICEINV + ); + d_24_IFF_IFFDMUX_41 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_24_INBUF, + O => d_24_IFF_IFFDMUX + ); + d_24_IFF_IMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_24_INBUF, + O => N4619 + ); + d_24_IFF_ICLK1INV : X_INV + port map ( + I => clk_BUFGP, + O => d_24_IFF_ICLK1INVNOT + ); + d_24_IFF_ICEINV_42 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0002, + O => d_24_IFF_ICEINV + ); + d_25_IFF_IFFDMUX_43 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_25_INBUF, + O => d_25_IFF_IFFDMUX + ); + d_25_IFF_IMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_25_INBUF, + O => N4621 + ); + d_25_IFF_ICLK1INV : X_INV + port map ( + I => clk_BUFGP, + O => d_25_IFF_ICLK1INVNOT + ); + d_25_IFF_ICEINV_44 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0002, + O => d_25_IFF_ICEINV + ); + d_17_IOBUF_OBUFT : X_TRI_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_17_O, + CTL => d_17_ENABLE, + O => d(17) + ); + d_17_ENABLEINV : X_INV + port map ( + I => d_17_GTS_OR_T, + O => d_17_ENABLE + ); + d_17_GTS_OR_T_45 : X_OR2 + port map ( + I0 => GTS, + I1 => d_17_T, + O => d_17_GTS_OR_T + ); + d_17_IOBUF_IBUF : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d(17), + O => d_17_INBUF + ); + d_26_IFF_ICEINV_46 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0002, + O => d_26_IFF_ICEINV + ); + d_26_IFF_ICLK1INV : X_INV + port map ( + I => clk_BUFGP, + O => d_26_IFF_ICLK1INVNOT + ); + d_26_IFF_IMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_26_INBUF, + O => N4625 + ); + d_26_IFF_IFFDMUX_47 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_26_INBUF, + O => d_26_IFF_IFFDMUX + ); + d_26_IOBUF_OBUFT : X_TRI_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_26_O, + CTL => d_26_ENABLE, + O => d(26) + ); + d_26_ENABLEINV : X_INV + port map ( + I => d_26_GTS_OR_T, + O => d_26_ENABLE + ); + d_26_GTS_OR_T_48 : X_OR2 + port map ( + I0 => GTS, + I1 => d_26_T, + O => d_26_GTS_OR_T + ); + d_26_IOBUF_IBUF : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d(26), + O => d_26_INBUF + ); + d_18_IOBUF_OBUFT : X_TRI_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_18_O, + CTL => d_18_ENABLE, + O => d(18) + ); + d_18_ENABLEINV : X_INV + port map ( + I => d_18_GTS_OR_T, + O => d_18_ENABLE + ); + d_18_GTS_OR_T_49 : X_OR2 + port map ( + I0 => GTS, + I1 => d_18_T, + O => d_18_GTS_OR_T + ); + d_18_IOBUF_IBUF : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d(18), + O => d_18_INBUF + ); + d_27_IFF_ICEINV_50 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0002, + O => d_27_IFF_ICEINV + ); + d_27_IFF_ICLK1INV : X_INV + port map ( + I => clk_BUFGP, + O => d_27_IFF_ICLK1INVNOT + ); + d_27_IFF_IMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_27_INBUF, + O => N4629 + ); + d_27_IFF_IFFDMUX_51 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_27_INBUF, + O => d_27_IFF_IFFDMUX + ); + reg_c_27 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => d_27_IFF_IFFDMUX, + CE => d_27_IFF_ICEINV, + CLK => d_27_IFF_ICLK1INVNOT, + SET => GND, + RST => d_27_IFF_IFF1_RST, + O => reg_c(27) + ); + d_27_IFF_IFF1_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => d_27_IFF_IFF1_RST + ); + d_27_IOBUF_OBUFT : X_TRI_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_27_O, + CTL => d_27_ENABLE, + O => d(27) + ); + d_27_ENABLEINV : X_INV + port map ( + I => d_27_GTS_OR_T, + O => d_27_ENABLE + ); + d_27_GTS_OR_T_52 : X_OR2 + port map ( + I0 => GTS, + I1 => d_27_T, + O => d_27_GTS_OR_T + ); + d_27_IOBUF_IBUF : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d(27), + O => d_27_INBUF + ); + d_19_IFF_IFF1_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => d_19_IFF_IFF1_RST + ); + reg_c_19 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => d_19_IFF_IFFDMUX, + CE => d_19_IFF_ICEINV, + CLK => d_19_IFF_ICLK1INVNOT, + SET => GND, + RST => d_19_IFF_IFF1_RST, + O => reg_c(19) + ); + d_19_IFF_ICEINV_53 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0002, + O => d_19_IFF_ICEINV + ); + d_19_IFF_ICLK1INV : X_INV + port map ( + I => clk_BUFGP, + O => d_19_IFF_ICLK1INVNOT + ); + d_19_IFF_IMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_19_INBUF, + O => N4617 + ); + d_19_IFF_IFFDMUX_54 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_19_INBUF, + O => d_19_IFF_IFFDMUX + ); + d_19_IOBUF_OBUFT : X_TRI_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_19_O, + CTL => d_19_ENABLE, + O => d(19) + ); + d_19_ENABLEINV : X_INV + port map ( + I => d_19_GTS_OR_T, + O => d_19_ENABLE + ); + d_19_GTS_OR_T_55 : X_OR2 + port map ( + I0 => GTS, + I1 => d_19_T, + O => d_19_GTS_OR_T + ); + d_19_IOBUF_IBUF : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d(19), + O => d_19_INBUF + ); + csn_IBUF_56 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => csn, + O => csn_INBUF + ); + dmuxo_8_34 : X_LUT4 + generic map( + INIT => X"0207" + ) + port map ( + ADR0 => a_5_IBUF, + ADR1 => N4780, + ADR2 => a_6_IBUF, + ADR3 => N4778, + O => dmuxo_8_F + ); + d_28_IOBUF_OBUFT : X_TRI_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_28_O, + CTL => d_28_ENABLE, + O => d(28) + ); + d_28_ENABLEINV : X_INV + port map ( + I => d_28_GTS_OR_T, + O => d_28_ENABLE + ); + d_28_GTS_OR_T_57 : X_OR2 + port map ( + I0 => GTS, + I1 => d_28_T, + O => d_28_GTS_OR_T + ); + d_28_IOBUF_IBUF : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d(28), + O => d_28_INBUF + ); + d_29_IOBUF_OBUFT : X_TRI_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_29_O, + CTL => d_29_ENABLE, + O => d(29) + ); + d_29_ENABLEINV : X_INV + port map ( + I => d_29_GTS_OR_T, + O => d_29_ENABLE + ); + d_29_GTS_OR_T_58 : X_OR2 + port map ( + I0 => GTS, + I1 => d_29_T, + O => d_29_GTS_OR_T + ); + d_29_IOBUF_IBUF : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d(29), + O => d_29_INBUF + ); + a_4_IBUF_59 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => a(4), + O => a_4_INBUF + ); + a_5_IBUF_60 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => a(5), + O => a_5_INBUF + ); + a_6_IBUF_61 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => a(6), + O => a_6_INBUF + ); + a_7_IBUF_62 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => a(7), + O => a_7_INBUF + ); + wen_IBUF_63 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => wen, + O => wen_INBUF + ); + d_0_IOBUF_OBUFT : X_TRI_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_0_O, + CTL => d_0_ENABLE, + O => d(0) + ); + d_0_ENABLEINV : X_INV + port map ( + I => d_0_GTS_OR_T, + O => d_0_ENABLE + ); + d_0_GTS_OR_T_64 : X_OR2 + port map ( + I0 => GTS, + I1 => d_0_T, + O => d_0_GTS_OR_T + ); + d_0_IOBUF_IBUF : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d(0), + O => d_0_INBUF + ); + d_1_IFF_ICEINV_65 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0002, + O => d_1_IFF_ICEINV + ); + d_1_IFF_ICLK1INV : X_INV + port map ( + I => clk_BUFGP, + O => d_1_IFF_ICLK1INVNOT + ); + d_1_IFF_IMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_1_INBUF, + O => N4637 + ); + d_1_IFF_IFFDMUX_66 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_1_INBUF, + O => d_1_IFF_IFFDMUX + ); + d_1_IOBUF_OBUFT : X_TRI_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_1_O, + CTL => d_1_ENABLE, + O => d(1) + ); + d_1_ENABLEINV : X_INV + port map ( + I => d_1_GTS_OR_T, + O => d_1_ENABLE + ); + d_1_GTS_OR_T_67 : X_OR2 + port map ( + I0 => GTS, + I1 => d_1_T, + O => d_1_GTS_OR_T + ); + d_1_IOBUF_IBUF : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d(1), + O => d_1_INBUF + ); + d_2_IOBUF_OBUFT : X_TRI_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_2_O, + CTL => d_2_ENABLE, + O => d(2) + ); + d_2_ENABLEINV : X_INV + port map ( + I => d_2_GTS_OR_T, + O => d_2_ENABLE + ); + d_2_GTS_OR_T_68 : X_OR2 + port map ( + I0 => GTS, + I1 => d_2_T, + O => d_2_GTS_OR_T + ); + d_2_IOBUF_IBUF : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d(2), + O => d_2_INBUF + ); + d_3_IFF_ICEINV_69 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0002, + O => d_3_IFF_ICEINV + ); + d_3_IFF_ICLK1INV : X_INV + port map ( + I => clk_BUFGP, + O => d_3_IFF_ICLK1INVNOT + ); + d_3_IFF_IMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_3_INBUF, + O => N4641 + ); + d_3_IFF_IFFDMUX_70 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_3_INBUF, + O => d_3_IFF_IFFDMUX + ); + d_3_IOBUF_OBUFT : X_TRI_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_3_O, + CTL => d_3_ENABLE, + O => d(3) + ); + d_3_ENABLEINV : X_INV + port map ( + I => d_3_GTS_OR_T, + O => d_3_ENABLE + ); + d_3_GTS_OR_T_71 : X_OR2 + port map ( + I0 => GTS, + I1 => d_3_T, + O => d_3_GTS_OR_T + ); + d_3_IOBUF_IBUF : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d(3), + O => d_3_INBUF + ); + d_4_IOBUF_OBUFT : X_TRI_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_4_O, + CTL => d_4_ENABLE, + O => d(4) + ); + d_4_ENABLEINV : X_INV + port map ( + I => d_4_GTS_OR_T, + O => d_4_ENABLE + ); + d_4_GTS_OR_T_72 : X_OR2 + port map ( + I0 => GTS, + I1 => d_4_T, + O => d_4_GTS_OR_T + ); + d_4_IOBUF_IBUF : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d(4), + O => d_4_INBUF + ); + d_5_IFF_ICEINV_73 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0002, + O => d_5_IFF_ICEINV + ); + d_5_IFF_ICLK1INV : X_INV + port map ( + I => clk_BUFGP, + O => d_5_IFF_ICLK1INVNOT + ); + d_5_IFF_IMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_5_INBUF, + O => N4645 + ); + d_5_IFF_IFFDMUX_74 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_5_INBUF, + O => d_5_IFF_IFFDMUX + ); + d_5_IOBUF_OBUFT : X_TRI_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_5_O, + CTL => d_5_ENABLE, + O => d(5) + ); + d_5_ENABLEINV : X_INV + port map ( + I => d_5_GTS_OR_T, + O => d_5_ENABLE + ); + d_5_GTS_OR_T_75 : X_OR2 + port map ( + I0 => GTS, + I1 => d_5_T, + O => d_5_GTS_OR_T + ); + d_5_IOBUF_IBUF : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d(5), + O => d_5_INBUF + ); + d_6_IOBUF_OBUFT : X_TRI_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_6_O, + CTL => d_6_ENABLE, + O => d(6) + ); + d_6_ENABLEINV : X_INV + port map ( + I => d_6_GTS_OR_T, + O => d_6_ENABLE + ); + d_6_GTS_OR_T_76 : X_OR2 + port map ( + I0 => GTS, + I1 => d_6_T, + O => d_6_GTS_OR_T + ); + d_6_IOBUF_IBUF : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d(6), + O => d_6_INBUF + ); + clk_BUFGP_BUFG : X_BUFGMUX + port map ( + I0 => clk_BUFGP_IBUFG, + I1 => GND, + S => clk_BUFGP_BUFG_S_INVNOT, + O => clk_BUFGP, + GSR => GSR + ); + clk_BUFGP_BUFG_SINV : X_INV + port map ( + I => GLOBAL_LOGIC1, + O => clk_BUFGP_BUFG_S_INVNOT + ); + dmuxo_31_34_SW1 : X_LUT4 + generic map( + INIT => X"FFF3" + ) + port map ( + ADR0 => VCC, + ADR1 => reg_c(31), + ADR2 => a_7_IBUF, + ADR3 => a_4_IBUF, + O => N4786_F + ); + dmuxo_12_XUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_12_F5MUX, + O => dmuxo(12) + ); + dmuxo_12_F5MUX_77 : X_MUX2 + port map ( + IA => N4846, + IB => N4848, + SEL => dmuxo_12_BXINV, + O => dmuxo_12_F5MUX + ); + dmuxo_12_BXINV_78 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => a_5_IBUF, + O => dmuxo_12_BXINV + ); + dmuxo_20_19_F : X_LUT4 + generic map( + INIT => X"FBEA" + ) + port map ( + ADR0 => N2377, + ADR1 => a_4_IBUF, + ADR2 => reg_b(20), + ADR3 => reg_a(20), + O => N4831 + ); + dmuxo_20_XUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_20_F5MUX, + O => dmuxo(20) + ); + dmuxo_20_F5MUX_79 : X_MUX2 + port map ( + IA => N4831, + IB => N4833, + SEL => dmuxo_20_BXINV, + O => dmuxo_20_F5MUX + ); + dmuxo_20_BXINV_80 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => a_5_IBUF, + O => dmuxo_20_BXINV + ); + dmuxo_21_19_F : X_LUT4 + generic map( + INIT => X"FFCA" + ) + port map ( + ADR0 => reg_a(21), + ADR1 => reg_b(21), + ADR2 => a_4_IBUF, + ADR3 => N2377, + O => N4856 + ); + dmuxo_21_XUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_21_F5MUX, + O => dmuxo(21) + ); + dmuxo_21_F5MUX_81 : X_MUX2 + port map ( + IA => N4856, + IB => N4858, + SEL => dmuxo_21_BXINV, + O => dmuxo_21_F5MUX + ); + dmuxo_21_BXINV_82 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => a_5_IBUF, + O => dmuxo_21_BXINV + ); + dmuxo_3_XUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_3_F5MUX, + O => dmuxo(3) + ); + dmuxo_3_F5MUX_83 : X_MUX2 + port map ( + IA => N4836, + IB => N4838, + SEL => dmuxo_3_BXINV, + O => dmuxo_3_F5MUX + ); + dmuxo_3_BXINV_84 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => a_5_IBUF, + O => dmuxo_3_BXINV + ); + dmuxo_14_19_F : X_LUT4 + generic map( + INIT => X"FFCA" + ) + port map ( + ADR0 => reg_a(14), + ADR1 => reg_b(14), + ADR2 => a_4_IBUF, + ADR3 => N2377, + O => N4881 + ); + dmuxo_14_XUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_14_F5MUX, + O => dmuxo(14) + ); + dmuxo_14_F5MUX_85 : X_MUX2 + port map ( + IA => N4881, + IB => N4883, + SEL => dmuxo_14_BXINV, + O => dmuxo_14_F5MUX + ); + dmuxo_14_BXINV_86 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => a_5_IBUF, + O => dmuxo_14_BXINV + ); + dmuxo_4_19_F : X_LUT4 + generic map( + INIT => X"FFCA" + ) + port map ( + ADR0 => reg_a(4), + ADR1 => reg_b(4), + ADR2 => a_4_IBUF, + ADR3 => N2377, + O => N4851 + ); + dmuxo_4_XUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_4_F5MUX, + O => dmuxo(4) + ); + dmuxo_4_F5MUX_87 : X_MUX2 + port map ( + IA => N4851, + IB => N4853, + SEL => dmuxo_4_BXINV, + O => dmuxo_4_F5MUX + ); + dmuxo_4_BXINV_88 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => a_5_IBUF, + O => dmuxo_4_BXINV + ); + dmuxo_5_19_F : X_LUT4 + generic map( + INIT => X"FFB8" + ) + port map ( + ADR0 => reg_b(5), + ADR1 => a_4_IBUF, + ADR2 => reg_a(5), + ADR3 => N2377, + O => N4861 + ); + dmuxo_5_XUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_5_F5MUX, + O => dmuxo(5) + ); + dmuxo_5_F5MUX_89 : X_MUX2 + port map ( + IA => N4861, + IB => N4863, + SEL => dmuxo_5_BXINV, + O => dmuxo_5_F5MUX + ); + dmuxo_5_BXINV_90 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => a_5_IBUF, + O => dmuxo_5_BXINV + ); + dmuxo_6_19_F : X_LUT4 + generic map( + INIT => X"FEBA" + ) + port map ( + ADR0 => N2377, + ADR1 => a_4_IBUF, + ADR2 => reg_a(6), + ADR3 => reg_b(6), + O => N4871 + ); + dmuxo_6_XUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_6_F5MUX, + O => dmuxo(6) + ); + dmuxo_6_F5MUX_91 : X_MUX2 + port map ( + IA => N4871, + IB => N4873, + SEL => dmuxo_6_BXINV, + O => dmuxo_6_F5MUX + ); + dmuxo_6_BXINV_92 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => a_5_IBUF, + O => dmuxo_6_BXINV + ); + dmuxo_25_19_F : X_LUT4 + generic map( + INIT => X"FBEA" + ) + port map ( + ADR0 => N2377, + ADR1 => a_4_IBUF, + ADR2 => reg_b(25), + ADR3 => reg_a(25), + O => N4866 + ); + dmuxo_25_XUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_25_F5MUX, + O => dmuxo(25) + ); + dmuxo_25_F5MUX_93 : X_MUX2 + port map ( + IA => N4866, + IB => N4868, + SEL => dmuxo_25_BXINV, + O => dmuxo_25_F5MUX + ); + dmuxo_25_BXINV_94 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => a_5_IBUF, + O => dmuxo_25_BXINV + ); + dmuxo_18_19_F : X_LUT4 + generic map( + INIT => X"FFAC" + ) + port map ( + ADR0 => reg_b(18), + ADR1 => reg_a(18), + ADR2 => a_4_IBUF, + ADR3 => N2377, + O => N4841 + ); + dmuxo_18_XUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_18_F5MUX, + O => dmuxo(18) + ); + dmuxo_18_F5MUX_95 : X_MUX2 + port map ( + IA => N4841, + IB => N4843, + SEL => dmuxo_18_BXINV, + O => dmuxo_18_F5MUX + ); + dmuxo_18_BXINV_96 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => a_5_IBUF, + O => dmuxo_18_BXINV + ); + dmuxo_9_19_F : X_LUT4 + generic map( + INIT => X"FFAC" + ) + port map ( + ADR0 => reg_b(9), + ADR1 => reg_a(9), + ADR2 => a_4_IBUF, + ADR3 => N2377, + O => N4826 + ); + dmuxo_9_XUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_9_F5MUX, + O => dmuxo(9) + ); + dmuxo_9_F5MUX_97 : X_MUX2 + port map ( + IA => N4826, + IB => N4828, + SEL => dmuxo_9_BXINV, + O => dmuxo_9_F5MUX + ); + dmuxo_9_BXINV_98 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => a_5_IBUF, + O => dmuxo_9_BXINV + ); + dmuxo_28_19_F : X_LUT4 + generic map( + INIT => X"FBEA" + ) + port map ( + ADR0 => N2377, + ADR1 => a_4_IBUF, + ADR2 => reg_b(28), + ADR3 => reg_a(28), + O => N4876 + ); + dmuxo_28_XUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_28_F5MUX, + O => dmuxo(28) + ); + dmuxo_28_F5MUX_99 : X_MUX2 + port map ( + IA => N4876, + IB => N4878, + SEL => dmuxo_28_BXINV, + O => dmuxo_28_F5MUX + ); + dmuxo_28_BXINV_100 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => a_5_IBUF, + O => dmuxo_28_BXINV + ); + dmuxo_10_19_F : X_LUT4 + generic map( + INIT => X"FFE4" + ) + port map ( + ADR0 => a_4_IBUF, + ADR1 => reg_a(10), + ADR2 => reg_b(10), + ADR3 => N2377, + O => N4821 + ); + dmuxo_10_XUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_10_F5MUX, + O => dmuxo(10) + ); + dmuxo_10_F5MUX_101 : X_MUX2 + port map ( + IA => N4821, + IB => N4823, + SEL => dmuxo_10_BXINV, + O => dmuxo_10_F5MUX + ); + dmuxo_10_BXINV_102 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => a_5_IBUF, + O => dmuxo_10_BXINV + ); + dmuxo_29_34_SW0 : X_LUT4 + generic map( + INIT => X"FF53" + ) + port map ( + ADR0 => reg_b(29), + ADR1 => reg_a(29), + ADR2 => a_4_IBUF, + ADR3 => a_7_IBUF, + O => dmuxo_29_G + ); + dmuxo_29_XUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_29_F, + O => dmuxo(29) + ); + dmuxo_29_YUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_29_G, + O => N4814 + ); + dmuxo_29_34_SW1 : X_LUT4 + generic map( + INIT => X"FDFD" + ) + port map ( + ADR0 => reg_c(29), + ADR1 => a_4_IBUF, + ADR2 => a_7_IBUF, + ADR3 => VCC, + O => N4798_G + ); + N4798_XUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4798_F, + O => N4798 + ); + N4798_YUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4798_G, + O => N4816 + ); + reg_a_11_DXMUX_103 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4593, + O => reg_a_11_DXMUX + ); + reg_a_11_DYMUX_104 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4655, + O => reg_a_11_DYMUX + ); + reg_a_11_CLKINV : X_INV + port map ( + I => clk_BUFGP, + O => reg_a_11_CLKINVNOT + ); + reg_a_11_CEINV_105 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0000, + O => reg_a_11_CEINV + ); + dmuxo_13_34_SW0 : X_LUT4 + generic map( + INIT => X"CFDD" + ) + port map ( + ADR0 => reg_a(13), + ADR1 => a_7_IBUF, + ADR2 => reg_b(13), + ADR3 => a_4_IBUF, + O => dmuxo_13_G + ); + reg_a_21_DXMUX_106 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4607, + O => reg_a_21_DXMUX + ); + reg_a_21_DYMUX_107 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4603, + O => reg_a_21_DYMUX + ); + reg_a_21_CLKINV : X_INV + port map ( + I => clk_BUFGP, + O => reg_a_21_CLKINVNOT + ); + reg_a_21_CEINV_108 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0000, + O => reg_a_21_CEINV + ); + dmuxo_17_34_SW1 : X_LUT4 + generic map( + INIT => X"FAFF" + ) + port map ( + ADR0 => a_7_IBUF, + ADR1 => VCC, + ADR2 => a_4_IBUF, + ADR3 => reg_c(17), + O => N4738_F + ); + reg_a_13_DXMUX_109 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4597, + O => reg_a_13_DXMUX + ); + reg_a_13_DYMUX_110 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4595, + O => reg_a_13_DYMUX + ); + reg_a_13_CLKINV : X_INV + port map ( + I => clk_BUFGP, + O => reg_a_13_CLKINVNOT + ); + reg_a_13_CEINV_111 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0000, + O => reg_a_13_CEINV + ); + reg_a_30_DYMUX_112 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4623, + O => reg_a_30_DYMUX + ); + reg_a_30_CLKINV : X_INV + port map ( + I => clk_BUFGP, + O => reg_a_30_CLKINVNOT + ); + reg_a_30_CEINV_113 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0000, + O => reg_a_30_CEINV + ); + reg_a_23_DXMUX_114 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4615, + O => reg_a_23_DXMUX + ); + reg_a_23_DYMUX_115 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4611, + O => reg_a_23_DYMUX + ); + reg_a_23_CLKINV : X_INV + port map ( + I => clk_BUFGP, + O => reg_a_23_CLKINVNOT + ); + reg_a_23_CEINV_116 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0000, + O => reg_a_23_CEINV + ); + reg_a_15_DXMUX_117 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4601, + O => reg_a_15_DXMUX + ); + reg_a_15_DYMUX_118 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4599, + O => reg_a_15_DYMUX + ); + reg_a_15_CLKINV : X_INV + port map ( + I => clk_BUFGP, + O => reg_a_15_CLKINVNOT + ); + reg_a_15_CEINV_119 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0000, + O => reg_a_15_CEINV + ); + reg_a_25_DXMUX_120 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4621, + O => reg_a_25_DXMUX + ); + reg_a_25_DYMUX_121 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4619, + O => reg_a_25_DYMUX + ); + reg_a_25_CLKINV : X_INV + port map ( + I => clk_BUFGP, + O => reg_a_25_CLKINVNOT + ); + reg_a_25_CEINV_122 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0000, + O => reg_a_25_CEINV + ); + reg_a_17_DXMUX_123 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4609, + O => reg_a_17_DXMUX + ); + reg_a_17_DYMUX_124 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4605, + O => reg_a_17_DYMUX + ); + reg_a_17_CLKINV : X_INV + port map ( + I => clk_BUFGP, + O => reg_a_17_CLKINVNOT + ); + reg_a_17_CEINV_125 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0000, + O => reg_a_17_CEINV + ); + dmuxo_30_XUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_30_F, + O => dmuxo(30) + ); + dmuxo_30_YUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_30_G, + O => N4711 + ); + dmuxo_22_34_SW0 : X_LUT4 + generic map( + INIT => X"DCDF" + ) + port map ( + ADR0 => reg_b(22), + ADR1 => a_7_IBUF, + ADR2 => a_4_IBUF, + ADR3 => reg_a(22), + O => dmuxo_22_G + ); + dmuxo_22_XUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_22_F, + O => dmuxo(22) + ); + dmuxo_22_YUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_22_G, + O => N4808 + ); + reg_a_27_DXMUX_126 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4629, + O => reg_a_27_DXMUX + ); + reg_a_27_DYMUX_127 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4625, + O => reg_a_27_DYMUX + ); + reg_a_27_CLKINV : X_INV + port map ( + I => clk_BUFGP, + O => reg_a_27_CLKINVNOT + ); + reg_a_27_CEINV_128 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0000, + O => reg_a_27_CEINV + ); + reg_a_19_DXMUX_129 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4617, + O => reg_a_19_DXMUX + ); + reg_a_19_DYMUX_130 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4613, + O => reg_a_19_DYMUX + ); + reg_a_19_CLKINV : X_INV + port map ( + I => clk_BUFGP, + O => reg_a_19_CLKINVNOT + ); + reg_a_19_CEINV_131 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0000, + O => reg_a_19_CEINV + ); + reg_b_11_DXMUX_132 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4593, + O => reg_b_11_DXMUX + ); + reg_b_11_DYMUX_133 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4655, + O => reg_b_11_DYMUX + ); + reg_b_11_CLKINV : X_INV + port map ( + I => clk_BUFGP, + O => reg_b_11_CLKINVNOT + ); + reg_b_11_CEINV_134 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0001, + O => reg_b_11_CEINV + ); + N4804_XUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4804_F, + O => N4804 + ); + N4804_YUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4804_G, + O => N4810 + ); + N4768_XUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4768_F, + O => N4768 + ); + N4768_YUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4768_G, + O => N4713 + ); + reg_a_29_DXMUX_135 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4633, + O => reg_a_29_DXMUX + ); + reg_a_29_DYMUX_136 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4631, + O => reg_a_29_DYMUX + ); + reg_a_29_CLKINV : X_INV + port map ( + I => clk_BUFGP, + O => reg_a_29_CLKINVNOT + ); + reg_a_29_CEINV_137 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0000, + O => reg_a_29_CEINV + ); + reg_b_21_DXMUX_138 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4607, + O => reg_b_21_DXMUX + ); + reg_b_21_DYMUX_139 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4603, + O => reg_b_21_DYMUX + ); + reg_b_21_CLKINV : X_INV + port map ( + I => clk_BUFGP, + O => reg_b_21_CLKINVNOT + ); + reg_b_21_CEINV_140 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0001, + O => reg_b_21_CEINV + ); + reg_b_13_DXMUX_141 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4597, + O => reg_b_13_DXMUX + ); + reg_b_13_DYMUX_142 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4595, + O => reg_b_13_DYMUX + ); + reg_b_13_CLKINV : X_INV + port map ( + I => clk_BUFGP, + O => reg_b_13_CLKINVNOT + ); + reg_b_13_CEINV_143 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0001, + O => reg_b_13_CEINV + ); + reg_b_31_DXMUX_144 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4627, + O => reg_b_31_DXMUX + ); + reg_b_31_DYMUX_145 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4623, + O => reg_b_31_DYMUX + ); + reg_b_31_CLKINV : X_INV + port map ( + I => clk_BUFGP, + O => reg_b_31_CLKINVNOT + ); + reg_b_31_CEINV_146 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0001, + O => reg_b_31_CEINV + ); + reg_b_23_DXMUX_147 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4615, + O => reg_b_23_DXMUX + ); + reg_b_23_DYMUX_148 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4611, + O => reg_b_23_DYMUX + ); + reg_b_23_CLKINV : X_INV + port map ( + I => clk_BUFGP, + O => reg_b_23_CLKINVNOT + ); + reg_b_23_CEINV_149 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0001, + O => reg_b_23_CEINV + ); + dmuxo_13_34 : X_LUT4 + generic map( + INIT => X"0027" + ) + port map ( + ADR0 => a_5_IBUF, + ADR1 => N4707, + ADR2 => N4705, + ADR3 => a_6_IBUF, + O => dmuxo_13_F + ); + reg_b_15_DXMUX_150 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4601, + O => reg_b_15_DXMUX + ); + reg_b_15_DYMUX_151 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4599, + O => reg_b_15_DYMUX + ); + reg_b_15_CLKINV : X_INV + port map ( + I => clk_BUFGP, + O => reg_b_15_CLKINVNOT + ); + reg_b_15_CEINV_152 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0001, + O => reg_b_15_CEINV + ); + reg_b_25_DXMUX_153 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4621, + O => reg_b_25_DXMUX + ); + reg_b_25_DYMUX_154 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4619, + O => reg_b_25_DYMUX + ); + reg_b_25_CLKINV : X_INV + port map ( + I => clk_BUFGP, + O => reg_b_25_CLKINVNOT + ); + reg_b_25_CEINV_155 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0001, + O => reg_b_25_CEINV + ); + reg_b_17_DXMUX_156 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4609, + O => reg_b_17_DXMUX + ); + reg_b_17_DYMUX_157 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4605, + O => reg_b_17_DYMUX + ); + reg_b_17_CLKINV : X_INV + port map ( + I => clk_BUFGP, + O => reg_b_17_CLKINVNOT + ); + reg_b_17_CEINV_158 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0001, + O => reg_b_17_CEINV + ); + dmuxo_26_XUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_26_F, + O => dmuxo(26) + ); + dmuxo_26_YUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_26_G, + O => N4730 + ); + reg_b_27_DXMUX_159 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4629, + O => reg_b_27_DXMUX + ); + reg_b_27_DYMUX_160 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4625, + O => reg_b_27_DYMUX + ); + reg_b_27_CLKINV : X_INV + port map ( + I => clk_BUFGP, + O => reg_b_27_CLKINVNOT + ); + reg_b_27_CEINV_161 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0001, + O => reg_b_27_CEINV + ); + reg_b_19_DXMUX_162 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4617, + O => reg_b_19_DXMUX + ); + reg_b_19_DYMUX_163 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4613, + O => reg_b_19_DYMUX + ); + reg_b_19_CLKINV : X_INV + port map ( + I => clk_BUFGP, + O => reg_b_19_CLKINVNOT + ); + reg_b_19_CEINV_164 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0001, + O => reg_b_19_CEINV + ); + N4762_XUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4762_F, + O => N4762 + ); + N4762_YUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4762_G, + O => N4732 + ); + dmuxo_2_XUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_2_F, + O => dmuxo(2) + ); + dmuxo_2_YUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_2_G, + O => N4802 + ); + reg_b_29_DXMUX_165 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4633, + O => reg_b_29_DXMUX + ); + reg_b_29_DYMUX_166 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4631, + O => reg_b_29_DYMUX + ); + reg_b_29_CLKINV : X_INV + port map ( + I => clk_BUFGP, + O => reg_b_29_CLKINVNOT + ); + reg_b_29_CEINV_167 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0001, + O => reg_b_29_CEINV + ); + reg_c_31_DYMUX_168 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4627, + O => reg_c_31_DYMUX + ); + reg_c_31_CLKINV : X_INV + port map ( + I => clk_BUFGP, + O => reg_c_31_CLKINVNOT + ); + reg_c_31_CEINV_169 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0002, + O => reg_c_31_CEINV + ); + reg_a_1_DXMUX_170 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4637, + O => reg_a_1_DXMUX + ); + reg_a_1_DYMUX_171 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4635, + O => reg_a_1_DYMUX + ); + reg_a_1_CLKINV : X_INV + port map ( + I => clk_BUFGP, + O => reg_a_1_CLKINVNOT + ); + reg_a_1_CEINV_172 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0000, + O => reg_a_1_CEINV + ); + reg_a_3_DXMUX_173 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4641, + O => reg_a_3_DXMUX + ); + reg_a_3_DYMUX_174 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4639, + O => reg_a_3_DYMUX + ); + reg_a_3_CLKINV : X_INV + port map ( + I => clk_BUFGP, + O => reg_a_3_CLKINVNOT + ); + reg_a_3_CEINV_175 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0000, + O => reg_a_3_CEINV + ); + reg_a_5_DXMUX_176 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4645, + O => reg_a_5_DXMUX + ); + reg_a_5_DYMUX_177 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4643, + O => reg_a_5_DYMUX + ); + reg_a_5_CLKINV : X_INV + port map ( + I => clk_BUFGP, + O => reg_a_5_CLKINVNOT + ); + reg_a_5_CEINV_178 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0000, + O => reg_a_5_CEINV + ); + reg_b_1_DXMUX_179 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4637, + O => reg_b_1_DXMUX + ); + reg_b_1_DYMUX_180 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4635, + O => reg_b_1_DYMUX + ); + reg_b_1_CLKINV : X_INV + port map ( + I => clk_BUFGP, + O => reg_b_1_CLKINVNOT + ); + reg_b_1_CEINV_181 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0001, + O => reg_b_1_CEINV + ); + dmuxo_11_XUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_11_F, + O => dmuxo(11) + ); + dmuxo_11_YUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_11_G, + O => N4723 + ); + dmuxo_24_34_SW1 : X_LUT4 + generic map( + INIT => X"FFDD" + ) + port map ( + ADR0 => reg_c(24), + ADR1 => a_4_IBUF, + ADR2 => VCC, + ADR3 => a_7_IBUF, + O => N4719_F + ); + reg_a_7_DXMUX_182 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4649, + O => reg_a_7_DXMUX + ); + reg_a_7_DYMUX_183 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4647, + O => reg_a_7_DYMUX + ); + reg_a_7_CLKINV : X_INV + port map ( + I => clk_BUFGP, + O => reg_a_7_CLKINVNOT + ); + reg_a_7_CEINV_184 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0000, + O => reg_a_7_CEINV + ); + reg_b_3_DXMUX_185 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4641, + O => reg_b_3_DXMUX + ); + reg_b_3_DYMUX_186 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4639, + O => reg_b_3_DYMUX + ); + reg_b_3_CLKINV : X_INV + port map ( + I => clk_BUFGP, + O => reg_b_3_CLKINVNOT + ); + reg_b_3_CEINV_187 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0001, + O => reg_b_3_CEINV + ); + reg_a_9_DXMUX_188 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4653, + O => reg_a_9_DXMUX + ); + reg_a_9_DYMUX_189 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4651, + O => reg_a_9_DYMUX + ); + reg_a_9_CLKINV : X_INV + port map ( + I => clk_BUFGP, + O => reg_a_9_CLKINVNOT + ); + reg_a_9_CEINV_190 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0000, + O => reg_a_9_CEINV + ); + reg_b_5_DXMUX_191 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4645, + O => reg_b_5_DXMUX + ); + reg_b_5_DYMUX_192 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4643, + O => reg_b_5_DYMUX + ); + reg_b_5_CLKINV : X_INV + port map ( + I => clk_BUFGP, + O => reg_b_5_CLKINVNOT + ); + reg_b_5_CEINV_193 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0001, + O => reg_b_5_CEINV + ); + reg_b_7_DXMUX_194 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4649, + O => reg_b_7_DXMUX + ); + reg_b_7_DYMUX_195 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4647, + O => reg_b_7_DYMUX + ); + reg_b_7_CLKINV : X_INV + port map ( + I => clk_BUFGP, + O => reg_b_7_CLKINVNOT + ); + reg_b_7_CEINV_196 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0001, + O => reg_b_7_CEINV + ); + dmuxo_15_XUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_15_F, + O => dmuxo(15) + ); + dmuxo_15_YUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_15_G, + O => N4760 + ); + dmuxo_23_XUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_23_F, + O => dmuxo(23) + ); + dmuxo_23_YUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_23_G, + O => N4790 + ); + dmuxo_31_XUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_31_F, + O => dmuxo(31) + ); + dmuxo_31_YUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_31_G, + O => N4784 + ); + reg_b_9_DXMUX_197 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4653, + O => reg_b_9_DXMUX + ); + reg_b_9_DYMUX_198 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => N4651, + O => reg_b_9_DYMUX + ); + reg_b_9_CLKINV : X_INV + port map ( + I => clk_BUFGP, + O => reg_b_9_CLKINVNOT + ); + reg_b_9_CEINV_199 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0001, + O => reg_b_9_CEINV + ); + I3_N174_YUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => I3_N174_G, + O => I3_N174 + ); + dmuxo_19_XUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_19_F, + O => dmuxo(19) + ); + dmuxo_19_YUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_19_G, + O => N4748 + ); + dmuxo_27_XUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_27_F, + O => dmuxo(27) + ); + dmuxo_27_YUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_27_G, + O => N4766 + ); + dmuxo_7_XUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_7_F, + O => dmuxo(7) + ); + dmuxo_7_YUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_7_G, + O => N4796 + ); + dmuxo_24_XUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_24_F, + O => dmuxo(24) + ); + dmuxo_24_YUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_24_G, + O => N4717 + ); + dmuxo_16_XUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_16_F, + O => dmuxo(16) + ); + dmuxo_16_YUSED : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo_16_G, + O => N4772 + ); + Q_n00021 : X_LUT4 + generic map( + INIT => X"2200" + ) + port map ( + ADR0 => a_5_IBUF, + ADR1 => a_4_IBUF, + ADR2 => VCC, + ADR3 => N2469, + O => Q_n0002_F + ); + reg_c_5 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => d_5_IFF_IFFDMUX, + CE => d_5_IFF_ICEINV, + CLK => d_5_IFF_ICLK1INVNOT, + SET => GND, + RST => d_5_IFF_IFF1_RST, + O => reg_c(5) + ); + d_5_IFF_IFF1_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => d_5_IFF_IFF1_RST + ); + d_6_IFF_IFFDMUX_200 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_6_INBUF, + O => d_6_IFF_IFFDMUX + ); + d_6_IFF_IMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_6_INBUF, + O => N4647 + ); + d_6_IFF_ICLK1INV : X_INV + port map ( + I => clk_BUFGP, + O => d_6_IFF_ICLK1INVNOT + ); + d_6_IFF_ICEINV_201 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0002, + O => d_6_IFF_ICEINV + ); + reg_c_6 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => d_6_IFF_IFFDMUX, + CE => d_6_IFF_ICEINV, + CLK => d_6_IFF_ICLK1INVNOT, + SET => GND, + RST => d_6_IFF_IFF1_RST, + O => reg_c(6) + ); + d_6_IFF_IFF1_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => d_6_IFF_IFF1_RST + ); + reg_c_23 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => d_23_IFF_IFFDMUX, + CE => d_23_IFF_ICEINV, + CLK => d_23_IFF_ICLK1INVNOT, + SET => GND, + RST => d_23_IFF_IFF1_RST, + O => reg_c(23) + ); + d_23_IFF_IFF1_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => d_23_IFF_IFF1_RST + ); + d_15_IFF_IFF1_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => d_15_IFF_IFF1_RST + ); + reg_c_15 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => d_15_IFF_IFFDMUX, + CE => d_15_IFF_ICEINV, + CLK => d_15_IFF_ICLK1INVNOT, + SET => GND, + RST => d_15_IFF_IFF1_RST, + O => reg_c(15) + ); + d_15_IFF_IFFDMUX_202 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_15_INBUF, + O => d_15_IFF_IFFDMUX + ); + d_15_IFF_IMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_15_INBUF, + O => N4601 + ); + d_15_IFF_ICLK1INV : X_INV + port map ( + I => clk_BUFGP, + O => d_15_IFF_ICLK1INVNOT + ); + d_15_IFF_ICEINV_203 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0002, + O => d_15_IFF_ICEINV + ); + d_0_IFF_IFFDMUX_204 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_0_INBUF, + O => d_0_IFF_IFFDMUX + ); + d_0_IFF_IMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_0_INBUF, + O => N4635 + ); + d_0_IFF_ICLK1INV : X_INV + port map ( + I => clk_BUFGP, + O => d_0_IFF_ICLK1INVNOT + ); + d_0_IFF_ICEINV_205 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0002, + O => d_0_IFF_ICEINV + ); + reg_c_0 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => d_0_IFF_IFFDMUX, + CE => d_0_IFF_ICEINV, + CLK => d_0_IFF_ICLK1INVNOT, + SET => GND, + RST => d_0_IFF_IFF1_RST, + O => reg_c(0) + ); + d_0_IFF_IFF1_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => d_0_IFF_IFF1_RST + ); + reg_c_1 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => d_1_IFF_IFFDMUX, + CE => d_1_IFF_ICEINV, + CLK => d_1_IFF_ICLK1INVNOT, + SET => GND, + RST => d_1_IFF_IFF1_RST, + O => reg_c(1) + ); + d_1_IFF_IFF1_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => d_1_IFF_IFF1_RST + ); + d_2_IFF_IFFDMUX_206 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_2_INBUF, + O => d_2_IFF_IFFDMUX + ); + d_2_IFF_IMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_2_INBUF, + O => N4639 + ); + d_2_IFF_ICLK1INV : X_INV + port map ( + I => clk_BUFGP, + O => d_2_IFF_ICLK1INVNOT + ); + d_2_IFF_ICEINV_207 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0002, + O => d_2_IFF_ICEINV + ); + reg_c_2 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => d_2_IFF_IFFDMUX, + CE => d_2_IFF_ICEINV, + CLK => d_2_IFF_ICLK1INVNOT, + SET => GND, + RST => d_2_IFF_IFF1_RST, + O => reg_c(2) + ); + d_2_IFF_IFF1_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => d_2_IFF_IFF1_RST + ); + dmuxo_15_34 : X_LUT4 + generic map( + INIT => X"0131" + ) + port map ( + ADR0 => N4760, + ADR1 => a_6_IBUF, + ADR2 => a_5_IBUF, + ADR3 => N4762, + O => dmuxo_15_F + ); + dmuxo_31_34_SW0 : X_LUT4 + generic map( + INIT => X"F1FD" + ) + port map ( + ADR0 => reg_a(31), + ADR1 => a_4_IBUF, + ADR2 => a_7_IBUF, + ADR3 => reg_b(31), + O => dmuxo_31_G + ); + dmuxo_23_34 : X_LUT4 + generic map( + INIT => X"1013" + ) + port map ( + ADR0 => N4792, + ADR1 => a_6_IBUF, + ADR2 => a_5_IBUF, + ADR3 => N4790, + O => dmuxo_23_F + ); + dmuxo_31_34 : X_LUT4 + generic map( + INIT => X"010D" + ) + port map ( + ADR0 => N4784, + ADR1 => a_5_IBUF, + ADR2 => a_6_IBUF, + ADR3 => N4786, + O => dmuxo_31_F + ); + dmuxo_19_34_SW0 : X_LUT4 + generic map( + INIT => X"ABFB" + ) + port map ( + ADR0 => a_7_IBUF, + ADR1 => reg_a(19), + ADR2 => a_4_IBUF, + ADR3 => reg_b(19), + O => dmuxo_19_G + ); + reg_b_8 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_b_9_DYMUX, + CE => reg_b_9_CEINV, + CLK => reg_b_9_CLKINVNOT, + SET => GND, + RST => reg_b_9_FFY_RST, + O => reg_b(8) + ); + reg_b_9_FFY_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_b_9_FFY_RST + ); + I3_EnableTr_INV1 : X_LUT4 + generic map( + INIT => X"F3F3" + ) + port map ( + ADR0 => VCC, + ADR1 => wen_IBUF, + ADR2 => csn_IBUF, + ADR3 => VCC, + O => I3_N174_G + ); + reg_b_9 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_b_9_DXMUX, + CE => reg_b_9_CEINV, + CLK => reg_b_9_CLKINVNOT, + SET => GND, + RST => reg_b_9_FFX_RST, + O => reg_b(9) + ); + reg_b_9_FFX_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_b_9_FFX_RST + ); + dmuxo_7_34_SW0 : X_LUT4 + generic map( + INIT => X"F4F7" + ) + port map ( + ADR0 => reg_b(7), + ADR1 => a_4_IBUF, + ADR2 => a_7_IBUF, + ADR3 => reg_a(7), + O => dmuxo_7_G + ); + dmuxo_27_34_SW0 : X_LUT4 + generic map( + INIT => X"F1FD" + ) + port map ( + ADR0 => reg_a(27), + ADR1 => a_4_IBUF, + ADR2 => a_7_IBUF, + ADR3 => reg_b(27), + O => dmuxo_27_G + ); + dmuxo_19_34 : X_LUT4 + generic map( + INIT => X"0407" + ) + port map ( + ADR0 => N4750, + ADR1 => a_5_IBUF, + ADR2 => a_6_IBUF, + ADR3 => N4748, + O => dmuxo_19_F + ); + reg_c_13 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => d_13_IFF_IFFDMUX, + CE => d_13_IFF_ICEINV, + CLK => d_13_IFF_ICLK1INVNOT, + SET => GND, + RST => d_13_IFF_IFF1_RST, + O => reg_c(13) + ); + d_13_IFF_IFF1_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => d_13_IFF_IFF1_RST + ); + d_30_IFF_IFF1_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => d_30_IFF_IFF1_RST + ); + reg_c_30 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => d_30_IFF_IFFDMUX, + CE => d_30_IFF_ICEINV, + CLK => d_30_IFF_ICLK1INVNOT, + SET => GND, + RST => d_30_IFF_IFF1_RST, + O => reg_c(30) + ); + d_30_IFF_IFFDMUX_208 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_30_INBUF, + O => d_30_IFF_IFFDMUX + ); + d_30_IFF_IMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_30_INBUF, + O => N4623 + ); + d_30_IFF_ICLK1INV : X_INV + port map ( + I => clk_BUFGP, + O => d_30_IFF_ICLK1INVNOT + ); + d_30_IFF_ICEINV_209 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0002, + O => d_30_IFF_ICEINV + ); + reg_c_24 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => d_24_IFF_IFFDMUX, + CE => d_24_IFF_ICEINV, + CLK => d_24_IFF_ICLK1INVNOT, + SET => GND, + RST => d_24_IFF_IFF1_RST, + O => reg_c(24) + ); + d_24_IFF_IFF1_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => d_24_IFF_IFF1_RST + ); + d_16_IFF_IFFDMUX_210 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_16_INBUF, + O => d_16_IFF_IFFDMUX + ); + d_16_IFF_IMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_16_INBUF, + O => N4605 + ); + d_16_IFF_ICLK1INV : X_INV + port map ( + I => clk_BUFGP, + O => d_16_IFF_ICLK1INVNOT + ); + d_16_IFF_ICEINV_211 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0002, + O => d_16_IFF_ICEINV + ); + reg_c_16 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => d_16_IFF_IFFDMUX, + CE => d_16_IFF_ICEINV, + CLK => d_16_IFF_ICLK1INVNOT, + SET => GND, + RST => d_16_IFF_IFF1_RST, + O => reg_c(16) + ); + d_16_IFF_IFF1_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => d_16_IFF_IFF1_RST + ); + reg_c_22 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => d_22_IFF_IFFDMUX, + CE => d_22_IFF_ICEINV, + CLK => d_22_IFF_ICLK1INVNOT, + SET => GND, + RST => d_22_IFF_IFF1_RST, + O => reg_c(22) + ); + d_22_IFF_IFF1_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => d_22_IFF_IFF1_RST + ); + reg_c_14 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => d_14_IFF_IFFDMUX, + CE => d_14_IFF_ICEINV, + CLK => d_14_IFF_ICLK1INVNOT, + SET => GND, + RST => d_14_IFF_IFF1_RST, + O => reg_c(14) + ); + d_14_IFF_IFF1_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => d_14_IFF_IFF1_RST + ); + d_28_IFF_IFFDMUX_212 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_28_INBUF, + O => d_28_IFF_IFFDMUX + ); + d_28_IFF_IMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_28_INBUF, + O => N4631 + ); + d_28_IFF_ICLK1INV : X_INV + port map ( + I => clk_BUFGP, + O => d_28_IFF_ICLK1INVNOT + ); + d_28_IFF_ICEINV_213 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0002, + O => d_28_IFF_ICEINV + ); + reg_c_28 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => d_28_IFF_IFFDMUX, + CE => d_28_IFF_ICEINV, + CLK => d_28_IFF_ICLK1INVNOT, + SET => GND, + RST => d_28_IFF_IFF1_RST, + O => reg_c(28) + ); + d_28_IFF_IFF1_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => d_28_IFF_IFF1_RST + ); + d_29_IFF_IFF1_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => d_29_IFF_IFF1_RST + ); + reg_c_29 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => d_29_IFF_IFFDMUX, + CE => d_29_IFF_ICEINV, + CLK => d_29_IFF_ICLK1INVNOT, + SET => GND, + RST => d_29_IFF_IFF1_RST, + O => reg_c(29) + ); + d_29_IFF_IFFDMUX_214 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_29_INBUF, + O => d_29_IFF_IFFDMUX + ); + d_29_IFF_IMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_29_INBUF, + O => N4633 + ); + d_29_IFF_ICLK1INV : X_INV + port map ( + I => clk_BUFGP, + O => d_29_IFF_ICLK1INVNOT + ); + d_29_IFF_ICEINV_215 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0002, + O => d_29_IFF_ICEINV + ); + reg_c_12 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => d_12_IFF_IFFDMUX, + CE => d_12_IFF_ICEINV, + CLK => d_12_IFF_ICLK1INVNOT, + SET => GND, + RST => d_12_IFF_IFF1_RST, + O => reg_c(12) + ); + d_12_IFF_IFF1_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => d_12_IFF_IFF1_RST + ); + d_21_IFF_IFF1_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => d_21_IFF_IFF1_RST + ); + reg_c_21 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => d_21_IFF_IFFDMUX, + CE => d_21_IFF_ICEINV, + CLK => d_21_IFF_ICLK1INVNOT, + SET => GND, + RST => d_21_IFF_IFF1_RST, + O => reg_c(21) + ); + d_21_IFF_IFFDMUX_216 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_21_INBUF, + O => d_21_IFF_IFFDMUX + ); + d_21_IFF_IMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_21_INBUF, + O => N4607 + ); + d_21_IFF_ICLK1INV : X_INV + port map ( + I => clk_BUFGP, + O => d_21_IFF_ICLK1INVNOT + ); + d_21_IFF_ICEINV_217 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0002, + O => d_21_IFF_ICEINV + ); + reg_c_9 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => d_9_IFF_IFFDMUX, + CE => d_9_IFF_ICEINV, + CLK => d_9_IFF_ICLK1INVNOT, + SET => GND, + RST => d_9_IFF_IFF1_RST, + O => reg_c(9) + ); + d_9_IFF_IFF1_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => d_9_IFF_IFF1_RST + ); + d_10_IFF_IFF1_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => d_10_IFF_IFF1_RST + ); + reg_c_10 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => d_10_IFF_IFFDMUX, + CE => d_10_IFF_ICEINV, + CLK => d_10_IFF_ICLK1INVNOT, + SET => GND, + RST => d_10_IFF_IFF1_RST, + O => reg_c(10) + ); + d_10_IFF_IFFDMUX_218 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_10_INBUF, + O => d_10_IFF_IFFDMUX + ); + d_10_IFF_IMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_10_INBUF, + O => N4655 + ); + d_10_IFF_ICLK1INV : X_INV + port map ( + I => clk_BUFGP, + O => d_10_IFF_ICLK1INVNOT + ); + d_10_IFF_ICEINV_219 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0002, + O => d_10_IFF_ICEINV + ); + reg_c_3 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => d_3_IFF_IFFDMUX, + CE => d_3_IFF_ICEINV, + CLK => d_3_IFF_ICLK1INVNOT, + SET => GND, + RST => d_3_IFF_IFF1_RST, + O => reg_c(3) + ); + d_3_IFF_IFF1_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => d_3_IFF_IFF1_RST + ); + d_4_IFF_IFFDMUX_220 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_4_INBUF, + O => d_4_IFF_IFFDMUX + ); + d_4_IFF_IMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_4_INBUF, + O => N4643 + ); + d_4_IFF_ICLK1INV : X_INV + port map ( + I => clk_BUFGP, + O => d_4_IFF_ICLK1INVNOT + ); + d_4_IFF_ICEINV_221 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0002, + O => d_4_IFF_ICEINV + ); + reg_c_4 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => d_4_IFF_IFFDMUX, + CE => d_4_IFF_ICEINV, + CLK => d_4_IFF_ICLK1INVNOT, + SET => GND, + RST => d_4_IFF_IFF1_RST, + O => reg_c(4) + ); + d_4_IFF_IFF1_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => d_4_IFF_IFF1_RST + ); + reg_a_24 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_a_25_DYMUX, + CE => reg_a_25_CEINV, + CLK => reg_a_25_CLKINVNOT, + SET => GND, + RST => reg_a_25_FFY_RST, + O => reg_a(24) + ); + reg_a_25_FFY_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_a_25_FFY_RST + ); + reg_a_25 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_a_25_DXMUX, + CE => reg_a_25_CEINV, + CLK => reg_a_25_CLKINVNOT, + SET => GND, + RST => reg_a_25_FFX_RST, + O => reg_a(25) + ); + reg_a_25_FFX_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_a_25_FFX_RST + ); + reg_a_16 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_a_17_DYMUX, + CE => reg_a_17_CEINV, + CLK => reg_a_17_CLKINVNOT, + SET => GND, + RST => reg_a_17_FFY_RST, + O => reg_a(16) + ); + reg_a_17_FFY_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_a_17_FFY_RST + ); + reg_a_17 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_a_17_DXMUX, + CE => reg_a_17_CEINV, + CLK => reg_a_17_CLKINVNOT, + SET => GND, + RST => reg_a_17_FFX_RST, + O => reg_a(17) + ); + reg_a_17_FFX_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_a_17_FFX_RST + ); + dmuxo_30_34 : X_LUT4 + generic map( + INIT => X"1013" + ) + port map ( + ADR0 => N4713, + ADR1 => a_6_IBUF, + ADR2 => a_5_IBUF, + ADR3 => N4711, + O => dmuxo_30_F + ); + dmuxo_22_34 : X_LUT4 + generic map( + INIT => X"0027" + ) + port map ( + ADR0 => a_5_IBUF, + ADR1 => N4810, + ADR2 => N4808, + ADR3 => a_6_IBUF, + O => dmuxo_22_F + ); + reg_a_26 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_a_27_DYMUX, + CE => reg_a_27_CEINV, + CLK => reg_a_27_CLKINVNOT, + SET => GND, + RST => reg_a_27_FFY_RST, + O => reg_a(26) + ); + reg_a_27_FFY_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_a_27_FFY_RST + ); + dmuxo_29_34 : X_LUT4 + generic map( + INIT => X"0415" + ) + port map ( + ADR0 => a_6_IBUF, + ADR1 => a_5_IBUF, + ADR2 => N4816, + ADR3 => N4814, + O => dmuxo_29_F + ); + dmuxo_7_34_SW1 : X_LUT4 + generic map( + INIT => X"FCFF" + ) + port map ( + ADR0 => VCC, + ADR1 => a_4_IBUF, + ADR2 => a_7_IBUF, + ADR3 => reg_c(7), + O => N4798_F + ); + reg_a_10 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_a_11_DYMUX, + CE => reg_a_11_CEINV, + CLK => reg_a_11_CLKINVNOT, + SET => GND, + RST => reg_a_11_FFY_RST, + O => reg_a(10) + ); + reg_a_11_FFY_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_a_11_FFY_RST + ); + reg_a_11 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_a_11_DXMUX, + CE => reg_a_11_CEINV, + CLK => reg_a_11_CLKINVNOT, + SET => GND, + RST => reg_a_11_FFX_RST, + O => reg_a(11) + ); + reg_a_11_FFX_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_a_11_FFX_RST + ); + reg_a_20 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_a_21_DYMUX, + CE => reg_a_21_CEINV, + CLK => reg_a_21_CLKINVNOT, + SET => GND, + RST => reg_a_21_FFY_RST, + O => reg_a(20) + ); + reg_a_21_FFY_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_a_21_FFY_RST + ); + reg_c_26 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => d_26_IFF_IFFDMUX, + CE => d_26_IFF_ICEINV, + CLK => d_26_IFF_ICLK1INVNOT, + SET => GND, + RST => d_26_IFF_IFF1_RST, + O => reg_c(26) + ); + d_26_IFF_IFF1_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => d_26_IFF_IFF1_RST + ); + d_18_IFF_IFF1_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => d_18_IFF_IFF1_RST + ); + reg_c_18 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => d_18_IFF_IFFDMUX, + CE => d_18_IFF_ICEINV, + CLK => d_18_IFF_ICLK1INVNOT, + SET => GND, + RST => d_18_IFF_IFF1_RST, + O => reg_c(18) + ); + d_18_IFF_IFFDMUX_222 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_18_INBUF, + O => d_18_IFF_IFFDMUX + ); + d_18_IFF_IMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_18_INBUF, + O => N4613 + ); + d_18_IFF_ICLK1INV : X_INV + port map ( + I => clk_BUFGP, + O => d_18_IFF_ICLK1INVNOT + ); + d_18_IFF_ICEINV_223 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0002, + O => d_18_IFF_ICEINV + ); + reg_a_4 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_a_5_DYMUX, + CE => reg_a_5_CEINV, + CLK => reg_a_5_CLKINVNOT, + SET => GND, + RST => reg_a_5_FFY_RST, + O => reg_a(4) + ); + reg_a_5_FFY_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_a_5_FFY_RST + ); + reg_a_5 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_a_5_DXMUX, + CE => reg_a_5_CEINV, + CLK => reg_a_5_CLKINVNOT, + SET => GND, + RST => reg_a_5_FFX_RST, + O => reg_a(5) + ); + reg_a_5_FFX_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_a_5_FFX_RST + ); + reg_b_0 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_b_1_DYMUX, + CE => reg_b_1_CEINV, + CLK => reg_b_1_CLKINVNOT, + SET => GND, + RST => reg_b_1_FFY_RST, + O => reg_b(0) + ); + reg_b_1_FFY_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_b_1_FFY_RST + ); + dmuxo_11_34_SW0 : X_LUT4 + generic map( + INIT => X"CDFD" + ) + port map ( + ADR0 => reg_a(11), + ADR1 => a_7_IBUF, + ADR2 => a_4_IBUF, + ADR3 => reg_b(11), + O => dmuxo_11_G + ); + reg_b_1 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_b_1_DXMUX, + CE => reg_b_1_CEINV, + CLK => reg_b_1_CLKINVNOT, + SET => GND, + RST => reg_b_1_FFX_RST, + O => reg_b(1) + ); + reg_b_1_FFX_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_b_1_FFX_RST + ); + dmuxo_11_34 : X_LUT4 + generic map( + INIT => X"1105" + ) + port map ( + ADR0 => a_6_IBUF, + ADR1 => N4725, + ADR2 => N4723, + ADR3 => a_5_IBUF, + O => dmuxo_11_F + ); + reg_a_6 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_a_7_DYMUX, + CE => reg_a_7_CEINV, + CLK => reg_a_7_CLKINVNOT, + SET => GND, + RST => reg_a_7_FFY_RST, + O => reg_a(6) + ); + reg_a_7_FFY_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_a_7_FFY_RST + ); + reg_a_7 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_a_7_DXMUX, + CE => reg_a_7_CEINV, + CLK => reg_a_7_CLKINVNOT, + SET => GND, + RST => reg_a_7_FFX_RST, + O => reg_a(7) + ); + reg_a_7_FFX_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_a_7_FFX_RST + ); + dmuxo_12_19_F : X_LUT4 + generic map( + INIT => X"FFB8" + ) + port map ( + ADR0 => reg_b(12), + ADR1 => a_4_IBUF, + ADR2 => reg_a(12), + ADR3 => N2377, + O => N4846 + ); + dmuxo_12_19_G : X_LUT4 + generic map( + INIT => X"FFEE" + ) + port map ( + ADR0 => N2377, + ADR1 => a_4_IBUF, + ADR2 => VCC, + ADR3 => reg_c(12), + O => N4848 + ); + dmuxo_20_19_G : X_LUT4 + generic map( + INIT => X"FFEE" + ) + port map ( + ADR0 => N2377, + ADR1 => a_4_IBUF, + ADR2 => VCC, + ADR3 => reg_c(20), + O => N4833 + ); + dmuxo_3_19_F : X_LUT4 + generic map( + INIT => X"FFAC" + ) + port map ( + ADR0 => reg_b(3), + ADR1 => reg_a(3), + ADR2 => a_4_IBUF, + ADR3 => N2377, + O => N4836 + ); + reg_c_25 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => d_25_IFF_IFFDMUX, + CE => d_25_IFF_ICEINV, + CLK => d_25_IFF_ICLK1INVNOT, + SET => GND, + RST => d_25_IFF_IFF1_RST, + O => reg_c(25) + ); + d_25_IFF_IFF1_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => d_25_IFF_IFF1_RST + ); + d_17_IFF_IFF1_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => d_17_IFF_IFF1_RST + ); + reg_c_17 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => d_17_IFF_IFFDMUX, + CE => d_17_IFF_ICEINV, + CLK => d_17_IFF_ICLK1INVNOT, + SET => GND, + RST => d_17_IFF_IFF1_RST, + O => reg_c(17) + ); + d_17_IFF_IFFDMUX_224 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_17_INBUF, + O => d_17_IFF_IFFDMUX + ); + d_17_IFF_IMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => d_17_INBUF, + O => N4609 + ); + d_17_IFF_ICLK1INV : X_INV + port map ( + I => clk_BUFGP, + O => d_17_IFF_ICLK1INVNOT + ); + d_17_IFF_ICEINV_225 : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => Q_n0002, + O => d_17_IFF_ICEINV + ); + reg_a_28 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_a_29_DYMUX, + CE => reg_a_29_CEINV, + CLK => reg_a_29_CLKINVNOT, + SET => GND, + RST => reg_a_29_FFY_RST, + O => reg_a(28) + ); + reg_a_29_FFY_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_a_29_FFY_RST + ); + reg_a_29 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_a_29_DXMUX, + CE => reg_a_29_CEINV, + CLK => reg_a_29_CLKINVNOT, + SET => GND, + RST => reg_a_29_FFX_RST, + O => reg_a(29) + ); + reg_a_29_FFX_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_a_29_FFX_RST + ); + reg_b_20 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_b_21_DYMUX, + CE => reg_b_21_CEINV, + CLK => reg_b_21_CLKINVNOT, + SET => GND, + RST => reg_b_21_FFY_RST, + O => reg_b(20) + ); + reg_b_21_FFY_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_b_21_FFY_RST + ); + reg_b_21 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_b_21_DXMUX, + CE => reg_b_21_CEINV, + CLK => reg_b_21_CLKINVNOT, + SET => GND, + RST => reg_b_21_FFX_RST, + O => reg_b(21) + ); + reg_b_21_FFX_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_b_21_FFX_RST + ); + reg_b_12 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_b_13_DYMUX, + CE => reg_b_13_CEINV, + CLK => reg_b_13_CLKINVNOT, + SET => GND, + RST => reg_b_13_FFY_RST, + O => reg_b(12) + ); + reg_b_13_FFY_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_b_13_FFY_RST + ); + reg_b_13 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_b_13_DXMUX, + CE => reg_b_13_CEINV, + CLK => reg_b_13_CLKINVNOT, + SET => GND, + RST => reg_b_13_FFX_RST, + O => reg_b(13) + ); + reg_b_13_FFX_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_b_13_FFX_RST + ); + reg_b_30 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_b_31_DYMUX, + CE => reg_b_31_CEINV, + CLK => reg_b_31_CLKINVNOT, + SET => GND, + RST => reg_b_31_FFY_RST, + O => reg_b(30) + ); + reg_b_31_FFY_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_b_31_FFY_RST + ); + reg_b_31 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_b_31_DXMUX, + CE => reg_b_31_CEINV, + CLK => reg_b_31_CLKINVNOT, + SET => GND, + RST => reg_b_31_FFX_RST, + O => reg_b(31) + ); + reg_b_31_FFX_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_b_31_FFX_RST + ); + reg_b_22 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_b_23_DYMUX, + CE => reg_b_23_CEINV, + CLK => reg_b_23_CLKINVNOT, + SET => GND, + RST => reg_b_23_FFY_RST, + O => reg_b(22) + ); + reg_b_23_FFY_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_b_23_FFY_RST + ); + reg_b_23 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_b_23_DXMUX, + CE => reg_b_23_CEINV, + CLK => reg_b_23_CLKINVNOT, + SET => GND, + RST => reg_b_23_FFX_RST, + O => reg_b(23) + ); + reg_b_23_FFX_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_b_23_FFX_RST + ); + reg_b_14 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_b_15_DYMUX, + CE => reg_b_15_CEINV, + CLK => reg_b_15_CLKINVNOT, + SET => GND, + RST => reg_b_15_FFY_RST, + O => reg_b(14) + ); + reg_b_15_FFY_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_b_15_FFY_RST + ); + reg_b_15 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_b_15_DXMUX, + CE => reg_b_15_CEINV, + CLK => reg_b_15_CLKINVNOT, + SET => GND, + RST => reg_b_15_FFX_RST, + O => reg_b(15) + ); + reg_b_15_FFX_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_b_15_FFX_RST + ); + reg_b_24 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_b_25_DYMUX, + CE => reg_b_25_CEINV, + CLK => reg_b_25_CLKINVNOT, + SET => GND, + RST => reg_b_25_FFY_RST, + O => reg_b(24) + ); + reg_b_25_FFY_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_b_25_FFY_RST + ); + reg_b_25 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_b_25_DXMUX, + CE => reg_b_25_CEINV, + CLK => reg_b_25_CLKINVNOT, + SET => GND, + RST => reg_b_25_FFX_RST, + O => reg_b(25) + ); + reg_b_25_FFX_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_b_25_FFX_RST + ); + reg_b_16 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_b_17_DYMUX, + CE => reg_b_17_CEINV, + CLK => reg_b_17_CLKINVNOT, + SET => GND, + RST => reg_b_17_FFY_RST, + O => reg_b(16) + ); + reg_b_17_FFY_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_b_17_FFY_RST + ); + dmuxo_26_34_SW0 : X_LUT4 + generic map( + INIT => X"DCDF" + ) + port map ( + ADR0 => reg_b(26), + ADR1 => a_7_IBUF, + ADR2 => a_4_IBUF, + ADR3 => reg_a(26), + O => dmuxo_26_G + ); + dmuxo_21_19_G : X_LUT4 + generic map( + INIT => X"FFFA" + ) + port map ( + ADR0 => reg_c(21), + ADR1 => VCC, + ADR2 => a_4_IBUF, + ADR3 => N2377, + O => N4858 + ); + dmuxo_3_19_G : X_LUT4 + generic map( + INIT => X"FFFC" + ) + port map ( + ADR0 => VCC, + ADR1 => reg_c(3), + ADR2 => a_4_IBUF, + ADR3 => N2377, + O => N4838 + ); + dmuxo_14_19_G : X_LUT4 + generic map( + INIT => X"FFFC" + ) + port map ( + ADR0 => VCC, + ADR1 => reg_c(14), + ADR2 => a_4_IBUF, + ADR3 => N2377, + O => N4883 + ); + dmuxo_4_19_G : X_LUT4 + generic map( + INIT => X"FFFC" + ) + port map ( + ADR0 => VCC, + ADR1 => reg_c(4), + ADR2 => a_4_IBUF, + ADR3 => N2377, + O => N4853 + ); + dmuxo_5_19_G : X_LUT4 + generic map( + INIT => X"FFFC" + ) + port map ( + ADR0 => VCC, + ADR1 => a_4_IBUF, + ADR2 => reg_c(5), + ADR3 => N2377, + O => N4863 + ); + dmuxo_6_19_G : X_LUT4 + generic map( + INIT => X"FEFE" + ) + port map ( + ADR0 => N2377, + ADR1 => a_4_IBUF, + ADR2 => reg_c(6), + ADR3 => VCC, + O => N4873 + ); + dmuxo_25_19_G : X_LUT4 + generic map( + INIT => X"FFEE" + ) + port map ( + ADR0 => N2377, + ADR1 => a_4_IBUF, + ADR2 => VCC, + ADR3 => reg_c(25), + O => N4868 + ); + dmuxo_18_19_G : X_LUT4 + generic map( + INIT => X"FFFC" + ) + port map ( + ADR0 => VCC, + ADR1 => reg_c(18), + ADR2 => a_4_IBUF, + ADR3 => N2377, + O => N4843 + ); + dmuxo_9_19_G : X_LUT4 + generic map( + INIT => X"FFFC" + ) + port map ( + ADR0 => VCC, + ADR1 => reg_c(9), + ADR2 => a_4_IBUF, + ADR3 => N2377, + O => N4828 + ); + dmuxo_28_19_G : X_LUT4 + generic map( + INIT => X"FFEE" + ) + port map ( + ADR0 => N2377, + ADR1 => a_4_IBUF, + ADR2 => VCC, + ADR3 => reg_c(28), + O => N4878 + ); + dmuxo_10_19_G : X_LUT4 + generic map( + INIT => X"FFFC" + ) + port map ( + ADR0 => VCC, + ADR1 => reg_c(10), + ADR2 => a_4_IBUF, + ADR3 => N2377, + O => N4823 + ); + reg_a_27 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_a_27_DXMUX, + CE => reg_a_27_CEINV, + CLK => reg_a_27_CLKINVNOT, + SET => GND, + RST => reg_a_27_FFX_RST, + O => reg_a(27) + ); + reg_a_27_FFX_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_a_27_FFX_RST + ); + reg_a_18 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_a_19_DYMUX, + CE => reg_a_19_CEINV, + CLK => reg_a_19_CLKINVNOT, + SET => GND, + RST => reg_a_19_FFY_RST, + O => reg_a(18) + ); + reg_a_19_FFY_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_a_19_FFY_RST + ); + reg_a_19 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_a_19_DXMUX, + CE => reg_a_19_CEINV, + CLK => reg_a_19_CLKINVNOT, + SET => GND, + RST => reg_a_19_FFX_RST, + O => reg_a(19) + ); + reg_a_19_FFX_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_a_19_FFX_RST + ); + reg_b_10 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_b_11_DYMUX, + CE => reg_b_11_CEINV, + CLK => reg_b_11_CLKINVNOT, + SET => GND, + RST => reg_b_11_FFY_RST, + O => reg_b(10) + ); + reg_b_11_FFY_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_b_11_FFY_RST + ); + dmuxo_22_34_SW1 : X_LUT4 + generic map( + INIT => X"FFF3" + ) + port map ( + ADR0 => VCC, + ADR1 => reg_c(22), + ADR2 => a_4_IBUF, + ADR3 => a_7_IBUF, + O => N4804_G + ); + reg_b_11 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_b_11_DXMUX, + CE => reg_b_11_CEINV, + CLK => reg_b_11_CLKINVNOT, + SET => GND, + RST => reg_b_11_FFX_RST, + O => reg_b(11) + ); + reg_b_11_FFX_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_b_11_FFX_RST + ); + dmuxo_2_34_SW1 : X_LUT4 + generic map( + INIT => X"FFF5" + ) + port map ( + ADR0 => reg_c(2), + ADR1 => VCC, + ADR2 => a_4_IBUF, + ADR3 => a_7_IBUF, + O => N4804_F + ); + dmuxo_30_34_SW1 : X_LUT4 + generic map( + INIT => X"FAFF" + ) + port map ( + ADR0 => a_7_IBUF, + ADR1 => VCC, + ADR2 => a_4_IBUF, + ADR3 => reg_c(30), + O => N4768_G + ); + dmuxo_27_34_SW1 : X_LUT4 + generic map( + INIT => X"FBFB" + ) + port map ( + ADR0 => a_7_IBUF, + ADR1 => reg_c(27), + ADR2 => a_4_IBUF, + ADR3 => VCC, + O => N4768_F + ); + reg_a_21 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_a_21_DXMUX, + CE => reg_a_21_CEINV, + CLK => reg_a_21_CLKINVNOT, + SET => GND, + RST => reg_a_21_FFX_RST, + O => reg_a(21) + ); + reg_a_21_FFX_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_a_21_FFX_RST + ); + reg_a_12 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_a_13_DYMUX, + CE => reg_a_13_CEINV, + CLK => reg_a_13_CLKINVNOT, + SET => GND, + RST => reg_a_13_FFY_RST, + O => reg_a(12) + ); + reg_a_13_FFY_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_a_13_FFY_RST + ); + reg_a_13 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_a_13_DXMUX, + CE => reg_a_13_CEINV, + CLK => reg_a_13_CLKINVNOT, + SET => GND, + RST => reg_a_13_FFX_RST, + O => reg_a(13) + ); + reg_a_13_FFX_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_a_13_FFX_RST + ); + reg_a_30 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_a_30_DYMUX, + CE => reg_a_30_CEINV, + CLK => reg_a_30_CLKINVNOT, + SET => GND, + RST => reg_a_30_FFY_RST, + O => reg_a(30) + ); + reg_a_30_FFY_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_a_30_FFY_RST + ); + reg_a_22 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_a_23_DYMUX, + CE => reg_a_23_CEINV, + CLK => reg_a_23_CLKINVNOT, + SET => GND, + RST => reg_a_23_FFY_RST, + O => reg_a(22) + ); + reg_a_23_FFY_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_a_23_FFY_RST + ); + reg_a_23 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_a_23_DXMUX, + CE => reg_a_23_CEINV, + CLK => reg_a_23_CLKINVNOT, + SET => GND, + RST => reg_a_23_FFX_RST, + O => reg_a(23) + ); + reg_a_23_FFX_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_a_23_FFX_RST + ); + reg_a_14 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_a_15_DYMUX, + CE => reg_a_15_CEINV, + CLK => reg_a_15_CLKINVNOT, + SET => GND, + RST => reg_a_15_FFY_RST, + O => reg_a(14) + ); + reg_a_15_FFY_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_a_15_FFY_RST + ); + dmuxo_30_34_SW0 : X_LUT4 + generic map( + INIT => X"CFDD" + ) + port map ( + ADR0 => reg_a(30), + ADR1 => a_7_IBUF, + ADR2 => reg_b(30), + ADR3 => a_4_IBUF, + O => dmuxo_30_G + ); + reg_a_15 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_a_15_DXMUX, + CE => reg_a_15_CEINV, + CLK => reg_a_15_CLKINVNOT, + SET => GND, + RST => reg_a_15_FFX_RST, + O => reg_a(15) + ); + reg_a_15_FFX_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_a_15_FFX_RST + ); + reg_b_17 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_b_17_DXMUX, + CE => reg_b_17_CEINV, + CLK => reg_b_17_CLKINVNOT, + SET => GND, + RST => reg_b_17_FFX_RST, + O => reg_b(17) + ); + reg_b_17_FFX_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_b_17_FFX_RST + ); + dmuxo_26_34 : X_LUT4 + generic map( + INIT => X"0151" + ) + port map ( + ADR0 => a_6_IBUF, + ADR1 => N4730, + ADR2 => a_5_IBUF, + ADR3 => N4732, + O => dmuxo_26_F + ); + reg_b_26 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_b_27_DYMUX, + CE => reg_b_27_CEINV, + CLK => reg_b_27_CLKINVNOT, + SET => GND, + RST => reg_b_27_FFY_RST, + O => reg_b(26) + ); + reg_b_27_FFY_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_b_27_FFY_RST + ); + reg_b_27 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_b_27_DXMUX, + CE => reg_b_27_CEINV, + CLK => reg_b_27_CLKINVNOT, + SET => GND, + RST => reg_b_27_FFX_RST, + O => reg_b(27) + ); + reg_b_27_FFX_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_b_27_FFX_RST + ); + reg_b_18 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_b_19_DYMUX, + CE => reg_b_19_CEINV, + CLK => reg_b_19_CLKINVNOT, + SET => GND, + RST => reg_b_19_FFY_RST, + O => reg_b(18) + ); + reg_b_19_FFY_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_b_19_FFY_RST + ); + dmuxo_26_34_SW1 : X_LUT4 + generic map( + INIT => X"FDFD" + ) + port map ( + ADR0 => reg_c(26), + ADR1 => a_7_IBUF, + ADR2 => a_4_IBUF, + ADR3 => VCC, + O => N4762_G + ); + reg_b_19 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_b_19_DXMUX, + CE => reg_b_19_CEINV, + CLK => reg_b_19_CLKINVNOT, + SET => GND, + RST => reg_b_19_FFX_RST, + O => reg_b(19) + ); + reg_b_19_FFX_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_b_19_FFX_RST + ); + dmuxo_15_34_SW1 : X_LUT4 + generic map( + INIT => X"FCFF" + ) + port map ( + ADR0 => VCC, + ADR1 => a_7_IBUF, + ADR2 => a_4_IBUF, + ADR3 => reg_c(15), + O => N4762_F + ); + dmuxo_2_34_SW0 : X_LUT4 + generic map( + INIT => X"DCDF" + ) + port map ( + ADR0 => reg_b(2), + ADR1 => a_7_IBUF, + ADR2 => a_4_IBUF, + ADR3 => reg_a(2), + O => dmuxo_2_G + ); + dmuxo_2_34 : X_LUT4 + generic map( + INIT => X"1013" + ) + port map ( + ADR0 => N4804, + ADR1 => a_6_IBUF, + ADR2 => a_5_IBUF, + ADR3 => N4802, + O => dmuxo_2_F + ); + reg_b_28 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_b_29_DYMUX, + CE => reg_b_29_CEINV, + CLK => reg_b_29_CLKINVNOT, + SET => GND, + RST => reg_b_29_FFY_RST, + O => reg_b(28) + ); + reg_b_29_FFY_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_b_29_FFY_RST + ); + reg_b_29 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_b_29_DXMUX, + CE => reg_b_29_CEINV, + CLK => reg_b_29_CLKINVNOT, + SET => GND, + RST => reg_b_29_FFX_RST, + O => reg_b(29) + ); + reg_b_29_FFX_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_b_29_FFX_RST + ); + reg_c_31 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_c_31_DYMUX, + CE => reg_c_31_CEINV, + CLK => reg_c_31_CLKINVNOT, + SET => GND, + RST => reg_c_31_FFY_RST, + O => reg_c(31) + ); + reg_c_31_FFY_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_c_31_FFY_RST + ); + reg_a_0 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_a_1_DYMUX, + CE => reg_a_1_CEINV, + CLK => reg_a_1_CLKINVNOT, + SET => GND, + RST => reg_a_1_FFY_RST, + O => reg_a(0) + ); + reg_a_1_FFY_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_a_1_FFY_RST + ); + reg_a_1 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_a_1_DXMUX, + CE => reg_a_1_CEINV, + CLK => reg_a_1_CLKINVNOT, + SET => GND, + RST => reg_a_1_FFX_RST, + O => reg_a(1) + ); + reg_a_1_FFX_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_a_1_FFX_RST + ); + reg_a_2 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_a_3_DYMUX, + CE => reg_a_3_CEINV, + CLK => reg_a_3_CLKINVNOT, + SET => GND, + RST => reg_a_3_FFY_RST, + O => reg_a(2) + ); + reg_a_3_FFY_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_a_3_FFY_RST + ); + reg_a_3 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_a_3_DXMUX, + CE => reg_a_3_CEINV, + CLK => reg_a_3_CLKINVNOT, + SET => GND, + RST => reg_a_3_FFX_RST, + O => reg_a(3) + ); + reg_a_3_FFX_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_a_3_FFX_RST + ); + reg_b_2 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_b_3_DYMUX, + CE => reg_b_3_CEINV, + CLK => reg_b_3_CLKINVNOT, + SET => GND, + RST => reg_b_3_FFY_RST, + O => reg_b(2) + ); + reg_b_3_FFY_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_b_3_FFY_RST + ); + reg_b_3 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_b_3_DXMUX, + CE => reg_b_3_CEINV, + CLK => reg_b_3_CLKINVNOT, + SET => GND, + RST => reg_b_3_FFX_RST, + O => reg_b(3) + ); + reg_b_3_FFX_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_b_3_FFX_RST + ); + reg_a_8 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_a_9_DYMUX, + CE => reg_a_9_CEINV, + CLK => reg_a_9_CLKINVNOT, + SET => GND, + RST => reg_a_9_FFY_RST, + O => reg_a(8) + ); + reg_a_9_FFY_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_a_9_FFY_RST + ); + reg_a_9 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_a_9_DXMUX, + CE => reg_a_9_CEINV, + CLK => reg_a_9_CLKINVNOT, + SET => GND, + RST => reg_a_9_FFX_RST, + O => reg_a(9) + ); + reg_a_9_FFX_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_a_9_FFX_RST + ); + reg_b_4 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_b_5_DYMUX, + CE => reg_b_5_CEINV, + CLK => reg_b_5_CLKINVNOT, + SET => GND, + RST => reg_b_5_FFY_RST, + O => reg_b(4) + ); + reg_b_5_FFY_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_b_5_FFY_RST + ); + reg_b_5 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_b_5_DXMUX, + CE => reg_b_5_CEINV, + CLK => reg_b_5_CLKINVNOT, + SET => GND, + RST => reg_b_5_FFX_RST, + O => reg_b(5) + ); + reg_b_5_FFX_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_b_5_FFX_RST + ); + dmuxo_23_34_SW0 : X_LUT4 + generic map( + INIT => X"DCDF" + ) + port map ( + ADR0 => reg_b(23), + ADR1 => a_7_IBUF, + ADR2 => a_4_IBUF, + ADR3 => reg_a(23), + O => dmuxo_23_G + ); + reg_b_6 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_b_7_DYMUX, + CE => reg_b_7_CEINV, + CLK => reg_b_7_CLKINVNOT, + SET => GND, + RST => reg_b_7_FFY_RST, + O => reg_b(6) + ); + reg_b_7_FFY_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_b_7_FFY_RST + ); + dmuxo_15_34_SW0 : X_LUT4 + generic map( + INIT => X"DCDF" + ) + port map ( + ADR0 => reg_b(15), + ADR1 => a_7_IBUF, + ADR2 => a_4_IBUF, + ADR3 => reg_a(15), + O => dmuxo_15_G + ); + reg_b_7 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => reg_b_7_DXMUX, + CE => reg_b_7_CEINV, + CLK => reg_b_7_CLKINVNOT, + SET => GND, + RST => reg_b_7_FFX_RST, + O => reg_b(7) + ); + reg_b_7_FFX_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => GSR, + O => reg_b_7_FFX_RST + ); + dmuxo_27_34 : X_LUT4 + generic map( + INIT => X"1103" + ) + port map ( + ADR0 => N4768, + ADR1 => a_6_IBUF, + ADR2 => N4766, + ADR3 => a_5_IBUF, + O => dmuxo_27_F + ); + dmuxo_24_34_SW0 : X_LUT4 + generic map( + INIT => X"F1FB" + ) + port map ( + ADR0 => a_4_IBUF, + ADR1 => reg_a(24), + ADR2 => a_7_IBUF, + ADR3 => reg_b(24), + O => dmuxo_24_G + ); + dmuxo_7_34 : X_LUT4 + generic map( + INIT => X"0145" + ) + port map ( + ADR0 => a_6_IBUF, + ADR1 => a_5_IBUF, + ADR2 => N4796, + ADR3 => N4798, + O => dmuxo_7_F + ); + dmuxo_16_34_SW0 : X_LUT4 + generic map( + INIT => X"ABFB" + ) + port map ( + ADR0 => a_7_IBUF, + ADR1 => reg_a(16), + ADR2 => a_4_IBUF, + ADR3 => reg_b(16), + O => dmuxo_16_G + ); + dmuxo_24_34 : X_LUT4 + generic map( + INIT => X"1105" + ) + port map ( + ADR0 => a_6_IBUF, + ADR1 => N4719, + ADR2 => N4717, + ADR3 => a_5_IBUF, + O => dmuxo_24_F + ); + dmuxo_16_34 : X_LUT4 + generic map( + INIT => X"0305" + ) + port map ( + ADR0 => N4772, + ADR1 => N4774, + ADR2 => a_6_IBUF, + ADR3 => a_5_IBUF, + O => dmuxo_16_F + ); + PWR_VCC_0_LOGICAL_ONE : X_ONE + port map ( + O => GLOBAL_LOGIC1 + ); + d_7_OUTPUT_TFF_TMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => I3_N174, + O => d_7_T + ); + d_7_OUTPUT_OFF_OMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo(7), + O => d_7_O + ); + d_8_OUTPUT_TFF_TMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => I3_N174, + O => d_8_T + ); + d_8_OUTPUT_OFF_OMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo(8), + O => d_8_O + ); + d_9_OUTPUT_TFF_TMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => I3_N174, + O => d_9_T + ); + d_9_OUTPUT_OFF_OMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo(9), + O => d_9_O + ); + d_10_OUTPUT_TFF_TMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => I3_N174, + O => d_10_T + ); + d_10_OUTPUT_OFF_OMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo(10), + O => d_10_O + ); + clk_IFF_IMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => clk_INBUF, + O => clk_BUFGP_IBUFG + ); + d_11_OUTPUT_TFF_TMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => I3_N174, + O => d_11_T + ); + d_11_OUTPUT_OFF_OMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo(11), + O => d_11_O + ); + d_20_OUTPUT_TFF_TMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => I3_N174, + O => d_20_T + ); + d_20_OUTPUT_OFF_OMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo(20), + O => d_20_O + ); + d_12_OUTPUT_TFF_TMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => I3_N174, + O => d_12_T + ); + d_12_OUTPUT_OFF_OMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo(12), + O => d_12_O + ); + d_21_OUTPUT_TFF_TMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => I3_N174, + O => d_21_T + ); + d_21_OUTPUT_OFF_OMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo(21), + O => d_21_O + ); + d_13_OUTPUT_TFF_TMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => I3_N174, + O => d_13_T + ); + d_13_OUTPUT_OFF_OMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo(13), + O => d_13_O + ); + d_30_OUTPUT_TFF_TMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => I3_N174, + O => d_30_T + ); + d_30_OUTPUT_OFF_OMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo(30), + O => d_30_O + ); + d_22_OUTPUT_TFF_TMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => I3_N174, + O => d_22_T + ); + d_22_OUTPUT_OFF_OMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo(22), + O => d_22_O + ); + d_14_OUTPUT_TFF_TMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => I3_N174, + O => d_14_T + ); + d_14_OUTPUT_OFF_OMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo(14), + O => d_14_O + ); + d_31_OUTPUT_TFF_TMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => I3_N174, + O => d_31_T + ); + d_31_OUTPUT_OFF_OMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo(31), + O => d_31_O + ); + d_23_OUTPUT_TFF_TMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => I3_N174, + O => d_23_T + ); + d_23_OUTPUT_OFF_OMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo(23), + O => d_23_O + ); + d_15_OUTPUT_TFF_TMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => I3_N174, + O => d_15_T + ); + d_15_OUTPUT_OFF_OMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo(15), + O => d_15_O + ); + d_24_OUTPUT_TFF_TMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => I3_N174, + O => d_24_T + ); + d_24_OUTPUT_OFF_OMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo(24), + O => d_24_O + ); + d_16_OUTPUT_TFF_TMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => I3_N174, + O => d_16_T + ); + d_16_OUTPUT_OFF_OMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo(16), + O => d_16_O + ); + d_25_OUTPUT_TFF_TMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => I3_N174, + O => d_25_T + ); + d_25_OUTPUT_OFF_OMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo(25), + O => d_25_O + ); + d_17_OUTPUT_TFF_TMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => I3_N174, + O => d_17_T + ); + d_17_OUTPUT_OFF_OMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo(17), + O => d_17_O + ); + d_26_OUTPUT_TFF_TMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => I3_N174, + O => d_26_T + ); + d_26_OUTPUT_OFF_OMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo(26), + O => d_26_O + ); + d_18_OUTPUT_TFF_TMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => I3_N174, + O => d_18_T + ); + d_18_OUTPUT_OFF_OMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo(18), + O => d_18_O + ); + d_27_OUTPUT_TFF_TMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => I3_N174, + O => d_27_T + ); + d_27_OUTPUT_OFF_OMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo(27), + O => d_27_O + ); + d_19_OUTPUT_TFF_TMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => I3_N174, + O => d_19_T + ); + d_19_OUTPUT_OFF_OMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo(19), + O => d_19_O + ); + csn_IFF_IMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => csn_INBUF, + O => csn_IBUF + ); + d_28_OUTPUT_TFF_TMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => I3_N174, + O => d_28_T + ); + d_28_OUTPUT_OFF_OMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo(28), + O => d_28_O + ); + d_29_OUTPUT_TFF_TMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => I3_N174, + O => d_29_T + ); + d_29_OUTPUT_OFF_OMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo(29), + O => d_29_O + ); + a_4_IFF_IMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => a_4_INBUF, + O => a_4_IBUF + ); + a_5_IFF_IMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => a_5_INBUF, + O => a_5_IBUF + ); + a_6_IFF_IMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => a_6_INBUF, + O => a_6_IBUF + ); + a_7_IFF_IMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => a_7_INBUF, + O => a_7_IBUF + ); + wen_IFF_IMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => wen_INBUF, + O => wen_IBUF + ); + d_0_OUTPUT_TFF_TMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => I3_N174, + O => d_0_T + ); + d_0_OUTPUT_OFF_OMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo(0), + O => d_0_O + ); + d_1_OUTPUT_TFF_TMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => I3_N174, + O => d_1_T + ); + d_1_OUTPUT_OFF_OMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo(1), + O => d_1_O + ); + d_2_OUTPUT_TFF_TMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => I3_N174, + O => d_2_T + ); + d_2_OUTPUT_OFF_OMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo(2), + O => d_2_O + ); + d_3_OUTPUT_TFF_TMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => I3_N174, + O => d_3_T + ); + d_3_OUTPUT_OFF_OMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo(3), + O => d_3_O + ); + d_4_OUTPUT_TFF_TMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => I3_N174, + O => d_4_T + ); + d_4_OUTPUT_OFF_OMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo(4), + O => d_4_O + ); + d_5_OUTPUT_TFF_TMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => I3_N174, + O => d_5_T + ); + d_5_OUTPUT_OFF_OMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo(5), + O => d_5_O + ); + d_6_OUTPUT_TFF_TMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => I3_N174, + O => d_6_T + ); + d_6_OUTPUT_OFF_OMUX : X_BUF_PP + generic map( + PATHPULSE => 751 ps + ) + port map ( + I => dmuxo(6), + O => d_6_O + ); + NlwBlock_main_top_VCC : X_ONE + port map ( + O => VCC + ); + NlwBlock_main_top_GND : X_ZERO + port map ( + O => GND + ); + NlwBlockROC : X_ROC + generic map (ROC_WIDTH => 100 ns) + port map (O => GSR); + NlwBlockTOC : X_TOC + port map (O => GTS); + +end Structure; + diff --git a/projects/eval_dmux/main_top_translate.vhd b/projects/eval_dmux/main_top_translate.vhd new file mode 100644 index 0000000..92c6be9 --- /dev/null +++ b/projects/eval_dmux/main_top_translate.vhd @@ -0,0 +1,3922 @@ +-- Xilinx Vhdl netlist produced by netgen application (version G.30) +-- Command : -intstyle ise -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim main_top.ngd main_top_translate.vhd +-- Input file : main_top.ngd +-- Output file : main_top_translate.vhd +-- Design name : main_top +-- # of Entities : 1 +-- Xilinx : D:/Xilinx +-- Device : 3s50tq144-5 + +-- This vhdl netlist is a simulation model and uses simulation +-- primitives which may not represent the true implementation of the +-- device, however the netlist is functionally correct and should not +-- be modified. This file cannot be synthesized and should only be used +-- with supported simulation tools. + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library SIMPRIM; +use SIMPRIM.VCOMPONENTS.ALL; +use SIMPRIM.VPACKAGE.ALL; + +entity main_top is + port ( + clk : in STD_LOGIC := 'X'; + csn : in STD_LOGIC := 'X'; + wen : in STD_LOGIC := 'X'; + resn : in STD_LOGIC := 'X'; + a : in STD_LOGIC_VECTOR ( 31 downto 0 ); + d : inout STD_LOGIC_VECTOR ( 31 downto 0 ) + ); +end main_top; + +architecture Structure of main_top is + signal clk_BUFGP : STD_LOGIC; + signal csn_IBUF : STD_LOGIC; + signal wen_IBUF : STD_LOGIC; + signal Q_n0000 : STD_LOGIC; + signal Q_n0001 : STD_LOGIC; + signal Q_n0002 : STD_LOGIC; + signal I3_N174 : STD_LOGIC; + signal a_7_IBUF : STD_LOGIC; + signal a_6_IBUF : STD_LOGIC; + signal a_5_IBUF : STD_LOGIC; + signal a_4_IBUF : STD_LOGIC; + signal N2377 : STD_LOGIC; + signal N2469 : STD_LOGIC; + signal N4609 : STD_LOGIC; + signal N4611 : STD_LOGIC; + signal N4786 : STD_LOGIC; + signal N4768 : STD_LOGIC; + signal N4613 : STD_LOGIC; + signal N4780 : STD_LOGIC; + signal N4615 : STD_LOGIC; + signal N4756 : STD_LOGIC; + signal N4617 : STD_LOGIC; + signal N4619 : STD_LOGIC; + signal N4621 : STD_LOGIC; + signal N4808 : STD_LOGIC; + signal N4736 : STD_LOGIC; + signal N4623 : STD_LOGIC; + signal N4766 : STD_LOGIC; + signal N4625 : STD_LOGIC; + signal N4627 : STD_LOGIC; + signal N4742 : STD_LOGIC; + signal N4814 : STD_LOGIC; + signal N4629 : STD_LOGIC; + signal N4810 : STD_LOGIC; + signal N4711 : STD_LOGIC; + signal N4732 : STD_LOGIC; + signal N4778 : STD_LOGIC; + signal N4738 : STD_LOGIC; + signal N4631 : STD_LOGIC; + signal N4772 : STD_LOGIC; + signal N4633 : STD_LOGIC; + signal N4730 : STD_LOGIC; + signal N4790 : STD_LOGIC; + signal N4784 : STD_LOGIC; + signal N4635 : STD_LOGIC; + signal N4717 : STD_LOGIC; + signal N4705 : STD_LOGIC; + signal N4754 : STD_LOGIC; + signal N4725 : STD_LOGIC; + signal N4796 : STD_LOGIC; + signal N4707 : STD_LOGIC; + signal N4637 : STD_LOGIC; + signal N4723 : STD_LOGIC; + signal N4639 : STD_LOGIC; + signal N4760 : STD_LOGIC; + signal N4641 : STD_LOGIC; + signal N4643 : STD_LOGIC; + signal N4774 : STD_LOGIC; + signal N4645 : STD_LOGIC; + signal N4802 : STD_LOGIC; + signal N4748 : STD_LOGIC; + signal N4816 : STD_LOGIC; + signal N4647 : STD_LOGIC; + signal N4762 : STD_LOGIC; + signal N4649 : STD_LOGIC; + signal N4804 : STD_LOGIC; + signal N4719 : STD_LOGIC; + signal N4651 : STD_LOGIC; + signal N4653 : STD_LOGIC; + signal N4655 : STD_LOGIC; + signal N4792 : STD_LOGIC; + signal N4750 : STD_LOGIC; + signal N4798 : STD_LOGIC; + signal N4713 : STD_LOGIC; + signal N4744 : STD_LOGIC; + signal N4883 : STD_LOGIC; + signal N4881 : STD_LOGIC; + signal N4593 : STD_LOGIC; + signal N4595 : STD_LOGIC; + signal N4597 : STD_LOGIC; + signal N4599 : STD_LOGIC; + signal N4601 : STD_LOGIC; + signal N4603 : STD_LOGIC; + signal N4605 : STD_LOGIC; + signal N4607 : STD_LOGIC; + signal N4821 : STD_LOGIC; + signal N4823 : STD_LOGIC; + signal N4826 : STD_LOGIC; + signal N4828 : STD_LOGIC; + signal N4831 : STD_LOGIC; + signal N4833 : STD_LOGIC; + signal N4836 : STD_LOGIC; + signal N4838 : STD_LOGIC; + signal N4841 : STD_LOGIC; + signal N4843 : STD_LOGIC; + signal N4846 : STD_LOGIC; + signal N4848 : STD_LOGIC; + signal N4851 : STD_LOGIC; + signal N4853 : STD_LOGIC; + signal N4856 : STD_LOGIC; + signal N4858 : STD_LOGIC; + signal N4861 : STD_LOGIC; + signal N4863 : STD_LOGIC; + signal N4866 : STD_LOGIC; + signal N4868 : STD_LOGIC; + signal N4871 : STD_LOGIC; + signal N4873 : STD_LOGIC; + signal N4876 : STD_LOGIC; + signal N4878 : STD_LOGIC; + signal clk_BUFGP_IBUFG : STD_LOGIC; + signal GSR : STD_LOGIC; + signal GTS : STD_LOGIC; + signal d_11_IOBUF_OBUFT_GTS_AND : STD_LOGIC; + signal d_12_IOBUF_OBUFT_GTS_AND : STD_LOGIC; + signal d_13_IOBUF_OBUFT_GTS_AND : STD_LOGIC; + signal d_14_IOBUF_OBUFT_GTS_AND : STD_LOGIC; + signal d_15_IOBUF_OBUFT_GTS_AND : STD_LOGIC; + signal d_20_IOBUF_OBUFT_GTS_AND : STD_LOGIC; + signal d_16_IOBUF_OBUFT_GTS_AND : STD_LOGIC; + signal d_21_IOBUF_OBUFT_GTS_AND : STD_LOGIC; + signal d_17_IOBUF_OBUFT_GTS_AND : STD_LOGIC; + signal d_22_IOBUF_OBUFT_GTS_AND : STD_LOGIC; + signal d_18_IOBUF_OBUFT_GTS_AND : STD_LOGIC; + signal d_23_IOBUF_OBUFT_GTS_AND : STD_LOGIC; + signal d_19_IOBUF_OBUFT_GTS_AND : STD_LOGIC; + signal d_24_IOBUF_OBUFT_GTS_AND : STD_LOGIC; + signal d_25_IOBUF_OBUFT_GTS_AND : STD_LOGIC; + signal d_30_IOBUF_OBUFT_GTS_AND : STD_LOGIC; + signal d_26_IOBUF_OBUFT_GTS_AND : STD_LOGIC; + signal d_31_IOBUF_OBUFT_GTS_AND : STD_LOGIC; + signal d_27_IOBUF_OBUFT_GTS_AND : STD_LOGIC; + signal d_28_IOBUF_OBUFT_GTS_AND : STD_LOGIC; + signal d_29_IOBUF_OBUFT_GTS_AND : STD_LOGIC; + signal d_0_IOBUF_OBUFT_GTS_AND : STD_LOGIC; + signal d_1_IOBUF_OBUFT_GTS_AND : STD_LOGIC; + signal d_2_IOBUF_OBUFT_GTS_AND : STD_LOGIC; + signal d_3_IOBUF_OBUFT_GTS_AND : STD_LOGIC; + signal d_4_IOBUF_OBUFT_GTS_AND : STD_LOGIC; + signal d_5_IOBUF_OBUFT_GTS_AND : STD_LOGIC; + signal d_6_IOBUF_OBUFT_GTS_AND : STD_LOGIC; + signal d_7_IOBUF_OBUFT_GTS_AND : STD_LOGIC; + signal d_8_IOBUF_OBUFT_GTS_AND : STD_LOGIC; + signal d_9_IOBUF_OBUFT_GTS_AND : STD_LOGIC; + signal d_10_IOBUF_OBUFT_GTS_AND : STD_LOGIC; + signal NlwInverterSignal_reg_a_31_C : STD_LOGIC; + signal GND : STD_LOGIC; + signal NlwInverterSignal_reg_b_31_C : STD_LOGIC; + signal NlwInverterSignal_reg_c_31_C : STD_LOGIC; + signal NlwInverterSignal_reg_c_0_C : STD_LOGIC; + signal NlwInverterSignal_reg_c_1_C : STD_LOGIC; + signal NlwInverterSignal_reg_c_2_C : STD_LOGIC; + signal NlwInverterSignal_reg_c_3_C : STD_LOGIC; + signal NlwInverterSignal_reg_c_4_C : STD_LOGIC; + signal NlwInverterSignal_reg_c_5_C : STD_LOGIC; + signal NlwInverterSignal_reg_c_6_C : STD_LOGIC; + signal NlwInverterSignal_reg_c_7_C : STD_LOGIC; + signal NlwInverterSignal_reg_c_8_C : STD_LOGIC; + signal NlwInverterSignal_reg_c_9_C : STD_LOGIC; + signal NlwInverterSignal_reg_c_10_C : STD_LOGIC; + signal NlwInverterSignal_reg_c_11_C : STD_LOGIC; + signal NlwInverterSignal_reg_c_12_C : STD_LOGIC; + signal NlwInverterSignal_reg_c_13_C : STD_LOGIC; + signal NlwInverterSignal_reg_c_14_C : STD_LOGIC; + signal NlwInverterSignal_reg_c_15_C : STD_LOGIC; + signal NlwInverterSignal_reg_c_16_C : STD_LOGIC; + signal NlwInverterSignal_reg_c_17_C : STD_LOGIC; + signal NlwInverterSignal_reg_c_18_C : STD_LOGIC; + signal NlwInverterSignal_reg_c_19_C : STD_LOGIC; + signal NlwInverterSignal_reg_c_20_C : STD_LOGIC; + signal NlwInverterSignal_reg_c_21_C : STD_LOGIC; + signal NlwInverterSignal_reg_c_22_C : STD_LOGIC; + signal NlwInverterSignal_reg_c_23_C : STD_LOGIC; + signal NlwInverterSignal_reg_c_24_C : STD_LOGIC; + signal NlwInverterSignal_reg_c_25_C : STD_LOGIC; + signal NlwInverterSignal_reg_c_26_C : STD_LOGIC; + signal NlwInverterSignal_reg_c_27_C : STD_LOGIC; + signal NlwInverterSignal_reg_c_28_C : STD_LOGIC; + signal NlwInverterSignal_reg_c_29_C : STD_LOGIC; + signal NlwInverterSignal_reg_c_30_C : STD_LOGIC; + signal NlwInverterSignal_reg_b_0_C : STD_LOGIC; + signal NlwInverterSignal_reg_b_1_C : STD_LOGIC; + signal NlwInverterSignal_reg_b_2_C : STD_LOGIC; + signal NlwInverterSignal_reg_b_3_C : STD_LOGIC; + signal NlwInverterSignal_reg_b_4_C : STD_LOGIC; + signal NlwInverterSignal_reg_b_5_C : STD_LOGIC; + signal NlwInverterSignal_reg_b_6_C : STD_LOGIC; + signal NlwInverterSignal_reg_b_7_C : STD_LOGIC; + signal NlwInverterSignal_reg_b_8_C : STD_LOGIC; + signal NlwInverterSignal_reg_b_9_C : STD_LOGIC; + signal NlwInverterSignal_reg_b_10_C : STD_LOGIC; + signal NlwInverterSignal_reg_b_11_C : STD_LOGIC; + signal NlwInverterSignal_reg_b_12_C : STD_LOGIC; + signal NlwInverterSignal_reg_b_13_C : STD_LOGIC; + signal NlwInverterSignal_reg_b_14_C : STD_LOGIC; + signal NlwInverterSignal_reg_b_15_C : STD_LOGIC; + signal NlwInverterSignal_reg_b_16_C : STD_LOGIC; + signal NlwInverterSignal_reg_b_17_C : STD_LOGIC; + signal NlwInverterSignal_reg_b_18_C : STD_LOGIC; + signal NlwInverterSignal_reg_b_19_C : STD_LOGIC; + signal NlwInverterSignal_reg_b_20_C : STD_LOGIC; + signal NlwInverterSignal_reg_b_21_C : STD_LOGIC; + signal NlwInverterSignal_reg_b_22_C : STD_LOGIC; + signal NlwInverterSignal_reg_b_23_C : STD_LOGIC; + signal NlwInverterSignal_reg_b_24_C : STD_LOGIC; + signal NlwInverterSignal_reg_b_25_C : STD_LOGIC; + signal NlwInverterSignal_reg_b_26_C : STD_LOGIC; + signal NlwInverterSignal_reg_b_27_C : STD_LOGIC; + signal NlwInverterSignal_reg_b_28_C : STD_LOGIC; + signal NlwInverterSignal_reg_b_29_C : STD_LOGIC; + signal NlwInverterSignal_reg_b_30_C : STD_LOGIC; + signal NlwInverterSignal_reg_a_0_C : STD_LOGIC; + signal NlwInverterSignal_reg_a_1_C : STD_LOGIC; + signal NlwInverterSignal_reg_a_2_C : STD_LOGIC; + signal NlwInverterSignal_reg_a_3_C : STD_LOGIC; + signal NlwInverterSignal_reg_a_4_C : STD_LOGIC; + signal NlwInverterSignal_reg_a_5_C : STD_LOGIC; + signal NlwInverterSignal_reg_a_6_C : STD_LOGIC; + signal NlwInverterSignal_reg_a_7_C : STD_LOGIC; + signal NlwInverterSignal_reg_a_8_C : STD_LOGIC; + signal NlwInverterSignal_reg_a_9_C : STD_LOGIC; + signal NlwInverterSignal_reg_a_10_C : STD_LOGIC; + signal NlwInverterSignal_reg_a_11_C : STD_LOGIC; + signal NlwInverterSignal_reg_a_12_C : STD_LOGIC; + signal NlwInverterSignal_reg_a_13_C : STD_LOGIC; + signal NlwInverterSignal_reg_a_14_C : STD_LOGIC; + signal NlwInverterSignal_reg_a_15_C : STD_LOGIC; + signal NlwInverterSignal_reg_a_16_C : STD_LOGIC; + signal NlwInverterSignal_reg_a_17_C : STD_LOGIC; + signal NlwInverterSignal_reg_a_18_C : STD_LOGIC; + signal NlwInverterSignal_reg_a_19_C : STD_LOGIC; + signal NlwInverterSignal_reg_a_20_C : STD_LOGIC; + signal NlwInverterSignal_reg_a_21_C : STD_LOGIC; + signal NlwInverterSignal_reg_a_22_C : STD_LOGIC; + signal NlwInverterSignal_reg_a_23_C : STD_LOGIC; + signal NlwInverterSignal_reg_a_24_C : STD_LOGIC; + signal NlwInverterSignal_reg_a_25_C : STD_LOGIC; + signal NlwInverterSignal_reg_a_26_C : STD_LOGIC; + signal NlwInverterSignal_reg_a_27_C : STD_LOGIC; + signal NlwInverterSignal_reg_a_28_C : STD_LOGIC; + signal NlwInverterSignal_reg_a_29_C : STD_LOGIC; + signal NlwInverterSignal_reg_a_30_C : STD_LOGIC; + signal NlwInverterSignal_d_11_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; + signal NlwInverterSignal_d_11_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; + signal NlwInverterSignal_d_12_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; + signal NlwInverterSignal_d_12_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; + signal NlwInverterSignal_d_13_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; + signal NlwInverterSignal_d_13_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; + signal NlwInverterSignal_d_14_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; + signal NlwInverterSignal_d_14_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; + signal NlwInverterSignal_d_15_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; + signal NlwInverterSignal_d_15_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; + signal NlwInverterSignal_d_20_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; + signal NlwInverterSignal_d_20_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; + signal NlwInverterSignal_d_16_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; + signal NlwInverterSignal_d_16_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; + signal NlwInverterSignal_d_21_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; + signal NlwInverterSignal_d_21_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; + signal NlwInverterSignal_d_17_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; + signal NlwInverterSignal_d_17_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; + signal NlwInverterSignal_d_22_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; + signal NlwInverterSignal_d_22_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; + signal NlwInverterSignal_d_18_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; + signal NlwInverterSignal_d_18_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; + signal NlwInverterSignal_d_23_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; + signal NlwInverterSignal_d_23_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; + signal NlwInverterSignal_d_19_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; + signal NlwInverterSignal_d_19_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; + signal NlwInverterSignal_d_24_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; + signal NlwInverterSignal_d_24_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; + signal NlwInverterSignal_d_25_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; + signal NlwInverterSignal_d_25_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; + signal NlwInverterSignal_d_30_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; + signal NlwInverterSignal_d_30_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; + signal NlwInverterSignal_d_26_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; + signal NlwInverterSignal_d_26_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; + signal NlwInverterSignal_d_31_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; + signal NlwInverterSignal_d_31_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; + signal NlwInverterSignal_d_27_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; + signal NlwInverterSignal_d_27_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; + signal NlwInverterSignal_d_28_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; + signal NlwInverterSignal_d_28_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; + signal NlwInverterSignal_d_29_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; + signal NlwInverterSignal_d_29_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; + signal NlwInverterSignal_d_0_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; + signal NlwInverterSignal_d_0_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; + signal NlwInverterSignal_d_1_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; + signal NlwInverterSignal_d_1_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; + signal NlwInverterSignal_d_2_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; + signal NlwInverterSignal_d_2_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; + signal NlwInverterSignal_d_3_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; + signal NlwInverterSignal_d_3_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; + signal NlwInverterSignal_d_4_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; + signal NlwInverterSignal_d_4_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; + signal NlwInverterSignal_d_5_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; + signal NlwInverterSignal_d_5_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; + signal NlwInverterSignal_d_6_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; + signal NlwInverterSignal_d_6_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; + signal NlwInverterSignal_d_7_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; + signal NlwInverterSignal_d_7_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; + signal NlwInverterSignal_d_8_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; + signal NlwInverterSignal_d_8_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; + signal NlwInverterSignal_d_9_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; + signal NlwInverterSignal_d_9_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; + signal NlwInverterSignal_d_10_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; + signal NlwInverterSignal_d_10_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; + signal dmuxo : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal reg_c : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal reg_a : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal reg_b : STD_LOGIC_VECTOR ( 31 downto 0 ); +begin + dmuxo_30_34_SW1 : X_LUT3 + generic map( + INIT => X"FB" + ) + port map ( + ADR0 => a_4_IBUF, + ADR1 => reg_c(30), + ADR2 => a_7_IBUF, + O => N4713 + ); + a_4_IBUF_0 : X_BUF + port map ( + I => a(4), + O => a_4_IBUF + ); + dmuxo_14_19_G : X_LUT3 + generic map( + INIT => X"FE" + ) + port map ( + ADR0 => N2377, + ADR1 => a_4_IBUF, + ADR2 => reg_c(14), + O => N4883 + ); + Q_n00021 : X_LUT3 + generic map( + INIT => X"20" + ) + port map ( + ADR0 => N2469, + ADR1 => a_4_IBUF, + ADR2 => a_5_IBUF, + O => Q_n0002 + ); + Ker23751 : X_LUT2 + generic map( + INIT => X"E" + ) + port map ( + ADR0 => a_6_IBUF, + ADR1 => a_7_IBUF, + O => N2377 + ); + Q_n00001 : X_LUT3 + generic map( + INIT => X"04" + ) + port map ( + ADR0 => a_4_IBUF, + ADR1 => N2469, + ADR2 => a_5_IBUF, + O => Q_n0000 + ); + dmuxo_14_19_F : X_LUT4 + generic map( + INIT => X"FBEA" + ) + port map ( + ADR0 => N2377, + ADR1 => a_4_IBUF, + ADR2 => reg_b(14), + ADR3 => reg_a(14), + O => N4881 + ); + a_5_IBUF_1 : X_BUF + port map ( + I => a(5), + O => a_5_IBUF + ); + dmuxo_0_34_SW1 : X_LUT3 + generic map( + INIT => X"FB" + ) + port map ( + ADR0 => a_4_IBUF, + ADR1 => reg_c(0), + ADR2 => a_7_IBUF, + O => N4756 + ); + a_6_IBUF_2 : X_BUF + port map ( + I => a(6), + O => a_6_IBUF + ); + a_7_IBUF_3 : X_BUF + port map ( + I => a(7), + O => a_7_IBUF + ); + dmuxo_28_19_G : X_LUT3 + generic map( + INIT => X"FE" + ) + port map ( + ADR0 => N2377, + ADR1 => a_4_IBUF, + ADR2 => reg_c(28), + O => N4878 + ); + dmuxo_15_34_SW1 : X_LUT3 + generic map( + INIT => X"FB" + ) + port map ( + ADR0 => a_4_IBUF, + ADR1 => reg_c(15), + ADR2 => a_7_IBUF, + O => N4762 + ); + reg_a_31 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4627, + CE => Q_n0000, + CLK => NlwInverterSignal_reg_a_31_C, + O => reg_a(31), + SET => GND, + RST => GSR + ); + reg_b_31 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4627, + CE => Q_n0001, + CLK => NlwInverterSignal_reg_b_31_C, + O => reg_b(31), + SET => GND, + RST => GSR + ); + reg_c_31 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4627, + CE => Q_n0002, + CLK => NlwInverterSignal_reg_c_31_C, + O => reg_c(31), + SET => GND, + RST => GSR + ); + wen_IBUF_4 : X_BUF + port map ( + I => wen, + O => wen_IBUF + ); + dmuxo_26_34_SW0 : X_LUT4 + generic map( + INIT => X"F2F7" + ) + port map ( + ADR0 => a_4_IBUF, + ADR1 => reg_b(26), + ADR2 => a_7_IBUF, + ADR3 => reg_a(26), + O => N4730 + ); + dmuxo_13_34 : X_LUT4 + generic map( + INIT => X"0213" + ) + port map ( + ADR0 => a_5_IBUF, + ADR1 => a_6_IBUF, + ADR2 => N4707, + ADR3 => N4705, + O => dmuxo(13) + ); + dmuxo_6_19_G : X_LUT3 + generic map( + INIT => X"FE" + ) + port map ( + ADR0 => N2377, + ADR1 => a_4_IBUF, + ADR2 => reg_c(6), + O => N4873 + ); + dmuxo_26_34_SW1 : X_LUT3 + generic map( + INIT => X"FB" + ) + port map ( + ADR0 => a_4_IBUF, + ADR1 => reg_c(26), + ADR2 => a_7_IBUF, + O => N4732 + ); + dmuxo_30_34 : X_LUT4 + generic map( + INIT => X"0213" + ) + port map ( + ADR0 => a_5_IBUF, + ADR1 => a_6_IBUF, + ADR2 => N4713, + ADR3 => N4711, + O => dmuxo(30) + ); + dmuxo_1_34_SW1 : X_LUT3 + generic map( + INIT => X"FB" + ) + port map ( + ADR0 => a_4_IBUF, + ADR1 => reg_c(1), + ADR2 => a_7_IBUF, + O => N4744 + ); + dmuxo_24_34 : X_LUT4 + generic map( + INIT => X"0213" + ) + port map ( + ADR0 => a_5_IBUF, + ADR1 => a_6_IBUF, + ADR2 => N4719, + ADR3 => N4717, + O => dmuxo(24) + ); + dmuxo_16_34_SW1 : X_LUT3 + generic map( + INIT => X"FB" + ) + port map ( + ADR0 => a_4_IBUF, + ADR1 => reg_c(16), + ADR2 => a_7_IBUF, + O => N4774 + ); + csn_IBUF_5 : X_BUF + port map ( + I => csn, + O => csn_IBUF + ); + dmuxo_14_19 : X_MUX2 + port map ( + IA => N4881, + IB => N4883, + SEL => a_5_IBUF, + O => dmuxo(14) + ); + dmuxo_7_34 : X_LUT4 + generic map( + INIT => X"0213" + ) + port map ( + ADR0 => a_5_IBUF, + ADR1 => a_6_IBUF, + ADR2 => N4798, + ADR3 => N4796, + O => dmuxo(7) + ); + dmuxo_27_34_SW0 : X_LUT4 + generic map( + INIT => X"F2F7" + ) + port map ( + ADR0 => a_4_IBUF, + ADR1 => reg_b(27), + ADR2 => a_7_IBUF, + ADR3 => reg_a(27), + O => N4766 + ); + dmuxo_25_19_G : X_LUT3 + generic map( + INIT => X"FE" + ) + port map ( + ADR0 => N2377, + ADR1 => a_4_IBUF, + ADR2 => reg_c(25), + O => N4868 + ); + dmuxo_13_34_SW0 : X_LUT4 + generic map( + INIT => X"F2F7" + ) + port map ( + ADR0 => a_4_IBUF, + ADR1 => reg_b(13), + ADR2 => a_7_IBUF, + ADR3 => reg_a(13), + O => N4705 + ); + dmuxo_27_34_SW1 : X_LUT3 + generic map( + INIT => X"FB" + ) + port map ( + ADR0 => a_4_IBUF, + ADR1 => reg_c(27), + ADR2 => a_7_IBUF, + O => N4768 + ); + dmuxo_29_34 : X_LUT4 + generic map( + INIT => X"0213" + ) + port map ( + ADR0 => a_5_IBUF, + ADR1 => a_6_IBUF, + ADR2 => N4816, + ADR3 => N4814, + O => dmuxo(29) + ); + dmuxo_2_34_SW1 : X_LUT3 + generic map( + INIT => X"FB" + ) + port map ( + ADR0 => a_4_IBUF, + ADR1 => reg_c(2), + ADR2 => a_7_IBUF, + O => N4804 + ); + dmuxo_22_34 : X_LUT4 + generic map( + INIT => X"0213" + ) + port map ( + ADR0 => a_5_IBUF, + ADR1 => a_6_IBUF, + ADR2 => N4810, + ADR3 => N4808, + O => dmuxo(22) + ); + dmuxo_11_34 : X_LUT4 + generic map( + INIT => X"0213" + ) + port map ( + ADR0 => a_5_IBUF, + ADR1 => a_6_IBUF, + ADR2 => N4725, + ADR3 => N4723, + O => dmuxo(11) + ); + dmuxo_22_34_SW1 : X_LUT3 + generic map( + INIT => X"FB" + ) + port map ( + ADR0 => a_4_IBUF, + ADR1 => reg_c(22), + ADR2 => a_7_IBUF, + O => N4810 + ); + reg_c_0 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4635, + CE => Q_n0002, + CLK => NlwInverterSignal_reg_c_0_C, + O => reg_c(0), + SET => GND, + RST => GSR + ); + reg_c_1 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4637, + CE => Q_n0002, + CLK => NlwInverterSignal_reg_c_1_C, + O => reg_c(1), + SET => GND, + RST => GSR + ); + reg_c_2 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4639, + CE => Q_n0002, + CLK => NlwInverterSignal_reg_c_2_C, + O => reg_c(2), + SET => GND, + RST => GSR + ); + reg_c_3 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4641, + CE => Q_n0002, + CLK => NlwInverterSignal_reg_c_3_C, + O => reg_c(3), + SET => GND, + RST => GSR + ); + reg_c_4 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4643, + CE => Q_n0002, + CLK => NlwInverterSignal_reg_c_4_C, + O => reg_c(4), + SET => GND, + RST => GSR + ); + reg_c_5 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4645, + CE => Q_n0002, + CLK => NlwInverterSignal_reg_c_5_C, + O => reg_c(5), + SET => GND, + RST => GSR + ); + reg_c_6 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4647, + CE => Q_n0002, + CLK => NlwInverterSignal_reg_c_6_C, + O => reg_c(6), + SET => GND, + RST => GSR + ); + reg_c_7 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4649, + CE => Q_n0002, + CLK => NlwInverterSignal_reg_c_7_C, + O => reg_c(7), + SET => GND, + RST => GSR + ); + reg_c_8 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4651, + CE => Q_n0002, + CLK => NlwInverterSignal_reg_c_8_C, + O => reg_c(8), + SET => GND, + RST => GSR + ); + reg_c_9 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4653, + CE => Q_n0002, + CLK => NlwInverterSignal_reg_c_9_C, + O => reg_c(9), + SET => GND, + RST => GSR + ); + reg_c_10 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4655, + CE => Q_n0002, + CLK => NlwInverterSignal_reg_c_10_C, + O => reg_c(10), + SET => GND, + RST => GSR + ); + reg_c_11 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4593, + CE => Q_n0002, + CLK => NlwInverterSignal_reg_c_11_C, + O => reg_c(11), + SET => GND, + RST => GSR + ); + reg_c_12 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4595, + CE => Q_n0002, + CLK => NlwInverterSignal_reg_c_12_C, + O => reg_c(12), + SET => GND, + RST => GSR + ); + reg_c_13 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4597, + CE => Q_n0002, + CLK => NlwInverterSignal_reg_c_13_C, + O => reg_c(13), + SET => GND, + RST => GSR + ); + reg_c_14 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4599, + CE => Q_n0002, + CLK => NlwInverterSignal_reg_c_14_C, + O => reg_c(14), + SET => GND, + RST => GSR + ); + reg_c_15 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4601, + CE => Q_n0002, + CLK => NlwInverterSignal_reg_c_15_C, + O => reg_c(15), + SET => GND, + RST => GSR + ); + reg_c_16 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4605, + CE => Q_n0002, + CLK => NlwInverterSignal_reg_c_16_C, + O => reg_c(16), + SET => GND, + RST => GSR + ); + reg_c_17 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4609, + CE => Q_n0002, + CLK => NlwInverterSignal_reg_c_17_C, + O => reg_c(17), + SET => GND, + RST => GSR + ); + reg_c_18 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4613, + CE => Q_n0002, + CLK => NlwInverterSignal_reg_c_18_C, + O => reg_c(18), + SET => GND, + RST => GSR + ); + reg_c_19 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4617, + CE => Q_n0002, + CLK => NlwInverterSignal_reg_c_19_C, + O => reg_c(19), + SET => GND, + RST => GSR + ); + reg_c_20 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4603, + CE => Q_n0002, + CLK => NlwInverterSignal_reg_c_20_C, + O => reg_c(20), + SET => GND, + RST => GSR + ); + reg_c_21 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4607, + CE => Q_n0002, + CLK => NlwInverterSignal_reg_c_21_C, + O => reg_c(21), + SET => GND, + RST => GSR + ); + reg_c_22 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4611, + CE => Q_n0002, + CLK => NlwInverterSignal_reg_c_22_C, + O => reg_c(22), + SET => GND, + RST => GSR + ); + reg_c_23 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4615, + CE => Q_n0002, + CLK => NlwInverterSignal_reg_c_23_C, + O => reg_c(23), + SET => GND, + RST => GSR + ); + reg_c_24 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4619, + CE => Q_n0002, + CLK => NlwInverterSignal_reg_c_24_C, + O => reg_c(24), + SET => GND, + RST => GSR + ); + reg_c_25 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4621, + CE => Q_n0002, + CLK => NlwInverterSignal_reg_c_25_C, + O => reg_c(25), + SET => GND, + RST => GSR + ); + reg_c_26 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4625, + CE => Q_n0002, + CLK => NlwInverterSignal_reg_c_26_C, + O => reg_c(26), + SET => GND, + RST => GSR + ); + reg_c_27 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4629, + CE => Q_n0002, + CLK => NlwInverterSignal_reg_c_27_C, + O => reg_c(27), + SET => GND, + RST => GSR + ); + reg_c_28 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4631, + CE => Q_n0002, + CLK => NlwInverterSignal_reg_c_28_C, + O => reg_c(28), + SET => GND, + RST => GSR + ); + reg_c_29 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4633, + CE => Q_n0002, + CLK => NlwInverterSignal_reg_c_29_C, + O => reg_c(29), + SET => GND, + RST => GSR + ); + reg_c_30 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4623, + CE => Q_n0002, + CLK => NlwInverterSignal_reg_c_30_C, + O => reg_c(30), + SET => GND, + RST => GSR + ); + reg_b_0 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4635, + CE => Q_n0001, + CLK => NlwInverterSignal_reg_b_0_C, + O => reg_b(0), + SET => GND, + RST => GSR + ); + reg_b_1 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4637, + CE => Q_n0001, + CLK => NlwInverterSignal_reg_b_1_C, + O => reg_b(1), + SET => GND, + RST => GSR + ); + reg_b_2 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4639, + CE => Q_n0001, + CLK => NlwInverterSignal_reg_b_2_C, + O => reg_b(2), + SET => GND, + RST => GSR + ); + reg_b_3 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4641, + CE => Q_n0001, + CLK => NlwInverterSignal_reg_b_3_C, + O => reg_b(3), + SET => GND, + RST => GSR + ); + reg_b_4 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4643, + CE => Q_n0001, + CLK => NlwInverterSignal_reg_b_4_C, + O => reg_b(4), + SET => GND, + RST => GSR + ); + reg_b_5 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4645, + CE => Q_n0001, + CLK => NlwInverterSignal_reg_b_5_C, + O => reg_b(5), + SET => GND, + RST => GSR + ); + reg_b_6 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4647, + CE => Q_n0001, + CLK => NlwInverterSignal_reg_b_6_C, + O => reg_b(6), + SET => GND, + RST => GSR + ); + reg_b_7 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4649, + CE => Q_n0001, + CLK => NlwInverterSignal_reg_b_7_C, + O => reg_b(7), + SET => GND, + RST => GSR + ); + reg_b_8 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4651, + CE => Q_n0001, + CLK => NlwInverterSignal_reg_b_8_C, + O => reg_b(8), + SET => GND, + RST => GSR + ); + reg_b_9 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4653, + CE => Q_n0001, + CLK => NlwInverterSignal_reg_b_9_C, + O => reg_b(9), + SET => GND, + RST => GSR + ); + reg_b_10 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4655, + CE => Q_n0001, + CLK => NlwInverterSignal_reg_b_10_C, + O => reg_b(10), + SET => GND, + RST => GSR + ); + reg_b_11 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4593, + CE => Q_n0001, + CLK => NlwInverterSignal_reg_b_11_C, + O => reg_b(11), + SET => GND, + RST => GSR + ); + reg_b_12 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4595, + CE => Q_n0001, + CLK => NlwInverterSignal_reg_b_12_C, + O => reg_b(12), + SET => GND, + RST => GSR + ); + reg_b_13 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4597, + CE => Q_n0001, + CLK => NlwInverterSignal_reg_b_13_C, + O => reg_b(13), + SET => GND, + RST => GSR + ); + reg_b_14 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4599, + CE => Q_n0001, + CLK => NlwInverterSignal_reg_b_14_C, + O => reg_b(14), + SET => GND, + RST => GSR + ); + reg_b_15 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4601, + CE => Q_n0001, + CLK => NlwInverterSignal_reg_b_15_C, + O => reg_b(15), + SET => GND, + RST => GSR + ); + reg_b_16 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4605, + CE => Q_n0001, + CLK => NlwInverterSignal_reg_b_16_C, + O => reg_b(16), + SET => GND, + RST => GSR + ); + reg_b_17 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4609, + CE => Q_n0001, + CLK => NlwInverterSignal_reg_b_17_C, + O => reg_b(17), + SET => GND, + RST => GSR + ); + reg_b_18 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4613, + CE => Q_n0001, + CLK => NlwInverterSignal_reg_b_18_C, + O => reg_b(18), + SET => GND, + RST => GSR + ); + reg_b_19 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4617, + CE => Q_n0001, + CLK => NlwInverterSignal_reg_b_19_C, + O => reg_b(19), + SET => GND, + RST => GSR + ); + reg_b_20 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4603, + CE => Q_n0001, + CLK => NlwInverterSignal_reg_b_20_C, + O => reg_b(20), + SET => GND, + RST => GSR + ); + reg_b_21 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4607, + CE => Q_n0001, + CLK => NlwInverterSignal_reg_b_21_C, + O => reg_b(21), + SET => GND, + RST => GSR + ); + reg_b_22 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4611, + CE => Q_n0001, + CLK => NlwInverterSignal_reg_b_22_C, + O => reg_b(22), + SET => GND, + RST => GSR + ); + reg_b_23 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4615, + CE => Q_n0001, + CLK => NlwInverterSignal_reg_b_23_C, + O => reg_b(23), + SET => GND, + RST => GSR + ); + reg_b_24 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4619, + CE => Q_n0001, + CLK => NlwInverterSignal_reg_b_24_C, + O => reg_b(24), + SET => GND, + RST => GSR + ); + reg_b_25 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4621, + CE => Q_n0001, + CLK => NlwInverterSignal_reg_b_25_C, + O => reg_b(25), + SET => GND, + RST => GSR + ); + reg_b_26 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4625, + CE => Q_n0001, + CLK => NlwInverterSignal_reg_b_26_C, + O => reg_b(26), + SET => GND, + RST => GSR + ); + reg_b_27 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4629, + CE => Q_n0001, + CLK => NlwInverterSignal_reg_b_27_C, + O => reg_b(27), + SET => GND, + RST => GSR + ); + reg_b_28 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4631, + CE => Q_n0001, + CLK => NlwInverterSignal_reg_b_28_C, + O => reg_b(28), + SET => GND, + RST => GSR + ); + reg_b_29 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4633, + CE => Q_n0001, + CLK => NlwInverterSignal_reg_b_29_C, + O => reg_b(29), + SET => GND, + RST => GSR + ); + reg_b_30 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4623, + CE => Q_n0001, + CLK => NlwInverterSignal_reg_b_30_C, + O => reg_b(30), + SET => GND, + RST => GSR + ); + reg_a_0 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4635, + CE => Q_n0000, + CLK => NlwInverterSignal_reg_a_0_C, + O => reg_a(0), + SET => GND, + RST => GSR + ); + reg_a_1 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4637, + CE => Q_n0000, + CLK => NlwInverterSignal_reg_a_1_C, + O => reg_a(1), + SET => GND, + RST => GSR + ); + reg_a_2 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4639, + CE => Q_n0000, + CLK => NlwInverterSignal_reg_a_2_C, + O => reg_a(2), + SET => GND, + RST => GSR + ); + reg_a_3 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4641, + CE => Q_n0000, + CLK => NlwInverterSignal_reg_a_3_C, + O => reg_a(3), + SET => GND, + RST => GSR + ); + reg_a_4 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4643, + CE => Q_n0000, + CLK => NlwInverterSignal_reg_a_4_C, + O => reg_a(4), + SET => GND, + RST => GSR + ); + reg_a_5 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4645, + CE => Q_n0000, + CLK => NlwInverterSignal_reg_a_5_C, + O => reg_a(5), + SET => GND, + RST => GSR + ); + reg_a_6 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4647, + CE => Q_n0000, + CLK => NlwInverterSignal_reg_a_6_C, + O => reg_a(6), + SET => GND, + RST => GSR + ); + reg_a_7 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4649, + CE => Q_n0000, + CLK => NlwInverterSignal_reg_a_7_C, + O => reg_a(7), + SET => GND, + RST => GSR + ); + reg_a_8 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4651, + CE => Q_n0000, + CLK => NlwInverterSignal_reg_a_8_C, + O => reg_a(8), + SET => GND, + RST => GSR + ); + reg_a_9 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4653, + CE => Q_n0000, + CLK => NlwInverterSignal_reg_a_9_C, + O => reg_a(9), + SET => GND, + RST => GSR + ); + reg_a_10 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4655, + CE => Q_n0000, + CLK => NlwInverterSignal_reg_a_10_C, + O => reg_a(10), + SET => GND, + RST => GSR + ); + reg_a_11 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4593, + CE => Q_n0000, + CLK => NlwInverterSignal_reg_a_11_C, + O => reg_a(11), + SET => GND, + RST => GSR + ); + reg_a_12 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4595, + CE => Q_n0000, + CLK => NlwInverterSignal_reg_a_12_C, + O => reg_a(12), + SET => GND, + RST => GSR + ); + reg_a_13 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4597, + CE => Q_n0000, + CLK => NlwInverterSignal_reg_a_13_C, + O => reg_a(13), + SET => GND, + RST => GSR + ); + reg_a_14 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4599, + CE => Q_n0000, + CLK => NlwInverterSignal_reg_a_14_C, + O => reg_a(14), + SET => GND, + RST => GSR + ); + reg_a_15 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4601, + CE => Q_n0000, + CLK => NlwInverterSignal_reg_a_15_C, + O => reg_a(15), + SET => GND, + RST => GSR + ); + reg_a_16 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4605, + CE => Q_n0000, + CLK => NlwInverterSignal_reg_a_16_C, + O => reg_a(16), + SET => GND, + RST => GSR + ); + reg_a_17 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4609, + CE => Q_n0000, + CLK => NlwInverterSignal_reg_a_17_C, + O => reg_a(17), + SET => GND, + RST => GSR + ); + reg_a_18 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4613, + CE => Q_n0000, + CLK => NlwInverterSignal_reg_a_18_C, + O => reg_a(18), + SET => GND, + RST => GSR + ); + reg_a_19 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4617, + CE => Q_n0000, + CLK => NlwInverterSignal_reg_a_19_C, + O => reg_a(19), + SET => GND, + RST => GSR + ); + reg_a_20 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4603, + CE => Q_n0000, + CLK => NlwInverterSignal_reg_a_20_C, + O => reg_a(20), + SET => GND, + RST => GSR + ); + reg_a_21 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4607, + CE => Q_n0000, + CLK => NlwInverterSignal_reg_a_21_C, + O => reg_a(21), + SET => GND, + RST => GSR + ); + reg_a_22 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4611, + CE => Q_n0000, + CLK => NlwInverterSignal_reg_a_22_C, + O => reg_a(22), + SET => GND, + RST => GSR + ); + reg_a_23 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4615, + CE => Q_n0000, + CLK => NlwInverterSignal_reg_a_23_C, + O => reg_a(23), + SET => GND, + RST => GSR + ); + reg_a_24 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4619, + CE => Q_n0000, + CLK => NlwInverterSignal_reg_a_24_C, + O => reg_a(24), + SET => GND, + RST => GSR + ); + reg_a_25 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4621, + CE => Q_n0000, + CLK => NlwInverterSignal_reg_a_25_C, + O => reg_a(25), + SET => GND, + RST => GSR + ); + reg_a_26 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4625, + CE => Q_n0000, + CLK => NlwInverterSignal_reg_a_26_C, + O => reg_a(26), + SET => GND, + RST => GSR + ); + reg_a_27 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4629, + CE => Q_n0000, + CLK => NlwInverterSignal_reg_a_27_C, + O => reg_a(27), + SET => GND, + RST => GSR + ); + reg_a_28 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4631, + CE => Q_n0000, + CLK => NlwInverterSignal_reg_a_28_C, + O => reg_a(28), + SET => GND, + RST => GSR + ); + reg_a_29 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4633, + CE => Q_n0000, + CLK => NlwInverterSignal_reg_a_29_C, + O => reg_a(29), + SET => GND, + RST => GSR + ); + reg_a_30 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N4623, + CE => Q_n0000, + CLK => NlwInverterSignal_reg_a_30_C, + O => reg_a(30), + SET => GND, + RST => GSR + ); + I3_EnableTr_INV1 : X_LUT2 + generic map( + INIT => X"D" + ) + port map ( + ADR0 => wen_IBUF, + ADR1 => csn_IBUF, + O => I3_N174 + ); + Q_n00011 : X_LUT3 + generic map( + INIT => X"20" + ) + port map ( + ADR0 => N2469, + ADR1 => a_5_IBUF, + ADR2 => a_4_IBUF, + O => Q_n0001 + ); + dmuxo_5_19_G : X_LUT3 + generic map( + INIT => X"FE" + ) + port map ( + ADR0 => N2377, + ADR1 => a_4_IBUF, + ADR2 => reg_c(5), + O => N4863 + ); + dmuxo_26_34 : X_LUT4 + generic map( + INIT => X"0213" + ) + port map ( + ADR0 => a_5_IBUF, + ADR1 => a_6_IBUF, + ADR2 => N4732, + ADR3 => N4730, + O => dmuxo(26) + ); + dmuxo_22_34_SW0 : X_LUT4 + generic map( + INIT => X"F2F7" + ) + port map ( + ADR0 => a_4_IBUF, + ADR1 => reg_b(22), + ADR2 => a_7_IBUF, + ADR3 => reg_a(22), + O => N4808 + ); + dmuxo_21_19_G : X_LUT3 + generic map( + INIT => X"FE" + ) + port map ( + ADR0 => N2377, + ADR1 => a_4_IBUF, + ADR2 => reg_c(21), + O => N4858 + ); + dmuxo_17_34 : X_LUT4 + generic map( + INIT => X"0213" + ) + port map ( + ADR0 => a_5_IBUF, + ADR1 => a_6_IBUF, + ADR2 => N4738, + ADR3 => N4736, + O => dmuxo(17) + ); + dmuxo_0_34_SW0 : X_LUT4 + generic map( + INIT => X"F2F7" + ) + port map ( + ADR0 => a_4_IBUF, + ADR1 => reg_b(0), + ADR2 => a_7_IBUF, + ADR3 => reg_a(0), + O => N4754 + ); + dmuxo_29_34_SW0 : X_LUT4 + generic map( + INIT => X"F2F7" + ) + port map ( + ADR0 => a_4_IBUF, + ADR1 => reg_b(29), + ADR2 => a_7_IBUF, + ADR3 => reg_a(29), + O => N4814 + ); + dmuxo_1_34_SW0 : X_LUT4 + generic map( + INIT => X"F2F7" + ) + port map ( + ADR0 => a_4_IBUF, + ADR1 => reg_b(1), + ADR2 => a_7_IBUF, + ADR3 => reg_a(1), + O => N4742 + ); + dmuxo_4_19_G : X_LUT3 + generic map( + INIT => X"FE" + ) + port map ( + ADR0 => N2377, + ADR1 => a_4_IBUF, + ADR2 => reg_c(4), + O => N4853 + ); + dmuxo_8_34_SW1 : X_LUT3 + generic map( + INIT => X"FB" + ) + port map ( + ADR0 => a_4_IBUF, + ADR1 => reg_c(8), + ADR2 => a_7_IBUF, + O => N4780 + ); + dmuxo_31_34_SW0 : X_LUT4 + generic map( + INIT => X"F2F7" + ) + port map ( + ADR0 => a_4_IBUF, + ADR1 => reg_b(31), + ADR2 => a_7_IBUF, + ADR3 => reg_a(31), + O => N4784 + ); + dmuxo_11_34_SW0 : X_LUT4 + generic map( + INIT => X"F2F7" + ) + port map ( + ADR0 => a_4_IBUF, + ADR1 => reg_b(11), + ADR2 => a_7_IBUF, + ADR3 => reg_a(11), + O => N4723 + ); + dmuxo_7_34_SW1 : X_LUT3 + generic map( + INIT => X"FB" + ) + port map ( + ADR0 => a_4_IBUF, + ADR1 => reg_c(7), + ADR2 => a_7_IBUF, + O => N4798 + ); + dmuxo_29_34_SW1 : X_LUT3 + generic map( + INIT => X"FB" + ) + port map ( + ADR0 => a_4_IBUF, + ADR1 => reg_c(29), + ADR2 => a_7_IBUF, + O => N4816 + ); + dmuxo_23_34_SW0 : X_LUT4 + generic map( + INIT => X"F2F7" + ) + port map ( + ADR0 => a_4_IBUF, + ADR1 => reg_b(23), + ADR2 => a_7_IBUF, + ADR3 => reg_a(23), + O => N4790 + ); + dmuxo_19_34_SW1 : X_LUT3 + generic map( + INIT => X"FB" + ) + port map ( + ADR0 => a_4_IBUF, + ADR1 => reg_c(19), + ADR2 => a_7_IBUF, + O => N4750 + ); + dmuxo_12_19_G : X_LUT3 + generic map( + INIT => X"FE" + ) + port map ( + ADR0 => N2377, + ADR1 => a_4_IBUF, + ADR2 => reg_c(12), + O => N4848 + ); + dmuxo_24_34_SW1 : X_LUT3 + generic map( + INIT => X"FB" + ) + port map ( + ADR0 => a_4_IBUF, + ADR1 => reg_c(24), + ADR2 => a_7_IBUF, + O => N4719 + ); + dmuxo_13_34_SW1 : X_LUT3 + generic map( + INIT => X"FB" + ) + port map ( + ADR0 => a_4_IBUF, + ADR1 => reg_c(13), + ADR2 => a_7_IBUF, + O => N4707 + ); + dmuxo_17_34_SW1 : X_LUT3 + generic map( + INIT => X"FB" + ) + port map ( + ADR0 => a_4_IBUF, + ADR1 => reg_c(17), + ADR2 => a_7_IBUF, + O => N4738 + ); + dmuxo_1_34 : X_LUT4 + generic map( + INIT => X"0213" + ) + port map ( + ADR0 => a_5_IBUF, + ADR1 => a_6_IBUF, + ADR2 => N4744, + ADR3 => N4742, + O => dmuxo(1) + ); + dmuxo_18_19_G : X_LUT3 + generic map( + INIT => X"FE" + ) + port map ( + ADR0 => N2377, + ADR1 => a_4_IBUF, + ADR2 => reg_c(18), + O => N4843 + ); + dmuxo_19_34 : X_LUT4 + generic map( + INIT => X"0213" + ) + port map ( + ADR0 => a_5_IBUF, + ADR1 => a_6_IBUF, + ADR2 => N4750, + ADR3 => N4748, + O => dmuxo(19) + ); + dmuxo_0_34 : X_LUT4 + generic map( + INIT => X"0213" + ) + port map ( + ADR0 => a_5_IBUF, + ADR1 => a_6_IBUF, + ADR2 => N4756, + ADR3 => N4754, + O => dmuxo(0) + ); + dmuxo_17_34_SW0 : X_LUT4 + generic map( + INIT => X"F2F7" + ) + port map ( + ADR0 => a_4_IBUF, + ADR1 => reg_b(17), + ADR2 => a_7_IBUF, + ADR3 => reg_a(17), + O => N4736 + ); + dmuxo_31_34_SW1 : X_LUT3 + generic map( + INIT => X"FB" + ) + port map ( + ADR0 => a_4_IBUF, + ADR1 => reg_c(31), + ADR2 => a_7_IBUF, + O => N4786 + ); + dmuxo_3_19_G : X_LUT3 + generic map( + INIT => X"FE" + ) + port map ( + ADR0 => N2377, + ADR1 => a_4_IBUF, + ADR2 => reg_c(3), + O => N4838 + ); + dmuxo_19_34_SW0 : X_LUT4 + generic map( + INIT => X"F2F7" + ) + port map ( + ADR0 => a_4_IBUF, + ADR1 => reg_b(19), + ADR2 => a_7_IBUF, + ADR3 => reg_a(19), + O => N4748 + ); + dmuxo_15_34 : X_LUT4 + generic map( + INIT => X"0213" + ) + port map ( + ADR0 => a_5_IBUF, + ADR1 => a_6_IBUF, + ADR2 => N4762, + ADR3 => N4760, + O => dmuxo(15) + ); + dmuxo_8_34_SW0 : X_LUT4 + generic map( + INIT => X"F2F7" + ) + port map ( + ADR0 => a_4_IBUF, + ADR1 => reg_b(8), + ADR2 => a_7_IBUF, + ADR3 => reg_a(8), + O => N4778 + ); + dmuxo_20_19_G : X_LUT3 + generic map( + INIT => X"FE" + ) + port map ( + ADR0 => N2377, + ADR1 => a_4_IBUF, + ADR2 => reg_c(20), + O => N4833 + ); + dmuxo_27_34 : X_LUT4 + generic map( + INIT => X"0213" + ) + port map ( + ADR0 => a_5_IBUF, + ADR1 => a_6_IBUF, + ADR2 => N4768, + ADR3 => N4766, + O => dmuxo(27) + ); + dmuxo_11_34_SW1 : X_LUT3 + generic map( + INIT => X"FB" + ) + port map ( + ADR0 => a_4_IBUF, + ADR1 => reg_c(11), + ADR2 => a_7_IBUF, + O => N4725 + ); + dmuxo_2_34 : X_LUT4 + generic map( + INIT => X"0213" + ) + port map ( + ADR0 => a_5_IBUF, + ADR1 => a_6_IBUF, + ADR2 => N4804, + ADR3 => N4802, + O => dmuxo(2) + ); + dmuxo_16_34 : X_LUT4 + generic map( + INIT => X"0213" + ) + port map ( + ADR0 => a_5_IBUF, + ADR1 => a_6_IBUF, + ADR2 => N4774, + ADR3 => N4772, + O => dmuxo(16) + ); + dmuxo_2_34_SW0 : X_LUT4 + generic map( + INIT => X"F2F7" + ) + port map ( + ADR0 => a_4_IBUF, + ADR1 => reg_b(2), + ADR2 => a_7_IBUF, + ADR3 => reg_a(2), + O => N4802 + ); + dmuxo_30_34_SW0 : X_LUT4 + generic map( + INIT => X"F2F7" + ) + port map ( + ADR0 => a_4_IBUF, + ADR1 => reg_b(30), + ADR2 => a_7_IBUF, + ADR3 => reg_a(30), + O => N4711 + ); + dmuxo_9_19_G : X_LUT3 + generic map( + INIT => X"FE" + ) + port map ( + ADR0 => N2377, + ADR1 => a_4_IBUF, + ADR2 => reg_c(9), + O => N4828 + ); + dmuxo_7_34_SW0 : X_LUT4 + generic map( + INIT => X"F2F7" + ) + port map ( + ADR0 => a_4_IBUF, + ADR1 => reg_b(7), + ADR2 => a_7_IBUF, + ADR3 => reg_a(7), + O => N4796 + ); + dmuxo_16_34_SW0 : X_LUT4 + generic map( + INIT => X"F2F7" + ) + port map ( + ADR0 => a_4_IBUF, + ADR1 => reg_b(16), + ADR2 => a_7_IBUF, + ADR3 => reg_a(16), + O => N4772 + ); + dmuxo_8_34 : X_LUT4 + generic map( + INIT => X"0213" + ) + port map ( + ADR0 => a_5_IBUF, + ADR1 => a_6_IBUF, + ADR2 => N4780, + ADR3 => N4778, + O => dmuxo(8) + ); + dmuxo_31_34 : X_LUT4 + generic map( + INIT => X"0213" + ) + port map ( + ADR0 => a_5_IBUF, + ADR1 => a_6_IBUF, + ADR2 => N4786, + ADR3 => N4784, + O => dmuxo(31) + ); + dmuxo_23_34 : X_LUT4 + generic map( + INIT => X"0213" + ) + port map ( + ADR0 => a_5_IBUF, + ADR1 => a_6_IBUF, + ADR2 => N4792, + ADR3 => N4790, + O => dmuxo(23) + ); + dmuxo_10_19_G : X_LUT3 + generic map( + INIT => X"FE" + ) + port map ( + ADR0 => N2377, + ADR1 => a_4_IBUF, + ADR2 => reg_c(10), + O => N4823 + ); + dmuxo_15_34_SW0 : X_LUT4 + generic map( + INIT => X"F2F7" + ) + port map ( + ADR0 => a_4_IBUF, + ADR1 => reg_b(15), + ADR2 => a_7_IBUF, + ADR3 => reg_a(15), + O => N4760 + ); + dmuxo_23_34_SW1 : X_LUT3 + generic map( + INIT => X"FB" + ) + port map ( + ADR0 => a_4_IBUF, + ADR1 => reg_c(23), + ADR2 => a_7_IBUF, + O => N4792 + ); + dmuxo_24_34_SW0 : X_LUT4 + generic map( + INIT => X"F2F7" + ) + port map ( + ADR0 => a_4_IBUF, + ADR1 => reg_b(24), + ADR2 => a_7_IBUF, + ADR3 => reg_a(24), + O => N4717 + ); + Ker24671 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => a_6_IBUF, + ADR1 => a_7_IBUF, + ADR2 => csn_IBUF, + ADR3 => wen_IBUF, + O => N2469 + ); + dmuxo_10_19 : X_MUX2 + port map ( + IA => N4821, + IB => N4823, + SEL => a_5_IBUF, + O => dmuxo(10) + ); + dmuxo_10_19_F : X_LUT4 + generic map( + INIT => X"FBEA" + ) + port map ( + ADR0 => N2377, + ADR1 => a_4_IBUF, + ADR2 => reg_b(10), + ADR3 => reg_a(10), + O => N4821 + ); + dmuxo_9_19 : X_MUX2 + port map ( + IA => N4826, + IB => N4828, + SEL => a_5_IBUF, + O => dmuxo(9) + ); + dmuxo_9_19_F : X_LUT4 + generic map( + INIT => X"FBEA" + ) + port map ( + ADR0 => N2377, + ADR1 => a_4_IBUF, + ADR2 => reg_b(9), + ADR3 => reg_a(9), + O => N4826 + ); + dmuxo_20_19 : X_MUX2 + port map ( + IA => N4831, + IB => N4833, + SEL => a_5_IBUF, + O => dmuxo(20) + ); + dmuxo_20_19_F : X_LUT4 + generic map( + INIT => X"FBEA" + ) + port map ( + ADR0 => N2377, + ADR1 => a_4_IBUF, + ADR2 => reg_b(20), + ADR3 => reg_a(20), + O => N4831 + ); + dmuxo_3_19 : X_MUX2 + port map ( + IA => N4836, + IB => N4838, + SEL => a_5_IBUF, + O => dmuxo(3) + ); + dmuxo_3_19_F : X_LUT4 + generic map( + INIT => X"FBEA" + ) + port map ( + ADR0 => N2377, + ADR1 => a_4_IBUF, + ADR2 => reg_b(3), + ADR3 => reg_a(3), + O => N4836 + ); + dmuxo_18_19 : X_MUX2 + port map ( + IA => N4841, + IB => N4843, + SEL => a_5_IBUF, + O => dmuxo(18) + ); + dmuxo_18_19_F : X_LUT4 + generic map( + INIT => X"FBEA" + ) + port map ( + ADR0 => N2377, + ADR1 => a_4_IBUF, + ADR2 => reg_b(18), + ADR3 => reg_a(18), + O => N4841 + ); + dmuxo_12_19 : X_MUX2 + port map ( + IA => N4846, + IB => N4848, + SEL => a_5_IBUF, + O => dmuxo(12) + ); + dmuxo_12_19_F : X_LUT4 + generic map( + INIT => X"FBEA" + ) + port map ( + ADR0 => N2377, + ADR1 => a_4_IBUF, + ADR2 => reg_b(12), + ADR3 => reg_a(12), + O => N4846 + ); + dmuxo_4_19 : X_MUX2 + port map ( + IA => N4851, + IB => N4853, + SEL => a_5_IBUF, + O => dmuxo(4) + ); + dmuxo_4_19_F : X_LUT4 + generic map( + INIT => X"FBEA" + ) + port map ( + ADR0 => N2377, + ADR1 => a_4_IBUF, + ADR2 => reg_b(4), + ADR3 => reg_a(4), + O => N4851 + ); + dmuxo_21_19 : X_MUX2 + port map ( + IA => N4856, + IB => N4858, + SEL => a_5_IBUF, + O => dmuxo(21) + ); + dmuxo_21_19_F : X_LUT4 + generic map( + INIT => X"FBEA" + ) + port map ( + ADR0 => N2377, + ADR1 => a_4_IBUF, + ADR2 => reg_b(21), + ADR3 => reg_a(21), + O => N4856 + ); + dmuxo_5_19 : X_MUX2 + port map ( + IA => N4861, + IB => N4863, + SEL => a_5_IBUF, + O => dmuxo(5) + ); + dmuxo_5_19_F : X_LUT4 + generic map( + INIT => X"FBEA" + ) + port map ( + ADR0 => N2377, + ADR1 => a_4_IBUF, + ADR2 => reg_b(5), + ADR3 => reg_a(5), + O => N4861 + ); + dmuxo_25_19 : X_MUX2 + port map ( + IA => N4866, + IB => N4868, + SEL => a_5_IBUF, + O => dmuxo(25) + ); + dmuxo_25_19_F : X_LUT4 + generic map( + INIT => X"FBEA" + ) + port map ( + ADR0 => N2377, + ADR1 => a_4_IBUF, + ADR2 => reg_b(25), + ADR3 => reg_a(25), + O => N4866 + ); + dmuxo_6_19 : X_MUX2 + port map ( + IA => N4871, + IB => N4873, + SEL => a_5_IBUF, + O => dmuxo(6) + ); + dmuxo_6_19_F : X_LUT4 + generic map( + INIT => X"FBEA" + ) + port map ( + ADR0 => N2377, + ADR1 => a_4_IBUF, + ADR2 => reg_b(6), + ADR3 => reg_a(6), + O => N4871 + ); + dmuxo_28_19 : X_MUX2 + port map ( + IA => N4876, + IB => N4878, + SEL => a_5_IBUF, + O => dmuxo(28) + ); + dmuxo_28_19_F : X_LUT4 + generic map( + INIT => X"FBEA" + ) + port map ( + ADR0 => N2377, + ADR1 => a_4_IBUF, + ADR2 => reg_b(28), + ADR3 => reg_a(28), + O => N4876 + ); + d_30_IOBUF_OBUFT : X_TRI + port map ( + CTL => d_30_IOBUF_OBUFT_GTS_AND, + I => dmuxo(30), + O => d(30) + ); + d_30_IOBUF_IBUF : X_BUF + port map ( + I => d(30), + O => N4623 + ); + d_29_IOBUF_OBUFT : X_TRI + port map ( + CTL => d_29_IOBUF_OBUFT_GTS_AND, + I => dmuxo(29), + O => d(29) + ); + d_29_IOBUF_IBUF : X_BUF + port map ( + I => d(29), + O => N4633 + ); + d_28_IOBUF_OBUFT : X_TRI + port map ( + CTL => d_28_IOBUF_OBUFT_GTS_AND, + I => dmuxo(28), + O => d(28) + ); + d_28_IOBUF_IBUF : X_BUF + port map ( + I => d(28), + O => N4631 + ); + d_22_IOBUF_OBUFT : X_TRI + port map ( + CTL => d_22_IOBUF_OBUFT_GTS_AND, + I => dmuxo(22), + O => d(22) + ); + d_22_IOBUF_IBUF : X_BUF + port map ( + I => d(22), + O => N4611 + ); + d_21_IOBUF_OBUFT : X_TRI + port map ( + CTL => d_21_IOBUF_OBUFT_GTS_AND, + I => dmuxo(21), + O => d(21) + ); + d_21_IOBUF_IBUF : X_BUF + port map ( + I => d(21), + O => N4607 + ); + d_24_IOBUF_OBUFT : X_TRI + port map ( + CTL => d_24_IOBUF_OBUFT_GTS_AND, + I => dmuxo(24), + O => d(24) + ); + d_24_IOBUF_IBUF : X_BUF + port map ( + I => d(24), + O => N4619 + ); + d_27_IOBUF_OBUFT : X_TRI + port map ( + CTL => d_27_IOBUF_OBUFT_GTS_AND, + I => dmuxo(27), + O => d(27) + ); + d_27_IOBUF_IBUF : X_BUF + port map ( + I => d(27), + O => N4629 + ); + d_26_IOBUF_OBUFT : X_TRI + port map ( + CTL => d_26_IOBUF_OBUFT_GTS_AND, + I => dmuxo(26), + O => d(26) + ); + d_26_IOBUF_IBUF : X_BUF + port map ( + I => d(26), + O => N4625 + ); + d_25_IOBUF_OBUFT : X_TRI + port map ( + CTL => d_25_IOBUF_OBUFT_GTS_AND, + I => dmuxo(25), + O => d(25) + ); + d_25_IOBUF_IBUF : X_BUF + port map ( + I => d(25), + O => N4621 + ); + d_19_IOBUF_OBUFT : X_TRI + port map ( + CTL => d_19_IOBUF_OBUFT_GTS_AND, + I => dmuxo(19), + O => d(19) + ); + d_19_IOBUF_IBUF : X_BUF + port map ( + I => d(19), + O => N4617 + ); + d_31_IOBUF_OBUFT : X_TRI + port map ( + CTL => d_31_IOBUF_OBUFT_GTS_AND, + I => dmuxo(31), + O => d(31) + ); + d_31_IOBUF_IBUF : X_BUF + port map ( + I => d(31), + O => N4627 + ); + clk_BUFGP_BUFG : X_CKBUF + port map ( + I => clk_BUFGP_IBUFG, + O => clk_BUFGP + ); + clk_BUFGP_IBUFG_9 : X_CKBUF + port map ( + I => clk, + O => clk_BUFGP_IBUFG + ); + d_23_IOBUF_OBUFT : X_TRI + port map ( + CTL => d_23_IOBUF_OBUFT_GTS_AND, + I => dmuxo(23), + O => d(23) + ); + d_23_IOBUF_IBUF : X_BUF + port map ( + I => d(23), + O => N4615 + ); + d_20_IOBUF_OBUFT : X_TRI + port map ( + CTL => d_20_IOBUF_OBUFT_GTS_AND, + I => dmuxo(20), + O => d(20) + ); + d_20_IOBUF_IBUF : X_BUF + port map ( + I => d(20), + O => N4603 + ); + d_0_IOBUF_OBUFT : X_TRI + port map ( + CTL => d_0_IOBUF_OBUFT_GTS_AND, + I => dmuxo(0), + O => d(0) + ); + d_0_IOBUF_IBUF : X_BUF + port map ( + I => d(0), + O => N4635 + ); + d_1_IOBUF_OBUFT : X_TRI + port map ( + CTL => d_1_IOBUF_OBUFT_GTS_AND, + I => dmuxo(1), + O => d(1) + ); + d_1_IOBUF_IBUF : X_BUF + port map ( + I => d(1), + O => N4637 + ); + d_2_IOBUF_OBUFT : X_TRI + port map ( + CTL => d_2_IOBUF_OBUFT_GTS_AND, + I => dmuxo(2), + O => d(2) + ); + d_2_IOBUF_IBUF : X_BUF + port map ( + I => d(2), + O => N4639 + ); + d_3_IOBUF_OBUFT : X_TRI + port map ( + CTL => d_3_IOBUF_OBUFT_GTS_AND, + I => dmuxo(3), + O => d(3) + ); + d_3_IOBUF_IBUF : X_BUF + port map ( + I => d(3), + O => N4641 + ); + d_4_IOBUF_OBUFT : X_TRI + port map ( + CTL => d_4_IOBUF_OBUFT_GTS_AND, + I => dmuxo(4), + O => d(4) + ); + d_4_IOBUF_IBUF : X_BUF + port map ( + I => d(4), + O => N4643 + ); + d_5_IOBUF_OBUFT : X_TRI + port map ( + CTL => d_5_IOBUF_OBUFT_GTS_AND, + I => dmuxo(5), + O => d(5) + ); + d_5_IOBUF_IBUF : X_BUF + port map ( + I => d(5), + O => N4645 + ); + d_6_IOBUF_OBUFT : X_TRI + port map ( + CTL => d_6_IOBUF_OBUFT_GTS_AND, + I => dmuxo(6), + O => d(6) + ); + d_6_IOBUF_IBUF : X_BUF + port map ( + I => d(6), + O => N4647 + ); + d_7_IOBUF_OBUFT : X_TRI + port map ( + CTL => d_7_IOBUF_OBUFT_GTS_AND, + I => dmuxo(7), + O => d(7) + ); + d_7_IOBUF_IBUF : X_BUF + port map ( + I => d(7), + O => N4649 + ); + d_8_IOBUF_OBUFT : X_TRI + port map ( + CTL => d_8_IOBUF_OBUFT_GTS_AND, + I => dmuxo(8), + O => d(8) + ); + d_8_IOBUF_IBUF : X_BUF + port map ( + I => d(8), + O => N4651 + ); + d_9_IOBUF_OBUFT : X_TRI + port map ( + CTL => d_9_IOBUF_OBUFT_GTS_AND, + I => dmuxo(9), + O => d(9) + ); + d_9_IOBUF_IBUF : X_BUF + port map ( + I => d(9), + O => N4653 + ); + d_10_IOBUF_OBUFT : X_TRI + port map ( + CTL => d_10_IOBUF_OBUFT_GTS_AND, + I => dmuxo(10), + O => d(10) + ); + d_10_IOBUF_IBUF : X_BUF + port map ( + I => d(10), + O => N4655 + ); + d_11_IOBUF_OBUFT : X_TRI + port map ( + CTL => d_11_IOBUF_OBUFT_GTS_AND, + I => dmuxo(11), + O => d(11) + ); + d_11_IOBUF_IBUF : X_BUF + port map ( + I => d(11), + O => N4593 + ); + d_12_IOBUF_OBUFT : X_TRI + port map ( + CTL => d_12_IOBUF_OBUFT_GTS_AND, + I => dmuxo(12), + O => d(12) + ); + d_12_IOBUF_IBUF : X_BUF + port map ( + I => d(12), + O => N4595 + ); + d_13_IOBUF_OBUFT : X_TRI + port map ( + CTL => d_13_IOBUF_OBUFT_GTS_AND, + I => dmuxo(13), + O => d(13) + ); + d_13_IOBUF_IBUF : X_BUF + port map ( + I => d(13), + O => N4597 + ); + d_14_IOBUF_OBUFT : X_TRI + port map ( + CTL => d_14_IOBUF_OBUFT_GTS_AND, + I => dmuxo(14), + O => d(14) + ); + d_14_IOBUF_IBUF : X_BUF + port map ( + I => d(14), + O => N4599 + ); + d_15_IOBUF_OBUFT : X_TRI + port map ( + CTL => d_15_IOBUF_OBUFT_GTS_AND, + I => dmuxo(15), + O => d(15) + ); + d_15_IOBUF_IBUF : X_BUF + port map ( + I => d(15), + O => N4601 + ); + d_16_IOBUF_OBUFT : X_TRI + port map ( + CTL => d_16_IOBUF_OBUFT_GTS_AND, + I => dmuxo(16), + O => d(16) + ); + d_16_IOBUF_IBUF : X_BUF + port map ( + I => d(16), + O => N4605 + ); + d_17_IOBUF_OBUFT : X_TRI + port map ( + CTL => d_17_IOBUF_OBUFT_GTS_AND, + I => dmuxo(17), + O => d(17) + ); + d_17_IOBUF_IBUF : X_BUF + port map ( + I => d(17), + O => N4609 + ); + d_18_IOBUF_OBUFT : X_TRI + port map ( + CTL => d_18_IOBUF_OBUFT_GTS_AND, + I => dmuxo(18), + O => d(18) + ); + d_18_IOBUF_IBUF : X_BUF + port map ( + I => d(18), + O => N4613 + ); + d_11_IOBUF_OBUFT_GTS_AND_10 : X_AND2 + port map ( + I0 => NlwInverterSignal_d_11_IOBUF_OBUFT_GTS_AND_IN0, + I1 => NlwInverterSignal_d_11_IOBUF_OBUFT_GTS_AND_IN1, + O => d_11_IOBUF_OBUFT_GTS_AND + ); + d_12_IOBUF_OBUFT_GTS_AND_11 : X_AND2 + port map ( + I0 => NlwInverterSignal_d_12_IOBUF_OBUFT_GTS_AND_IN0, + I1 => NlwInverterSignal_d_12_IOBUF_OBUFT_GTS_AND_IN1, + O => d_12_IOBUF_OBUFT_GTS_AND + ); + d_13_IOBUF_OBUFT_GTS_AND_12 : X_AND2 + port map ( + I0 => NlwInverterSignal_d_13_IOBUF_OBUFT_GTS_AND_IN0, + I1 => NlwInverterSignal_d_13_IOBUF_OBUFT_GTS_AND_IN1, + O => d_13_IOBUF_OBUFT_GTS_AND + ); + d_14_IOBUF_OBUFT_GTS_AND_13 : X_AND2 + port map ( + I0 => NlwInverterSignal_d_14_IOBUF_OBUFT_GTS_AND_IN0, + I1 => NlwInverterSignal_d_14_IOBUF_OBUFT_GTS_AND_IN1, + O => d_14_IOBUF_OBUFT_GTS_AND + ); + d_15_IOBUF_OBUFT_GTS_AND_14 : X_AND2 + port map ( + I0 => NlwInverterSignal_d_15_IOBUF_OBUFT_GTS_AND_IN0, + I1 => NlwInverterSignal_d_15_IOBUF_OBUFT_GTS_AND_IN1, + O => d_15_IOBUF_OBUFT_GTS_AND + ); + d_20_IOBUF_OBUFT_GTS_AND_15 : X_AND2 + port map ( + I0 => NlwInverterSignal_d_20_IOBUF_OBUFT_GTS_AND_IN0, + I1 => NlwInverterSignal_d_20_IOBUF_OBUFT_GTS_AND_IN1, + O => d_20_IOBUF_OBUFT_GTS_AND + ); + d_16_IOBUF_OBUFT_GTS_AND_16 : X_AND2 + port map ( + I0 => NlwInverterSignal_d_16_IOBUF_OBUFT_GTS_AND_IN0, + I1 => NlwInverterSignal_d_16_IOBUF_OBUFT_GTS_AND_IN1, + O => d_16_IOBUF_OBUFT_GTS_AND + ); + d_21_IOBUF_OBUFT_GTS_AND_17 : X_AND2 + port map ( + I0 => NlwInverterSignal_d_21_IOBUF_OBUFT_GTS_AND_IN0, + I1 => NlwInverterSignal_d_21_IOBUF_OBUFT_GTS_AND_IN1, + O => d_21_IOBUF_OBUFT_GTS_AND + ); + d_17_IOBUF_OBUFT_GTS_AND_18 : X_AND2 + port map ( + I0 => NlwInverterSignal_d_17_IOBUF_OBUFT_GTS_AND_IN0, + I1 => NlwInverterSignal_d_17_IOBUF_OBUFT_GTS_AND_IN1, + O => d_17_IOBUF_OBUFT_GTS_AND + ); + d_22_IOBUF_OBUFT_GTS_AND_19 : X_AND2 + port map ( + I0 => NlwInverterSignal_d_22_IOBUF_OBUFT_GTS_AND_IN0, + I1 => NlwInverterSignal_d_22_IOBUF_OBUFT_GTS_AND_IN1, + O => d_22_IOBUF_OBUFT_GTS_AND + ); + d_18_IOBUF_OBUFT_GTS_AND_20 : X_AND2 + port map ( + I0 => NlwInverterSignal_d_18_IOBUF_OBUFT_GTS_AND_IN0, + I1 => NlwInverterSignal_d_18_IOBUF_OBUFT_GTS_AND_IN1, + O => d_18_IOBUF_OBUFT_GTS_AND + ); + d_23_IOBUF_OBUFT_GTS_AND_21 : X_AND2 + port map ( + I0 => NlwInverterSignal_d_23_IOBUF_OBUFT_GTS_AND_IN0, + I1 => NlwInverterSignal_d_23_IOBUF_OBUFT_GTS_AND_IN1, + O => d_23_IOBUF_OBUFT_GTS_AND + ); + d_19_IOBUF_OBUFT_GTS_AND_22 : X_AND2 + port map ( + I0 => NlwInverterSignal_d_19_IOBUF_OBUFT_GTS_AND_IN0, + I1 => NlwInverterSignal_d_19_IOBUF_OBUFT_GTS_AND_IN1, + O => d_19_IOBUF_OBUFT_GTS_AND + ); + d_24_IOBUF_OBUFT_GTS_AND_23 : X_AND2 + port map ( + I0 => NlwInverterSignal_d_24_IOBUF_OBUFT_GTS_AND_IN0, + I1 => NlwInverterSignal_d_24_IOBUF_OBUFT_GTS_AND_IN1, + O => d_24_IOBUF_OBUFT_GTS_AND + ); + d_25_IOBUF_OBUFT_GTS_AND_24 : X_AND2 + port map ( + I0 => NlwInverterSignal_d_25_IOBUF_OBUFT_GTS_AND_IN0, + I1 => NlwInverterSignal_d_25_IOBUF_OBUFT_GTS_AND_IN1, + O => d_25_IOBUF_OBUFT_GTS_AND + ); + d_30_IOBUF_OBUFT_GTS_AND_25 : X_AND2 + port map ( + I0 => NlwInverterSignal_d_30_IOBUF_OBUFT_GTS_AND_IN0, + I1 => NlwInverterSignal_d_30_IOBUF_OBUFT_GTS_AND_IN1, + O => d_30_IOBUF_OBUFT_GTS_AND + ); + d_26_IOBUF_OBUFT_GTS_AND_26 : X_AND2 + port map ( + I0 => NlwInverterSignal_d_26_IOBUF_OBUFT_GTS_AND_IN0, + I1 => NlwInverterSignal_d_26_IOBUF_OBUFT_GTS_AND_IN1, + O => d_26_IOBUF_OBUFT_GTS_AND + ); + d_31_IOBUF_OBUFT_GTS_AND_27 : X_AND2 + port map ( + I0 => NlwInverterSignal_d_31_IOBUF_OBUFT_GTS_AND_IN0, + I1 => NlwInverterSignal_d_31_IOBUF_OBUFT_GTS_AND_IN1, + O => d_31_IOBUF_OBUFT_GTS_AND + ); + d_27_IOBUF_OBUFT_GTS_AND_28 : X_AND2 + port map ( + I0 => NlwInverterSignal_d_27_IOBUF_OBUFT_GTS_AND_IN0, + I1 => NlwInverterSignal_d_27_IOBUF_OBUFT_GTS_AND_IN1, + O => d_27_IOBUF_OBUFT_GTS_AND + ); + d_28_IOBUF_OBUFT_GTS_AND_29 : X_AND2 + port map ( + I0 => NlwInverterSignal_d_28_IOBUF_OBUFT_GTS_AND_IN0, + I1 => NlwInverterSignal_d_28_IOBUF_OBUFT_GTS_AND_IN1, + O => d_28_IOBUF_OBUFT_GTS_AND + ); + d_29_IOBUF_OBUFT_GTS_AND_30 : X_AND2 + port map ( + I0 => NlwInverterSignal_d_29_IOBUF_OBUFT_GTS_AND_IN0, + I1 => NlwInverterSignal_d_29_IOBUF_OBUFT_GTS_AND_IN1, + O => d_29_IOBUF_OBUFT_GTS_AND + ); + d_0_IOBUF_OBUFT_GTS_AND_31 : X_AND2 + port map ( + I0 => NlwInverterSignal_d_0_IOBUF_OBUFT_GTS_AND_IN0, + I1 => NlwInverterSignal_d_0_IOBUF_OBUFT_GTS_AND_IN1, + O => d_0_IOBUF_OBUFT_GTS_AND + ); + d_1_IOBUF_OBUFT_GTS_AND_32 : X_AND2 + port map ( + I0 => NlwInverterSignal_d_1_IOBUF_OBUFT_GTS_AND_IN0, + I1 => NlwInverterSignal_d_1_IOBUF_OBUFT_GTS_AND_IN1, + O => d_1_IOBUF_OBUFT_GTS_AND + ); + d_2_IOBUF_OBUFT_GTS_AND_33 : X_AND2 + port map ( + I0 => NlwInverterSignal_d_2_IOBUF_OBUFT_GTS_AND_IN0, + I1 => NlwInverterSignal_d_2_IOBUF_OBUFT_GTS_AND_IN1, + O => d_2_IOBUF_OBUFT_GTS_AND + ); + d_3_IOBUF_OBUFT_GTS_AND_34 : X_AND2 + port map ( + I0 => NlwInverterSignal_d_3_IOBUF_OBUFT_GTS_AND_IN0, + I1 => NlwInverterSignal_d_3_IOBUF_OBUFT_GTS_AND_IN1, + O => d_3_IOBUF_OBUFT_GTS_AND + ); + d_4_IOBUF_OBUFT_GTS_AND_35 : X_AND2 + port map ( + I0 => NlwInverterSignal_d_4_IOBUF_OBUFT_GTS_AND_IN0, + I1 => NlwInverterSignal_d_4_IOBUF_OBUFT_GTS_AND_IN1, + O => d_4_IOBUF_OBUFT_GTS_AND + ); + d_5_IOBUF_OBUFT_GTS_AND_36 : X_AND2 + port map ( + I0 => NlwInverterSignal_d_5_IOBUF_OBUFT_GTS_AND_IN0, + I1 => NlwInverterSignal_d_5_IOBUF_OBUFT_GTS_AND_IN1, + O => d_5_IOBUF_OBUFT_GTS_AND + ); + d_6_IOBUF_OBUFT_GTS_AND_37 : X_AND2 + port map ( + I0 => NlwInverterSignal_d_6_IOBUF_OBUFT_GTS_AND_IN0, + I1 => NlwInverterSignal_d_6_IOBUF_OBUFT_GTS_AND_IN1, + O => d_6_IOBUF_OBUFT_GTS_AND + ); + d_7_IOBUF_OBUFT_GTS_AND_38 : X_AND2 + port map ( + I0 => NlwInverterSignal_d_7_IOBUF_OBUFT_GTS_AND_IN0, + I1 => NlwInverterSignal_d_7_IOBUF_OBUFT_GTS_AND_IN1, + O => d_7_IOBUF_OBUFT_GTS_AND + ); + d_8_IOBUF_OBUFT_GTS_AND_39 : X_AND2 + port map ( + I0 => NlwInverterSignal_d_8_IOBUF_OBUFT_GTS_AND_IN0, + I1 => NlwInverterSignal_d_8_IOBUF_OBUFT_GTS_AND_IN1, + O => d_8_IOBUF_OBUFT_GTS_AND + ); + d_9_IOBUF_OBUFT_GTS_AND_40 : X_AND2 + port map ( + I0 => NlwInverterSignal_d_9_IOBUF_OBUFT_GTS_AND_IN0, + I1 => NlwInverterSignal_d_9_IOBUF_OBUFT_GTS_AND_IN1, + O => d_9_IOBUF_OBUFT_GTS_AND + ); + d_10_IOBUF_OBUFT_GTS_AND_41 : X_AND2 + port map ( + I0 => NlwInverterSignal_d_10_IOBUF_OBUFT_GTS_AND_IN0, + I1 => NlwInverterSignal_d_10_IOBUF_OBUFT_GTS_AND_IN1, + O => d_10_IOBUF_OBUFT_GTS_AND + ); + NlwInverterBlock_reg_a_31_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_a_31_C + ); + NlwBlock_main_top_GND : X_ZERO + port map ( + O => GND + ); + NlwInverterBlock_reg_b_31_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_b_31_C + ); + NlwInverterBlock_reg_c_31_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_c_31_C + ); + NlwInverterBlock_reg_c_0_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_c_0_C + ); + NlwInverterBlock_reg_c_1_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_c_1_C + ); + NlwInverterBlock_reg_c_2_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_c_2_C + ); + NlwInverterBlock_reg_c_3_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_c_3_C + ); + NlwInverterBlock_reg_c_4_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_c_4_C + ); + NlwInverterBlock_reg_c_5_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_c_5_C + ); + NlwInverterBlock_reg_c_6_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_c_6_C + ); + NlwInverterBlock_reg_c_7_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_c_7_C + ); + NlwInverterBlock_reg_c_8_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_c_8_C + ); + NlwInverterBlock_reg_c_9_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_c_9_C + ); + NlwInverterBlock_reg_c_10_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_c_10_C + ); + NlwInverterBlock_reg_c_11_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_c_11_C + ); + NlwInverterBlock_reg_c_12_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_c_12_C + ); + NlwInverterBlock_reg_c_13_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_c_13_C + ); + NlwInverterBlock_reg_c_14_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_c_14_C + ); + NlwInverterBlock_reg_c_15_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_c_15_C + ); + NlwInverterBlock_reg_c_16_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_c_16_C + ); + NlwInverterBlock_reg_c_17_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_c_17_C + ); + NlwInverterBlock_reg_c_18_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_c_18_C + ); + NlwInverterBlock_reg_c_19_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_c_19_C + ); + NlwInverterBlock_reg_c_20_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_c_20_C + ); + NlwInverterBlock_reg_c_21_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_c_21_C + ); + NlwInverterBlock_reg_c_22_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_c_22_C + ); + NlwInverterBlock_reg_c_23_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_c_23_C + ); + NlwInverterBlock_reg_c_24_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_c_24_C + ); + NlwInverterBlock_reg_c_25_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_c_25_C + ); + NlwInverterBlock_reg_c_26_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_c_26_C + ); + NlwInverterBlock_reg_c_27_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_c_27_C + ); + NlwInverterBlock_reg_c_28_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_c_28_C + ); + NlwInverterBlock_reg_c_29_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_c_29_C + ); + NlwInverterBlock_reg_c_30_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_c_30_C + ); + NlwInverterBlock_reg_b_0_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_b_0_C + ); + NlwInverterBlock_reg_b_1_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_b_1_C + ); + NlwInverterBlock_reg_b_2_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_b_2_C + ); + NlwInverterBlock_reg_b_3_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_b_3_C + ); + NlwInverterBlock_reg_b_4_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_b_4_C + ); + NlwInverterBlock_reg_b_5_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_b_5_C + ); + NlwInverterBlock_reg_b_6_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_b_6_C + ); + NlwInverterBlock_reg_b_7_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_b_7_C + ); + NlwInverterBlock_reg_b_8_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_b_8_C + ); + NlwInverterBlock_reg_b_9_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_b_9_C + ); + NlwInverterBlock_reg_b_10_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_b_10_C + ); + NlwInverterBlock_reg_b_11_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_b_11_C + ); + NlwInverterBlock_reg_b_12_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_b_12_C + ); + NlwInverterBlock_reg_b_13_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_b_13_C + ); + NlwInverterBlock_reg_b_14_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_b_14_C + ); + NlwInverterBlock_reg_b_15_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_b_15_C + ); + NlwInverterBlock_reg_b_16_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_b_16_C + ); + NlwInverterBlock_reg_b_17_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_b_17_C + ); + NlwInverterBlock_reg_b_18_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_b_18_C + ); + NlwInverterBlock_reg_b_19_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_b_19_C + ); + NlwInverterBlock_reg_b_20_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_b_20_C + ); + NlwInverterBlock_reg_b_21_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_b_21_C + ); + NlwInverterBlock_reg_b_22_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_b_22_C + ); + NlwInverterBlock_reg_b_23_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_b_23_C + ); + NlwInverterBlock_reg_b_24_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_b_24_C + ); + NlwInverterBlock_reg_b_25_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_b_25_C + ); + NlwInverterBlock_reg_b_26_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_b_26_C + ); + NlwInverterBlock_reg_b_27_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_b_27_C + ); + NlwInverterBlock_reg_b_28_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_b_28_C + ); + NlwInverterBlock_reg_b_29_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_b_29_C + ); + NlwInverterBlock_reg_b_30_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_b_30_C + ); + NlwInverterBlock_reg_a_0_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_a_0_C + ); + NlwInverterBlock_reg_a_1_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_a_1_C + ); + NlwInverterBlock_reg_a_2_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_a_2_C + ); + NlwInverterBlock_reg_a_3_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_a_3_C + ); + NlwInverterBlock_reg_a_4_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_a_4_C + ); + NlwInverterBlock_reg_a_5_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_a_5_C + ); + NlwInverterBlock_reg_a_6_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_a_6_C + ); + NlwInverterBlock_reg_a_7_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_a_7_C + ); + NlwInverterBlock_reg_a_8_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_a_8_C + ); + NlwInverterBlock_reg_a_9_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_a_9_C + ); + NlwInverterBlock_reg_a_10_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_a_10_C + ); + NlwInverterBlock_reg_a_11_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_a_11_C + ); + NlwInverterBlock_reg_a_12_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_a_12_C + ); + NlwInverterBlock_reg_a_13_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_a_13_C + ); + NlwInverterBlock_reg_a_14_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_a_14_C + ); + NlwInverterBlock_reg_a_15_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_a_15_C + ); + NlwInverterBlock_reg_a_16_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_a_16_C + ); + NlwInverterBlock_reg_a_17_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_a_17_C + ); + NlwInverterBlock_reg_a_18_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_a_18_C + ); + NlwInverterBlock_reg_a_19_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_a_19_C + ); + NlwInverterBlock_reg_a_20_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_a_20_C + ); + NlwInverterBlock_reg_a_21_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_a_21_C + ); + NlwInverterBlock_reg_a_22_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_a_22_C + ); + NlwInverterBlock_reg_a_23_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_a_23_C + ); + NlwInverterBlock_reg_a_24_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_a_24_C + ); + NlwInverterBlock_reg_a_25_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_a_25_C + ); + NlwInverterBlock_reg_a_26_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_a_26_C + ); + NlwInverterBlock_reg_a_27_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_a_27_C + ); + NlwInverterBlock_reg_a_28_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_a_28_C + ); + NlwInverterBlock_reg_a_29_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_a_29_C + ); + NlwInverterBlock_reg_a_30_C : X_INV + port map ( + I => clk_BUFGP, + O => NlwInverterSignal_reg_a_30_C + ); + NlwInverterBlock_d_11_IOBUF_OBUFT_GTS_AND_IN0 : X_INV + port map ( + I => I3_N174, + O => NlwInverterSignal_d_11_IOBUF_OBUFT_GTS_AND_IN0 + ); + NlwInverterBlock_d_11_IOBUF_OBUFT_GTS_AND_IN1 : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_d_11_IOBUF_OBUFT_GTS_AND_IN1 + ); + NlwInverterBlock_d_12_IOBUF_OBUFT_GTS_AND_IN0 : X_INV + port map ( + I => I3_N174, + O => NlwInverterSignal_d_12_IOBUF_OBUFT_GTS_AND_IN0 + ); + NlwInverterBlock_d_12_IOBUF_OBUFT_GTS_AND_IN1 : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_d_12_IOBUF_OBUFT_GTS_AND_IN1 + ); + NlwInverterBlock_d_13_IOBUF_OBUFT_GTS_AND_IN0 : X_INV + port map ( + I => I3_N174, + O => NlwInverterSignal_d_13_IOBUF_OBUFT_GTS_AND_IN0 + ); + NlwInverterBlock_d_13_IOBUF_OBUFT_GTS_AND_IN1 : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_d_13_IOBUF_OBUFT_GTS_AND_IN1 + ); + NlwInverterBlock_d_14_IOBUF_OBUFT_GTS_AND_IN0 : X_INV + port map ( + I => I3_N174, + O => NlwInverterSignal_d_14_IOBUF_OBUFT_GTS_AND_IN0 + ); + NlwInverterBlock_d_14_IOBUF_OBUFT_GTS_AND_IN1 : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_d_14_IOBUF_OBUFT_GTS_AND_IN1 + ); + NlwInverterBlock_d_15_IOBUF_OBUFT_GTS_AND_IN0 : X_INV + port map ( + I => I3_N174, + O => NlwInverterSignal_d_15_IOBUF_OBUFT_GTS_AND_IN0 + ); + NlwInverterBlock_d_15_IOBUF_OBUFT_GTS_AND_IN1 : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_d_15_IOBUF_OBUFT_GTS_AND_IN1 + ); + NlwInverterBlock_d_20_IOBUF_OBUFT_GTS_AND_IN0 : X_INV + port map ( + I => I3_N174, + O => NlwInverterSignal_d_20_IOBUF_OBUFT_GTS_AND_IN0 + ); + NlwInverterBlock_d_20_IOBUF_OBUFT_GTS_AND_IN1 : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_d_20_IOBUF_OBUFT_GTS_AND_IN1 + ); + NlwInverterBlock_d_16_IOBUF_OBUFT_GTS_AND_IN0 : X_INV + port map ( + I => I3_N174, + O => NlwInverterSignal_d_16_IOBUF_OBUFT_GTS_AND_IN0 + ); + NlwInverterBlock_d_16_IOBUF_OBUFT_GTS_AND_IN1 : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_d_16_IOBUF_OBUFT_GTS_AND_IN1 + ); + NlwInverterBlock_d_21_IOBUF_OBUFT_GTS_AND_IN0 : X_INV + port map ( + I => I3_N174, + O => NlwInverterSignal_d_21_IOBUF_OBUFT_GTS_AND_IN0 + ); + NlwInverterBlock_d_21_IOBUF_OBUFT_GTS_AND_IN1 : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_d_21_IOBUF_OBUFT_GTS_AND_IN1 + ); + NlwInverterBlock_d_17_IOBUF_OBUFT_GTS_AND_IN0 : X_INV + port map ( + I => I3_N174, + O => NlwInverterSignal_d_17_IOBUF_OBUFT_GTS_AND_IN0 + ); + NlwInverterBlock_d_17_IOBUF_OBUFT_GTS_AND_IN1 : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_d_17_IOBUF_OBUFT_GTS_AND_IN1 + ); + NlwInverterBlock_d_22_IOBUF_OBUFT_GTS_AND_IN0 : X_INV + port map ( + I => I3_N174, + O => NlwInverterSignal_d_22_IOBUF_OBUFT_GTS_AND_IN0 + ); + NlwInverterBlock_d_22_IOBUF_OBUFT_GTS_AND_IN1 : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_d_22_IOBUF_OBUFT_GTS_AND_IN1 + ); + NlwInverterBlock_d_18_IOBUF_OBUFT_GTS_AND_IN0 : X_INV + port map ( + I => I3_N174, + O => NlwInverterSignal_d_18_IOBUF_OBUFT_GTS_AND_IN0 + ); + NlwInverterBlock_d_18_IOBUF_OBUFT_GTS_AND_IN1 : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_d_18_IOBUF_OBUFT_GTS_AND_IN1 + ); + NlwInverterBlock_d_23_IOBUF_OBUFT_GTS_AND_IN0 : X_INV + port map ( + I => I3_N174, + O => NlwInverterSignal_d_23_IOBUF_OBUFT_GTS_AND_IN0 + ); + NlwInverterBlock_d_23_IOBUF_OBUFT_GTS_AND_IN1 : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_d_23_IOBUF_OBUFT_GTS_AND_IN1 + ); + NlwInverterBlock_d_19_IOBUF_OBUFT_GTS_AND_IN0 : X_INV + port map ( + I => I3_N174, + O => NlwInverterSignal_d_19_IOBUF_OBUFT_GTS_AND_IN0 + ); + NlwInverterBlock_d_19_IOBUF_OBUFT_GTS_AND_IN1 : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_d_19_IOBUF_OBUFT_GTS_AND_IN1 + ); + NlwInverterBlock_d_24_IOBUF_OBUFT_GTS_AND_IN0 : X_INV + port map ( + I => I3_N174, + O => NlwInverterSignal_d_24_IOBUF_OBUFT_GTS_AND_IN0 + ); + NlwInverterBlock_d_24_IOBUF_OBUFT_GTS_AND_IN1 : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_d_24_IOBUF_OBUFT_GTS_AND_IN1 + ); + NlwInverterBlock_d_25_IOBUF_OBUFT_GTS_AND_IN0 : X_INV + port map ( + I => I3_N174, + O => NlwInverterSignal_d_25_IOBUF_OBUFT_GTS_AND_IN0 + ); + NlwInverterBlock_d_25_IOBUF_OBUFT_GTS_AND_IN1 : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_d_25_IOBUF_OBUFT_GTS_AND_IN1 + ); + NlwInverterBlock_d_30_IOBUF_OBUFT_GTS_AND_IN0 : X_INV + port map ( + I => I3_N174, + O => NlwInverterSignal_d_30_IOBUF_OBUFT_GTS_AND_IN0 + ); + NlwInverterBlock_d_30_IOBUF_OBUFT_GTS_AND_IN1 : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_d_30_IOBUF_OBUFT_GTS_AND_IN1 + ); + NlwInverterBlock_d_26_IOBUF_OBUFT_GTS_AND_IN0 : X_INV + port map ( + I => I3_N174, + O => NlwInverterSignal_d_26_IOBUF_OBUFT_GTS_AND_IN0 + ); + NlwInverterBlock_d_26_IOBUF_OBUFT_GTS_AND_IN1 : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_d_26_IOBUF_OBUFT_GTS_AND_IN1 + ); + NlwInverterBlock_d_31_IOBUF_OBUFT_GTS_AND_IN0 : X_INV + port map ( + I => I3_N174, + O => NlwInverterSignal_d_31_IOBUF_OBUFT_GTS_AND_IN0 + ); + NlwInverterBlock_d_31_IOBUF_OBUFT_GTS_AND_IN1 : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_d_31_IOBUF_OBUFT_GTS_AND_IN1 + ); + NlwInverterBlock_d_27_IOBUF_OBUFT_GTS_AND_IN0 : X_INV + port map ( + I => I3_N174, + O => NlwInverterSignal_d_27_IOBUF_OBUFT_GTS_AND_IN0 + ); + NlwInverterBlock_d_27_IOBUF_OBUFT_GTS_AND_IN1 : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_d_27_IOBUF_OBUFT_GTS_AND_IN1 + ); + NlwInverterBlock_d_28_IOBUF_OBUFT_GTS_AND_IN0 : X_INV + port map ( + I => I3_N174, + O => NlwInverterSignal_d_28_IOBUF_OBUFT_GTS_AND_IN0 + ); + NlwInverterBlock_d_28_IOBUF_OBUFT_GTS_AND_IN1 : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_d_28_IOBUF_OBUFT_GTS_AND_IN1 + ); + NlwInverterBlock_d_29_IOBUF_OBUFT_GTS_AND_IN0 : X_INV + port map ( + I => I3_N174, + O => NlwInverterSignal_d_29_IOBUF_OBUFT_GTS_AND_IN0 + ); + NlwInverterBlock_d_29_IOBUF_OBUFT_GTS_AND_IN1 : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_d_29_IOBUF_OBUFT_GTS_AND_IN1 + ); + NlwInverterBlock_d_0_IOBUF_OBUFT_GTS_AND_IN0 : X_INV + port map ( + I => I3_N174, + O => NlwInverterSignal_d_0_IOBUF_OBUFT_GTS_AND_IN0 + ); + NlwInverterBlock_d_0_IOBUF_OBUFT_GTS_AND_IN1 : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_d_0_IOBUF_OBUFT_GTS_AND_IN1 + ); + NlwInverterBlock_d_1_IOBUF_OBUFT_GTS_AND_IN0 : X_INV + port map ( + I => I3_N174, + O => NlwInverterSignal_d_1_IOBUF_OBUFT_GTS_AND_IN0 + ); + NlwInverterBlock_d_1_IOBUF_OBUFT_GTS_AND_IN1 : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_d_1_IOBUF_OBUFT_GTS_AND_IN1 + ); + NlwInverterBlock_d_2_IOBUF_OBUFT_GTS_AND_IN0 : X_INV + port map ( + I => I3_N174, + O => NlwInverterSignal_d_2_IOBUF_OBUFT_GTS_AND_IN0 + ); + NlwInverterBlock_d_2_IOBUF_OBUFT_GTS_AND_IN1 : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_d_2_IOBUF_OBUFT_GTS_AND_IN1 + ); + NlwInverterBlock_d_3_IOBUF_OBUFT_GTS_AND_IN0 : X_INV + port map ( + I => I3_N174, + O => NlwInverterSignal_d_3_IOBUF_OBUFT_GTS_AND_IN0 + ); + NlwInverterBlock_d_3_IOBUF_OBUFT_GTS_AND_IN1 : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_d_3_IOBUF_OBUFT_GTS_AND_IN1 + ); + NlwInverterBlock_d_4_IOBUF_OBUFT_GTS_AND_IN0 : X_INV + port map ( + I => I3_N174, + O => NlwInverterSignal_d_4_IOBUF_OBUFT_GTS_AND_IN0 + ); + NlwInverterBlock_d_4_IOBUF_OBUFT_GTS_AND_IN1 : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_d_4_IOBUF_OBUFT_GTS_AND_IN1 + ); + NlwInverterBlock_d_5_IOBUF_OBUFT_GTS_AND_IN0 : X_INV + port map ( + I => I3_N174, + O => NlwInverterSignal_d_5_IOBUF_OBUFT_GTS_AND_IN0 + ); + NlwInverterBlock_d_5_IOBUF_OBUFT_GTS_AND_IN1 : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_d_5_IOBUF_OBUFT_GTS_AND_IN1 + ); + NlwInverterBlock_d_6_IOBUF_OBUFT_GTS_AND_IN0 : X_INV + port map ( + I => I3_N174, + O => NlwInverterSignal_d_6_IOBUF_OBUFT_GTS_AND_IN0 + ); + NlwInverterBlock_d_6_IOBUF_OBUFT_GTS_AND_IN1 : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_d_6_IOBUF_OBUFT_GTS_AND_IN1 + ); + NlwInverterBlock_d_7_IOBUF_OBUFT_GTS_AND_IN0 : X_INV + port map ( + I => I3_N174, + O => NlwInverterSignal_d_7_IOBUF_OBUFT_GTS_AND_IN0 + ); + NlwInverterBlock_d_7_IOBUF_OBUFT_GTS_AND_IN1 : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_d_7_IOBUF_OBUFT_GTS_AND_IN1 + ); + NlwInverterBlock_d_8_IOBUF_OBUFT_GTS_AND_IN0 : X_INV + port map ( + I => I3_N174, + O => NlwInverterSignal_d_8_IOBUF_OBUFT_GTS_AND_IN0 + ); + NlwInverterBlock_d_8_IOBUF_OBUFT_GTS_AND_IN1 : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_d_8_IOBUF_OBUFT_GTS_AND_IN1 + ); + NlwInverterBlock_d_9_IOBUF_OBUFT_GTS_AND_IN0 : X_INV + port map ( + I => I3_N174, + O => NlwInverterSignal_d_9_IOBUF_OBUFT_GTS_AND_IN0 + ); + NlwInverterBlock_d_9_IOBUF_OBUFT_GTS_AND_IN1 : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_d_9_IOBUF_OBUFT_GTS_AND_IN1 + ); + NlwInverterBlock_d_10_IOBUF_OBUFT_GTS_AND_IN0 : X_INV + port map ( + I => I3_N174, + O => NlwInverterSignal_d_10_IOBUF_OBUFT_GTS_AND_IN0 + ); + NlwInverterBlock_d_10_IOBUF_OBUFT_GTS_AND_IN1 : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_d_10_IOBUF_OBUFT_GTS_AND_IN1 + ); + NlwBlockROC : X_ROC + generic map (ROC_WIDTH => 100 ns) + port map (O => GSR); + NlwBlockTOC : X_TOC + port map (O => GTS); + +end Structure; + diff --git a/projects/eval_dmux/pepExtractor.prj b/projects/eval_dmux/pepExtractor.prj new file mode 100644 index 0000000..c104b61 --- /dev/null +++ b/projects/eval_dmux/pepExtractor.prj @@ -0,0 +1 @@ +work main_top.vhdl diff --git a/projects/eval_dmux/wave.do b/projects/eval_dmux/wave.do new file mode 100644 index 0000000..f532a8b --- /dev/null +++ b/projects/eval_dmux/wave.do @@ -0,0 +1,28 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -format Logic /main_top_main_top_tb_vhd_tb/clk +add wave -noupdate -format Logic /main_top_main_top_tb_vhd_tb/resn +add wave -noupdate -format Literal -radix hexadecimal /main_top_main_top_tb_vhd_tb/a +add wave -noupdate -format Literal -radix hexadecimal /main_top_main_top_tb_vhd_tb/d +add wave -noupdate -format Logic /main_top_main_top_tb_vhd_tb/wen +add wave -noupdate -format Logic /main_top_main_top_tb_vhd_tb/csn +add wave -noupdate -format Literal -radix hexadecimal /main_top_main_top_tb_vhd_tb/uut/reg_a +add wave -noupdate -format Literal -radix hexadecimal /main_top_main_top_tb_vhd_tb/uut/reg_b +add wave -noupdate -format Literal -radix hexadecimal /main_top_main_top_tb_vhd_tb/uut/reg_c +add wave -noupdate -format Literal -radix hexadecimal /main_top_main_top_tb_vhd_tb/uut/dmuxo +add wave -noupdate -format Literal -radix hexadecimal /main_top_main_top_tb_vhd_tb/uut/mux_ctrl +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {684150 ps} 0} +WaveRestoreZoom {356007 ps} {1033895 ps} +configure wave -namecolwidth 150 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 diff --git a/projects/eval_fixed_ja/Makefile b/projects/eval_fixed_ja/Makefile new file mode 100644 index 0000000..218643e --- /dev/null +++ b/projects/eval_fixed_ja/Makefile @@ -0,0 +1,50 @@ +# ------------------------------------------------- +# Global options +# ------------------------------------------------- +LANG_STD := 93c +IEEE_STD := standard +WORK_PATH := work +SOURCE_PATH := src +LIB_PATH := ../lib + +# ------------------------------------------------- +# Target options +# ------------------------------------------------- +TARGET := tb_eval_fixed_ja +SOURCES := + +# ------------------------------------------------- +GHDL_OPT := --workdir=$(WORK_PATH) --std=$(LANG_STD) --ieee=$(IEEE_STD) + +# ------------------------------------------------- +all: elaborate + +.PHONY: syntax +syntax: + ghdl -s $(GHDL_OPT) $(SOURCE_PATH)/*.vhd + +import: + ghdl -i $(GHDL_OPT) $(LIB_PATH)/*.vhd + +analyze: import + ghdl -a $(GHDL_OPT) $(LIB_PATH)/*.vhd $(SOURCE_PATH)/*.vhd + +anaborate: import + ghdl -c $(GHDL_OPT) $(LIB_PATH)/*.vhd $(SOURCE_PATH)/*.vhd -e $(TARGET) + +makeunit: import + ghdl -m $(GHDL_OPT) $(TARGET) + +elaborate: analyze + ghdl -e $(GHDL_OPT) $(TARGET) + +run: elaborate + ghdl -r $(GHDL_OPT) $(TARGET) + +# ------------------------------------------------- +.PHONY: clean +clean: + rm -rf $(TARGET) + cd $(WORK_PATH); rm -rf *.o *.cf + +# ------------------------------------------------- diff --git a/projects/eval_fixed_ja/ise81/eval_fixed_ja.lso b/projects/eval_fixed_ja/ise81/eval_fixed_ja.lso new file mode 100644 index 0000000..22de730 --- /dev/null +++ b/projects/eval_fixed_ja/ise81/eval_fixed_ja.lso @@ -0,0 +1 @@ +work diff --git a/projects/eval_fixed_ja/ise81/eval_fixed_ja.prj b/projects/eval_fixed_ja/ise81/eval_fixed_ja.prj new file mode 100644 index 0000000..35a0201 --- /dev/null +++ b/projects/eval_fixed_ja/ise81/eval_fixed_ja.prj @@ -0,0 +1,2 @@ +vhdl work "W:/vhdl/lib/src/fixed_ja/fixed_ja.vhd" +vhdl work "W:/vhdl/projects/eval_fixed_ja/src/eval_fixed_ja_syn.vhd" diff --git a/projects/eval_fixed_ja/ise81/eval_fixed_ja.xst b/projects/eval_fixed_ja/ise81/eval_fixed_ja.xst new file mode 100644 index 0000000..44ba20b --- /dev/null +++ b/projects/eval_fixed_ja/ise81/eval_fixed_ja.xst @@ -0,0 +1,55 @@ +set -tmpdir ./xst/projnav.tmp +set -xsthdpdir ./xst +run +-ifn eval_fixed_ja.prj +-ifmt mixed +-ofn eval_fixed_ja +-ofmt NGC +-p xc4vsx35-10-ff668 +-top eval_fixed_ja +-opt_mode Speed +-opt_level 1 +-iuc NO +-lso eval_fixed_ja.lso +-keep_hierarchy NO +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case maintain +-slice_utilization_ratio 100 +-dsp_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style lut +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract YES +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-mux_extract YES +-resource_sharing YES +-use_dsp48 auto +-iobuf YES +-max_fanout 500 +-bufg 32 +-bufr 24 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-use_clock_enable Auto +-use_sync_set Auto +-use_sync_reset Auto +-iob auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/projects/eval_fixed_ja/ise81/eval_fixed_ja_syn.ise b/projects/eval_fixed_ja/ise81/eval_fixed_ja_syn.ise new file mode 100644 index 0000000..85394e3 Binary files /dev/null and b/projects/eval_fixed_ja/ise81/eval_fixed_ja_syn.ise differ diff --git a/projects/eval_fixed_ja/ise81/tb_eval_fixed_ja_vhd.fdo b/projects/eval_fixed_ja/ise81/tb_eval_fixed_ja_vhd.fdo new file mode 100644 index 0000000..65518c0 --- /dev/null +++ b/projects/eval_fixed_ja/ise81/tb_eval_fixed_ja_vhd.fdo @@ -0,0 +1,15 @@ +## NOTE: Do not edit this file. +## Autogenerated by ProjNav (creatfdo.tcl) on Tue May 22 21:51:13 Westeuropäische Sommerzeit 2007 +## +vlib work +vcom -explicit -93 "W:/vhdl/lib/src/fixed_ja/fixed_ja.vhd" +vcom -explicit -93 "W:/vhdl/lib/src/fixed_ja/fixed_ja_body.vhd" +vcom -explicit -93 "W:/vhdl/projects/eval_fixed_ja/src/eval_fixed_ja_syn.vhd" +vcom -explicit -93 "W:/vhdl/projects/eval_fixed_ja/src/tb_eval_fixed_ja_syn.vhd" +vsim -t 1ps -lib work tb_eval_fixed_ja_vhd +do {tb_eval_fixed_ja_vhd.udo} +view wave +add wave * +view structure +view signals +run 1000ns diff --git a/projects/eval_fixed_ja/ise81/tb_eval_fixed_ja_vhd.udo b/projects/eval_fixed_ja/ise81/tb_eval_fixed_ja_vhd.udo new file mode 100644 index 0000000..ec75f19 --- /dev/null +++ b/projects/eval_fixed_ja/ise81/tb_eval_fixed_ja_vhd.udo @@ -0,0 +1,4 @@ +-- ProjNav VHDL simulation template: tb_eval_fixed_ja_vhd.udo +-- You may edit this file after the line that starts with +-- '-- START' to customize your simulation +-- START user-defined simulation commands diff --git a/projects/eval_fixed_ja/ise91/eval_fixed.ise b/projects/eval_fixed_ja/ise91/eval_fixed.ise new file mode 100644 index 0000000..4d018e3 Binary files /dev/null and b/projects/eval_fixed_ja/ise91/eval_fixed.ise differ diff --git a/projects/eval_fixed_ja/ise91/eval_fixed_ja.lso b/projects/eval_fixed_ja/ise91/eval_fixed_ja.lso new file mode 100644 index 0000000..22de730 --- /dev/null +++ b/projects/eval_fixed_ja/ise91/eval_fixed_ja.lso @@ -0,0 +1 @@ +work diff --git a/projects/eval_fixed_ja/ise91/eval_fixed_ja.prj b/projects/eval_fixed_ja/ise91/eval_fixed_ja.prj new file mode 100644 index 0000000..69fed8c --- /dev/null +++ b/projects/eval_fixed_ja/ise91/eval_fixed_ja.prj @@ -0,0 +1,2 @@ +vhdl ieee_proposed "C:/Programme/Xilinx9/vhdl/src/ieee_proposed/fixed_pkg_c.vhd" +vhdl work "../src/eval_fixed_ja_syn.vhd" diff --git a/projects/eval_fixed_ja/ise91/eval_fixed_ja.xst b/projects/eval_fixed_ja/ise91/eval_fixed_ja.xst new file mode 100644 index 0000000..1cd1a6d --- /dev/null +++ b/projects/eval_fixed_ja/ise91/eval_fixed_ja.xst @@ -0,0 +1,59 @@ +set -tmpdir "./xst/projnav.tmp" +set -xsthdpdir "./xst" +run +-ifn eval_fixed_ja.prj +-ifmt mixed +-ofn eval_fixed_ja +-ofmt NGC +-p xc4vsx35-10-ff668 +-top eval_fixed_ja +-opt_mode Speed +-opt_level 1 +-power NO +-iuc NO +-lso eval_fixed_ja.lso +-keep_hierarchy NO +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-dsp_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style lut +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract YES +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-auto_bram_packing NO +-mux_extract YES +-resource_sharing YES +-async_to_sync NO +-use_dsp48 auto +-iobuf YES +-max_fanout 500 +-bufg 32 +-bufr 24 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-use_clock_enable Auto +-use_sync_set Auto +-use_sync_reset Auto +-iob auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/projects/eval_fixed_ja/ise91/eval_fixed_ja_vhdl.prj b/projects/eval_fixed_ja/ise91/eval_fixed_ja_vhdl.prj new file mode 100644 index 0000000..d45d072 --- /dev/null +++ b/projects/eval_fixed_ja/ise91/eval_fixed_ja_vhdl.prj @@ -0,0 +1,2 @@ +vhdl ieee_proposed "C:\Programme\Xilinx9\vhdl\src\ieee_proposed\fixed_pkg_c.vhd" +vhdl work "H:\vhdl\projects\eval_fixed_ja\src\eval_fixed_ja_syn.vhd" diff --git a/projects/eval_fixed_ja/ise91/tb_eval_fixed_ja_vhd.fdo b/projects/eval_fixed_ja/ise91/tb_eval_fixed_ja_vhd.fdo new file mode 100644 index 0000000..9d72c32 --- /dev/null +++ b/projects/eval_fixed_ja/ise91/tb_eval_fixed_ja_vhd.fdo @@ -0,0 +1,15 @@ +## NOTE: Do not edit this file. +## Autogenerated by ProjNav (creatfdo.tcl) on Thu May 24 11:58:33 Westeuropäische Normalzeit 2007 +## +vlib work +vlib ieee_proposed +vcom -explicit -93 -work ieee_proposed "C:/Programme/Xilinx9/vhdl/src/ieee_proposed/fixed_pkg_c.vhd" +vcom -explicit -93 "../src/eval_fixed_ja_syn.vhd" +vcom -explicit -93 "../src/tb_eval_fixed_ja_syn.vhd" +vsim -t 1ps -lib work tb_eval_fixed_ja_vhd +view wave +add wave * +do {tb_eval_fixed_ja_vhd.udo} +view structure +view signals +run 1000ns diff --git a/projects/eval_fixed_ja/ise91/tb_eval_fixed_ja_vhd.ndo b/projects/eval_fixed_ja/ise91/tb_eval_fixed_ja_vhd.ndo new file mode 100644 index 0000000..a831698 --- /dev/null +++ b/projects/eval_fixed_ja/ise91/tb_eval_fixed_ja_vhd.ndo @@ -0,0 +1,15 @@ +## NOTE: Do not edit this file. +## Auto generated by Project Navigator for Post-Translate Simulation +## +vlib work +## Compile Post-Translate Model +vcom -explicit -93 "netgen/translate/eval_fixed_ja_translate.vhd" +vcom -explicit -93 "../src/tb_eval_fixed_ja_syn.vhd" +vsim -t 1ps -lib work tb_eval_fixed_ja_vhd +do {tb_eval_fixed_ja_vhd.udo} +view wave +add wave * +view structure +view signals +run 1000ns +## End diff --git a/projects/eval_fixed_ja/ise91/tb_eval_fixed_ja_vhd.udo b/projects/eval_fixed_ja/ise91/tb_eval_fixed_ja_vhd.udo new file mode 100644 index 0000000..ec75f19 --- /dev/null +++ b/projects/eval_fixed_ja/ise91/tb_eval_fixed_ja_vhd.udo @@ -0,0 +1,4 @@ +-- ProjNav VHDL simulation template: tb_eval_fixed_ja_vhd.udo +-- You may edit this file after the line that starts with +-- '-- START' to customize your simulation +-- START user-defined simulation commands diff --git a/projects/eval_fixed_ja/make.do b/projects/eval_fixed_ja/make.do new file mode 100644 index 0000000..3908346 --- /dev/null +++ b/projects/eval_fixed_ja/make.do @@ -0,0 +1,12 @@ +vlib work +vcom -explicit -93 "../lib/fixed_ja.vhd" +vcom -explicit -93 "../lib/fixed_ja_body.vhd" +vcom -explicit -93 "../lib/PCK_FIO_1993.vhd" +vcom -explicit -93 "../lib/PCK_FIO_1993_BODY.vhd" +vcom -explicit -93 "src/tb_eval_fixed_ja.vhd" +vsim -t 1ps -lib work tb_eval_fixed_ja +#do {wave.do} +view wave +view structure +view signals +run 1000ns diff --git a/projects/eval_fixed_ja/quartus/eval_fixed_ja.out.sdc b/projects/eval_fixed_ja/quartus/eval_fixed_ja.out.sdc new file mode 100644 index 0000000..8d847b6 --- /dev/null +++ b/projects/eval_fixed_ja/quartus/eval_fixed_ja.out.sdc @@ -0,0 +1,107 @@ +## Generated SDC file "eval_fixed_ja.out.sdc" + +## Copyright (C) 1991-2008 Altera Corporation +## Your use of Altera Corporation's design tools, logic functions +## and other software and tools, and its AMPP partner logic +## functions, and any output files from any of the foregoing +## (including device programming or simulation files), and any +## associated documentation or information are expressly subject +## to the terms and conditions of the Altera Program License +## Subscription Agreement, Altera MegaCore Function License +## Agreement, or other applicable license agreement, including, +## without limitation, that your use is for the sole purpose of +## programming logic devices manufactured by Altera and sold by +## Altera or its authorized distributors. Please refer to the +## applicable agreement for further details. + + +## VENDOR "Altera" +## PROGRAM "Quartus II" +## VERSION "Version 8.1 Build 163 10/28/2008 SJ Web Edition" + +## DATE "Thu Dec 18 22:26:14 2008" + +## +## DEVICE "EP3C25Q240C8" +## + + +#************************************************************** +# Time Information +#************************************************************** + +set_time_format -unit ns -decimal_places 3 + + + +#************************************************************** +# Create Clock +#************************************************************** + +create_clock -name {ccc} -period 10.000 -waveform { 0.000 5.000 } [get_ports {clk}] + + +#************************************************************** +# Create Generated Clock +#************************************************************** + + + +#************************************************************** +# Set Clock Latency +#************************************************************** + + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** + + + +#************************************************************** +# Set Input Delay +#************************************************************** + + + +#************************************************************** +# Set Output Delay +#************************************************************** + + + +#************************************************************** +# Set Clock Groups +#************************************************************** + + + +#************************************************************** +# Set False Path +#************************************************************** + + + +#************************************************************** +# Set Multicycle Path +#************************************************************** + + + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** + diff --git a/projects/eval_fixed_ja/quartus/eval_fixed_ja.qpf b/projects/eval_fixed_ja/quartus/eval_fixed_ja.qpf new file mode 100644 index 0000000..1d14dc6 --- /dev/null +++ b/projects/eval_fixed_ja/quartus/eval_fixed_ja.qpf @@ -0,0 +1,23 @@ +# Copyright (C) 1991-2008 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + + +QUARTUS_VERSION = "8.1" +DATE = "10:27:40 December 18, 2008" + + +# Revisions + +PROJECT_REVISION = "eval_fixed_ja" diff --git a/projects/eval_fixed_ja/quartus/eval_fixed_ja.qsf b/projects/eval_fixed_ja/quartus/eval_fixed_ja.qsf new file mode 100644 index 0000000..95f4fec --- /dev/null +++ b/projects/eval_fixed_ja/quartus/eval_fixed_ja.qsf @@ -0,0 +1,47 @@ +# Copyright (C) 1991-2008 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + +# The default values for assignments are stored in the file +# eval_fixed_ja_assignment_defaults.qdf +# If this file doesn't exist, and for assignments not listed, see file +# assignment_defaults.qdf + +# Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. + + +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name DEVICE EP3C25Q240C8 +set_global_assignment -name TOP_LEVEL_ENTITY eval_fixed_ja +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:27:40 DECEMBER 18, 2008" +set_global_assignment -name LAST_QUARTUS_VERSION 8.1 +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER clk -section_id clock +set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON +set_global_assignment -name SDC_FILE eval_fixed_ja.out.sdc +set_global_assignment -name VHDL_FILE ../../../lib/fixed/fixed_pkg_c.vhd +set_global_assignment -name VHDL_FILE ../src/eval_fixed_ja_syn.vhd +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON \ No newline at end of file diff --git a/projects/eval_fixed_ja/quartus/eval_fixed_ja.qws b/projects/eval_fixed_ja/quartus/eval_fixed_ja.qws new file mode 100644 index 0000000..d1bd51b --- /dev/null +++ b/projects/eval_fixed_ja/quartus/eval_fixed_ja.qws @@ -0,0 +1,29 @@ +[ProjectWorkspace] +ptn_Child1=Frames +[ProjectWorkspace.Frames] +ptn_Child1=ChildFrames +[ProjectWorkspace.Frames.ChildFrames] +ptn_Child1=Document-0 +ptn_Child2=Document-1 +ptn_Child3=Document-2 +ptn_Child4=Document-3 +[ProjectWorkspace.Frames.ChildFrames.Document-2] +ptn_Child1=ViewFrame-0 +[ProjectWorkspace.Frames.ChildFrames.Document-2.ViewFrame-0] +DocPathName=eval_fixed_ja.sdc +DocumentCLSID={c5dd978f-562d-48b1-a72f-0e9994df79df} +IsChildFrameDetached=False +IsActiveChildFrame=False +ptn_Child1=StateMap +[ProjectWorkspace.Frames.ChildFrames.Document-2.ViewFrame-0.StateMap] +AFC_IN_REPORT=False +[ProjectWorkspace.Frames.ChildFrames.Document-3] +ptn_Child1=ViewFrame-0 +[ProjectWorkspace.Frames.ChildFrames.Document-3.ViewFrame-0] +DocPathName=eval_fixed_ja.out.sdc +DocumentCLSID={c5dd978f-562d-48b1-a72f-0e9994df79df} +IsChildFrameDetached=False +IsActiveChildFrame=False +ptn_Child1=StateMap +[ProjectWorkspace.Frames.ChildFrames.Document-3.ViewFrame-0.StateMap] +AFC_IN_REPORT=False diff --git a/projects/eval_fixed_ja/quartus/eval_fixed_ja.sdc b/projects/eval_fixed_ja/quartus/eval_fixed_ja.sdc new file mode 100644 index 0000000..41197e5 --- /dev/null +++ b/projects/eval_fixed_ja/quartus/eval_fixed_ja.sdc @@ -0,0 +1,56 @@ +########################################################################### +# +# Generated by : Version 8.1 Build 163 10/28/2008 SJ Web Edition +# +# Project : eval_fixed_ja +# Revision : eval_fixed_ja +# +# Date : Thu Dec 18 22:17:10 Westeuropäische Normalzeit 2008 +# +########################################################################### + + +# WARNING: Expected ENABLE_CLOCK_LATENCY to be set to 'ON', but it is set to 'OFF' +# In SDC, create_generated_clock auto-generates clock latency +# +# ------------------------------------------ +# +# Create generated clocks based on PLLs +derive_pll_clocks -use_tan_name +# +# ------------------------------------------ + +# ** Clock Latency +# ------------- + +# ** Clock Uncertainty +# ----------------- + +# ** Multicycles +# ----------- +# ** Cuts +# ---- + +# ** Input/Output Delays +# ------------------- + + + + +# ** Tpd requirements +# ---------------- + +# ** Setup/Hold Relationships +# ------------------------ + +# ** Tsu/Th requirements +# ------------------- + + +# ** Tco/MinTco requirements +# ----------------------- + + + +# --------------------------------------------- + diff --git a/projects/eval_fixed_ja/result.txt b/projects/eval_fixed_ja/result.txt new file mode 100644 index 0000000..d66342d --- /dev/null +++ b/projects/eval_fixed_ja/result.txt @@ -0,0 +1,876 @@ +Fixed Point Library Testbench 0.1 +---------------------- + Without saturation +---------------------- + +* No rounding + +U: 101.0011 => 01.0011 ...passed +U: 1.001101 => 001. ...passed +U: 101.01 => 1.0 ...passed +U: 1010.1 => 10. ...passed +U: 101.11 => 101. ...passed +U: .11 => 0. ...passed +U: .1011 => 0.10 ...passed +U: 0.0000000001 => 0. ...passed +U: 1.0000000001 => 1.0 ...passed +U: 1.0000000001 => 1. ...passed +U: 10.000000001 => 10.000 ...passed +U: 1. => 1.00000000000000000 ...passed +U: 0. => 0.00000000000000000 ...passed +U: 1. => .000000000000000000 ...passed +U: 0. => .000000000000000000 ...passed +U: 10.101 => 010.1010 ...passed +U: 10.101 => 10.10 ...passed +U: 10.101 => 10.1010 ...passed +S: 101.0011 => 01.0011 ...passed +S: -1.001101 => -001. ...passed +S: -101.01 => -1.0 ...passed +S: 1010.1 => 10. ...passed +S: 101.11 => 101. ...passed +S: -.11 => 0. ...passed +S: -.1011 => -0.10 ...passed +S: 0.0000000001 => 0. ...passed +S: -1.0000000001 => -1.0 ...passed +S: -1.0000000001 => -1. ...passed +S: -10.000000001 => -10.000 ...passed +S: 1. => 1.00000000000000000 ...passed +S: 0. => 0.00000000000000000 ...passed +S: 1. => .000000000000000000 ...passed +S: 0. => .000000000000000000 ...passed +S: 10.101 => 010.1010 ...passed +S: -10.101 => -10.10 ...passed +S: 10.101 => 10.1010 ...passed + +* Round to zero + +U: 101.0011 => 01.0011 ...passed +U: 1.001101 => 001. ...passed +U: 101.01 => 1.0 ...passed +U: 1010.1 => 10. ...passed +U: 101.11 => 101. ...passed +U: .11 => 0. ...passed +U: .1011 => 0.10 ...passed +U: 0.0000000001 => 0. ...passed +U: 1.0000000001 => 1.0 ...passed +U: 1.0000000001 => 1. ...passed +U: 10.000000001 => 10.000 ...passed +U: 1. => 1.00000000000000000 ...passed +U: 0. => 0.00000000000000000 ...passed +U: 1. => .000000000000000000 ...passed +U: 0. => .000000000000000000 ...passed +U: 10.101 => 010.1010 ...passed +U: 10.101 => 10.10 ...passed +U: 10.101 => 10.1010 ...passed +S: 101.0011 => 01.0011 ...passed +S: -1.001101 => -001. ...passed +S: -101.01 => -1.0 ...passed +S: 1010.1 => 10. ...passed +S: 101.11 => 101. ...passed +S: -.11 => 0. ...passed +S: -.1011 => -0.10 ...passed +S: 0.0000000001 => 0. ...passed +S: -1.0000000001 => -1.0 ...passed +S: -1.0000000001 => -1. ...passed +S: -10.000000001 => -10.000 ...passed +S: 1. => 1.00000000000000000 ...passed +S: 0. => 0.00000000000000000 ...passed +S: 1. => .000000000000000000 ...passed +S: 0. => .000000000000000000 ...passed +S: 10.101 => 010.1010 ...passed +S: -10.101 => -10.10 ...passed +S: 10.101 => 10.1010 ...passed + +* Round to infinity + +U: 101.0011 => 01.0011 ...passed +U: 1.001101 => 010. ...passed +U: 101.01 => 1.1 ...passed +U: 1010.1 => 11. ...passed +U: 101.11 => 110. ...passed +U: .11 => 1. ...passed +U: .1011 => 0.11 ...passed +U: 0.0000000001 => 1. ...passed +U: 1.0000000001 => 1.1 ...passed +U: 1.0000000001 => 0. ...passed +U: 10.000000001 => 10.001 ...passed +U: 1. => 1.00000000000000000 ...passed +U: 0. => 0.00000000000000000 ...passed +U: 1. => .000000000000000000 ...passed +U: 0. => .000000000000000000 ...passed +U: 10.101 => 010.1010 ...passed +U: 10.101 => 10.11 ...passed +U: 10.101 => 10.1010 ...passed +S: 101.0011 => 01.0011 ...passed +S: -10.001101 => -010. ...passed +S: -101.01 => -1.0 ...passed +S: 1010.1 => 11. ...passed +S: 101.11 => 110. ...passed +S: -.11 => 0. ...passed +S: -.1011 => -0.10 ...passed +S: 0.0000000001 => 1. ...passed +S: -1.0000000001 => -1.0 ...passed +S: 1.0000000001 => 0. ...passed +S: -10.000000001 => -10.000 ...passed +S: 1. => 1.00000000000000000 ...passed +S: 0. => 0.00000000000000000 ...passed +S: 1. => .000000000000000000 ...passed +S: 0. => .000000000000000000 ...passed +S: 10.101 => 010.1010 ...passed +S: -10.101 => -10.10 ...passed +S: 10.101 => 10.1010 ...passed + +* Round half up + +U: 101.0011 => 01.0011 ...passed +U: 1.001101 => 001. ...passed +U: 101.01 => 1.1 ...passed +U: 1010.1 => 11. ...passed +U: 101.11 => 110. ...passed +U: .11 => 1. ...passed +U: .1011 => 0.11 ...passed +U: 0.0000000001 => 0. ...passed +U: 1.0000000001 => 1.0 ...passed +U: 1.0000000001 => 1. ...passed +U: 10.000000001 => 10.000 ...passed +U: 1. => 1.00000000000000000 ...passed +U: 0. => 0.00000000000000000 ...passed +U: 1. => .000000000000000000 ...passed +U: 0. => .000000000000000000 ...passed +U: 10.101 => 010.1010 ...passed +U: 10.101 => 10.11 ...passed +U: 10.101 => 10.1010 ...passed +S: 101.0011 => 01.0011 ...passed +S: -10.001101 => -010. ...passed +S: -101.01 => -1.0 ...passed +S: 1010.1 => 11. ...passed +S: 101.11 => 110. ...passed +S: -.11 => -1. ...passed +S: -.1011 => -0.11 ...passed +S: 0.0000000001 => 0. ...passed +S: -1.0000000001 => -1.0 ...passed +S: 1.0000000001 => 1. ...passed +S: -10.000000001 => -10.000 ...passed +S: 1. => 1.00000000000000000 ...passed +S: 0. => 0.00000000000000000 ...passed +S: 1. => .000000000000000000 ...passed +S: 0. => .000000000000000000 ...passed +S: 10.101 => 010.1010 ...passed +S: -10.1011 => -10.11 ...passed +S: -10.101 => -10.10 ...passed +S: -0.1111 => -0.111 ...passed +S: -0.11110 => -0.111 ...passed +S: -0.11111 => -1.000 ...passed + +* Round convergent + +U: 01.001 => 01.00 ...passed +U: 01.0010 => 01.00 ...passed +U: 01.0011 => 01.01 ...passed +U: 01.011 => 01.10 ...passed +U: 01.0110 => 01.10 ...passed +U: 01.0111 => 01.10 ...passed +S: 01.001 => 01.00 ...passed +S: 01.0010 => 01.00 ...passed +S: 01.0011 => 01.01 ...passed +S: 01.011 => 01.10 ...passed +S: 01.0110 => 01.10 ...passed +S: 01.0111 => 01.10 ...passed +S: -01.001 => -01.00 ...passed +S: -01.0010 => -01.00 ...passed +S: -01.0011 => -01.01 ...passed +S: -01.011 => -01.10 ...passed +S: -01.0110 => -01.10 ...passed +S: -01.0111 => -01.10 ...passed + +---------------------- + With saturation +---------------------- + +* No rounding + +U: 101.0011 => 11.1111 ...passed +U: 1.001101 => 001. ...passed +U: 101.01 => 1.1 ...passed +U: 1010.1 => 11. ...passed +U: 101.11 => 101. ...passed +U: .11 => 0. ...passed +U: .1011 => 0.10 ...passed +U: 0.0000000001 => 0. ...passed +U: 1.0000000001 => 1.0 ...passed +U: 1.0000000001 => 1. ...passed +U: 10.000000001 => 10.000 ...passed +U: 1. => 1.00000000000000000 ...passed +U: 0. => 0.00000000000000000 ...passed +U: 1. => .111111111111111111 ...passed +U: 0. => .000000000000000000 ...passed +U: 10.101 => 010.1010 ...passed +U: 10.101 => 10.10 ...passed +U: 10.101 => 10.1010 ...passed +U: 1.0000 => .11111 ...passed +U: 01.000 => .11111 ...passed +U: 11.000 => .11111 ...passed +U: 0.1000 => .10000 ...passed +U: 00.100 => .10000 ...passed +U: 1.0001 => .11111 ...passed +U: 01.001 => .11111 ...passed +U: 01.010 => .11111 ...passed +U: 11.001 => .11111 ...passed +U: 0.1001 => .10010 ...passed +U: 00.101 => .10100 ...passed +U: 1.000000000000000001 => .111111111111111 ...passed +U: 01.00000000000000001 => .111111111111111 ...passed +U: 1.00000000000000 => .111111111111111 ...passed +S: -101.0011 => -11.1111 ...passed +S: 1.001101 => 001. ...passed +S: 101.01 => 1.1 ...passed +S: 1010.1 => 11. ...passed +S: 101.11 => 101. ...passed +S: .11 => 0. ...passed +S: .1011 => 0.10 ...passed +S: -0.0000000001 => 0. ...passed +S: -1.0000000001 => -1.0 ...passed +S: 1.0000000001 => 1. ...passed +S: 10.000000001 => 10.000 ...passed +S: 1. => 1.00000000000000000 ...passed +S: 0. => 0.00000000000000000 ...passed +S: -1. => -.111111111111111111 ...passed +S: 0. => .000000000000000000 ...passed +S: -10.101 => -010.1010 ...passed +S: -10.101 => -10.10 ...passed +S: -10.101 => -10.1010 ...passed +S: -1.0000 => -.11111 ...passed +S: -01.000 => -.11111 ...passed +S: -11.000 => -.11111 ...passed +S: -0.1000 => -.10000 ...passed +S: -00.100 => -.10000 ...passed +S: -1.0001 => -.11111 ...passed +S: -01.001 => -.11111 ...passed +S: -01.010 => -.11111 ...passed +S: -11.001 => -.11111 ...passed +S: -0.1001 => -.10010 ...passed +S: -00.101 => -.10100 ...passed +S: -1.000000000000000001 => -.111111111111111 ...passed +S: -01.00000000000000001 => -.111111111111111 ...passed +S: -1.00000000000000 => -.111111111111111 ...passed +S: 1.000000000000000001 => .111111111111111 ...passed +S: 01.00000000000000001 => .111111111111111 ...passed +S: 1.00000000000000 => .111111111111111 ...passed +S: 1.0000 => .11111 ...passed +S: 01.000 => .11111 ...passed +S: 0.1000 => .10000 ...passed +S: 00.100 => .10000 ...passed + +* Round to zero + +U: 101.0011 => 11.1111 ...passed +U: 1.001101 => 001. ...passed +U: 101.01 => 1.1 ...passed +U: 1010.1 => 11. ...passed +U: 101.11 => 101. ...passed +U: .11 => 0. ...passed +U: .1011 => 0.10 ...passed +U: 0.0000000001 => 0. ...passed +U: 1.0000000001 => 1.0 ...passed +U: 1.0000000001 => 1. ...passed +U: 10.000000001 => 10.000 ...passed +U: 1. => 1.00000000000000000 ...passed +U: 0. => 0.00000000000000000 ...passed +U: 1. => .111111111111111111 ...passed +U: 0. => .000000000000000000 ...passed +U: 10.101 => 010.1010 ...passed +U: 10.101 => 10.10 ...passed +U: 10.101 => 10.1010 ...passed +U: 1.000000000000000001 => .111111111111111 ...passed +U: 01.00000000000000001 => .111111111111111 ...passed +U: 1.00000000000000 => .111111111111111 ...passed +S: 101.0011 => 11.1111 ...passed +S: 1.001101 => 001. ...passed +S: 101.01 => 1.1 ...passed +S: 1010.1 => 11. ...passed +S: 101.11 => 101. ...passed +S: .11 => 0. ...passed +S: .1011 => 0.10 ...passed +S: 0.0000000001 => 0. ...passed +S: 1.0000000001 => 1.0 ...passed +S: 1.0000000001 => 1. ...passed +S: 10.000000001 => 10.000 ...passed +S: 1. => 1.00000000000000000 ...passed +S: 0. => 0.00000000000000000 ...passed +S: 1. => .111111111111111111 ...passed +S: 0. => .000000000000000000 ...passed +S: 10.101 => 010.1010 ...passed +S: 10.101 => 10.10 ...passed +S: 10.101 => 10.1010 ...passed +S: -1.000000000000000001 => -.111111111111111 ...passed +S: -01.00000000000000001 => -.111111111111111 ...passed +S: -1.00000000000000 => -.111111111111111 ...passed +S: 1.000000000000000001 => .111111111111111 ...passed +S: 01.00000000000000001 => .111111111111111 ...passed +S: 1.00000000000000 => .111111111111111 ...passed +S: 1.0000 => .11111 ...passed +S: 01.000 => .11111 ...passed +S: 0.1000 => .10000 ...passed +S: 00.100 => .10000 ...passed + +* Round to infinity + +U: 101.0011 => 11.1111 ...passed +U: 1.001101 => 010. ...passed +U: 101.01 => 1.1 ...passed +U: 1010.1 => 11. ...passed +U: 101.11 => 110. ...passed +U: .11 => 1. ...passed +U: .1011 => 0.11 ...passed +U: 0.0000000001 => 1. ...passed +U: 1.0000000001 => 1.1 ...passed +U: 1.0000000001 => 1. ...passed +U: 10.000000001 => 10.001 ...passed +U: 1. => 1.00000000000000000 ...passed +U: 0. => 0.00000000000000000 ...passed +U: 1. => .111111111111111111 ...passed +U: 0. => .000000000000000000 ...passed +U: 10.101 => 010.1010 ...passed +U: 10.101 => 10.11 ...passed +U: 10.101 => 10.1010 ...passed +U: 1.000000000000000001 => .111111111111111 ...passed +U: 01.00000000000000001 => .111111111111111 ...passed +U: 1.00000000000000 => .111111111111111 ...passed +S: 101.0011 => 11.1111 ...passed +S: 1.001101 => 010. ...passed +S: 101.01 => 1.1 ...passed +S: 1010.1 => 11. ...passed +S: 101.11 => 110. ...passed +S: .11 => 1. ...passed +S: .1011 => 0.11 ...passed +S: 0.0000000001 => 1. ...passed +S: 1.0000000001 => 1.1 ...passed +S: 1.0000000001 => 1. ...passed +S: 10.000000001 => 10.001 ...passed +S: 1. => 1.00000000000000000 ...passed +S: 0. => 0.00000000000000000 ...passed +S: 1. => .111111111111111111 ...passed +S: 0. => .000000000000000000 ...passed +S: 10.101 => 010.1010 ...passed +S: 10.101 => 10.11 ...passed +S: 10.101 => 10.1010 ...passed +S: -1.000000000000000001 => -.111111111111111 ...passed +S: -01.00000000000000001 => -.111111111111111 ...passed +S: -1.00000000000000 => -.111111111111111 ...passed +S: 1.000000000000000001 => .111111111111111 ...passed +S: 01.00000000000000001 => .111111111111111 ...passed +S: 1.00000000000000 => .111111111111111 ...passed +S: 1.0000 => .11111 ...passed +S: 01.000 => .11111 ...passed +S: 0.1000 => .10000 ...passed +S: 00.100 => .10000 ...passed + +* Round half up + +U: 101.0011 => 11.1111 ...passed +U: 1.001101 => 001. ...passed +U: 101.01 => 1.1 ...passed +U: 1010.1 => 11. ...passed +U: 101.11 => 110. ...passed +U: .11 => 1. ...passed +U: .1011 => 0.11 ...passed +U: 0.0000000001 => 0. ...passed +U: 1.0000000001 => 1.0 ...passed +U: 1.0000000001 => 1. ...passed +U: 10.000000001 => 10.000 ...passed +U: 1. => 1.00000000000000000 ...passed +U: 0. => 0.00000000000000000 ...passed +U: 1. => .111111111111111111 ...passed +U: 0. => .000000000000000000 ...passed +U: 10.101 => 010.1010 ...passed +U: 10.101 => 10.11 ...passed +U: 10.101 => 10.1010 ...passed +U: 1.000000000000000001 => .111111111111111 ...passed +U: 01.00000000000000001 => .111111111111111 ...passed +U: 1.00000000000000 => .111111111111111 ...passed +S: 101.0011 => 11.1111 ...passed +S: 1.001101 => 001. ...passed +S: 101.01 => 1.1 ...passed +S: 1010.1 => 11. ...passed +S: 101.11 => 110. ...passed +S: -.11 => -1. ...passed +S: -.1 => 0. ...passed +S: .1011 => 0.11 ...passed +S: 0.0000000001 => 0. ...passed +S: 1.0000000001 => 1.0 ...passed +S: 1.0000000001 => 1. ...passed +S: 10.000000001 => 10.000 ...passed +S: 1. => 1.00000000000000000 ...passed +S: 0. => 0.00000000000000000 ...passed +S: 1. => .111111111111111111 ...passed +S: 0. => .000000000000000000 ...passed +S: 10.101 => 010.1010 ...passed +S: 10.101 => 10.11 ...passed +S: 10.101 => 10.1010 ...passed +S: -1.000000000000000000 => -.111111111111111 ...passed +S: -1.000000000000000001 => -.111111111111111 ...passed +S: -01.00000000000000000 => -.111111111111111 ...passed +S: -01.00000000000000001 => -.111111111111111 ...passed +S: -01.0000000000000 => -.111111111111111 ...passed +S: -01.0000000000001 => -.111111111111111 ...passed +S: -01.0000000000000 => -.11111111111111 ...passed +S: -01.0000000000001 => -.11111111111111 ...passed +S: -01.0000000000000 => -.1111111111111111 ...passed +S: -01.0000000000001 => -.1111111111111111 ...passed +S: -00.1111111111111 => -.111111111111100 ...passed +S: -00.111111111111111 => -.11111111111111 ...passed +S: -00.111111111111111 => -1.0000000000000 ...passed +S: -1.000000000000000001 => -.111111111111111 ...passed +S: -01.00000000000000001 => -.111111111111111 ...passed +S: -1.0000000000000000001 => -.111111111111111 ...passed +S: -01.000000000000000001 => -.111111111111111 ...passed +S: -1.00000000000000000001 => -.111111111111111 ...passed +S: -01.0000000000000000001 => -.111111111111111 ...passed +S: -1.000000000000000000001 => -.111111111111111 ...passed +S: -01.00000000000000000001 => -.111111111111111 ...passed +S: -1.0000000000000000000001 => -.111111111111111 ...passed +S: -01.000000000000000000001 => -.111111111111111 ...passed +S: -1.000000000000000011 => -.111111111111111 ...passed +S: -01.00000000000000011 => -.111111111111111 ...passed +S: -1.0000000000000000011 => -.111111111111111 ...passed +S: -01.000000000000000011 => -.111111111111111 ...passed +S: -1.00000000000000000011 => -.111111111111111 ...passed +S: -01.0000000000000000011 => -.111111111111111 ...passed +S: -1.000000000000000000011 => -.111111111111111 ...passed +S: -01.00000000000000000011 => -.111111111111111 ...passed +S: -1.0000000000000000000011 => -.111111111111111 ...passed +S: -01.000000000000000000011 => -.111111111111111 ...passed +S: -1.00000000000000 => -.111111111111111 ...passed +S: 1.0000 => .11111 ...passed +S: 01.000 => .11111 ...passed +S: 0.1000 => .10000 ...passed +S: 00.100 => .10000 ...passed + +U: .10000000 + .01000000 = 0.11000000 ...passed +U: .01100000 + .01000000 = 0.10100000 ...passed +U: 0.0110000 - .01000000 = 0.00100000 ...passed +U: .10000000 + .01000000 = 0.11000000 ...passed +U: .10000000 - .01000000 = .01000000 ...passed +U: .01000000 + .01000000 = 0.10000000 ...passed +U: .01000000 - .01000000 = .00000000 ...passed +U: .0100 + 000.01000 = 000.10000 ...passed +U: 1.0000 + 1.0000 = 10.0000 ...passed +U: 0.1001 + 0.0110 = 00.1111 ...passed +U: 0.0011 + 0.0110 = 00.1001 ...passed +U: 0.1111 + 1.0001 = 10.0000 ...passed +U: 10.0000 - 1.0000 = 01.0000 ...passed +U: 00.1111 - 0.1001 = 00.0110 ...passed +U: 00.1001 - 0.0011 = 00.0110 ...passed +U: 10.0000 - 0.1111 = 01.0001 ...passed +U: .10000000 * 100.10000 = 10.01000000000000 ...passed +U: .10000000 * .10000000 = .0100000000000000 ...passed +U: 0.1000000 * .10000000 = .0100000000000000 ...passed +U: 0.1000000 * 0.1000000 = 00.01000000000000 ...passed +U: 0.1000000 * .10000000 = .0100000000000000 ...passed +U: 00.100000 * 0.1000000 = 000.0100000000000 ...passed +U: 01.1000000 * .10000000 = 0.1100000000000000 ...passed +U: .10000000 * 01.1000000 = 0.1100000000000000 ...passed +U: 01.100000 * .100000000 = 0.1100000000000000 ...passed +U: .100000000 * 01.100000 = 0.1100000000000000 ...passed +S: .011 + .0100000 = 0.1010000 ...passed +S: .0110000 - .0100000 = .0010000 ...passed +S: .1000000 + .0100000 = 0.1100000 ...passed +S: .1000000 - .0100000 = .0100000 ...passed +S: .0100000 + .0100000 = 0.1000000 ...passed +S: .0100000 - .0100000 = .0000000 ...passed +S: .010 + 000.0100 = 000.1000 ...passed +S: -.100 * 100.1000 = -10.010000000 ...passed +S: -.1000000 * .1000000 = -.010000000000000 ...passed +S: -0.100000 * .1000000 = -.010000000000000 ...passed +S: -0.100000 * 0.100000 = -00.0100000000000 ...passed +S: .100 * 100.1000 = 10.010000000 ...passed +S: .1000000 * .1000000 = .010000000000000 ...passed +S: 0.100000 * .1000000 = .010000000000000 ...passed +S: 0.100000 * 0.100000 = 00.0100000000000 ...passed +---------------------- + Arithmetic Test +---------------------- +Test finished + + +Positive ufixed +1.000 sla 0 = 1.000 +1.000 sla 1 = 0.000 +1.000 sla 2 = 0.000 +1.000 sla 3 = 0.000 +1.000 sla 4 = 0.000 + +1.000 sla 0 = 1.000 +1.000 sla -1 = 0.100 +1.000 sla -2 = 0.010 +1.000 sla -3 = 0.001 +1.000 sla -4 = 0.000 + +1.000 sra 0 = 1.000 +1.000 sra 1 = 0.100 +1.000 sra 2 = 0.010 +1.000 sra 3 = 0.001 +1.000 sra 4 = 0.000 + +1.000 sra 0 = 1.000 +1.000 sra -1 = 0.000 +1.000 sra -2 = 0.000 +1.000 sra -3 = 0.000 +1.000 sra -4 = 0.000 + +Positive sfixed +1.000 sla 0 = 1.000 +1.000 sla 1 = 0.000 +1.000 sla 2 = 0.000 +1.000 sla 3 = 0.000 +1.000 sla 4 = 0.000 +1.000 sla 5 = 0.000 + +1.000 sla 0 = 1.000 +1.000 sla -1 = 0.100 +1.000 sla -2 = 0.010 +1.000 sla -3 = 0.001 +1.000 sla -4 = 0.000 +1.000 sla -5 = 0.000 + +1.000 sra 0 = 1.000 +1.000 sra 1 = 0.100 +1.000 sra 2 = 0.010 +1.000 sra 3 = 0.001 +1.000 sra 4 = 0.000 +1.000 sra 5 = 0.000 + +1.000 sra 0 = 1.000 +1.000 sra -1 = 0.000 +1.000 sra -2 = 0.000 +1.000 sra -3 = 0.000 +1.000 sra -4 = 0.000 +1.000 sra -5 = 0.000 + +Negative sfixed +-1.000 sla 0 = -1.000 +-1.000 sla 1 = -0.000 +-1.000 sla 2 = -0.000 +-1.000 sla 3 = -0.000 +-1.000 sla 4 = 0.000 +-1.000 sla 5 = 0.000 + +-1.000 sla 0 = -1.000 +-1.000 sla -1 = -0.100 +-1.000 sla -2 = -0.010 +-1.000 sla -3 = -0.001 +-1.000 sla -4 = 0.000 +-1.000 sla -5 = 0.000 + +-1.000 sra 0 = -1.000 +-1.000 sra 1 = -0.100 +-1.000 sra 2 = -0.010 +-1.000 sra 3 = -0.001 +-1.000 sra 4 = 0.000 +-1.000 sra 5 = 0.000 + +-1.000 sra 0 = -1.000 +-1.000 sra -1 = -0.000 +-1.000 sra -2 = -0.000 +-1.000 sra -3 = -0.000 +-1.000 sra -4 = 0.000 +-1.000 sra -5 = 0.000 + +Positive ufixed +1.001 sla 0 = 1.001 +1.001 sla 1 = 0.010 +1.001 sla 2 = 0.100 +1.001 sla 3 = 1.000 +1.001 sla 4 = 0.000 + +1.001 sla 0 = 1.001 +1.001 sla -1 = 0.100 +1.001 sla -2 = 0.010 +1.001 sla -3 = 0.001 +1.001 sla -4 = 0.000 + +1.001 sra 0 = 1.001 +1.001 sra 1 = 0.100 +1.001 sra 2 = 0.010 +1.001 sra 3 = 0.001 +1.001 sra 4 = 0.000 + +1.001 sra 0 = 1.001 +1.001 sra -1 = 0.010 +1.001 sra -2 = 0.100 +1.001 sra -3 = 1.000 +1.001 sra -4 = 0.000 + +Positive sfixed +1.001 sla 0 = 1.001 +1.001 sla 1 = 0.010 +1.001 sla 2 = 0.100 +1.001 sla 3 = 1.000 +1.001 sla 4 = 0.000 +1.001 sla 5 = 0.000 + +1.001 sla 0 = 1.001 +1.001 sla -1 = 0.100 +1.001 sla -2 = 0.010 +1.001 sla -3 = 0.001 +1.001 sla -4 = 0.000 +1.001 sla -5 = 0.000 + +1.001 sra 0 = 1.001 +1.001 sra 1 = 0.100 +1.001 sra 2 = 0.010 +1.001 sra 3 = 0.001 +1.001 sra 4 = 0.000 +1.001 sra 5 = 0.000 + +1.001 sra 0 = 1.001 +1.001 sra -1 = 0.010 +1.001 sra -2 = 0.100 +1.001 sra -3 = 1.000 +1.001 sra -4 = 0.000 +1.001 sra -5 = 0.000 + +Negative sfixed +-1.001 sla 0 = -1.001 +-1.001 sla 1 = -0.010 +-1.001 sla 2 = -0.100 +-1.001 sla 3 = -1.000 +-1.001 sla 4 = 0.000 +-1.001 sla 5 = 0.000 + +-1.001 sla 0 = -1.001 +-1.001 sla -1 = -0.100 +-1.001 sla -2 = -0.010 +-1.001 sla -3 = -0.001 +-1.001 sla -4 = 0.000 +-1.001 sla -5 = 0.000 + +-1.001 sra 0 = -1.001 +-1.001 sra 1 = -0.100 +-1.001 sra 2 = -0.010 +-1.001 sra 3 = -0.001 +-1.001 sra 4 = 0.000 +-1.001 sra 5 = 0.000 + +-1.001 sra 0 = -1.001 +-1.001 sra -1 = -0.010 +-1.001 sra -2 = -0.100 +-1.001 sra -3 = -1.000 +-1.001 sra -4 = 0.000 +-1.001 sra -5 = 0.000 +Positive ufixed +U'length = 10 +U'high(left) = -1(-1) +U'low(right) = -10(-10) +U'value = B.0100000000 +U'value = 2.5e-1 + +U'length = 10 +U'high(left) = -1(-1) +U'low(right) = -10(-10) +U'value = B.0100000000 +U'value = 2.5e-1 + +U'length = 10 +U'high(left) = -1(-1) +U'low(right) = -10(-10) +U'value = B.0100000000 +U'value = 2.5e-1 + +U'length = 10 +U'high(left) = 1(1) +U'low(right) = -8(-8) +U'value = B00.01000000 +U'value = 2.5e-1 + +U'length = 10 +U'high(left) = 0(0) +U'low(right) = -9(-9) +U'value = B0.010000000 +U'value = 2.5e-1 + +U'length = 10 +U'high(left) = 0(0) +U'low(right) = -9(-9) +U'value = B0.010000000 +U'value = 2.5e-1 + +Positive sfixed +S'length = 10 +S'high(left) = 0(0) +S'low(right) = -9(-9) +S'value = B.010000000 +S'value = 2.5e-1 + +S'length = 10 +S'high(left) = 0(0) +S'low(right) = -9(-9) +S'value = B.010000000 +S'value = 2.5e-1 + +S'length = 10 +S'high(left) = 0(0) +S'low(right) = -9(-9) +S'value = B.010000000 +S'value = 2.5e-1 + +S'length = 10 +S'high(left) = 2(2) +S'low(right) = -7(-7) +S'value = B00.0100000 +S'value = 2.5e-1 + +S'length = 10 +S'high(left) = 1(1) +S'low(right) = -8(-8) +S'value = B0.01000000 +S'value = 2.5e-1 + +S'length = 10 +S'high(left) = 1(1) +S'low(right) = -8(-8) +S'value = B0.01000000 +S'value = 2.5e-1 + +Neg/Pos sfixed +S'length = 10 +S'high(left) = 0(0) +S'low(right) = -9(-9) +S'value = B-.010000000 +S'value = -2.5e-1 + +S'length = 10 +S'high(left) = 0(0) +S'low(right) = -9(-9) +S'value = B-.010000000 +S'value = -2.5e-1 + +S'length = 10 +S'high(left) = 0(0) +S'low(right) = -9(-9) +S'value = B-.010000000 +S'value = -2.5e-1 + +S'length = 10 +S'high(left) = 2(2) +S'low(right) = -7(-7) +S'value = B-00.0100000 +S'value = -2.5e-1 + +S'length = 10 +S'high(left) = 1(1) +S'low(right) = -8(-8) +S'value = B-0.01000000 +S'value = -2.5e-1 + +S'length = 10 +S'high(left) = 1(1) +S'low(right) = -8(-8) +S'value = B-0.01000000 +S'value = -2.5e-1 + +Pos/Neg sfixed +S'length = 10 +S'high(left) = 0(0) +S'low(right) = -9(-9) +S'value = B-.010000000 +S'value = -2.5e-1 + +S'length = 10 +S'high(left) = 0(0) +S'low(right) = -9(-9) +S'value = B-.010000000 +S'value = -2.5e-1 + +S'length = 10 +S'high(left) = 0(0) +S'low(right) = -9(-9) +S'value = B-.010000000 +S'value = -2.5e-1 + +S'length = 10 +S'high(left) = 2(2) +S'low(right) = -7(-7) +S'value = B-00.0100000 +S'value = -2.5e-1 + +S'length = 10 +S'high(left) = 1(1) +S'low(right) = -8(-8) +S'value = B-0.01000000 +S'value = -2.5e-1 + +S'length = 10 +S'high(left) = 1(1) +S'low(right) = -8(-8) +S'value = B-0.01000000 +S'value = -2.5e-1 + +Neg/Neg sfixed +S'length = 10 +S'high(left) = 0(0) +S'low(right) = -9(-9) +S'value = B.010000000 +S'value = 2.5e-1 + +S'length = 10 +S'high(left) = 0(0) +S'low(right) = -9(-9) +S'value = B.010000000 +S'value = 2.5e-1 + +S'length = 10 +S'high(left) = 0(0) +S'low(right) = -9(-9) +S'value = B.010000000 +S'value = 2.5e-1 + +S'length = 10 +S'high(left) = 2(2) +S'low(right) = -7(-7) +S'value = B00.0100000 +S'value = 2.5e-1 + +S'length = 10 +S'high(left) = 1(1) +S'low(right) = -8(-8) +S'value = B0.01000000 +S'value = 2.5e-1 + +S'length = 10 +S'high(left) = 1(1) +S'low(right) = -8(-8) +S'value = B0.01000000 +S'value = 2.5e-1 + +Test 1.1001000: +Test 1.100100: +Test -1.100100: +Test 00.011001: +Test 00.01100: +Test -00.01100: +Integer Test 00.00000: +R: Bit 11.110010: +U: Bit 11.110010: +S: Bit 11.110010: +S: Bit 00.001110: +S: Bit 3.50: +S: Bit -242: +S1'length = 130 +S1'high(left) = 13(13) +S1'low(right) = -116(-116) +S1'value = B0111101010101.01100010110111010011100101101101011111010101101000110100101010101010111011010000111011000110000101000001010010100111 +S1'value = 3.925386188115339e3 + +S2'length = 130 +S2'high(left) = 13(13) +S2'low(right) = -116(-116) +S2'value = B0010110111011.11100001100111000100101000110101111111101101000100001110010011100111000110110110010100101001010010100111100011000010 +S2'value = 1.467881291044409e3 + +R1'length = 260 +R1'high(left) = 26(26) +R1'low(right) = -233(-233) +R1'value = B00010101111110101111010000.11110010000101101010111100111010001101011101111110010111000100110100001101100001011110100000111111111110100001011011101000011010000101001110100001100100111111111100101000111011011011111100111000001011001111000010101111101110100011100 +R1'value = 5.762000945658637e6 + diff --git a/projects/eval_fixed_ja/src/eval_fixed_ja.vhd b/projects/eval_fixed_ja/src/eval_fixed_ja.vhd new file mode 100644 index 0000000..d5a2eda --- /dev/null +++ b/projects/eval_fixed_ja/src/eval_fixed_ja.vhd @@ -0,0 +1,89 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 00:28:57 07/10/2006 +-- Design Name: +-- Module Name: adder_registered - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; + +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +use IEEE.MATH_REAL.ALL; +use std.textio.all; -- Imports the standard textio package. + +library work; +use work.fixed_ja.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity eval_fixed_ja is + Generic ( + nbits : integer := 32; + nbits_int : integer := 2); +end eval_fixed_ja; + +architecture Behavioral of eval_fixed_ja is +--------------------------------------------------------------------- + +type my_range is range 0 downto -10; + +begin + +process +constant c1 : ufixed_t (0 downto -10) := "11111111000"; +constant c2 : ufixed_t := to_ufixed(3.141592654, nbits, 4); +constant c3 : ufixed_t := to_ufixed(1.0/3.141592654, nbits, 1); +variable t1 : ufixed_t (uproto(8,1)'range); +variable L : line; + +variable slv : string (15 downto 1) := (others => '-'); +constant jens : string (10 downto 7) := "JENS"; + + +begin + + +-- slv := (1 => '1', 2 => 'J', jens'range => jens(jens'range), others => '1'); + + slv(jens'range) := "Jens"; + slv(jens'range) := jens; + + print_info(c2, "c2"); + print_info(c3, "c3"); + + t1 := to_ufixed(c1, t1, round_to_zero, saturate); + print_info(c1, "c1"); + print_info(t1, "t1"); + + t1 := to_ufixed(c1, t1, round_half_up, saturate); + print_info(c1, "c1"); + print_info(t1, "t1"); + + print_info(to_ufixed(c2*c2, 32, 2, none, saturate), "c2*c2"); + print_info(to_ufixed(c2*c3, 32, 0, round_half_up, none), "c2*c3"); + + write (L, slv); + writeline (output, L); + + wait; +end process; + +--------------------------------------------------------------------- +end Behavioral; + diff --git a/projects/eval_fixed_ja/src/eval_fixed_ja_syn.vhd b/projects/eval_fixed_ja/src/eval_fixed_ja_syn.vhd new file mode 100644 index 0000000..f8b093e --- /dev/null +++ b/projects/eval_fixed_ja/src/eval_fixed_ja_syn.vhd @@ -0,0 +1,80 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 00:28:57 07/10/2006 +-- Design Name: +-- Module Name: adder_registered - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; + +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library ieee_proposed; +use ieee_proposed.fixed_pkg.all; +use std.textio.all; -- Imports the standard textio package. + +library work; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity eval_fixed_ja is + Generic ( + nbits : integer := 8; + nbits_int : integer := 0 + ); + Port + ( + srst : in std_logic; + clk : in std_logic; + di1 : in std_logic_vector(nbits-1 downto 0); + di2 : in std_logic_vector(nbits-1 downto 0); + in_valid : in std_logic; + do : out std_logic_vector(nbits-1 downto 0); + out_valid : out std_logic + ); + +end eval_fixed_ja; + +architecture Behavioral of eval_fixed_ja is +signal op1, op2 : sfixed(nbits_int downto -(nbits-1)); +signal result : sfixed(2*nbits_int downto -(2*nbits-1)); +begin + +op1 <= to_sfixed(di1, op1); +op2 <= to_sfixed(di2, op2); + +do <= to_slv(resize(result, op1, false, false)); + +--------------------------------------------------------------------- +process(srst, clk, in_valid, di1, di2) +begin + if rising_edge(clk) then + if srst = '1' then + result <= (others => '0'); + elsif in_valid = '1' then + result <= op1 * op2; + end if; + out_valid <= in_valid; + end if; +end process; + + +--------------------------------------------------------------------- +end Behavioral; + diff --git a/projects/eval_fixed_ja/src/tb_eval_fixed_ja.vhd b/projects/eval_fixed_ja/src/tb_eval_fixed_ja.vhd new file mode 100644 index 0000000..4f8f2d6 --- /dev/null +++ b/projects/eval_fixed_ja/src/tb_eval_fixed_ja.vhd @@ -0,0 +1,1033 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 00:28:57 07/10/2006 +-- Design Name: +-- Module Name: tb_eval_fixed_ja - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; + +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +use IEEE.MATH_REAL.ALL; +use std.textio.all; -- Imports the standard textio package. + +library work; +use work.fixed_ja.all; +use work.PCK_FIO.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity tb_eval_fixed_ja is + Generic ( + nbits : integer := 32; + nbits_int : integer := 2; + halt_on_error : boolean := true); + +end tb_eval_fixed_ja; + +architecture Behavioral of tb_eval_fixed_ja is +--------------------------------------------------------------------- + +type my_range is range 0 downto -10; + +--------------------------------------------------------------------- +procedure PerformRoundTest (op1 : in ufixed_t; required : in ufixed_t; rnd : in round_mode_t; sat : in saturate_mode_t) is +variable result : ufixed_t(required'range); +variable bad_result : boolean := false; + +variable L : line; +begin + + result := to_ufixed(op1, required, rnd, sat); + bad_result := not(result = required); + + write (L, "U: " & to_string(op1) & " => " & to_string(result)); + + if bad_result then + write (L, String'(" ...failed")); + writeline (output, L); + writeline (output, L); + write (L, String'("Bad result. Should be:") & CR & LF); + write (L, to_string(op1) & " => " & to_string(required)); + writeline (output, L); + writeline (output, L); + else + write (L, String'(" ...passed")); + writeline (output, L); + end if; + + assert not (bad_result and halt_on_error) report "Test failed" severity error; + +end PerformRoundTest; + +--------------------------------------------------------------------- +procedure PerformRoundTest (op1 : in sfixed_t; required : in sfixed_t; rnd : in round_mode_t; sat : in saturate_mode_t) is +variable result : sfixed_t(required'range); +variable bad_result : boolean := false; + +variable L : line; +begin + + result := to_sfixed(op1, required, rnd, sat); + bad_result := not(result = required); + + write (L, "S: " & to_string(op1) & " => " & to_string(result)); + + if bad_result then + write (L, String'(" ...failed")); + writeline (output, L); + writeline (output, L); + write (L, String'("Bad result. Should be:") & CR & LF); + write (L, to_string(op1) & " => " & to_string(required)); + writeline (output, L); + writeline (output, L); + else + write (L, String'(" ...passed")); + writeline (output, L); + end if; + + assert not (bad_result and halt_on_error) report "Test failed" severity error; + +end PerformRoundTest; + +--------------------------------------------------------------------- +procedure PerformArithTest (op1 : in ufixed_t; op : in character; op2 : in ufixed_t; required : in ufixed_t) is +variable result : ufixed_t(required'range); +variable bad_result : boolean := false; + +variable L : line; +begin + + case op is + when '+' => + result := op1 + op2; + + when '-' => + result := op1 - op2; + + when '*' => + result := op1 * op2; + + when others => + assert false report "PerformArithTest: Bad operand" severity error; + + end case; + + bad_result := not(result = required); + + write (L, "U: " & to_string(op1) & " " & op & " " & to_string(op2) & " = " & to_string(result)); + + if bad_result then + write (L, String'(" ...failed")); + writeline (output, L); + writeline (output, L); + write (L, String'("Bad result. Should be:") & CR & LF); + write (L, to_string(op1) & " " & op & " " & to_string(op2) & " = " & to_string(required)); + writeline (output, L); + writeline (output, L); + else + write (L, String'(" ...passed")); + writeline (output, L); + end if; + + assert not (bad_result and halt_on_error) report "Test failed" severity error; + +end PerformArithTest; + +--------------------------------------------------------------------- +procedure PerformArithTest (op1 : in sfixed_t; op : in character; op2 : in sfixed_t; required : in sfixed_t) is +variable result : sfixed_t(required'range); +variable bad_result : boolean := false; + +variable L : line; +begin + + case op is + when '+' => + result := op1 + op2; + + when '-' => + result := op1 - op2; + + when '*' => + result := op1 * op2; + + when others => + assert false report "PerformArithTest: Bad operand" severity error; + + end case; + + bad_result := not(result = required); + + write (L, "S: " & to_string(op1) & " " & op & " " & to_string(op2) & " = " & to_string(result)); + + if bad_result then + write (L, String'(" ...failed")); + writeline (output, L); + writeline (output, L); + write (L, String'("Bad result. Should be:") & CR & LF); + write (L, to_string(op1) & " " & op & " " & to_string(op2) & " = " & to_string(required)); + writeline (output, L); + writeline (output, L); + else + write (L, String'(" ...passed")); + writeline (output, L); + end if; + + assert not (bad_result and halt_on_error) report "Test failed" severity error; + +end PerformArithTest; + +--------------------------------------------------------------------- +begin + +process + +variable rnd : round_mode_t := none; +variable sat : saturate_mode_t := none; +file RESULT: text open write_mode is "STD_OUTPUT"; +file file_sum_test_u: text open write_mode is "sum_test_u.txt"; +file file_sum_test_s: text open write_mode is "sum_test_s.txt"; +variable L, STR: line; +constant uconst0 : ufixed_t := to_ufixed(string'("1.000")); +constant sconst0 : sfixed_t := to_sfixed(string'("1.000")); +constant uconst1 : ufixed_t := to_ufixed(string'("1.001")); +constant sconst1 : sfixed_t := to_sfixed(string'("1.001")); +constant s1 : sfixed_t := to_sfixed(string'("0111101010101.01100010110111010011100101101101011111010101101000110100101010101010111011010000111011000110000101000001010010100111")); +constant s2 : sfixed_t := to_sfixed(string'("0010110111011.11100001100111000100101000110101111111101101000100001110010011100111000110110110010100101001010010100111100011000010")); +variable r1 : sfixed_t(sproto(s1, '*', s2)'range); +variable ures : ufixed_t(uconst0'range); +variable sres : sfixed_t(sconst0'range); +constant incu : ufixed_t := to_ufixed(string'(".0000001")); +variable yu : ufixed_t(uproto(4,0)'range); +variable xu : ufixed_t(uproto(8,1)'range); +constant incs : sfixed_t := to_sfixed(string'(".0000001")); +variable ys : sfixed_t(sproto(5,0)'range); +variable xs : sfixed_t(sproto(9,1)'range); +begin + +-- slv := (1 => '1', 2 => 'J', jens'range => jens(jens'range), others => '1'); + + rnd := round_nearest; + sat := saturate; + + -- 1.) Sum test + xu := to_ufixed(0, xu); + for i in 0 to 2**xu'length-1 loop + yu := to_ufixed(xu, yu, rnd, sat); + fprint(file_sum_test_u, L,"%s %s\n", REAL'image(to_real(xu)), REAL'image(to_real(yu))); +-- fprint(file_sum_test_u, L,"%s %s\n", to_string(xu), to_string(yu)); + xu := xu + 1; + end loop; + xs := to_sfixed(-(2**(xs'length-1)-1), xs); + for i in 0 to 2**xs'length-1 loop + ys := to_sfixed(xs, ys, rnd, sat); + fprint(file_sum_test_s, L,"%s %s\n", REAL'image(to_real(xs)), REAL'image(to_real(ys))); +-- fprint(file_sum_test_s, L,"%s %s\n", to_string(xs), to_string(ys)); + xs := xs + 1; + end loop; + + write (L, String'("Fixed Point Library Testbench 0.1")); + writeline (output, L); + + write (L, String'("----------------------" & CR & LF)); + write (L, String'(" Without saturation " & CR & LF)); + write (L, String'("----------------------" & CR & LF)); + writeline (output, L); + + --------------------------------------------------------------------- + write (L, String'("* No rounding" & CR & LF)); + writeline (output, L); + + rnd := none; + sat := none; + + PerformRoundTest (to_ufixed(string'("101.0011")), to_ufixed(string'("01.0011")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.001101")), to_ufixed(string'("001.")), rnd, sat); + PerformRoundTest (to_ufixed(string'("101.01")), to_ufixed(string'("1.0")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1010.1")), to_ufixed(string'("10.")), rnd, sat); + PerformRoundTest (to_ufixed(string'("101.11")), to_ufixed(string'("101.")), rnd, sat); + PerformRoundTest (to_ufixed(string'(".11")), to_ufixed(string'("0.")), rnd, sat); + PerformRoundTest (to_ufixed(string'(".1011")), to_ufixed(string'("0.10")), rnd, sat); + PerformRoundTest (to_ufixed(string'("0.0000000001")), to_ufixed(string'("0.")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.0000000001")), to_ufixed(string'("1.0")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.0000000001")), to_ufixed(string'("1.")), rnd, sat); + PerformRoundTest (to_ufixed(string'("10.000000001")), to_ufixed(string'("10.000")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.")), to_ufixed(string'("1.00000000000000000")), rnd, sat); + PerformRoundTest (to_ufixed(string'("0.")), to_ufixed(string'("0.00000000000000000")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.")), to_ufixed(string'(".000000000000000000")), rnd, sat); + PerformRoundTest (to_ufixed(string'("0.")), to_ufixed(string'(".000000000000000000")), rnd, sat); + PerformRoundTest (to_ufixed(string'("10.101")), to_ufixed(string'("010.1010")), rnd, sat); + PerformRoundTest (to_ufixed(string'("10.101")), to_ufixed(string'("10.10")), rnd, sat); + PerformRoundTest (to_ufixed(string'("10.101")), to_ufixed(string'("10.1010")), rnd, sat); + + PerformRoundTest (to_sfixed(string'("101.0011")), to_sfixed(string'("01.0011")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-1.001101")), to_sfixed(string'("-001.")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-101.01")), to_sfixed(string'("-1.0")), rnd, sat); + PerformRoundTest (to_sfixed(string'("1010.1")), to_sfixed(string'("10.")), rnd, sat); + PerformRoundTest (to_sfixed(string'("101.11")), to_sfixed(string'("101.")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-.11")), to_sfixed(string'("0.")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-.1011")), to_sfixed(string'("-0.10")), rnd, sat); + PerformRoundTest (to_sfixed(string'("0.0000000001")), to_sfixed(string'("0.")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-1.0000000001")), to_sfixed(string'("-1.0")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-1.0000000001")), to_sfixed(string'("-1.")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-10.000000001")), to_sfixed(string'("-10.000")), rnd, sat); + PerformRoundTest (to_sfixed(string'("1.")), to_sfixed(string'("1.00000000000000000")), rnd, sat); + PerformRoundTest (to_sfixed(string'("0.")), to_sfixed(string'("0.00000000000000000")), rnd, sat); + PerformRoundTest (to_sfixed(string'("1.")), to_sfixed(string'(".000000000000000000")), rnd, sat); + PerformRoundTest (to_sfixed(string'("0.")), to_sfixed(string'(".000000000000000000")), rnd, sat); + PerformRoundTest (to_sfixed(string'("10.101")), to_sfixed(string'("010.1010")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-10.101")), to_sfixed(string'("-10.10")), rnd, sat); + PerformRoundTest (to_sfixed(string'("10.101")), to_sfixed(string'("10.1010")), rnd, sat); + + --------------------------------------------------------------------- + writeline (output, L); + write (L, String'("* Round to zero" & CR & LF)); + writeline (output, L); + + rnd := round_to_zero; + sat := none; + + PerformRoundTest (to_ufixed(string'("101.0011")), to_ufixed(string'("01.0011")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.001101")), to_ufixed(string'("001.")), rnd, sat); + PerformRoundTest (to_ufixed(string'("101.01")), to_ufixed(string'("1.0")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1010.1")), to_ufixed(string'("10.")), rnd, sat); + PerformRoundTest (to_ufixed(string'("101.11")), to_ufixed(string'("101.")), rnd, sat); + PerformRoundTest (to_ufixed(string'(".11")), to_ufixed(string'("0.")), rnd, sat); + PerformRoundTest (to_ufixed(string'(".1011")), to_ufixed(string'("0.10")), rnd, sat); + PerformRoundTest (to_ufixed(string'("0.0000000001")), to_ufixed(string'("0.")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.0000000001")), to_ufixed(string'("1.0")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.0000000001")), to_ufixed(string'("1.")), rnd, sat); + PerformRoundTest (to_ufixed(string'("10.000000001")), to_ufixed(string'("10.000")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.")), to_ufixed(string'("1.00000000000000000")), rnd, sat); + PerformRoundTest (to_ufixed(string'("0.")), to_ufixed(string'("0.00000000000000000")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.")), to_ufixed(string'(".000000000000000000")), rnd, sat); + PerformRoundTest (to_ufixed(string'("0.")), to_ufixed(string'(".000000000000000000")), rnd, sat); + PerformRoundTest (to_ufixed(string'("10.101")), to_ufixed(string'("010.1010")), rnd, sat); + PerformRoundTest (to_ufixed(string'("10.101")), to_ufixed(string'("10.10")), rnd, sat); + PerformRoundTest (to_ufixed(string'("10.101")), to_ufixed(string'("10.1010")), rnd, sat); + + PerformRoundTest (to_sfixed(string'("101.0011")), to_sfixed(string'("01.0011")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-1.001101")), to_sfixed(string'("-001.")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-101.01")), to_sfixed(string'("-1.0")), rnd, sat); + PerformRoundTest (to_sfixed(string'("1010.1")), to_sfixed(string'("10.")), rnd, sat); + PerformRoundTest (to_sfixed(string'("101.11")), to_sfixed(string'("101.")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-.11")), to_sfixed(string'("0.")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-.1011")), to_sfixed(string'("-0.10")), rnd, sat); + PerformRoundTest (to_sfixed(string'("0.0000000001")), to_sfixed(string'("0.")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-1.0000000001")), to_sfixed(string'("-1.0")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-1.0000000001")), to_sfixed(string'("-1.")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-10.000000001")), to_sfixed(string'("-10.000")), rnd, sat); + PerformRoundTest (to_sfixed(string'("1.")), to_sfixed(string'("1.00000000000000000")), rnd, sat); + PerformRoundTest (to_sfixed(string'("0.")), to_sfixed(string'("0.00000000000000000")), rnd, sat); + PerformRoundTest (to_sfixed(string'("1.")), to_sfixed(string'(".000000000000000000")), rnd, sat); + PerformRoundTest (to_sfixed(string'("0.")), to_sfixed(string'(".000000000000000000")), rnd, sat); + PerformRoundTest (to_sfixed(string'("10.101")), to_sfixed(string'("010.1010")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-10.101")), to_sfixed(string'("-10.10")), rnd, sat); + PerformRoundTest (to_sfixed(string'("10.101")), to_sfixed(string'("10.1010")), rnd, sat); + + --------------------------------------------------------------------- + + writeline (output, L); + write (L, String'("* Round to infinity" & CR & LF)); + writeline (output, L); + + rnd := round_pos_infinity; + sat := none; + + PerformRoundTest (to_ufixed(string'("101.0011")), to_ufixed(string'("01.0011")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.001101")), to_ufixed(string'("010.")), rnd, sat); + PerformRoundTest (to_ufixed(string'("101.01")), to_ufixed(string'("1.1")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1010.1")), to_ufixed(string'("11.")), rnd, sat); + PerformRoundTest (to_ufixed(string'("101.11")), to_ufixed(string'("110.")), rnd, sat); + PerformRoundTest (to_ufixed(string'(".11")), to_ufixed(string'("1.")), rnd, sat); + PerformRoundTest (to_ufixed(string'(".1011")), to_ufixed(string'("0.11")), rnd, sat); + PerformRoundTest (to_ufixed(string'("0.0000000001")), to_ufixed(string'("1.")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.0000000001")), to_ufixed(string'("1.1")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.0000000001")), to_ufixed(string'("0.")), rnd, sat); + PerformRoundTest (to_ufixed(string'("10.000000001")), to_ufixed(string'("10.001")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.")), to_ufixed(string'("1.00000000000000000")), rnd, sat); + PerformRoundTest (to_ufixed(string'("0.")), to_ufixed(string'("0.00000000000000000")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.")), to_ufixed(string'(".000000000000000000")), rnd, sat); + PerformRoundTest (to_ufixed(string'("0.")), to_ufixed(string'(".000000000000000000")), rnd, sat); + PerformRoundTest (to_ufixed(string'("10.101")), to_ufixed(string'("010.1010")), rnd, sat); + PerformRoundTest (to_ufixed(string'("10.101")), to_ufixed(string'("10.11")), rnd, sat); + PerformRoundTest (to_ufixed(string'("10.101")), to_ufixed(string'("10.1010")), rnd, sat); + + PerformRoundTest (to_sfixed(string'("101.0011")), to_sfixed(string'("01.0011")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-10.001101")), to_sfixed(string'("-010.")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-101.01")), to_sfixed(string'("-1.0")), rnd, sat); + PerformRoundTest (to_sfixed(string'("1010.1")), to_sfixed(string'("11.")), rnd, sat); + PerformRoundTest (to_sfixed(string'("101.11")), to_sfixed(string'("110.")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-.11")), to_sfixed(string'("0.")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-.1011")), to_sfixed(string'("-0.10")), rnd, sat); + PerformRoundTest (to_sfixed(string'("0.0000000001")), to_sfixed(string'("1.")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-1.0000000001")), to_sfixed(string'("-1.0")), rnd, sat); + PerformRoundTest (to_sfixed(string'("1.0000000001")), to_sfixed(string'("0.")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-10.000000001")), to_sfixed(string'("-10.000")), rnd, sat); + PerformRoundTest (to_sfixed(string'("1.")), to_sfixed(string'("1.00000000000000000")), rnd, sat); + PerformRoundTest (to_sfixed(string'("0.")), to_sfixed(string'("0.00000000000000000")), rnd, sat); + PerformRoundTest (to_sfixed(string'("1.")), to_sfixed(string'(".000000000000000000")), rnd, sat); + PerformRoundTest (to_sfixed(string'("0.")), to_sfixed(string'(".000000000000000000")), rnd, sat); + PerformRoundTest (to_sfixed(string'("10.101")), to_sfixed(string'("010.1010")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-10.101")), to_sfixed(string'("-10.10")), rnd, sat); + PerformRoundTest (to_sfixed(string'("10.101")), to_sfixed(string'("10.1010")), rnd, sat); + + --------------------------------------------------------------------- + writeline (output, L); + write (L, String'("* Round half up" & CR & LF)); + writeline (output, L); + + rnd := round_half_up; + sat := none; + + PerformRoundTest (to_ufixed(string'("101.0011")), to_ufixed(string'("01.0011")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.001101")), to_ufixed(string'("001.")), rnd, sat); + PerformRoundTest (to_ufixed(string'("101.01")), to_ufixed(string'("1.1")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1010.1")), to_ufixed(string'("11.")), rnd, sat); + PerformRoundTest (to_ufixed(string'("101.11")), to_ufixed(string'("110.")), rnd, sat); + PerformRoundTest (to_ufixed(string'(".11")), to_ufixed(string'("1.")), rnd, sat); + PerformRoundTest (to_ufixed(string'(".1011")), to_ufixed(string'("0.11")), rnd, sat); + PerformRoundTest (to_ufixed(string'("0.0000000001")), to_ufixed(string'("0.")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.0000000001")), to_ufixed(string'("1.0")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.0000000001")), to_ufixed(string'("1.")), rnd, sat); + PerformRoundTest (to_ufixed(string'("10.000000001")), to_ufixed(string'("10.000")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.")), to_ufixed(string'("1.00000000000000000")), rnd, sat); + PerformRoundTest (to_ufixed(string'("0.")), to_ufixed(string'("0.00000000000000000")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.")), to_ufixed(string'(".000000000000000000")), rnd, sat); + PerformRoundTest (to_ufixed(string'("0.")), to_ufixed(string'(".000000000000000000")), rnd, sat); + PerformRoundTest (to_ufixed(string'("10.101")), to_ufixed(string'("010.1010")), rnd, sat); + PerformRoundTest (to_ufixed(string'("10.101")), to_ufixed(string'("10.11")), rnd, sat); + PerformRoundTest (to_ufixed(string'("10.101")), to_ufixed(string'("10.1010")), rnd, sat); + + PerformRoundTest (to_sfixed(string'("101.0011")), to_sfixed(string'("01.0011")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-10.001101")), to_sfixed(string'("-010.")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-101.01")), to_sfixed(string'("-1.0")), rnd, sat); + PerformRoundTest (to_sfixed(string'("1010.1")), to_sfixed(string'("11.")), rnd, sat); + PerformRoundTest (to_sfixed(string'("101.11")), to_sfixed(string'("110.")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-.11")), to_sfixed(string'("-1.")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-.1011")), to_sfixed(string'("-0.11")), rnd, sat); + PerformRoundTest (to_sfixed(string'("0.0000000001")), to_sfixed(string'("0.")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-1.0000000001")), to_sfixed(string'("-1.0")), rnd, sat); + PerformRoundTest (to_sfixed(string'("1.0000000001")), to_sfixed(string'("1.")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-10.000000001")), to_sfixed(string'("-10.000")), rnd, sat); + PerformRoundTest (to_sfixed(string'("1.")), to_sfixed(string'("1.00000000000000000")), rnd, sat); + PerformRoundTest (to_sfixed(string'("0.")), to_sfixed(string'("0.00000000000000000")), rnd, sat); + PerformRoundTest (to_sfixed(string'("1.")), to_sfixed(string'(".000000000000000000")), rnd, sat); + PerformRoundTest (to_sfixed(string'("0.")), to_sfixed(string'(".000000000000000000")), rnd, sat); + PerformRoundTest (to_sfixed(string'("10.101")), to_sfixed(string'("010.1010")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-10.1011")), to_sfixed(string'("-10.11")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-10.101")), to_sfixed(string'("-10.10")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-0.1111")), to_sfixed(string'("-0.111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-0.11110")), to_sfixed(string'("-0.111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-0.11111")), to_sfixed(string'("-1.000")), rnd, sat); + + --------------------------------------------------------------------- + writeline (output, L); + write (L, String'("* Round convergent" & CR & LF)); + writeline (output, L); + + rnd := round_convergent; + sat := none; + + PerformRoundTest (to_ufixed(string'("01.001")), to_ufixed(string'("01.00")), rnd, sat); + PerformRoundTest (to_ufixed(string'("01.0010")), to_ufixed(string'("01.00")), rnd, sat); + PerformRoundTest (to_ufixed(string'("01.0011")), to_ufixed(string'("01.01")), rnd, sat); + PerformRoundTest (to_ufixed(string'("01.011")), to_ufixed(string'("01.10")), rnd, sat); + PerformRoundTest (to_ufixed(string'("01.0110")), to_ufixed(string'("01.10")), rnd, sat); + PerformRoundTest (to_ufixed(string'("01.0111")), to_ufixed(string'("01.10")), rnd, sat); + + PerformRoundTest (to_sfixed(string'("01.001")), to_sfixed(string'("01.00")), rnd, sat); + PerformRoundTest (to_sfixed(string'("01.0010")), to_sfixed(string'("01.00")), rnd, sat); + PerformRoundTest (to_sfixed(string'("01.0011")), to_sfixed(string'("01.01")), rnd, sat); + PerformRoundTest (to_sfixed(string'("01.011")), to_sfixed(string'("01.10")), rnd, sat); + PerformRoundTest (to_sfixed(string'("01.0110")), to_sfixed(string'("01.10")), rnd, sat); + PerformRoundTest (to_sfixed(string'("01.0111")), to_sfixed(string'("01.10")), rnd, sat); + + PerformRoundTest (to_sfixed(string'("-01.001")), to_sfixed(string'("-01.00")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-01.0010")), to_sfixed(string'("-01.00")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-01.0011")), to_sfixed(string'("-01.01")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-01.011")), to_sfixed(string'("-01.10")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-01.0110")), to_sfixed(string'("-01.10")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-01.0111")), to_sfixed(string'("-01.10")), rnd, sat); + + --------------------------------------------------------------------- + + writeline (output, L); + write (L, String'("----------------------" & CR & LF)); + write (L, String'(" With saturation " & CR & LF)); + write (L, String'("----------------------" & CR & LF)); + writeline (output, L); + + write (L, String'("* No rounding" & CR & LF)); + writeline (output, L); + + rnd := none; + sat := saturate; + + PerformRoundTest (to_ufixed(string'("101.0011")), to_ufixed(string'("11.1111")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.001101")), to_ufixed(string'("001.")), rnd, sat); + PerformRoundTest (to_ufixed(string'("101.01")), to_ufixed(string'("1.1")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1010.1")), to_ufixed(string'("11.")), rnd, sat); + PerformRoundTest (to_ufixed(string'("101.11")), to_ufixed(string'("101.")), rnd, sat); + PerformRoundTest (to_ufixed(string'(".11")), to_ufixed(string'("0.")), rnd, sat); + PerformRoundTest (to_ufixed(string'(".1011")), to_ufixed(string'("0.10")), rnd, sat); + PerformRoundTest (to_ufixed(string'("0.0000000001")), to_ufixed(string'("0.")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.0000000001")), to_ufixed(string'("1.0")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.0000000001")), to_ufixed(string'("1.")), rnd, sat); + PerformRoundTest (to_ufixed(string'("10.000000001")), to_ufixed(string'("10.000")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.")), to_ufixed(string'("1.00000000000000000")), rnd, sat); + PerformRoundTest (to_ufixed(string'("0.")), to_ufixed(string'("0.00000000000000000")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.")), to_ufixed(string'(".111111111111111111")), rnd, sat); + PerformRoundTest (to_ufixed(string'("0.")), to_ufixed(string'(".000000000000000000")), rnd, sat); + PerformRoundTest (to_ufixed(string'("10.101")), to_ufixed(string'("010.1010")), rnd, sat); + PerformRoundTest (to_ufixed(string'("10.101")), to_ufixed(string'("10.10")), rnd, sat); + PerformRoundTest (to_ufixed(string'("10.101")), to_ufixed(string'("10.1010")), rnd, sat); + + PerformRoundTest (to_ufixed(string'("1.0000")), to_ufixed(string'(".11111")), rnd, sat); + PerformRoundTest (to_ufixed(string'("01.000")), to_ufixed(string'(".11111")), rnd, sat); + PerformRoundTest (to_ufixed(string'("11.000")), to_ufixed(string'(".11111")), rnd, sat); + PerformRoundTest (to_ufixed(string'("0.1000")), to_ufixed(string'(".10000")), rnd, sat); + PerformRoundTest (to_ufixed(string'("00.100")), to_ufixed(string'(".10000")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.0001")), to_ufixed(string'(".11111")), rnd, sat); + PerformRoundTest (to_ufixed(string'("01.001")), to_ufixed(string'(".11111")), rnd, sat); + PerformRoundTest (to_ufixed(string'("01.010")), to_ufixed(string'(".11111")), rnd, sat); + PerformRoundTest (to_ufixed(string'("11.001")), to_ufixed(string'(".11111")), rnd, sat); + PerformRoundTest (to_ufixed(string'("0.1001")), to_ufixed(string'(".10010")), rnd, sat); + PerformRoundTest (to_ufixed(string'("00.101")), to_ufixed(string'(".10100")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.000000000000000001")), to_ufixed(string'(".111111111111111")), rnd, sat); + PerformRoundTest (to_ufixed(string'("01.00000000000000001")), to_ufixed(string'(".111111111111111")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.00000000000000")), to_ufixed(string'(".111111111111111")), rnd, sat); + + + PerformRoundTest (to_sfixed(string'("-101.0011")), to_sfixed(string'("-11.1111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("1.001101")), to_sfixed(string'("001.")), rnd, sat); + PerformRoundTest (to_sfixed(string'("101.01")), to_sfixed(string'("1.1")), rnd, sat); + PerformRoundTest (to_sfixed(string'("1010.1")), to_sfixed(string'("11.")), rnd, sat); + PerformRoundTest (to_sfixed(string'("101.11")), to_sfixed(string'("101.")), rnd, sat); + PerformRoundTest (to_sfixed(string'(".11")), to_sfixed(string'("0.")), rnd, sat); + PerformRoundTest (to_sfixed(string'(".1011")), to_sfixed(string'("0.10")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-0.0000000001")), to_sfixed(string'("0.")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-1.0000000001")), to_sfixed(string'("-1.0")), rnd, sat); + PerformRoundTest (to_sfixed(string'("1.0000000001")), to_sfixed(string'("1.")), rnd, sat); + PerformRoundTest (to_sfixed(string'("10.000000001")), to_sfixed(string'("10.000")), rnd, sat); + PerformRoundTest (to_sfixed(string'("1.")), to_sfixed(string'("1.00000000000000000")), rnd, sat); + PerformRoundTest (to_sfixed(string'("0.")), to_sfixed(string'("0.00000000000000000")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-1.")), to_sfixed(string'("-.111111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-0.")), to_sfixed(string'(".000000000000000000")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-10.101")), to_sfixed(string'("-010.1010")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-10.101")), to_sfixed(string'("-10.10")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-10.101")), to_sfixed(string'("-10.1010")), rnd, sat); + + PerformRoundTest (to_sfixed(string'("-1.0000")), to_sfixed(string'("-.11111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-01.000")), to_sfixed(string'("-.11111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-11.000")), to_sfixed(string'("-.11111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-0.1000")), to_sfixed(string'("-.10000")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-00.100")), to_sfixed(string'("-.10000")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-1.0001")), to_sfixed(string'("-.11111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-01.001")), to_sfixed(string'("-.11111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-01.010")), to_sfixed(string'("-.11111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-11.001")), to_sfixed(string'("-.11111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-0.1001")), to_sfixed(string'("-.10010")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-00.101")), to_sfixed(string'("-.10100")), rnd, sat); + + PerformRoundTest (to_sfixed(string'("-1.000000000000000001")), to_sfixed(string'("-.111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-01.00000000000000001")), to_sfixed(string'("-.111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-1.00000000000000")), to_sfixed(string'("-.111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("1.000000000000000001")), to_sfixed(string'(".111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("01.00000000000000001")), to_sfixed(string'(".111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("1.00000000000000")), to_sfixed(string'(".111111111111111")), rnd, sat); + + PerformRoundTest (to_sfixed(string'("1.0000")), to_sfixed(string'(".11111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("01.000")), to_sfixed(string'(".11111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("0.1000")), to_sfixed(string'(".10000")), rnd, sat); + PerformRoundTest (to_sfixed(string'("00.100")), to_sfixed(string'(".10000")), rnd, sat); + + + --------------------------------------------------------------------- + + writeline (output, L); + write (L, String'("* Round to zero" & CR & LF)); + writeline (output, L); + + rnd := round_to_zero; + sat := saturate; + + PerformRoundTest (to_ufixed(string'("101.0011")), to_ufixed(string'("11.1111")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.001101")), to_ufixed(string'("001.")), rnd, sat); + PerformRoundTest (to_ufixed(string'("101.01")), to_ufixed(string'("1.1")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1010.1")), to_ufixed(string'("11.")), rnd, sat); + PerformRoundTest (to_ufixed(string'("101.11")), to_ufixed(string'("101.")), rnd, sat); + PerformRoundTest (to_ufixed(string'(".11")), to_ufixed(string'("0.")), rnd, sat); + PerformRoundTest (to_ufixed(string'(".1011")), to_ufixed(string'("0.10")), rnd, sat); + PerformRoundTest (to_ufixed(string'("0.0000000001")), to_ufixed(string'("0.")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.0000000001")), to_ufixed(string'("1.0")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.0000000001")), to_ufixed(string'("1.")), rnd, sat); + PerformRoundTest (to_ufixed(string'("10.000000001")), to_ufixed(string'("10.000")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.")), to_ufixed(string'("1.00000000000000000")), rnd, sat); + PerformRoundTest (to_ufixed(string'("0.")), to_ufixed(string'("0.00000000000000000")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.")), to_ufixed(string'(".111111111111111111")), rnd, sat); + PerformRoundTest (to_ufixed(string'("0.")), to_ufixed(string'(".000000000000000000")), rnd, sat); + PerformRoundTest (to_ufixed(string'("10.101")), to_ufixed(string'("010.1010")), rnd, sat); + PerformRoundTest (to_ufixed(string'("10.101")), to_ufixed(string'("10.10")), rnd, sat); + PerformRoundTest (to_ufixed(string'("10.101")), to_ufixed(string'("10.1010")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.000000000000000001")), to_ufixed(string'(".111111111111111")), rnd, sat); + PerformRoundTest (to_ufixed(string'("01.00000000000000001")), to_ufixed(string'(".111111111111111")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.00000000000000")), to_ufixed(string'(".111111111111111")), rnd, sat); + + PerformRoundTest (to_sfixed(string'("101.0011")), to_sfixed(string'("11.1111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("1.001101")), to_sfixed(string'("001.")), rnd, sat); + PerformRoundTest (to_sfixed(string'("101.01")), to_sfixed(string'("1.1")), rnd, sat); + PerformRoundTest (to_sfixed(string'("1010.1")), to_sfixed(string'("11.")), rnd, sat); + PerformRoundTest (to_sfixed(string'("101.11")), to_sfixed(string'("101.")), rnd, sat); + PerformRoundTest (to_sfixed(string'(".11")), to_sfixed(string'("0.")), rnd, sat); + PerformRoundTest (to_sfixed(string'(".1011")), to_sfixed(string'("0.10")), rnd, sat); + PerformRoundTest (to_sfixed(string'("0.0000000001")), to_sfixed(string'("0.")), rnd, sat); + PerformRoundTest (to_sfixed(string'("1.0000000001")), to_sfixed(string'("1.0")), rnd, sat); + PerformRoundTest (to_sfixed(string'("1.0000000001")), to_sfixed(string'("1.")), rnd, sat); + PerformRoundTest (to_sfixed(string'("10.000000001")), to_sfixed(string'("10.000")), rnd, sat); + PerformRoundTest (to_sfixed(string'("1.")), to_sfixed(string'("1.00000000000000000")), rnd, sat); + PerformRoundTest (to_sfixed(string'("0.")), to_sfixed(string'("0.00000000000000000")), rnd, sat); + PerformRoundTest (to_sfixed(string'("1.")), to_sfixed(string'(".111111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("0.")), to_sfixed(string'(".000000000000000000")), rnd, sat); + PerformRoundTest (to_sfixed(string'("10.101")), to_sfixed(string'("010.1010")), rnd, sat); + PerformRoundTest (to_sfixed(string'("10.101")), to_sfixed(string'("10.10")), rnd, sat); + PerformRoundTest (to_sfixed(string'("10.101")), to_sfixed(string'("10.1010")), rnd, sat); + + PerformRoundTest (to_sfixed(string'("-1.000000000000000001")), to_sfixed(string'("-.111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-01.00000000000000001")), to_sfixed(string'("-.111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-1.00000000000000")), to_sfixed(string'("-.111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("1.000000000000000001")), to_sfixed(string'(".111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("01.00000000000000001")), to_sfixed(string'(".111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("1.00000000000000")), to_sfixed(string'(".111111111111111")), rnd, sat); + + PerformRoundTest (to_sfixed(string'("1.0000")), to_sfixed(string'(".11111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("01.000")), to_sfixed(string'(".11111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("0.1000")), to_sfixed(string'(".10000")), rnd, sat); + PerformRoundTest (to_sfixed(string'("00.100")), to_sfixed(string'(".10000")), rnd, sat); + + --------------------------------------------------------------------- + + writeline (output, L); + write (L, String'("* Round to infinity" & CR & LF)); + writeline (output, L); + + rnd := round_pos_infinity; + sat := saturate; + + PerformRoundTest (to_ufixed(string'("101.0011")), to_ufixed(string'("11.1111")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.001101")), to_ufixed(string'("010.")), rnd, sat); + PerformRoundTest (to_ufixed(string'("101.01")), to_ufixed(string'("1.1")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1010.1")), to_ufixed(string'("11.")), rnd, sat); + PerformRoundTest (to_ufixed(string'("101.11")), to_ufixed(string'("110.")), rnd, sat); + PerformRoundTest (to_ufixed(string'(".11")), to_ufixed(string'("1.")), rnd, sat); + PerformRoundTest (to_ufixed(string'(".1011")), to_ufixed(string'("0.11")), rnd, sat); + PerformRoundTest (to_ufixed(string'("0.0000000001")), to_ufixed(string'("1.")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.0000000001")), to_ufixed(string'("1.1")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.0000000001")), to_ufixed(string'("1.")), rnd, sat); + PerformRoundTest (to_ufixed(string'("10.000000001")), to_ufixed(string'("10.001")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.")), to_ufixed(string'("1.00000000000000000")), rnd, sat); + PerformRoundTest (to_ufixed(string'("0.")), to_ufixed(string'("0.00000000000000000")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.")), to_ufixed(string'(".111111111111111111")), rnd, sat); + PerformRoundTest (to_ufixed(string'("0.")), to_ufixed(string'(".000000000000000000")), rnd, sat); + PerformRoundTest (to_ufixed(string'("10.101")), to_ufixed(string'("010.1010")), rnd, sat); + PerformRoundTest (to_ufixed(string'("10.101")), to_ufixed(string'("10.11")), rnd, sat); + PerformRoundTest (to_ufixed(string'("10.101")), to_ufixed(string'("10.1010")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.000000000000000001")), to_ufixed(string'(".111111111111111")), rnd, sat); + PerformRoundTest (to_ufixed(string'("01.00000000000000001")), to_ufixed(string'(".111111111111111")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.00000000000000")), to_ufixed(string'(".111111111111111")), rnd, sat); + + PerformRoundTest (to_sfixed(string'("101.0011")), to_sfixed(string'("11.1111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("1.001101")), to_sfixed(string'("010.")), rnd, sat); + PerformRoundTest (to_sfixed(string'("101.01")), to_sfixed(string'("1.1")), rnd, sat); + PerformRoundTest (to_sfixed(string'("1010.1")), to_sfixed(string'("11.")), rnd, sat); + PerformRoundTest (to_sfixed(string'("101.11")), to_sfixed(string'("110.")), rnd, sat); + PerformRoundTest (to_sfixed(string'(".11")), to_sfixed(string'("1.")), rnd, sat); + PerformRoundTest (to_sfixed(string'(".1011")), to_sfixed(string'("0.11")), rnd, sat); + PerformRoundTest (to_sfixed(string'("0.0000000001")), to_sfixed(string'("1.")), rnd, sat); + PerformRoundTest (to_sfixed(string'("1.0000000001")), to_sfixed(string'("1.1")), rnd, sat); + PerformRoundTest (to_sfixed(string'("1.0000000001")), to_sfixed(string'("1.")), rnd, sat); + PerformRoundTest (to_sfixed(string'("10.000000001")), to_sfixed(string'("10.001")), rnd, sat); + PerformRoundTest (to_sfixed(string'("1.")), to_sfixed(string'("1.00000000000000000")), rnd, sat); + PerformRoundTest (to_sfixed(string'("0.")), to_sfixed(string'("0.00000000000000000")), rnd, sat); + PerformRoundTest (to_sfixed(string'("1.")), to_sfixed(string'(".111111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("0.")), to_sfixed(string'(".000000000000000000")), rnd, sat); + PerformRoundTest (to_sfixed(string'("10.101")), to_sfixed(string'("010.1010")), rnd, sat); + PerformRoundTest (to_sfixed(string'("10.101")), to_sfixed(string'("10.11")), rnd, sat); + PerformRoundTest (to_sfixed(string'("10.101")), to_sfixed(string'("10.1010")), rnd, sat); + + PerformRoundTest (to_sfixed(string'("-1.000000000000000001")), to_sfixed(string'("-.111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-01.00000000000000001")), to_sfixed(string'("-.111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-1.00000000000000")), to_sfixed(string'("-.111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("1.000000000000000001")), to_sfixed(string'(".111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("01.00000000000000001")), to_sfixed(string'(".111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("1.00000000000000")), to_sfixed(string'(".111111111111111")), rnd, sat); + + PerformRoundTest (to_sfixed(string'("1.0000")), to_sfixed(string'(".11111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("01.000")), to_sfixed(string'(".11111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("0.1000")), to_sfixed(string'(".10000")), rnd, sat); + PerformRoundTest (to_sfixed(string'("00.100")), to_sfixed(string'(".10000")), rnd, sat); + + --------------------------------------------------------------------- + + writeline (output, L); + write (L, String'("* Round half up" & CR & LF)); + writeline (output, L); + + rnd := round_half_up; + sat := saturate; + + PerformRoundTest (to_ufixed(string'("101.0011")), to_ufixed(string'("11.1111")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.001101")), to_ufixed(string'("001.")), rnd, sat); + PerformRoundTest (to_ufixed(string'("101.01")), to_ufixed(string'("1.1")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1010.1")), to_ufixed(string'("11.")), rnd, sat); + PerformRoundTest (to_ufixed(string'("101.11")), to_ufixed(string'("110.")), rnd, sat); + PerformRoundTest (to_ufixed(string'(".11")), to_ufixed(string'("1.")), rnd, sat); + PerformRoundTest (to_ufixed(string'(".1011")), to_ufixed(string'("0.11")), rnd, sat); + PerformRoundTest (to_ufixed(string'("0.0000000001")), to_ufixed(string'("0.")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.0000000001")), to_ufixed(string'("1.0")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.0000000001")), to_ufixed(string'("1.")), rnd, sat); + PerformRoundTest (to_ufixed(string'("10.000000001")), to_ufixed(string'("10.000")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.")), to_ufixed(string'("1.00000000000000000")), rnd, sat); + PerformRoundTest (to_ufixed(string'("0.")), to_ufixed(string'("0.00000000000000000")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.")), to_ufixed(string'(".111111111111111111")), rnd, sat); + PerformRoundTest (to_ufixed(string'("0.")), to_ufixed(string'(".000000000000000000")), rnd, sat); + PerformRoundTest (to_ufixed(string'("10.101")), to_ufixed(string'("010.1010")), rnd, sat); + PerformRoundTest (to_ufixed(string'("10.101")), to_ufixed(string'("10.11")), rnd, sat); + PerformRoundTest (to_ufixed(string'("10.101")), to_ufixed(string'("10.1010")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.000000000000000001")), to_ufixed(string'(".111111111111111")), rnd, sat); + PerformRoundTest (to_ufixed(string'("01.00000000000000001")), to_ufixed(string'(".111111111111111")), rnd, sat); + PerformRoundTest (to_ufixed(string'("1.00000000000000")), to_ufixed(string'(".111111111111111")), rnd, sat); + + PerformRoundTest (to_sfixed(string'("101.0011")), to_sfixed(string'("11.1111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("1.001101")), to_sfixed(string'("001.")), rnd, sat); + PerformRoundTest (to_sfixed(string'("101.01")), to_sfixed(string'("1.1")), rnd, sat); + PerformRoundTest (to_sfixed(string'("1010.1")), to_sfixed(string'("11.")), rnd, sat); + PerformRoundTest (to_sfixed(string'("101.11")), to_sfixed(string'("110.")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-.11")), to_sfixed(string'("-1.")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-.1")), to_sfixed(string'("0.")), rnd, sat); + PerformRoundTest (to_sfixed(string'(".1011")), to_sfixed(string'("0.11")), rnd, sat); + PerformRoundTest (to_sfixed(string'("0.0000000001")), to_sfixed(string'("0.")), rnd, sat); + PerformRoundTest (to_sfixed(string'("1.0000000001")), to_sfixed(string'("1.0")), rnd, sat); + PerformRoundTest (to_sfixed(string'("1.0000000001")), to_sfixed(string'("1.")), rnd, sat); + PerformRoundTest (to_sfixed(string'("10.000000001")), to_sfixed(string'("10.000")), rnd, sat); + PerformRoundTest (to_sfixed(string'("1.")), to_sfixed(string'("1.00000000000000000")), rnd, sat); + PerformRoundTest (to_sfixed(string'("0.")), to_sfixed(string'("0.00000000000000000")), rnd, sat); + PerformRoundTest (to_sfixed(string'("1.")), to_sfixed(string'(".111111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("0.")), to_sfixed(string'(".000000000000000000")), rnd, sat); + PerformRoundTest (to_sfixed(string'("10.101")), to_sfixed(string'("010.1010")), rnd, sat); + PerformRoundTest (to_sfixed(string'("10.101")), to_sfixed(string'("10.11")), rnd, sat); + PerformRoundTest (to_sfixed(string'("10.101")), to_sfixed(string'("10.1010")), rnd, sat); + + PerformRoundTest (to_sfixed(string'("-1.000000000000000000")), to_sfixed(string'("-.111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-1.000000000000000001")), to_sfixed(string'("-.111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-01.00000000000000000")), to_sfixed(string'("-.111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-01.00000000000000001")), to_sfixed(string'("-.111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-01.0000000000000")), to_sfixed(string'("-.111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-01.0000000000001")), to_sfixed(string'("-.111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-01.0000000000000")), to_sfixed(string'("-.11111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-01.0000000000001")), to_sfixed(string'("-.11111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-01.0000000000000")), to_sfixed(string'("-.1111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-01.0000000000001")), to_sfixed(string'("-.1111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-00.1111111111111")), to_sfixed(string'("-.111111111111100")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-00.111111111111111")), to_sfixed(string'("-.11111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-00.111111111111111")), to_sfixed(string'("-1.0000000000000")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-1.000000000000000001")), to_sfixed(string'("-.111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-01.00000000000000001")), to_sfixed(string'("-.111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-1.0000000000000000001")), to_sfixed(string'("-.111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-01.000000000000000001")), to_sfixed(string'("-.111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-1.00000000000000000001")), to_sfixed(string'("-.111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-01.0000000000000000001")), to_sfixed(string'("-.111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-1.000000000000000000001")), to_sfixed(string'("-.111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-01.00000000000000000001")), to_sfixed(string'("-.111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-1.0000000000000000000001")), to_sfixed(string'("-.111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-01.000000000000000000001")), to_sfixed(string'("-.111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-1.000000000000000011")), to_sfixed(string'("-.111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-01.00000000000000011")), to_sfixed(string'("-.111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-1.0000000000000000011")), to_sfixed(string'("-.111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-01.000000000000000011")), to_sfixed(string'("-.111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-1.00000000000000000011")), to_sfixed(string'("-.111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-01.0000000000000000011")), to_sfixed(string'("-.111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-1.000000000000000000011")), to_sfixed(string'("-.111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-01.00000000000000000011")), to_sfixed(string'("-.111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-1.0000000000000000000011")), to_sfixed(string'("-.111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-01.000000000000000000011")), to_sfixed(string'("-.111111111111111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("-1.00000000000000")), to_sfixed(string'("-.111111111111111")), rnd, sat); + + PerformRoundTest (to_sfixed(string'("1.0000")), to_sfixed(string'(".11111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("01.000")), to_sfixed(string'(".11111")), rnd, sat); + PerformRoundTest (to_sfixed(string'("0.1000")), to_sfixed(string'(".10000")), rnd, sat); + PerformRoundTest (to_sfixed(string'("00.100")), to_sfixed(string'(".10000")), rnd, sat); + + --------------------------------------------------------------------- + + writeline (output, L); + write (L, String'("----------------------" & CR & LF)); + write (L, String'(" Arithmetic Test " & CR & LF)); + write (L, String'("----------------------" & CR & LF)); + +if true then + + PerformArithTest(to_ufixed(0.500, 8, 0), '+', to_ufixed(0.250, 8, 0), to_ufixed(0.500 + 0.250, 9, 1)); + PerformArithTest(to_ufixed(0.375, 8, 0), '+', to_ufixed(0.250, 8, 0), to_ufixed(0.375 + 0.250, 9, 1)); + PerformArithTest(to_ufixed(0.375, 8, 1), '-', to_ufixed(0.250, 8, 0), to_ufixed(0.375 - 0.250, 9, 1)); + PerformArithTest(to_ufixed(0.500, 8, 0), '+', to_ufixed(0.250, 8, 0), to_ufixed(0.500 + 0.250, 9, 1)); + PerformArithTest(to_ufixed(0.500, 8, 0), '-', to_ufixed(0.250, 8, 0), to_ufixed(0.500 - 0.250, 8, 0)); + PerformArithTest(to_ufixed(0.250, 8, 0), '+', to_ufixed(0.250, 8, 0), to_ufixed(0.250 + 0.250, 9, 1)); + PerformArithTest(to_ufixed(0.250, 8, 0), '-', to_ufixed(0.250, 8, 0), to_ufixed(0.250 - 0.250, 8, 0)); + PerformArithTest(to_ufixed(0.250, 4, 0), '+', to_ufixed(0.250, 8, 3), to_ufixed(0.250 + 0.250, 8, 3)); + + PerformArithTest(to_ufixed(string'("1.0000")), '+', to_ufixed(string'("1.0000")), to_ufixed(string'("10.0000"))); + PerformArithTest(to_ufixed(string'("0.1001")), '+', to_ufixed(string'("0.0110")), to_ufixed(string'("00.1111"))); + PerformArithTest(to_ufixed(string'("0.0011")), '+', to_ufixed(string'("0.0110")), to_ufixed(string'("00.1001"))); + PerformArithTest(to_ufixed(string'("0.1111")), '+', to_ufixed(string'("1.0001")), to_ufixed(string'("10.0000"))); + PerformArithTest(to_ufixed(string'("10.0000")), '-', to_ufixed(string'("1.0000")), to_ufixed(string'("01.0000"))); + PerformArithTest(to_ufixed(string'("00.1111")), '-', to_ufixed(string'("0.1001")), to_ufixed(string'("00.0110"))); + PerformArithTest(to_ufixed(string'("00.1001")), '-', to_ufixed(string'("0.0011")), to_ufixed(string'("00.0110"))); + PerformArithTest(to_ufixed(string'("10.0000")), '-', to_ufixed(string'("0.1111")), to_ufixed(string'("01.0001"))); + + PerformArithTest(to_ufixed(0.500, 8, 0), '*', to_ufixed(4.500, 8, 3), to_ufixed(0.500 * 4.500, 16, 2)); + PerformArithTest(to_ufixed(0.500, 8, 0), '*', to_ufixed(0.500, 8, 0), to_ufixed(0.500 * 0.500, 16, 0)); + PerformArithTest(to_ufixed(0.500, 8, 1), '*', to_ufixed(0.500, 8, 0), to_ufixed(0.500 * 0.500, 16, 0)); + PerformArithTest(to_ufixed(0.500, 8, 1), '*', to_ufixed(0.500, 8, 1), to_ufixed(0.500 * 0.500, 16, 2)); + + PerformArithTest(to_ufixed(0.500, 8, 1), '*', to_ufixed(0.500, 8, 0), to_ufixed(0.500 * 0.500, 16, 0)); + PerformArithTest(to_ufixed(0.500, 8, 2), '*', to_ufixed(0.500, 8, 1), to_ufixed(0.500 * 0.500, 16, 3)); + PerformArithTest(to_ufixed(1.500, 9, 2), '*', to_ufixed(0.500, 8, 0), to_ufixed(1.500 * 0.500, 17, 1)); + PerformArithTest(to_ufixed(0.500, 8, 0), '*', to_ufixed(1.500, 9, 2), to_ufixed(1.500 * 0.500, 17, 1)); + PerformArithTest(to_ufixed(1.500, 8, 2), '*', to_ufixed(0.500, 9, 0), to_ufixed(1.500 * 0.500, 17, 1)); + PerformArithTest(to_ufixed(0.500, 9, 0), '*', to_ufixed(1.500, 8, 2), to_ufixed(1.500 * 0.500, 17, 1)); + + PerformArithTest(to_sfixed(0.375, 4, 0), '+', to_sfixed(0.250, 8, 0), to_sfixed(0.375 + 0.250, 9, 1)); + PerformArithTest(to_sfixed(0.375, 8, 0), '-', to_sfixed(0.250, 8, 0), to_sfixed(0.375 - 0.250, 8, 0)); + PerformArithTest(to_sfixed(0.500, 8, 0), '+', to_sfixed(0.250, 8, 0), to_sfixed(0.500 + 0.250, 9, 1)); + PerformArithTest(to_sfixed(0.500, 8, 0), '-', to_sfixed(0.250, 8, 0), to_sfixed(0.500 - 0.250, 8, 0)); + PerformArithTest(to_sfixed(0.250, 8, 0), '+', to_sfixed(0.250, 8, 0), to_sfixed(0.250 + 0.250, 9, 1)); + PerformArithTest(to_sfixed(0.250, 8, 0), '-', to_sfixed(0.250, 8, 0), to_sfixed(0.250 - 0.250, 8, 0)); + PerformArithTest(to_sfixed(0.250, 4, 0), '+', to_sfixed(0.250, 8, 3), to_sfixed(0.250 + 0.250, 8, 3)); + PerformArithTest(to_sfixed(-0.500, 4, 0), '*', to_sfixed(4.500, 8, 3), to_sfixed(-0.500 * 4.500, 12, 2)); + PerformArithTest(to_sfixed(-0.500, 8, 0), '*', to_sfixed(0.500, 8, 0), to_sfixed(-0.500 * 0.500, 16, 0)); + PerformArithTest(to_sfixed(-0.500, 8, 1), '*', to_sfixed(0.500, 8, 0), to_sfixed(-0.500 * 0.500, 16, 0)); + PerformArithTest(to_sfixed(-0.500, 8, 1), '*', to_sfixed(0.500, 8, 1), to_sfixed(-0.500 * 0.500, 16, 2)); + PerformArithTest(to_sfixed(0.500, 4, 0), '*', to_sfixed(4.500, 8, 3), to_sfixed(0.500 * 4.500, 12, 2)); + PerformArithTest(to_sfixed(0.500, 8, 0), '*', to_sfixed(0.500, 8, 0), to_sfixed(0.500 * 0.500, 16, 0)); + PerformArithTest(to_sfixed(0.500, 8, 1), '*', to_sfixed(0.500, 8, 0), to_sfixed(0.500 * 0.500, 16, 0)); + PerformArithTest(to_sfixed(0.500, 8, 1), '*', to_sfixed(0.500, 8, 1), to_sfixed(0.500 * 0.500, 16, 2)); + + fprint(RESULT, L, "Test finished\n\n"); + +end if; +if true then + + fprint(RESULT, L, "\nPositive ufixed\n"); + for i in 0 to uconst0'length loop + ures := uconst0 sla i; + fprint(RESULT, L, "%s sla %d = %s\n", to_string(uconst0), fo(i), to_string(ures)); + end loop; + fprint(RESULT, L, "\n"); + for i in 0 to uconst0'length loop + ures := uconst0 sla -i; + fprint(RESULT, L, "%s sla %d = %s\n", to_string(uconst0), fo(-i), to_string(ures)); + end loop; + fprint(RESULT, L, "\n"); + for i in 0 to uconst0'length loop + ures := uconst0 sra i; + fprint(RESULT, L, "%s sra %d = %s\n", to_string(uconst0), fo(i), to_string(ures)); + end loop; + fprint(RESULT, L, "\n"); + for i in 0 to uconst0'length loop + ures := uconst0 sra -i; + fprint(RESULT, L, "%s sra %d = %s\n", to_string(uconst0), fo(-i), to_string(ures)); + end loop; + + fprint(RESULT, L, "\nPositive sfixed\n"); + for i in 0 to sconst0'length loop + sres := sconst0 sla i; + fprint(RESULT, L, "%s sla %d = %s\n", to_string(sconst0), fo(i), to_string(sres)); + end loop; + fprint(RESULT, L, "\n"); + for i in 0 to sconst0'length loop + sres := sconst0 sla -i; + fprint(RESULT, L, "%s sla %d = %s\n", to_string(sconst0), fo(-i), to_string(sres)); + end loop; + fprint(RESULT, L, "\n"); + for i in 0 to sconst0'length loop + sres := sconst0 sra i; + fprint(RESULT, L, "%s sra %d = %s\n", to_string(sconst0), fo(i), to_string(sres)); + end loop; + fprint(RESULT, L, "\n"); + for i in 0 to sconst0'length loop + sres := sconst0 sra -i; + fprint(RESULT, L, "%s sra %d = %s\n", to_string(sconst0), fo(-i), to_string(sres)); + end loop; + + fprint(RESULT, L, "\nNegative sfixed\n"); + for i in 0 to sconst0'length loop + sres := -sconst0 sla i; + fprint(RESULT, L, "%s sla %d = %s\n", to_string(-sconst0), fo(i), to_string(sres)); + end loop; + fprint(RESULT, L, "\n"); + for i in 0 to sconst0'length loop + sres := -sconst0 sla -i; + fprint(RESULT, L, "%s sla %d = %s\n", to_string(-sconst0), fo(-i), to_string(sres)); + end loop; + fprint(RESULT, L, "\n"); + for i in 0 to sconst0'length loop + sres := -sconst0 sra i; + fprint(RESULT, L, "%s sra %d = %s\n", to_string(-sconst0), fo(i), to_string(sres)); + end loop; + fprint(RESULT, L, "\n"); + for i in 0 to sconst0'length loop + sres := -sconst0 sra -i; + fprint(RESULT, L, "%s sra %d = %s\n", to_string(-sconst0), fo(-i), to_string(sres)); + end loop; + + + fprint(RESULT, L, "\nPositive ufixed\n"); + for i in 0 to uconst1'length loop + ures := uconst1 sla i; + fprint(RESULT, L, "%s sla %d = %s\n", to_string(uconst1), fo(i), to_string(ures)); + end loop; + fprint(RESULT, L, "\n"); + for i in 0 to uconst1'length loop + ures := uconst1 sla -i; + fprint(RESULT, L, "%s sla %d = %s\n", to_string(uconst1), fo(-i), to_string(ures)); + end loop; + fprint(RESULT, L, "\n"); + for i in 0 to uconst1'length loop + ures := uconst1 sra i; + fprint(RESULT, L, "%s sra %d = %s\n", to_string(uconst1), fo(i), to_string(ures)); + end loop; + fprint(RESULT, L, "\n"); + for i in 0 to uconst1'length loop + ures := uconst1 sra -i; + fprint(RESULT, L, "%s sra %d = %s\n", to_string(uconst1), fo(-i), to_string(ures)); + end loop; + + fprint(RESULT, L, "\nPositive sfixed\n"); + for i in 0 to sconst1'length loop + sres := sconst1 sla i; + fprint(RESULT, L, "%s sla %d = %s\n", to_string(sconst1), fo(i), to_string(sres)); + end loop; + fprint(RESULT, L, "\n"); + for i in 0 to sconst1'length loop + sres := sconst1 sla -i; + fprint(RESULT, L, "%s sla %d = %s\n", to_string(sconst1), fo(-i), to_string(sres)); + end loop; + fprint(RESULT, L, "\n"); + for i in 0 to sconst1'length loop + sres := sconst1 sra i; + fprint(RESULT, L, "%s sra %d = %s\n", to_string(sconst1), fo(i), to_string(sres)); + end loop; + fprint(RESULT, L, "\n"); + for i in 0 to sconst1'length loop + sres := sconst1 sra -i; + fprint(RESULT, L, "%s sra %d = %s\n", to_string(sconst1), fo(-i), to_string(sres)); + end loop; + + fprint(RESULT, L, "\nNegative sfixed\n"); + for i in 0 to sconst1'length loop + sres := -sconst1 sla i; + fprint(RESULT, L, "%s sla %d = %s\n", to_string(-sconst1), fo(i), to_string(sres)); + end loop; + fprint(RESULT, L, "\n"); + for i in 0 to sconst1'length loop + sres := -sconst1 sla -i; + fprint(RESULT, L, "%s sla %d = %s\n", to_string(-sconst1), fo(-i), to_string(sres)); + end loop; + fprint(RESULT, L, "\n"); + for i in 0 to sconst1'length loop + sres := -sconst1 sra i; + fprint(RESULT, L, "%s sra %d = %s\n", to_string(-sconst1), fo(i), to_string(sres)); + end loop; + fprint(RESULT, L, "\n"); + for i in 0 to sconst1'length loop + sres := -sconst1 sra -i; + fprint(RESULT, L, "%s sra %d = %s\n", to_string(-sconst1), fo(-i), to_string(sres)); + end loop; + +end if; + +if true then + write (L, String'("Positive ufixed"));writeline (output, L); + print_info(to_ufixed(0.5,5,0)*to_ufixed(0.5,5,0), string'("U")); + print_info(to_ufixed(0.5,5,1)*to_ufixed(0.5,5,0), string'("U")); + print_info(to_ufixed(0.5,5,0)*to_ufixed(0.5,5,1), string'("U")); + print_info(to_ufixed(0.5,5,1)*to_ufixed(0.5,5,1), string'("U")); + print_info(to_ufixed(0.5,5,0)*to_ufixed(0.5,5,2), string'("U")); + print_info(to_ufixed(0.5,5,2)*to_ufixed(0.5,5,0), string'("U")); + + write (L, String'("Positive sfixed"));writeline (output, L); + print_info(to_sfixed(0.5,5,0)*to_sfixed(0.5,5,0), string'("S")); + print_info(to_sfixed(0.5,5,1)*to_sfixed(0.5,5,0), string'("S")); + print_info(to_sfixed(0.5,5,0)*to_sfixed(0.5,5,1), string'("S")); + print_info(to_sfixed(0.5,5,1)*to_sfixed(0.5,5,1), string'("S")); + print_info(to_sfixed(0.5,5,0)*to_sfixed(0.5,5,2), string'("S")); + print_info(to_sfixed(0.5,5,2)*to_sfixed(0.5,5,0), string'("S")); + + write (L, String'("Neg/Pos sfixed"));writeline (output, L); + print_info(to_sfixed(-0.5,5,0)*to_sfixed(0.5,5,0), string'("S")); + print_info(to_sfixed(-0.5,5,1)*to_sfixed(0.5,5,0), string'("S")); + print_info(to_sfixed(-0.5,5,0)*to_sfixed(0.5,5,1), string'("S")); + print_info(to_sfixed(-0.5,5,1)*to_sfixed(0.5,5,1), string'("S")); + print_info(to_sfixed(-0.5,5,0)*to_sfixed(0.5,5,2), string'("S")); + print_info(to_sfixed(-0.5,5,2)*to_sfixed(0.5,5,0), string'("S")); + + write (L, String'("Pos/Neg sfixed"));writeline (output, L); + print_info(to_sfixed(0.5,5,0)*to_sfixed(-0.5,5,0), string'("S")); + print_info(to_sfixed(0.5,5,1)*to_sfixed(-0.5,5,0), string'("S")); + print_info(to_sfixed(0.5,5,0)*to_sfixed(-0.5,5,1), string'("S")); + print_info(to_sfixed(0.5,5,1)*to_sfixed(-0.5,5,1), string'("S")); + print_info(to_sfixed(0.5,5,0)*to_sfixed(-0.5,5,2), string'("S")); + print_info(to_sfixed(0.5,5,2)*to_sfixed(-0.5,5,0), string'("S")); + + write (L, String'("Neg/Neg sfixed"));writeline (output, L); + print_info(to_sfixed(-0.5,5,0)*to_sfixed(-0.5,5,0), string'("S")); + print_info(to_sfixed(-0.5,5,1)*to_sfixed(-0.5,5,0), string'("S")); + print_info(to_sfixed(-0.5,5,0)*to_sfixed(-0.5,5,1), string'("S")); + print_info(to_sfixed(-0.5,5,1)*to_sfixed(-0.5,5,1), string'("S")); + print_info(to_sfixed(-0.5,5,0)*to_sfixed(-0.5,5,2), string'("S")); + print_info(to_sfixed(-0.5,5,2)*to_sfixed(-0.5,5,0), string'("S")); + + fprint(RESULT, L,"Test %s:\n", to_string(to_sfixed(to_ufixed(to_ufixed(0.785398, 8, 0),8,1) sla 1))); + fprint(RESULT, L,"Test %s:\n", to_string(to_sfixed(to_sfixed(0.785398, 8, 0),8,1) sla 1)); + fprint(RESULT, L,"Test %s:\n", to_string(to_sfixed(to_sfixed(-0.785398, 8, 0),8,1) sla 1)); + fprint(RESULT, L,"Test %s:\n", to_string(to_ufixed(to_ufixed(0.785398, 8, 0),8,2) sla -1)); + fprint(RESULT, L,"Test %s:\n", to_string(to_sfixed(to_sfixed(0.785398, 8, 0),8,2) sla -1)); + fprint(RESULT, L,"Test %s:\n", to_string(to_sfixed(-to_ufixed(-0.785398, 8, 0),8,2) sla -1)); + + fprint(RESULT, L,"Integer Test %s:\n", to_string(to_sfixed(0, 8,2))); + fprint(RESULT, L,"R: Bit %s:\n", to_string(to_ufixed(3.785398, 8, 2))); + fprint(RESULT, L,"U: Bit %s.%s:\n", to_string(to_slv(ipart(to_ufixed(3.785398, 8, 2)))), to_string(to_slv(fpart(to_ufixed(3.785398, 8, 2))))); + fprint(RESULT, L,"S: Bit %s.%s:\n", to_string(to_slv(ipart(to_sfixed(3.785398, 9, 2)))), to_string(to_slv(fpart(to_sfixed(3.785398, 9, 2))))); + fprint(RESULT, L,"S: Bit %s.%s:\n", to_string(to_slv(ipart(-to_sfixed(3.785398, 9, 2)))), to_string(to_slv(fpart(-to_sfixed(3.785398, 9, 2))))); + fprint(RESULT, L,"S: Bit %d.%d:\n", fo(to_slv(ipart(to_sfixed(3.785398, 9, 2)))), fo(to_slv(fpart(to_sfixed(3.785398, 9, 2))))); + fprint(RESULT, L,"S: Bit %d:\n", fo(to_signed(to_sfixed(-3.785398, 9, 2)))); + print_info(s1, "S1"); + print_info(s2, "S2"); + print_info(s1*s2, "R1"); + print_info(to_sfixed(1.0E-6, 32, 0), "precision_test"); +end if; + + wait; +end process; + +--------------------------------------------------------------------- +end Behavioral; + diff --git a/projects/eval_fixed_ja/src/tb_eval_fixed_ja_syn.vhd b/projects/eval_fixed_ja/src/tb_eval_fixed_ja_syn.vhd new file mode 100644 index 0000000..c217741 --- /dev/null +++ b/projects/eval_fixed_ja/src/tb_eval_fixed_ja_syn.vhd @@ -0,0 +1,104 @@ + +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 20:01:25 05/22/2007 +-- Design Name: eval_fixed_ja +-- Module Name: H:/vhdl/projects/eval_fixed_ja/ise/tb_eval_fixed_ja.vhd +-- Project Name: eval_fixed +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: eval_fixed_ja +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE ieee.numeric_std.ALL; + +ENTITY tb_eval_fixed_ja_vhd IS +END tb_eval_fixed_ja_vhd; + +ARCHITECTURE behavior OF tb_eval_fixed_ja_vhd IS + + -- Component Declaration for the Unit Under Test (UUT) + COMPONENT eval_fixed_ja + PORT( + srst : IN std_logic; + clk : IN std_logic; + di1 : IN std_logic_vector(7 downto 0); + di2 : IN std_logic_vector(7 downto 0); + in_valid : IN std_logic; + do : OUT std_logic_vector(7 downto 0); + out_valid : OUT std_logic + ); + END COMPONENT; + + --Inputs + SIGNAL srst : std_logic := '1'; + SIGNAL clk : std_logic := '0'; + SIGNAL in_valid : std_logic := '0'; + SIGNAL di1 : std_logic_vector(7 downto 0) := (others=>'0'); + SIGNAL di2 : std_logic_vector(7 downto 0) := (others=>'0'); + + --Outputs + SIGNAL do : std_logic_vector(7 downto 0); + SIGNAL out_valid : std_logic; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: eval_fixed_ja PORT MAP( + srst => srst, + clk => clk, + di1 => di1, + di2 => di2, + in_valid => in_valid, + do => do, + out_valid => out_valid + ); + + clk_gen : PROCESS + BEGIN + wait for 10 ns; + clk <= not clk; + END PROCESS; + + tb : PROCESS + BEGIN + + -- Wait 100 ns for global reset to finish + wait for 100 ns; + srst <= '0'; + di1 <= X"40"; + di2 <= X"20"; + + wait for 20 ns; + wait until rising_edge(clk); + in_valid <= '1'; + wait until rising_edge(clk); + in_valid <= '0'; + wait for 20 ns; + + + -- Place stimulus here + + wait; -- will wait forever + END PROCESS; + +END; diff --git a/projects/eval_fixed_ja/sum_test_s.txt b/projects/eval_fixed_ja/sum_test_s.txt new file mode 100644 index 0000000..70179b7 --- /dev/null +++ b/projects/eval_fixed_ja/sum_test_s.txt @@ -0,0 +1,512 @@ +-1.992188e+000 0.000000e+000 +-1.984375e+000 0.000000e+000 +-1.976563e+000 0.000000e+000 +-1.968750e+000 0.000000e+000 +-1.960938e+000 -9.375000e-001 +-1.953125e+000 -9.375000e-001 +-1.945313e+000 -9.375000e-001 +-1.937500e+000 -9.375000e-001 +-1.929688e+000 -9.375000e-001 +-1.921875e+000 -9.375000e-001 +-1.914063e+000 -9.375000e-001 +-1.906250e+000 -9.375000e-001 +-1.898438e+000 -9.375000e-001 +-1.890625e+000 -9.375000e-001 +-1.882813e+000 -9.375000e-001 +-1.875000e+000 -9.375000e-001 +-1.867188e+000 -9.375000e-001 +-1.859375e+000 -9.375000e-001 +-1.851563e+000 -9.375000e-001 +-1.843750e+000 -9.375000e-001 +-1.835938e+000 -9.375000e-001 +-1.828125e+000 -9.375000e-001 +-1.820313e+000 -9.375000e-001 +-1.812500e+000 -9.375000e-001 +-1.804688e+000 -9.375000e-001 +-1.796875e+000 -9.375000e-001 +-1.789063e+000 -9.375000e-001 +-1.781250e+000 -9.375000e-001 +-1.773438e+000 -9.375000e-001 +-1.765625e+000 -9.375000e-001 +-1.757813e+000 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9.375000e-001 +1.976563e+000 9.375000e-001 +1.984375e+000 9.375000e-001 +1.992188e+000 9.375000e-001 diff --git a/projects/eval_fixed_ja/tb_eval_fixed_ja.fdo b/projects/eval_fixed_ja/tb_eval_fixed_ja.fdo new file mode 100644 index 0000000..c64db6e --- /dev/null +++ b/projects/eval_fixed_ja/tb_eval_fixed_ja.fdo @@ -0,0 +1,12 @@ +vlib work +vcom -explicit -93 "../../lib/src/fixed_ja/fixed_ja.vhd" +vcom -explicit -93 "../../lib/src/fixed_ja/fixed_ja_body.vhd" +vcom -explicit -93 "../../lib/src/PCK_FIO-2002.7/PCK_FIO_1993.vhd" +vcom -explicit -93 "../../lib/src/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd" +vcom -explicit -93 "src/tb_eval_fixed_ja.vhd" +vsim -t 1ps -lib work tb_eval_fixed_ja +#do {wave.do} +view wave +view structure +view signals +run 1000ns diff --git a/projects/eval_fixed_ja/tb_results.m b/projects/eval_fixed_ja/tb_results.m new file mode 100644 index 0000000..67e1768 --- /dev/null +++ b/projects/eval_fixed_ja/tb_results.m @@ -0,0 +1,14 @@ +% Read data +[xu,yu] = TEXTREAD('sum_test_u.txt'); +[xs,ys] = TEXTREAD('sum_test_s.txt'); + + +close all; + +plot(0:length(xu)-1, xu, 0:length(yu)-1, yu); +grid; + +figure; + +plot(0:length(xs)-1, xs, 0:length(ys)-1, ys); +grid; diff --git a/projects/eval_gray_counter/eval_gray_counter.ise b/projects/eval_gray_counter/eval_gray_counter.ise new file mode 100644 index 0000000..b5899d4 Binary files /dev/null and b/projects/eval_gray_counter/eval_gray_counter.ise differ diff --git a/projects/eval_gray_counter/fifo_ctrl_pkg.vhd b/projects/eval_gray_counter/fifo_ctrl_pkg.vhd new file mode 100644 index 0000000..92ddc96 --- /dev/null +++ b/projects/eval_gray_counter/fifo_ctrl_pkg.vhd @@ -0,0 +1,43 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; + +package fifo_ctrl_pkg is + + -- Constants + -- Types + + -- Functions + function bin2gray(xb : unsigned) return unsigned; + function gray2bin(xg : unsigned) return unsigned; + +end fifo_ctrl_pkg; + +package body fifo_ctrl_pkg is + + function bin2gray(xb : unsigned) return unsigned is + variable xg : unsigned(xb'left downto xb'right); + begin + + xg(xg'left) := xb(xb'left); + for i in 1 to xb'left loop + xg(xg'left-i) := xb(xb'left-i+1) xor xb(xb'left-i); + end loop; + + return xg; + end bin2gray; + + function gray2bin(xg : unsigned) return unsigned is + variable xb : unsigned(xg'left downto xg'right); + begin + + xb(xb'left) := xg(xg'left); + for i in 1 to xg'left loop + xb(xb'left-i) := xb(xb'left-i+1) xor xg(xg'left-i); + end loop; + + return xb; + end gray2bin; + +end fifo_ctrl_pkg; + diff --git a/projects/eval_gray_counter/top.lso b/projects/eval_gray_counter/top.lso new file mode 100644 index 0000000..22de730 --- /dev/null +++ b/projects/eval_gray_counter/top.lso @@ -0,0 +1 @@ +work diff --git a/projects/eval_gray_counter/top.prj b/projects/eval_gray_counter/top.prj new file mode 100644 index 0000000..895757f --- /dev/null +++ b/projects/eval_gray_counter/top.prj @@ -0,0 +1,3 @@ +vhdl work "fifo_ctrl_pkg.vhd" +vhdl work "../../lib/FIFO/src/gray_counter.vhd" +vhdl work "top.vhd" diff --git a/projects/eval_gray_counter/top.vhd b/projects/eval_gray_counter/top.vhd new file mode 100644 index 0000000..f08b55f --- /dev/null +++ b/projects/eval_gray_counter/top.vhd @@ -0,0 +1,60 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 15:55:59 09/18/2007 +-- Design Name: +-- Module Name: top - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +LIBRARY WORK; +USE WORK.FIFO_CTRL_PKG.ALL; + +entity top is + Port ( rst : in STD_LOGIC; + clk : in STD_LOGIC; + ce : in STD_LOGIC; + gcnt : out unsigned (13 downto 0); + bcnt : out unsigned (13 downto 0); + gnxt : out unsigned (13 downto 0); + bnxt : out unsigned (13 downto 0) + ); +end top; + +architecture Behavioral of top is + +begin + +inst_gray_counter : entity work.gray_counter + generic map (width => 14) + port map ( + rst => rst, + clk => clk, + ce => ce, + bcnt => bcnt, + bnxt => bnxt, + gcnt => gcnt, + gnxt => gnxt + ); + +end Behavioral; + diff --git a/projects/eval_gray_counter/top.xst b/projects/eval_gray_counter/top.xst new file mode 100644 index 0000000..a9f68e0 --- /dev/null +++ b/projects/eval_gray_counter/top.xst @@ -0,0 +1,59 @@ +set -tmpdir "./xst/projnav.tmp" +set -xsthdpdir "./xst" +run +-ifn top.prj +-ifmt mixed +-ofn top +-ofmt NGC +-p xc4vsx35-10-ff668 +-top top +-opt_mode Speed +-opt_level 1 +-power NO +-iuc NO +-lso top.lso +-keep_hierarchy NO +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-dsp_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style lut +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract YES +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-auto_bram_packing NO +-mux_extract YES +-resource_sharing YES +-async_to_sync NO +-use_dsp48 auto +-iobuf YES +-max_fanout 500 +-bufg 32 +-bufr 24 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-use_clock_enable Auto +-use_sync_set Auto +-use_sync_reset Auto +-iob auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/projects/eval_gray_counter/top_vhdl.prj b/projects/eval_gray_counter/top_vhdl.prj new file mode 100644 index 0000000..e07a599 --- /dev/null +++ b/projects/eval_gray_counter/top_vhdl.prj @@ -0,0 +1,3 @@ +vhdl work "W:\vhdl\projects\eval_gray_counter\fifo_ctrl_pkg.vhd" +vhdl work "W:\vhdl\lib\FIFO\src\gray_counter.vhd" +vhdl work "W:\vhdl\projects\eval_gray_counter\top.vhd" diff --git a/projects/eval_sync/ise/d_ff.prj b/projects/eval_sync/ise/d_ff.prj new file mode 100644 index 0000000..c8b4d51 --- /dev/null +++ b/projects/eval_sync/ise/d_ff.prj @@ -0,0 +1 @@ +vhdl work "d_ff.vhd" diff --git a/projects/eval_sync/ise/eval_sync.ise b/projects/eval_sync/ise/eval_sync.ise new file mode 100644 index 0000000..129efb5 Binary files /dev/null and b/projects/eval_sync/ise/eval_sync.ise differ diff --git a/projects/eval_sync/ise/eval_synch_top.lso b/projects/eval_sync/ise/eval_synch_top.lso new file mode 100644 index 0000000..22de730 --- /dev/null +++ b/projects/eval_sync/ise/eval_synch_top.lso @@ -0,0 +1 @@ +work diff --git a/projects/eval_sync/ise/eval_synch_top.prj b/projects/eval_sync/ise/eval_synch_top.prj new file mode 100644 index 0000000..b415e4c --- /dev/null +++ b/projects/eval_sync/ise/eval_synch_top.prj @@ -0,0 +1,2 @@ +vhdl work "d_ff.vhd" +vhdl work "eval_synch_top.vhd" diff --git a/projects/eval_sync/ise/tb_eval_synch_vhd.fdo b/projects/eval_sync/ise/tb_eval_synch_vhd.fdo new file mode 100644 index 0000000..1182230 --- /dev/null +++ b/projects/eval_sync/ise/tb_eval_synch_vhd.fdo @@ -0,0 +1,14 @@ +## NOTE: Do not edit this file. +## Autogenerated by ProjNav (creatfdo.tcl) on Sat Oct 08 13:45:11 Westeuropäische Sommerzeit 2005 +## +vlib work +vcom -93 -explicit d_ff.vhd +vcom -93 -explicit eval_synch_top.vhd +vcom -93 -explicit tb_eval_synch.vhd +vsim -t 1ps -lib work tb_eval_synch_vhd +do {tb_eval_synch_vhd.udo} +view wave +add wave * +view structure +view signals +run 1000ns diff --git a/projects/eval_sync/ise/tb_eval_synch_vhd.udo b/projects/eval_sync/ise/tb_eval_synch_vhd.udo new file mode 100644 index 0000000..b855b44 --- /dev/null +++ b/projects/eval_sync/ise/tb_eval_synch_vhd.udo @@ -0,0 +1,4 @@ +-- ProjNav VHDL simulation template: tb_eval_synch_vhd.udo +-- You may edit this file after the line that starts with +-- '-- START' to customize your simulation +-- START user-defined simulation commands diff --git a/projects/eval_sync/src/d_ff.vhd b/projects/eval_sync/src/d_ff.vhd new file mode 100644 index 0000000..02ec55a --- /dev/null +++ b/projects/eval_sync/src/d_ff.vhd @@ -0,0 +1,53 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 13:19:14 10/08/05 +-- Design Name: +-- Module Name: d_ff - Behavioral +-- Project Name: +-- Target Device: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity d_ff is + Generic ( + tpd : time := 1 ns + ); + Port ( rst : in std_logic; + clk : in std_logic; + din : in std_logic; + dout : out std_logic); +end d_ff; + +architecture Behavioral of d_ff is + +begin + +d_ff_proc : process(rst, clk, din) +begin + if (rst = '1') then + dout <= '0' after tpd; + elsif rising_edge(clk) then + dout <= din after tpd; + end if; +end process; + +end Behavioral; diff --git a/projects/eval_sync/src/eval_synch_top.vhd b/projects/eval_sync/src/eval_synch_top.vhd new file mode 100644 index 0000000..09e71a8 --- /dev/null +++ b/projects/eval_sync/src/eval_synch_top.vhd @@ -0,0 +1,71 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 12:33:39 10/08/05 +-- Design Name: +-- Module Name: eval_synch_top - Behavioral +-- Project Name: +-- Target Device: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity eval_synch_top is + Generic (N : integer := 8); + Port ( rst : in std_logic; + clk : in std_logic; + din : in std_logic; + dout : out std_logic_vector(0 to N-1)); +end eval_synch_top; + +architecture Behavioral of eval_synch_top is + + COMPONENT d_ff + GENERIC(tpd : time); + PORT( + rst : IN std_logic; + clk : IN std_logic; + din : IN std_logic; + dout : OUT std_logic + ); + END COMPONENT; + +------------------------------------------------- +signal d_i : std_logic_vector(0 to N); + +begin + +d_i(0) <= din; +dout <= d_i(1 to N); + +inst_shift_reg : for i in 1 to N generate + + Inst_d_ff: d_ff + GENERIC MAP(tpd => 2.5 ns) + PORT MAP( + rst => rst, + clk => clk, + din => d_i(i-1), + dout => d_i(i) + ); + +end generate; + +end Behavioral; diff --git a/projects/eval_sync/src/tb_eval_synch.vhd b/projects/eval_sync/src/tb_eval_synch.vhd new file mode 100644 index 0000000..787eb5d --- /dev/null +++ b/projects/eval_sync/src/tb_eval_synch.vhd @@ -0,0 +1,106 @@ + +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 13:42:54 10/08/2005 +-- Design Name: eval_synch_top +-- Module Name: tb_eval_synch.vhd +-- Project Name: eval_sync +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: eval_synch_top +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE ieee.numeric_std.ALL; + +ENTITY tb_eval_synch_vhd IS +END tb_eval_synch_vhd; + +ARCHITECTURE behavior OF tb_eval_synch_vhd IS + + -- Component Declaration for the Unit Under Test (UUT) + COMPONENT eval_synch_top + PORT( + rst : IN std_logic; + clk : IN std_logic; + din : IN std_logic; + dout : OUT std_logic_vector(0 to 7) + ); + END COMPONENT; + + --Constants + constant PERIOD : time := 10 ns; + + --Inputs + SIGNAL rst : std_logic := '1'; + SIGNAL clk : std_logic := '0'; + SIGNAL din : std_logic := '0'; + + --Outputs + SIGNAL dout : std_logic_vector(0 to 7); + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: eval_synch_top PORT MAP( + rst => rst, + clk => clk, + din => din, + dout => dout + ); + + tb_clk : PROCESS + BEGIN + clk <= not clk; + wait for PERIOD/2; + END PROCESS; + + tb : PROCESS + BEGIN + + -- Wait 100 ns for global reset to finish + wait for 2*PERIOD; + rst <= '0'; + + wait for 1.0*PERIOD + 0 ns; + din <= '1'; + + wait for PERIOD; + din <= '0'; + + wait for PERIOD; + din <= '1'; + + wait for PERIOD; + din <= '1'; + + wait for PERIOD; + din <= '0'; + + -- Wait 100 ns for global reset to finish + wait for 100 ns; + + -- Place stimulus here + + wait; -- will wait forever + END PROCESS; + +END; diff --git a/projects/eval_timingconstraint/main_top.lso b/projects/eval_timingconstraint/main_top.lso new file mode 100644 index 0000000..22de730 --- /dev/null +++ b/projects/eval_timingconstraint/main_top.lso @@ -0,0 +1 @@ +work diff --git a/projects/eval_timingconstraint/main_top.prj b/projects/eval_timingconstraint/main_top.prj new file mode 100644 index 0000000..b52eb62 --- /dev/null +++ b/projects/eval_timingconstraint/main_top.prj @@ -0,0 +1 @@ +vhdl work main_top.vhdl diff --git a/projects/eval_timingconstraint/main_top.ucf b/projects/eval_timingconstraint/main_top.ucf new file mode 100644 index 0000000..a21fd58 --- /dev/null +++ b/projects/eval_timingconstraint/main_top.ucf @@ -0,0 +1,8 @@ +INST "clki" TNM = "TNM_clk"; +NET "clki" PERIOD = 20 ns LOW 50 %; + +INST "di" TNM = "testgrp_in"; +INST "do" TNM = "testgrp_out"; +TIMEGRP "testgrp_in" OFFSET = IN 10 ns BEFORE "clki" ; +TIMEGRP "testgrp_out" OFFSET = OUT 25 ns AFTER "clki" ; +#OFFSET = OUT 2 ns BEFORE "clk" TIMEGRP "TNM_clk" ; diff --git a/projects/eval_timingconstraint/main_top.vhdl b/projects/eval_timingconstraint/main_top.vhdl new file mode 100644 index 0000000..9e0e987 --- /dev/null +++ b/projects/eval_timingconstraint/main_top.vhdl @@ -0,0 +1,92 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following lines to use the declarations that are +-- provided for instantiating Xilinx primitive components. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity main_top is + Port ( res : in std_logic; + clki : in std_logic; + clko : out std_logic; + di : in std_logic; + do : out std_logic); +end main_top; + +architecture Behavioral of main_top is + +type state_type is (idle, active, release); +signal state, nextstate : state_type; +signal clk : std_logic; +shared variable test : std_logic; + + component BUFG + port (I: in std_logic; O: out std_logic); + end component; + +--**Insert the following after the 'begin' keyword** + + +begin +--U1: BUFG port map (I => clki, O => clk); + +clk <= clki; + +process (res, clk, di, state) +begin + if (res = '1') then + clko <= '0'; + else + clko <= '1'; + case state is + + when idle => + if (di = '1') then + nextstate <= active; + else + nextstate <= idle; + end if; + + when active => + if (di = '1') then + nextstate <= active; + else + nextstate <= idle; + end if; + + when release => + nextstate <= idle; + + end case; + end if; +end process; + +process (res, clk, state) +begin + if (res = '1') then + do <= '0'; + else + + do <= '0'; + case state is + when active => + do <= '1'; + + when others => + end case; + end if; +end process; + +process (res, clk) +begin + if (res = '1') then + state <= idle; + elsif clk'event and clk = '1' then + state <= nextstate; + end if; +end process; + +end Behavioral; diff --git a/projects/eval_timingconstraint/main_top_main_top_tb_vhd_tb.fdo b/projects/eval_timingconstraint/main_top_main_top_tb_vhd_tb.fdo new file mode 100644 index 0000000..95a997d --- /dev/null +++ b/projects/eval_timingconstraint/main_top_main_top_tb_vhd_tb.fdo @@ -0,0 +1,13 @@ +## NOTE: Do not edit this file. +## Autogenerated by ProjNav (creatfdo.tcl) on Tue Jun 08 23:46:14 Westeuropäische Sommerzeit 2004 +## +vlib work +vcom -93 -explicit main_top.vhdl +vcom -93 -explicit main_top_tb.vhd +vsim -t 1ps -lib work main_top_main_top_tb_vhd_tb +do main_top_main_top_tb_vhd_tb.udo +view wave +add wave * +view structure +view signals +run 1000ns diff --git a/projects/eval_timingconstraint/main_top_main_top_tb_vhd_tb.tdo b/projects/eval_timingconstraint/main_top_main_top_tb_vhd_tb.tdo new file mode 100644 index 0000000..042d91d --- /dev/null +++ b/projects/eval_timingconstraint/main_top_main_top_tb_vhd_tb.tdo @@ -0,0 +1,15 @@ +## NOTE: Do not edit this file. +## Auto generated by Project Navigator for VHDL Post-PAR Simulation +## +vlib work +## Compile Post-PAR Model for Module main_top +vcom -87 -explicit main_top_timesim.vhd +vcom -93 -explicit main_top_tb.vhd +vsim -t 1ps -sdfmax /UUT=main_top_timesim.sdf -lib work main_top_main_top_tb_vhd_tb +do main_top_main_top_tb_vhd_tb.udo +view wave +add wave * +view structure +view signals +run 1000ns +## End diff --git a/projects/eval_timingconstraint/main_top_main_top_tb_vhd_tb.udo b/projects/eval_timingconstraint/main_top_main_top_tb_vhd_tb.udo new file mode 100644 index 0000000..9d670db --- /dev/null +++ b/projects/eval_timingconstraint/main_top_main_top_tb_vhd_tb.udo @@ -0,0 +1,4 @@ +-- ProjNav VHDL simulation template: main_top_main_top_tb_vhd_tb.udo +-- You may edit this file after the line that starts with +-- '-- START' to customize your simulation +-- START user-defined simulation commands diff --git a/projects/eval_timingconstraint/main_top_tb.vhd b/projects/eval_timingconstraint/main_top_tb.vhd new file mode 100644 index 0000000..225031a --- /dev/null +++ b/projects/eval_timingconstraint/main_top_tb.vhd @@ -0,0 +1,74 @@ + +-- VHDL Test Bench Created from source file main_top.vhd -- 22:41:27 06/08/2004 +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY main_top_main_top_tb_vhd_tb IS +END main_top_main_top_tb_vhd_tb; + +ARCHITECTURE behavior OF main_top_main_top_tb_vhd_tb IS + + COMPONENT main_top + PORT( + res : IN std_logic; + clki : IN std_logic; + di : IN std_logic; + clko : OUT std_logic; + do : OUT std_logic + ); + END COMPONENT; + + constant ClockPeriod : Time := 20 ns; + SIGNAL res : std_logic := '1'; + SIGNAL clki : std_logic; + SIGNAL clko : std_logic; + SIGNAL di : std_logic := '0'; + SIGNAL do : std_logic; + +BEGIN + + uut: main_top PORT MAP( + res => res, + clki => clki, + clko => clko, + di => di, + do => do + ); + + clkgen: process + begin + clki <= '1'; + loop + wait for (ClockPeriod / 2); + clki <= not clki; + end loop; + end process; + +-- *** Test Bench - User Defined Section *** + tb : PROCESS + BEGIN + res <= '1'; + + wait for 5*ClockPeriod; + res <= '0'; + + wait for 5*ClockPeriod; + di <= '1'; + + wait for 14.5*ClockPeriod; + di <= '0'; + + wait; -- will wait forever + END PROCESS; +-- *** End Test Bench - User Defined Section *** + +END; diff --git a/projects/eval_timingconstraint/main_top_timesim.vhd b/projects/eval_timingconstraint/main_top_timesim.vhd new file mode 100644 index 0000000..d91b049 --- /dev/null +++ b/projects/eval_timingconstraint/main_top_timesim.vhd @@ -0,0 +1,432 @@ +-- Xilinx Vhdl netlist produced by netgen application (version G.30) +-- Command : -intstyle ise -s 6 -pcf main_top.pcf -ngm main_top.ngm -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim main_top.ncd main_top_timesim.vhd +-- Input file : main_top.ncd +-- Output file : main_top_timesim.vhd +-- Design name : main_top +-- # of Entities : 1 +-- Xilinx : D:/Xilinx +-- Device : 2v250cs144-6 (PRODUCTION 1.118 2004-03-12, STEPPING 1) + +-- This vhdl netlist is a simulation model and uses simulation +-- primitives which may not represent the true implementation of the +-- device, however the netlist is functionally correct and should not +-- be modified. This file cannot be synthesized and should only be used +-- with supported simulation tools. + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library SIMPRIM; +use SIMPRIM.VCOMPONENTS.ALL; +use SIMPRIM.VPACKAGE.ALL; + +entity main_top is + port ( + clko : out STD_LOGIC; + do : out STD_LOGIC; + res : in STD_LOGIC := 'X'; + clki : in STD_LOGIC := 'X'; + di : in STD_LOGIC := 'X' + ); +end main_top; + +architecture Structure of main_top is + signal di_IBUF : STD_LOGIC; + signal do_OBUF : STD_LOGIC; + signal clki_IBUFG : STD_LOGIC; + signal clko_OBUF : STD_LOGIC; + signal res_BUFGP_IBUFG : STD_LOGIC; + signal GLOBAL_LOGIC1 : STD_LOGIC; + signal res_BUFGP : STD_LOGIC; + signal GLOBAL_LOGIC1_0 : STD_LOGIC; + signal GSR : STD_LOGIC; + signal GTS : STD_LOGIC; + signal di_INBUF : STD_LOGIC; + signal do_ENABLE : STD_LOGIC; + signal do_GTS_OR_T : STD_LOGIC; + signal do_O : STD_LOGIC; + signal clki_INBUF : STD_LOGIC; + signal clko_ENABLE : STD_LOGIC; + signal clko_GTS_OR_T : STD_LOGIC; + signal clko_O : STD_LOGIC; + signal res_INBUF : STD_LOGIC; + signal U1_S_INVNOT : STD_LOGIC; + signal res_BUFGP_BUFG_S_INVNOT : STD_LOGIC; + signal nextstate_1_DXMUX : STD_LOGIC; + signal nextstate_1_F : STD_LOGIC; + signal nextstate_1_DYMUX : STD_LOGIC; + signal nextstate_1_G : STD_LOGIC; + signal nextstate_1_CLKINV : STD_LOGIC; + signal state_1_DXMUX : STD_LOGIC; + signal state_1_DYMUX : STD_LOGIC; + signal state_1_SRFFMUX : STD_LOGIC; + signal state_1_CLKINV : STD_LOGIC; + signal do_OBUF_G : STD_LOGIC; + signal nextstate_1_FFY_SET : STD_LOGIC; + signal nextstate_1_FFX_RST : STD_LOGIC; + signal state_1_FFY_SET : STD_LOGIC; + signal state_1_FFX_RST : STD_LOGIC; + signal GND : STD_LOGIC; + signal VCC : STD_LOGIC; + signal NlwInverterSignal_nextstate_0_CLK : STD_LOGIC; + signal NlwInverterSignal_nextstate_1_CLK : STD_LOGIC; + signal state : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal Q_n0003 : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal nextstate : STD_LOGIC_VECTOR ( 1 downto 0 ); +begin + di_IBUF_0 : X_BUF_PP + generic map( + PATHPULSE => 605 ps + ) + port map ( + I => di, + O => di_INBUF + ); + do_OBUF_1 : X_TRI_PP + generic map( + PATHPULSE => 605 ps + ) + port map ( + I => do_O, + CTL => do_ENABLE, + O => do + ); + do_ENABLEINV : X_INV + port map ( + I => do_GTS_OR_T, + O => do_ENABLE + ); + do_GTS_OR_T_2 : X_BUF_PP + generic map( + PATHPULSE => 605 ps + ) + port map ( + I => GTS, + O => do_GTS_OR_T + ); + clki_IBUFG_3 : X_BUF_PP + generic map( + PATHPULSE => 605 ps + ) + port map ( + I => clki, + O => clki_INBUF + ); + clko_OBUF_4 : X_TRI_PP + generic map( + PATHPULSE => 605 ps + ) + port map ( + I => clko_O, + CTL => clko_ENABLE, + O => clko + ); + clko_ENABLEINV : X_INV + port map ( + I => clko_GTS_OR_T, + O => clko_ENABLE + ); + clko_GTS_OR_T_5 : X_BUF_PP + generic map( + PATHPULSE => 605 ps + ) + port map ( + I => GTS, + O => clko_GTS_OR_T + ); + res_BUFGP_IBUFG_6 : X_BUF_PP + generic map( + PATHPULSE => 605 ps + ) + port map ( + I => res, + O => res_INBUF + ); + U1 : X_BUFGMUX + port map ( + I0 => clki_IBUFG, + I1 => GND, + S => U1_S_INVNOT, + O => clko_OBUF, + GSR => GSR + ); + U1_SINV : X_INV + port map ( + I => GLOBAL_LOGIC1, + O => U1_S_INVNOT + ); + res_BUFGP_BUFG : X_BUFGMUX + port map ( + I0 => res_BUFGP_IBUFG, + I1 => GND, + S => res_BUFGP_BUFG_S_INVNOT, + O => res_BUFGP, + GSR => GSR + ); + res_BUFGP_BUFG_SINV : X_INV + port map ( + I => GLOBAL_LOGIC1_0, + O => res_BUFGP_BUFG_S_INVNOT + ); + nextstate_1_DXMUX_7 : X_BUF_PP + generic map( + PATHPULSE => 605 ps + ) + port map ( + I => Q_n0003(1), + O => nextstate_1_DXMUX + ); + nextstate_1_XUSED : X_BUF_PP + generic map( + PATHPULSE => 605 ps + ) + port map ( + I => nextstate_1_F, + O => Q_n0003(1) + ); + nextstate_1_DYMUX_8 : X_BUF_PP + generic map( + PATHPULSE => 605 ps + ) + port map ( + I => Q_n0003(0), + O => nextstate_1_DYMUX + ); + nextstate_1_YUSED : X_BUF_PP + generic map( + PATHPULSE => 605 ps + ) + port map ( + I => nextstate_1_G, + O => Q_n0003(0) + ); + nextstate_1_CLKINV_9 : X_BUF_PP + generic map( + PATHPULSE => 605 ps + ) + port map ( + I => res_BUFGP, + O => nextstate_1_CLKINV + ); + state_1_DXMUX_10 : X_BUF_PP + generic map( + PATHPULSE => 605 ps + ) + port map ( + I => nextstate(1), + O => state_1_DXMUX + ); + state_1_DYMUX_11 : X_BUF_PP + generic map( + PATHPULSE => 605 ps + ) + port map ( + I => nextstate(0), + O => state_1_DYMUX + ); + state_1_SRFFMUX_12 : X_BUF_PP + generic map( + PATHPULSE => 605 ps + ) + port map ( + I => res_BUFGP, + O => state_1_SRFFMUX + ); + state_1_CLKINV_13 : X_BUF_PP + generic map( + PATHPULSE => 605 ps + ) + port map ( + I => clko_OBUF, + O => state_1_CLKINV + ); + do_OBUF_YUSED : X_BUF_PP + generic map( + PATHPULSE => 605 ps + ) + port map ( + I => do_OBUF_G, + O => do_OBUF + ); + Q_n0003_0_1 : X_LUT4 + generic map( + INIT => X"5544" + ) + port map ( + ADR0 => di_IBUF, + ADR1 => state(1), + ADR2 => VCC, + ADR3 => state(0), + O => nextstate_1_G + ); + nextstate_0 : X_LATCHE + generic map( + INIT => '1' + ) + port map ( + I => nextstate_1_DYMUX, + GE => VCC, + CLK => NlwInverterSignal_nextstate_0_CLK, + SET => nextstate_1_FFY_SET, + RST => GND, + O => nextstate(0) + ); + nextstate_1_FFY_SETOR : X_BUF_PP + generic map( + PATHPULSE => 605 ps + ) + port map ( + I => GSR, + O => nextstate_1_FFY_SET + ); + Q_n0003_1_1 : X_LUT4 + generic map( + INIT => X"AA88" + ) + port map ( + ADR0 => di_IBUF, + ADR1 => state(1), + ADR2 => VCC, + ADR3 => state(0), + O => nextstate_1_F + ); + nextstate_1 : X_LATCHE + generic map( + INIT => '0' + ) + port map ( + I => nextstate_1_DXMUX, + GE => VCC, + CLK => NlwInverterSignal_nextstate_1_CLK, + SET => GND, + RST => nextstate_1_FFX_RST, + O => nextstate(1) + ); + nextstate_1_FFX_RSTOR : X_BUF_PP + generic map( + PATHPULSE => 605 ps + ) + port map ( + I => GSR, + O => nextstate_1_FFX_RST + ); + state_0 : X_FF + generic map( + INIT => '1' + ) + port map ( + I => state_1_DYMUX, + CE => VCC, + CLK => state_1_CLKINV, + SET => state_1_FFY_SET, + RST => GND, + O => state(0) + ); + state_1_FFY_SETOR : X_OR2 + port map ( + I0 => GSR, + I1 => state_1_SRFFMUX, + O => state_1_FFY_SET + ); + Q_n00061 : X_LUT4 + generic map( + INIT => X"4444" + ) + port map ( + ADR0 => res_BUFGP, + ADR1 => state(1), + ADR2 => VCC, + ADR3 => VCC, + O => do_OBUF_G + ); + state_1 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => state_1_DXMUX, + CE => VCC, + CLK => state_1_CLKINV, + SET => GND, + RST => state_1_FFX_RST, + O => state(1) + ); + state_1_FFX_RSTOR : X_OR2 + port map ( + I0 => state_1_SRFFMUX, + I1 => GSR, + O => state_1_FFX_RST + ); + PWR_VCC_0_LOGICAL_ONE : X_ONE + port map ( + O => GLOBAL_LOGIC1 + ); + PWR_VCC_1_LOGICAL_ONE : X_ONE + port map ( + O => GLOBAL_LOGIC1_0 + ); + di_IFF_IMUX : X_BUF_PP + generic map( + PATHPULSE => 605 ps + ) + port map ( + I => di_INBUF, + O => di_IBUF + ); + do_OUTPUT_OFF_OMUX : X_BUF_PP + generic map( + PATHPULSE => 605 ps + ) + port map ( + I => do_OBUF, + O => do_O + ); + clki_IFF_IMUX : X_BUF_PP + generic map( + PATHPULSE => 605 ps + ) + port map ( + I => clki_INBUF, + O => clki_IBUFG + ); + clko_OUTPUT_OFF_OMUX : X_BUF_PP + generic map( + PATHPULSE => 605 ps + ) + port map ( + I => clko_OBUF, + O => clko_O + ); + res_IFF_IMUX : X_BUF_PP + generic map( + PATHPULSE => 605 ps + ) + port map ( + I => res_INBUF, + O => res_BUFGP_IBUFG + ); + NlwBlock_main_top_GND : X_ZERO + port map ( + O => GND + ); + NlwBlock_main_top_VCC : X_ONE + port map ( + O => VCC + ); + NlwInverterBlock_nextstate_0_CLK : X_INV + port map ( + I => nextstate_1_CLKINV, + O => NlwInverterSignal_nextstate_0_CLK + ); + NlwInverterBlock_nextstate_1_CLK : X_INV + port map ( + I => nextstate_1_CLKINV, + O => NlwInverterSignal_nextstate_1_CLK + ); + NlwBlockROC : X_ROC + generic map (ROC_WIDTH => 100 ns) + port map (O => GSR); + NlwBlockTOC : X_TOC + port map (O => GTS); + +end Structure; + diff --git a/projects/eval_timingconstraint/main_top_vhdl.prj b/projects/eval_timingconstraint/main_top_vhdl.prj new file mode 100644 index 0000000..bdb3bfc --- /dev/null +++ b/projects/eval_timingconstraint/main_top_vhdl.prj @@ -0,0 +1 @@ +work main_top.vhdl diff --git a/projects/eval_timingconstraint/pepExtractor.prj b/projects/eval_timingconstraint/pepExtractor.prj new file mode 100644 index 0000000..c104b61 --- /dev/null +++ b/projects/eval_timingconstraint/pepExtractor.prj @@ -0,0 +1 @@ +work main_top.vhdl diff --git a/projects/eval_twoclocks/eval2clk.lso b/projects/eval_twoclocks/eval2clk.lso new file mode 100644 index 0000000..22de730 --- /dev/null +++ b/projects/eval_twoclocks/eval2clk.lso @@ -0,0 +1 @@ +work diff --git a/projects/eval_twoclocks/eval2clk.prj b/projects/eval_twoclocks/eval2clk.prj new file mode 100644 index 0000000..b46a177 --- /dev/null +++ b/projects/eval_twoclocks/eval2clk.prj @@ -0,0 +1 @@ +vhdl work vconfig.vhdl diff --git a/projects/eval_twoclocks/eval2clk_tb.fdo b/projects/eval_twoclocks/eval2clk_tb.fdo new file mode 100644 index 0000000..df24188 --- /dev/null +++ b/projects/eval_twoclocks/eval2clk_tb.fdo @@ -0,0 +1,13 @@ +## NOTE: Do not edit this file. +## Autogenerated by ProjNav (creatfdo.tcl) on Wed Jun 02 00:12:48 Westeuropäische Sommerzeit 2004 +## +vlib work +vcom -93 -explicit vconfig.vhdl +vcom -93 -explicit eval2clk_tb.vhd +vsim -t 1ps -lib work eval2clk_tb +do eval2clk_tb.udo +view wave +add wave * +view structure +view signals +run 2000ns diff --git a/projects/eval_twoclocks/eval2clk_tb.tdo b/projects/eval_twoclocks/eval2clk_tb.tdo new file mode 100644 index 0000000..519eab9 --- /dev/null +++ b/projects/eval_twoclocks/eval2clk_tb.tdo @@ -0,0 +1,15 @@ +## NOTE: Do not edit this file. +## Auto generated by Project Navigator for VHDL Post-PAR Simulation +## +vlib work +## Compile Post-PAR Model for Module eval2clk +vcom -87 -explicit eval2clk_timesim.vhd +vcom -93 -explicit eval2clk_tb.vhd +vsim -t 1ps -sdfmax /UUT=eval2clk_timesim.sdf -lib work eval2clk_tb +do eval2clk_tb.udo +view wave +add wave * +view structure +view signals +run 2000ns +## End diff --git a/projects/eval_twoclocks/eval2clk_tb.udo b/projects/eval_twoclocks/eval2clk_tb.udo new file mode 100644 index 0000000..0373d6e --- /dev/null +++ b/projects/eval_twoclocks/eval2clk_tb.udo @@ -0,0 +1,4 @@ +-- ProjNav VHDL simulation template: eval2clk_tb.udo +-- You may edit this file after the line that starts with +-- '-- START' to customize your simulation +-- START user-defined simulation commands diff --git a/projects/eval_twoclocks/eval2clk_tb.vhd b/projects/eval_twoclocks/eval2clk_tb.vhd new file mode 100644 index 0000000..032b35f --- /dev/null +++ b/projects/eval_twoclocks/eval2clk_tb.vhd @@ -0,0 +1,67 @@ + +-- VHDL Test Bench Created from source file vconfig.vhd -- 20:20:01 05/01/2004 +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY eval2clk_tb IS +END eval2clk_tb; + +ARCHITECTURE behavior OF eval2clk_tb IS + + COMPONENT eval2clk + PORT( + RES : IN std_logic; + CLK : IN std_logic; + SCLK : INOUT std_logic; + dummy_out : INOUT std_logic + ); + END COMPONENT; + + + SIGNAL RES : std_logic := '1'; + SIGNAL CLK : std_logic := '0'; + SIGNAL SCLK : std_logic; + SIGNAL dummy_out : std_logic := '0'; + + constant ClockPeriod : Time := 16.667 ns; + +BEGIN + + uut: eval2clk PORT MAP( + RES => RES, + CLK => CLK, + SCLK => SCLK, + dummy_out => dummy_out + ); + + busclock: process + begin + CLK <= '1'; + loop + wait for (ClockPeriod / 2); + CLK <= not CLK; + end loop; + end process; + +-- *** Test Bench - User Defined Section *** + tb : PROCESS + BEGIN + + wait for 20*ClockPeriod; + RES <= '0'; + + + wait; -- will wait forever + END PROCESS; +-- *** End Test Bench - User Defined Section *** + +END; diff --git a/projects/eval_twoclocks/eval2clk_timesim.vhd b/projects/eval_twoclocks/eval2clk_timesim.vhd new file mode 100644 index 0000000..443e44d --- /dev/null +++ b/projects/eval_twoclocks/eval2clk_timesim.vhd @@ -0,0 +1,1494 @@ +-- Xilinx Vhdl netlist produced by netgen application (version G.30) +-- Command : -rpw 100 -ar Structure -xon true -w -ofmt vhdl -sim eval2clk.nga eval2clk_timesim.vhd +-- Input file : eval2clk.nga +-- Output file : eval2clk_timesim.vhd +-- Design name : eval2clk.nga +-- # of Entities : 1 +-- Xilinx : D:/Xilinx +-- Device : XC95288XL-6-TQ144 (Speed File: Version 3.0) + +-- This vhdl netlist is a simulation model and uses simulation +-- primitives which may not represent the true implementation of the +-- device, however the netlist is functionally correct and should not +-- be modified. This file cannot be synthesized and should only be used +-- with supported simulation tools. + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library SIMPRIM; +use SIMPRIM.VCOMPONENTS.ALL; +use SIMPRIM.VPACKAGE.ALL; + +entity eval2clk is + port ( + RES : in STD_LOGIC := 'X'; + CLK : in STD_LOGIC := 'X'; + dummy_out : out STD_LOGIC; + SCLK : out STD_LOGIC + ); +end eval2clk; + +architecture Structure of eval2clk is + signal SCLK_OBUF : STD_LOGIC; + signal FSRIO_1 : STD_LOGIC; + signal FCLKIO_0 : STD_LOGIC; + signal dummy_out_OBUF_Q : STD_LOGIC; + signal SCLK_OBUF_BUF0 : STD_LOGIC; + signal dummy_out_OBUF_Q_0 : STD_LOGIC; + signal dummy_out_OBUF_D : STD_LOGIC; + signal dummy_out_OBUF_tsimcreated_xor_Q : STD_LOGIC; + signal PRLD : STD_LOGIC; + signal dummy_out_OBUF_tsimcreated_prld_Q : STD_LOGIC; + signal dummy_out_OBUF_CLKF : STD_LOGIC; + signal Gnd : STD_LOGIC; + signal dummy_out_OBUF_CE : STD_LOGIC; + signal dummy_out_OBUF_D1 : STD_LOGIC; + signal dummy_out_OBUF_D2 : STD_LOGIC; + signal SCLK1 : STD_LOGIC; + signal SCLK1_Q : STD_LOGIC; + signal SCLK1_D : STD_LOGIC; + signal SCLK1_tsimcreated_xor_Q : STD_LOGIC; + signal SCLK1_tsimcreated_prld_Q : STD_LOGIC; + signal SCLK1_CE : STD_LOGIC; + signal SCLK1_D1 : STD_LOGIC; + signal SCLK1_D2 : STD_LOGIC; + signal count_0_Q : STD_LOGIC; + signal count_0_D : STD_LOGIC; + signal count_0_tsimcreated_xor_Q : STD_LOGIC; + signal count_0_tsimcreated_prld_Q : STD_LOGIC; + signal Vcc : STD_LOGIC; + signal count_0_D1 : STD_LOGIC; + signal count_0_D2 : STD_LOGIC; + signal count_4_Q : STD_LOGIC; + signal count_4_D : STD_LOGIC; + signal count_4_tsimcreated_xor_Q : STD_LOGIC; + signal count_4_tsimcreated_prld_Q : STD_LOGIC; + signal count_4_D1 : STD_LOGIC; + signal count_4_D2 : STD_LOGIC; + signal count_4_D2_PT_0 : STD_LOGIC; + signal count_4_D2_PT_1 : STD_LOGIC; + signal scount_0_Q : STD_LOGIC; + signal scount_0_D : STD_LOGIC; + signal scount_0_tsimcreated_xor_Q : STD_LOGIC; + signal scount_0_tsimcreated_prld_Q : STD_LOGIC; + signal scount_0_CLKF : STD_LOGIC; + signal scount_0_D1 : STD_LOGIC; + signal scount_0_D2 : STD_LOGIC; + signal scount_4_Q : STD_LOGIC; + signal scount_4_D : STD_LOGIC; + signal scount_4_tsimcreated_xor_Q : STD_LOGIC; + signal scount_4_tsimcreated_prld_Q : STD_LOGIC; + signal scount_4_CLKF : STD_LOGIC; + signal scount_4_D1 : STD_LOGIC; + signal scount_4_D2 : STD_LOGIC; + signal scount_4_D2_PT_0 : STD_LOGIC; + signal scount_4_D2_PT_1 : STD_LOGIC; + signal count_1_Q : STD_LOGIC; + signal count_1_D : STD_LOGIC; + signal count_1_tsimcreated_xor_Q : STD_LOGIC; + signal count_1_tsimcreated_prld_Q : STD_LOGIC; + signal count_1_D1 : STD_LOGIC; + signal count_1_D2 : STD_LOGIC; + signal count_1_D2_PT_0 : STD_LOGIC; + signal count_1_D2_PT_1 : STD_LOGIC; + signal count_2_Q : STD_LOGIC; + signal count_2_D : STD_LOGIC; + signal count_2_tsimcreated_xor_Q : STD_LOGIC; + signal count_2_D1 : STD_LOGIC; + signal count_2_D2 : STD_LOGIC; + signal count_3_Q : STD_LOGIC; + signal count_3_D : STD_LOGIC; + signal count_3_tsimcreated_xor_Q : STD_LOGIC; + signal count_3_tsimcreated_prld_Q : STD_LOGIC; + signal count_3_D1 : STD_LOGIC; + signal count_3_D2 : STD_LOGIC; + signal count_3_D2_PT_0 : STD_LOGIC; + signal count_3_D2_PT_1 : STD_LOGIC; + signal count_3_D2_PT_2 : STD_LOGIC; + signal scount_1_Q : STD_LOGIC; + signal scount_1_D : STD_LOGIC; + signal scount_1_tsimcreated_xor_Q : STD_LOGIC; + signal scount_1_CLKF : STD_LOGIC; + signal scount_1_D1 : STD_LOGIC; + signal scount_1_D2 : STD_LOGIC; + signal scount_2_Q : STD_LOGIC; + signal scount_2_D : STD_LOGIC; + signal scount_2_tsimcreated_xor_Q : STD_LOGIC; + signal scount_2_tsimcreated_prld_Q : STD_LOGIC; + signal scount_2_CLKF : STD_LOGIC; + signal scount_2_D1 : STD_LOGIC; + signal scount_2_D2 : STD_LOGIC; + signal scount_2_D2_PT_0 : STD_LOGIC; + signal scount_2_D2_PT_1 : STD_LOGIC; + signal scount_2_D2_PT_2 : STD_LOGIC; + signal scount_3_Q : STD_LOGIC; + signal scount_3_D : STD_LOGIC; + signal scount_3_tsimcreated_xor_Q : STD_LOGIC; + signal scount_3_tsimcreated_prld_Q : STD_LOGIC; + signal scount_3_CLKF : STD_LOGIC; + signal scount_3_D1 : STD_LOGIC; + signal scount_3_D2 : STD_LOGIC; + signal scount_3_D2_PT_0 : STD_LOGIC; + signal scount_3_D2_PT_1 : STD_LOGIC; + signal scount_3_D2_PT_2 : STD_LOGIC; + signal count_5_Q : STD_LOGIC; + signal count_5_D : STD_LOGIC; + signal count_5_tsimcreated_xor_Q : STD_LOGIC; + signal count_5_tsimcreated_prld_Q : STD_LOGIC; + signal count_5_D1 : STD_LOGIC; + signal count_5_D2 : STD_LOGIC; + signal scount_5_Q : STD_LOGIC; + signal scount_5_D : STD_LOGIC; + signal scount_5_tsimcreated_xor_Q : STD_LOGIC; + signal scount_5_tsimcreated_prld_Q : STD_LOGIC; + signal scount_5_CLKF : STD_LOGIC; + signal scount_5_D1 : STD_LOGIC; + signal scount_5_D2 : STD_LOGIC; + signal SCLK_OBUF_BUF0_Q : STD_LOGIC; + signal SCLK_OBUF_BUF0_D : STD_LOGIC; + signal SCLK_OBUF_BUF0_D1 : STD_LOGIC; + signal SCLK_OBUF_BUF0_D2 : STD_LOGIC; + signal NlwInverterSignal_dummy_out_OBUF_CE_IN0 : STD_LOGIC; + signal NlwInverterSignal_dummy_out_OBUF_CE_IN1 : STD_LOGIC; + signal NlwInverterSignal_dummy_out_OBUF_CE_IN2 : STD_LOGIC; + signal NlwInverterSignal_dummy_out_OBUF_CE_IN3 : STD_LOGIC; + signal NlwInverterSignal_dummy_out_OBUF_CE_IN4 : STD_LOGIC; + signal NlwInverterSignal_dummy_out_OBUF_CE_IN5 : STD_LOGIC; + signal NlwInverterSignal_SCLK1_CE_IN0 : STD_LOGIC; + signal NlwInverterSignal_SCLK1_CE_IN1 : STD_LOGIC; + signal NlwInverterSignal_SCLK1_CE_IN2 : STD_LOGIC; + signal NlwInverterSignal_SCLK1_CE_IN3 : STD_LOGIC; + signal NlwInverterSignal_SCLK1_CE_IN4 : STD_LOGIC; + signal NlwInverterSignal_SCLK1_CE_IN5 : STD_LOGIC; + signal NlwInverterSignal_count_0_D_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_0_D2_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_0_D2_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_0_D2_IN2 : STD_LOGIC; + signal NlwInverterSignal_count_0_D2_IN3 : STD_LOGIC; + signal NlwInverterSignal_count_0_D2_IN4 : STD_LOGIC; + signal NlwInverterSignal_count_0_D2_IN5 : STD_LOGIC; + signal NlwInverterSignal_count_4_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_4_D2_PT_0_IN2 : STD_LOGIC; + signal NlwInverterSignal_count_4_D2_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_count_4_D2_PT_0_IN4 : STD_LOGIC; + signal NlwInverterSignal_count_4_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_4_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_4_D2_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_count_4_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_scount_0_D_IN0 : STD_LOGIC; + signal NlwInverterSignal_scount_0_D2_IN0 : STD_LOGIC; + signal NlwInverterSignal_scount_0_D2_IN1 : STD_LOGIC; + signal NlwInverterSignal_scount_0_D2_IN2 : STD_LOGIC; + signal NlwInverterSignal_scount_0_D2_IN3 : STD_LOGIC; + signal NlwInverterSignal_scount_0_D2_IN4 : STD_LOGIC; + signal NlwInverterSignal_scount_0_D2_IN5 : STD_LOGIC; + signal NlwInverterSignal_scount_4_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_scount_4_D2_PT_0_IN2 : STD_LOGIC; + signal NlwInverterSignal_scount_4_D2_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_scount_4_D2_PT_0_IN4 : STD_LOGIC; + signal NlwInverterSignal_scount_4_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_scount_4_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_scount_4_D2_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_scount_4_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_count_1_D_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_1_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_1_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_1_D2_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_count_1_D2_PT_1_IN3 : STD_LOGIC; + signal NlwInverterSignal_count_1_D2_PT_1_IN4 : STD_LOGIC; + signal NlwInverterSignal_count_2_D2_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_2_D2_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_3_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_3_D2_PT_0_IN2 : STD_LOGIC; + signal NlwInverterSignal_count_3_D2_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_count_3_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_3_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_3_D2_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_count_3_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_3_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_3_D2_PT_2_IN2 : STD_LOGIC; + signal NlwInverterSignal_scount_1_D_IN0 : STD_LOGIC; + signal NlwInverterSignal_scount_2_D_IN0 : STD_LOGIC; + signal NlwInverterSignal_scount_2_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_scount_2_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_scount_2_D2_PT_2_IN2 : STD_LOGIC; + signal NlwInverterSignal_scount_2_D2_PT_2_IN3 : STD_LOGIC; + signal NlwInverterSignal_scount_3_D2_PT_0_IN0 : STD_LOGIC; + signal NlwInverterSignal_scount_3_D2_PT_0_IN2 : STD_LOGIC; + signal NlwInverterSignal_scount_3_D2_PT_0_IN3 : STD_LOGIC; + signal NlwInverterSignal_scount_3_D2_PT_1_IN0 : STD_LOGIC; + signal NlwInverterSignal_scount_3_D2_PT_1_IN1 : STD_LOGIC; + signal NlwInverterSignal_scount_3_D2_PT_1_IN2 : STD_LOGIC; + signal NlwInverterSignal_scount_3_D2_PT_2_IN0 : STD_LOGIC; + signal NlwInverterSignal_scount_3_D2_PT_2_IN1 : STD_LOGIC; + signal NlwInverterSignal_scount_3_D2_PT_2_IN2 : STD_LOGIC; + signal NlwInverterSignal_count_5_D2_IN0 : STD_LOGIC; + signal NlwInverterSignal_count_5_D2_IN1 : STD_LOGIC; + signal NlwInverterSignal_count_5_D2_IN2 : STD_LOGIC; + signal NlwInverterSignal_count_5_D2_IN3 : STD_LOGIC; + signal NlwInverterSignal_count_5_D2_IN4 : STD_LOGIC; + signal NlwInverterSignal_scount_5_D2_IN0 : STD_LOGIC; + signal NlwInverterSignal_scount_5_D2_IN1 : STD_LOGIC; + signal NlwInverterSignal_scount_5_D2_IN2 : STD_LOGIC; + signal NlwInverterSignal_scount_5_D2_IN3 : STD_LOGIC; + signal NlwInverterSignal_scount_5_D2_IN4 : STD_LOGIC; + signal scount : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal count : STD_LOGIC_VECTOR ( 5 downto 0 ); +begin + SCLK_OBUF_1 : X_BUF + port map ( + I => RES, + O => SCLK_OBUF + ); + FSRIO_1_2 : X_BUF + port map ( + I => RES, + O => FSRIO_1 + ); + FCLKIO_0_3 : X_BUF + port map ( + I => CLK, + O => FCLKIO_0 + ); + dummy_out_4 : X_BUF + port map ( + I => dummy_out_OBUF_Q, + O => dummy_out + ); + SCLK_5 : X_BUF + port map ( + I => SCLK_OBUF_BUF0, + O => SCLK + ); + dummy_out_OBUF_Q_6 : X_BUF + port map ( + I => dummy_out_OBUF_Q_0, + O => dummy_out_OBUF_Q + ); + dummy_out_OBUF_tsimcreated_xor_Q_7 : X_XOR2 + port map ( + I0 => dummy_out_OBUF_D, + I1 => dummy_out_OBUF_Q_0, + O => dummy_out_OBUF_tsimcreated_xor_Q + ); + dummy_out_OBUF_tsimcreated_prld_Q_8 : X_OR2 + port map ( + I0 => FSRIO_1, + I1 => PRLD, + O => dummy_out_OBUF_tsimcreated_prld_Q + ); + dummy_out_OBUF_REG : X_FF + port map ( + I => dummy_out_OBUF_tsimcreated_xor_Q, + CE => dummy_out_OBUF_CE, + CLK => dummy_out_OBUF_CLKF, + SET => dummy_out_OBUF_tsimcreated_prld_Q, + RST => Gnd, + O => dummy_out_OBUF_Q_0 + ); + Gnd_9 : X_ZERO + port map ( + O => Gnd + ); + dummy_out_OBUF_D_10 : X_XOR2 + port map ( + I0 => dummy_out_OBUF_D1, + I1 => dummy_out_OBUF_D2, + O => dummy_out_OBUF_D + ); + dummy_out_OBUF_D1_11 : X_ZERO + port map ( + O => dummy_out_OBUF_D1 + ); + dummy_out_OBUF_D2_12 : X_ONE + port map ( + O => dummy_out_OBUF_D2 + ); + dummy_out_OBUF_CLKF_13 : X_AND2 + port map ( + I0 => SCLK1, + I1 => SCLK1, + O => dummy_out_OBUF_CLKF + ); + dummy_out_OBUF_CE_14 : X_AND6 + port map ( + I0 => NlwInverterSignal_dummy_out_OBUF_CE_IN0, + I1 => NlwInverterSignal_dummy_out_OBUF_CE_IN1, + I2 => NlwInverterSignal_dummy_out_OBUF_CE_IN2, + I3 => NlwInverterSignal_dummy_out_OBUF_CE_IN3, + I4 => NlwInverterSignal_dummy_out_OBUF_CE_IN4, + I5 => NlwInverterSignal_dummy_out_OBUF_CE_IN5, + O => dummy_out_OBUF_CE + ); + SCLK1_15 : X_BUF + port map ( + I => SCLK1_Q, + O => SCLK1 + ); + SCLK1_tsimcreated_xor_Q_16 : X_XOR2 + port map ( + I0 => SCLK1_D, + I1 => SCLK1_Q, + O => SCLK1_tsimcreated_xor_Q + ); + SCLK1_tsimcreated_prld_Q_17 : X_OR2 + port map ( + I0 => FSRIO_1, + I1 => PRLD, + O => SCLK1_tsimcreated_prld_Q + ); + SCLK1_REG : X_FF + port map ( + I => SCLK1_tsimcreated_xor_Q, + CE => SCLK1_CE, + CLK => FCLKIO_0, + SET => SCLK1_tsimcreated_prld_Q, + RST => Gnd, + O => SCLK1_Q + ); + SCLK1_D_18 : X_XOR2 + port map ( + I0 => SCLK1_D1, + I1 => SCLK1_D2, + O => SCLK1_D + ); + SCLK1_D1_19 : X_ZERO + port map ( + O => SCLK1_D1 + ); + SCLK1_D2_20 : X_ONE + port map ( + O => SCLK1_D2 + ); + SCLK1_CE_21 : X_AND6 + port map ( + I0 => NlwInverterSignal_SCLK1_CE_IN0, + I1 => NlwInverterSignal_SCLK1_CE_IN1, + I2 => NlwInverterSignal_SCLK1_CE_IN2, + I3 => NlwInverterSignal_SCLK1_CE_IN3, + I4 => NlwInverterSignal_SCLK1_CE_IN4, + I5 => NlwInverterSignal_SCLK1_CE_IN5, + O => SCLK1_CE + ); + count_0_Q_22 : X_BUF + port map ( + I => count_0_Q, + O => count(0) + ); + count_0_tsimcreated_xor_Q_23 : X_XOR2 + port map ( + I0 => count_0_D, + I1 => count_0_Q, + O => count_0_tsimcreated_xor_Q + ); + count_0_tsimcreated_prld_Q_24 : X_OR2 + port map ( + I0 => FSRIO_1, + I1 => PRLD, + O => count_0_tsimcreated_prld_Q + ); + count_0_REG : X_FF + port map ( + I => count_0_tsimcreated_xor_Q, + CE => Vcc, + CLK => FCLKIO_0, + SET => Gnd, + RST => count_0_tsimcreated_prld_Q, + O => count_0_Q + ); + Vcc_25 : X_ONE + port map ( + O => Vcc + ); + count_0_D_26 : X_XOR2 + port map ( + I0 => NlwInverterSignal_count_0_D_IN0, + I1 => count_0_D2, + O => count_0_D + ); + count_0_D1_27 : X_ZERO + port map ( + O => count_0_D1 + ); + count_0_D2_28 : X_AND6 + port map ( + I0 => NlwInverterSignal_count_0_D2_IN0, + I1 => NlwInverterSignal_count_0_D2_IN1, + I2 => NlwInverterSignal_count_0_D2_IN2, + I3 => NlwInverterSignal_count_0_D2_IN3, + I4 => NlwInverterSignal_count_0_D2_IN4, + I5 => NlwInverterSignal_count_0_D2_IN5, + O => count_0_D2 + ); + count_4_Q_29 : X_BUF + port map ( + I => count_4_Q, + O => count(4) + ); + count_4_tsimcreated_xor_Q_30 : X_XOR2 + port map ( + I0 => count_4_D, + I1 => count_4_Q, + O => count_4_tsimcreated_xor_Q + ); + count_4_tsimcreated_prld_Q_31 : X_OR2 + port map ( + I0 => FSRIO_1, + I1 => PRLD, + O => count_4_tsimcreated_prld_Q + ); + count_4_REG : X_FF + port map ( + I => count_4_tsimcreated_xor_Q, + CE => Vcc, + CLK => FCLKIO_0, + SET => Gnd, + RST => count_4_tsimcreated_prld_Q, + O => count_4_Q + ); + count_4_D_32 : X_XOR2 + port map ( + I0 => count_4_D1, + I1 => count_4_D2, + O => count_4_D + ); + count_4_D1_33 : X_ZERO + port map ( + O => count_4_D1 + ); + count_4_D2_PT_0_34 : X_AND5 + port map ( + I0 => NlwInverterSignal_count_4_D2_PT_0_IN0, + I1 => count(4), + I2 => NlwInverterSignal_count_4_D2_PT_0_IN2, + I3 => NlwInverterSignal_count_4_D2_PT_0_IN3, + I4 => NlwInverterSignal_count_4_D2_PT_0_IN4, + O => count_4_D2_PT_0 + ); + count_4_D2_PT_1_35 : X_AND5 + port map ( + I0 => NlwInverterSignal_count_4_D2_PT_1_IN0, + I1 => NlwInverterSignal_count_4_D2_PT_1_IN1, + I2 => NlwInverterSignal_count_4_D2_PT_1_IN2, + I3 => NlwInverterSignal_count_4_D2_PT_1_IN3, + I4 => count(5), + O => count_4_D2_PT_1 + ); + count_4_D2_36 : X_OR2 + port map ( + I0 => count_4_D2_PT_0, + I1 => count_4_D2_PT_1, + O => count_4_D2 + ); + scount_0_Q_37 : X_BUF + port map ( + I => scount_0_Q, + O => scount(0) + ); + scount_0_tsimcreated_xor_Q_38 : X_XOR2 + port map ( + I0 => scount_0_D, + I1 => scount_0_Q, + O => scount_0_tsimcreated_xor_Q + ); + scount_0_tsimcreated_prld_Q_39 : X_OR2 + port map ( + I0 => FSRIO_1, + I1 => PRLD, + O => scount_0_tsimcreated_prld_Q + ); + scount_0_REG : X_FF + port map ( + I => scount_0_tsimcreated_xor_Q, + CE => Vcc, + CLK => scount_0_CLKF, + SET => Gnd, + RST => scount_0_tsimcreated_prld_Q, + O => scount_0_Q + ); + scount_0_D_40 : X_XOR2 + port map ( + I0 => NlwInverterSignal_scount_0_D_IN0, + I1 => scount_0_D2, + O => scount_0_D + ); + scount_0_D1_41 : X_ZERO + port map ( + O => scount_0_D1 + ); + scount_0_D2_42 : X_AND6 + port map ( + I0 => NlwInverterSignal_scount_0_D2_IN0, + I1 => NlwInverterSignal_scount_0_D2_IN1, + I2 => NlwInverterSignal_scount_0_D2_IN2, + I3 => NlwInverterSignal_scount_0_D2_IN3, + I4 => NlwInverterSignal_scount_0_D2_IN4, + I5 => NlwInverterSignal_scount_0_D2_IN5, + O => scount_0_D2 + ); + scount_0_CLKF_43 : X_AND2 + port map ( + I0 => SCLK1, + I1 => SCLK1, + O => scount_0_CLKF + ); + scount_4_Q_44 : X_BUF + port map ( + I => scount_4_Q, + O => scount(4) + ); + scount_4_tsimcreated_xor_Q_45 : X_XOR2 + port map ( + I0 => scount_4_D, + I1 => scount_4_Q, + O => scount_4_tsimcreated_xor_Q + ); + scount_4_tsimcreated_prld_Q_46 : X_OR2 + port map ( + I0 => FSRIO_1, + I1 => PRLD, + O => scount_4_tsimcreated_prld_Q + ); + scount_4_REG : X_FF + port map ( + I => scount_4_tsimcreated_xor_Q, + CE => Vcc, + CLK => scount_4_CLKF, + SET => Gnd, + RST => scount_4_tsimcreated_prld_Q, + O => scount_4_Q + ); + scount_4_D_47 : X_XOR2 + port map ( + I0 => scount_4_D1, + I1 => scount_4_D2, + O => scount_4_D + ); + scount_4_D1_48 : X_ZERO + port map ( + O => scount_4_D1 + ); + scount_4_D2_PT_0_49 : X_AND5 + port map ( + I0 => NlwInverterSignal_scount_4_D2_PT_0_IN0, + I1 => scount(4), + I2 => NlwInverterSignal_scount_4_D2_PT_0_IN2, + I3 => NlwInverterSignal_scount_4_D2_PT_0_IN3, + I4 => NlwInverterSignal_scount_4_D2_PT_0_IN4, + O => scount_4_D2_PT_0 + ); + scount_4_D2_PT_1_50 : X_AND5 + port map ( + I0 => NlwInverterSignal_scount_4_D2_PT_1_IN0, + I1 => NlwInverterSignal_scount_4_D2_PT_1_IN1, + I2 => NlwInverterSignal_scount_4_D2_PT_1_IN2, + I3 => NlwInverterSignal_scount_4_D2_PT_1_IN3, + I4 => scount(5), + O => scount_4_D2_PT_1 + ); + scount_4_D2_51 : X_OR2 + port map ( + I0 => scount_4_D2_PT_0, + I1 => scount_4_D2_PT_1, + O => scount_4_D2 + ); + scount_4_CLKF_52 : X_AND2 + port map ( + I0 => SCLK1, + I1 => SCLK1, + O => scount_4_CLKF + ); + count_1_Q_53 : X_BUF + port map ( + I => count_1_Q, + O => count(1) + ); + count_1_tsimcreated_xor_Q_54 : X_XOR2 + port map ( + I0 => count_1_D, + I1 => count_1_Q, + O => count_1_tsimcreated_xor_Q + ); + count_1_tsimcreated_prld_Q_55 : X_OR2 + port map ( + I0 => FSRIO_1, + I1 => PRLD, + O => count_1_tsimcreated_prld_Q + ); + count_1_REG : X_FF + port map ( + I => count_1_tsimcreated_xor_Q, + CE => Vcc, + CLK => FCLKIO_0, + SET => Gnd, + RST => count_1_tsimcreated_prld_Q, + O => count_1_Q + ); + count_1_D_56 : X_XOR2 + port map ( + I0 => NlwInverterSignal_count_1_D_IN0, + I1 => count_1_D2, + O => count_1_D + ); + count_1_D1_57 : X_ZERO + port map ( + O => count_1_D1 + ); + count_1_D2_PT_0_58 : X_AND2 + port map ( + I0 => count(0), + I1 => count(0), + O => count_1_D2_PT_0 + ); + count_1_D2_PT_1_59 : X_AND5 + port map ( + I0 => NlwInverterSignal_count_1_D2_PT_1_IN0, + I1 => NlwInverterSignal_count_1_D2_PT_1_IN1, + I2 => NlwInverterSignal_count_1_D2_PT_1_IN2, + I3 => NlwInverterSignal_count_1_D2_PT_1_IN3, + I4 => NlwInverterSignal_count_1_D2_PT_1_IN4, + O => count_1_D2_PT_1 + ); + count_1_D2_60 : X_OR2 + port map ( + I0 => count_1_D2_PT_0, + I1 => count_1_D2_PT_1, + O => count_1_D2 + ); + count_2_Q_61 : X_BUF + port map ( + I => count_2_Q, + O => count(2) + ); + count_2_tsimcreated_xor_Q_62 : X_XOR2 + port map ( + I0 => count_2_D, + I1 => count_2_Q, + O => count_2_tsimcreated_xor_Q + ); + count_2_REG : X_FF + port map ( + I => count_2_tsimcreated_xor_Q, + CE => Vcc, + CLK => FCLKIO_0, + SET => FSRIO_1, + RST => PRLD, + O => count_2_Q + ); + count_2_D_63 : X_XOR2 + port map ( + I0 => count_2_D1, + I1 => count_2_D2, + O => count_2_D + ); + count_2_D1_64 : X_ZERO + port map ( + O => count_2_D1 + ); + count_2_D2_65 : X_AND2 + port map ( + I0 => NlwInverterSignal_count_2_D2_IN0, + I1 => NlwInverterSignal_count_2_D2_IN1, + O => count_2_D2 + ); + count_3_Q_66 : X_BUF + port map ( + I => count_3_Q, + O => count(3) + ); + count_3_tsimcreated_xor_Q_67 : X_XOR2 + port map ( + I0 => count_3_D, + I1 => count_3_Q, + O => count_3_tsimcreated_xor_Q + ); + count_3_tsimcreated_prld_Q_68 : X_OR2 + port map ( + I0 => FSRIO_1, + I1 => PRLD, + O => count_3_tsimcreated_prld_Q + ); + count_3_REG : X_FF + port map ( + I => count_3_tsimcreated_xor_Q, + CE => Vcc, + CLK => FCLKIO_0, + SET => Gnd, + RST => count_3_tsimcreated_prld_Q, + O => count_3_Q + ); + count_3_D_69 : X_XOR2 + port map ( + I0 => count_3_D1, + I1 => count_3_D2, + O => count_3_D + ); + count_3_D1_70 : X_ZERO + port map ( + O => count_3_D1 + ); + count_3_D2_PT_0_71 : X_AND4 + port map ( + I0 => NlwInverterSignal_count_3_D2_PT_0_IN0, + I1 => count(4), + I2 => NlwInverterSignal_count_3_D2_PT_0_IN2, + I3 => NlwInverterSignal_count_3_D2_PT_0_IN3, + O => count_3_D2_PT_0 + ); + count_3_D2_PT_1_72 : X_AND4 + port map ( + I0 => NlwInverterSignal_count_3_D2_PT_1_IN0, + I1 => NlwInverterSignal_count_3_D2_PT_1_IN1, + I2 => NlwInverterSignal_count_3_D2_PT_1_IN2, + I3 => count(3), + O => count_3_D2_PT_1 + ); + count_3_D2_PT_2_73 : X_AND4 + port map ( + I0 => NlwInverterSignal_count_3_D2_PT_2_IN0, + I1 => NlwInverterSignal_count_3_D2_PT_2_IN1, + I2 => NlwInverterSignal_count_3_D2_PT_2_IN2, + I3 => count(5), + O => count_3_D2_PT_2 + ); + count_3_D2_74 : X_OR3 + port map ( + I0 => count_3_D2_PT_0, + I1 => count_3_D2_PT_1, + I2 => count_3_D2_PT_2, + O => count_3_D2 + ); + scount_1_Q_75 : X_BUF + port map ( + I => scount_1_Q, + O => scount(1) + ); + scount_1_tsimcreated_xor_Q_76 : X_XOR2 + port map ( + I0 => scount_1_D, + I1 => scount_1_Q, + O => scount_1_tsimcreated_xor_Q + ); + scount_1_REG : X_FF + port map ( + I => scount_1_tsimcreated_xor_Q, + CE => Vcc, + CLK => scount_1_CLKF, + SET => FSRIO_1, + RST => PRLD, + O => scount_1_Q + ); + scount_1_D_77 : X_XOR2 + port map ( + I0 => NlwInverterSignal_scount_1_D_IN0, + I1 => scount_1_D2, + O => scount_1_D + ); + scount_1_D1_78 : X_ZERO + port map ( + O => scount_1_D1 + ); + scount_1_D2_79 : X_AND2 + port map ( + I0 => scount(0), + I1 => scount(0), + O => scount_1_D2 + ); + scount_1_CLKF_80 : X_AND2 + port map ( + I0 => SCLK1, + I1 => SCLK1, + O => scount_1_CLKF + ); + scount_2_Q_81 : X_BUF + port map ( + I => scount_2_Q, + O => scount(2) + ); + scount_2_tsimcreated_xor_Q_82 : X_XOR2 + port map ( + I0 => scount_2_D, + I1 => scount_2_Q, + O => scount_2_tsimcreated_xor_Q + ); + scount_2_tsimcreated_prld_Q_83 : X_OR2 + port map ( + I0 => FSRIO_1, + I1 => PRLD, + O => scount_2_tsimcreated_prld_Q + ); + scount_2_REG : X_FF + port map ( + I => scount_2_tsimcreated_xor_Q, + CE => Vcc, + CLK => scount_2_CLKF, + SET => Gnd, + RST => scount_2_tsimcreated_prld_Q, + O => scount_2_Q + ); + scount_2_D_84 : X_XOR2 + port map ( + I0 => NlwInverterSignal_scount_2_D_IN0, + I1 => scount_2_D2, + O => scount_2_D + ); + scount_2_D1_85 : X_ZERO + port map ( + O => scount_2_D1 + ); + scount_2_D2_PT_0_86 : X_AND2 + port map ( + I0 => scount(0), + I1 => scount(0), + O => scount_2_D2_PT_0 + ); + scount_2_D2_PT_1_87 : X_AND2 + port map ( + I0 => scount(1), + I1 => scount(1), + O => scount_2_D2_PT_1 + ); + scount_2_D2_PT_2_88 : X_AND4 + port map ( + I0 => NlwInverterSignal_scount_2_D2_PT_2_IN0, + I1 => NlwInverterSignal_scount_2_D2_PT_2_IN1, + I2 => NlwInverterSignal_scount_2_D2_PT_2_IN2, + I3 => NlwInverterSignal_scount_2_D2_PT_2_IN3, + O => scount_2_D2_PT_2 + ); + scount_2_D2_89 : X_OR3 + port map ( + I0 => scount_2_D2_PT_0, + I1 => scount_2_D2_PT_1, + I2 => scount_2_D2_PT_2, + O => scount_2_D2 + ); + scount_2_CLKF_90 : X_AND2 + port map ( + I0 => SCLK1, + I1 => SCLK1, + O => scount_2_CLKF + ); + scount_3_Q_91 : X_BUF + port map ( + I => scount_3_Q, + O => scount(3) + ); + scount_3_tsimcreated_xor_Q_92 : X_XOR2 + port map ( + I0 => scount_3_D, + I1 => scount_3_Q, + O => scount_3_tsimcreated_xor_Q + ); + scount_3_tsimcreated_prld_Q_93 : X_OR2 + port map ( + I0 => FSRIO_1, + I1 => PRLD, + O => scount_3_tsimcreated_prld_Q + ); + scount_3_REG : X_FF + port map ( + I => scount_3_tsimcreated_xor_Q, + CE => Vcc, + CLK => scount_3_CLKF, + SET => Gnd, + RST => scount_3_tsimcreated_prld_Q, + O => scount_3_Q + ); + scount_3_D_94 : X_XOR2 + port map ( + I0 => scount_3_D1, + I1 => scount_3_D2, + O => scount_3_D + ); + scount_3_D1_95 : X_ZERO + port map ( + O => scount_3_D1 + ); + scount_3_D2_PT_0_96 : X_AND4 + port map ( + I0 => NlwInverterSignal_scount_3_D2_PT_0_IN0, + I1 => scount(4), + I2 => NlwInverterSignal_scount_3_D2_PT_0_IN2, + I3 => NlwInverterSignal_scount_3_D2_PT_0_IN3, + O => scount_3_D2_PT_0 + ); + scount_3_D2_PT_1_97 : X_AND4 + port map ( + I0 => NlwInverterSignal_scount_3_D2_PT_1_IN0, + I1 => NlwInverterSignal_scount_3_D2_PT_1_IN1, + I2 => NlwInverterSignal_scount_3_D2_PT_1_IN2, + I3 => scount(3), + O => scount_3_D2_PT_1 + ); + scount_3_D2_PT_2_98 : X_AND4 + port map ( + I0 => NlwInverterSignal_scount_3_D2_PT_2_IN0, + I1 => NlwInverterSignal_scount_3_D2_PT_2_IN1, + I2 => NlwInverterSignal_scount_3_D2_PT_2_IN2, + I3 => scount(5), + O => scount_3_D2_PT_2 + ); + scount_3_D2_99 : X_OR3 + port map ( + I0 => scount_3_D2_PT_0, + I1 => scount_3_D2_PT_1, + I2 => scount_3_D2_PT_2, + O => scount_3_D2 + ); + scount_3_CLKF_100 : X_AND2 + port map ( + I0 => SCLK1, + I1 => SCLK1, + O => scount_3_CLKF + ); + count_5_Q_101 : X_BUF + port map ( + I => count_5_Q, + O => count(5) + ); + count_5_tsimcreated_xor_Q_102 : X_XOR2 + port map ( + I0 => count_5_D, + I1 => count_5_Q, + O => count_5_tsimcreated_xor_Q + ); + count_5_tsimcreated_prld_Q_103 : X_OR2 + port map ( + I0 => FSRIO_1, + I1 => PRLD, + O => count_5_tsimcreated_prld_Q + ); + count_5_REG : X_FF + port map ( + I => count_5_tsimcreated_xor_Q, + CE => Vcc, + CLK => FCLKIO_0, + SET => Gnd, + RST => count_5_tsimcreated_prld_Q, + O => count_5_Q + ); + count_5_D_104 : X_XOR2 + port map ( + I0 => count_5_D1, + I1 => count_5_D2, + O => count_5_D + ); + count_5_D1_105 : X_ZERO + port map ( + O => count_5_D1 + ); + count_5_D2_106 : X_AND6 + port map ( + I0 => NlwInverterSignal_count_5_D2_IN0, + I1 => NlwInverterSignal_count_5_D2_IN1, + I2 => NlwInverterSignal_count_5_D2_IN2, + I3 => NlwInverterSignal_count_5_D2_IN3, + I4 => NlwInverterSignal_count_5_D2_IN4, + I5 => count(5), + O => count_5_D2 + ); + scount_5_Q_107 : X_BUF + port map ( + I => scount_5_Q, + O => scount(5) + ); + scount_5_tsimcreated_xor_Q_108 : X_XOR2 + port map ( + I0 => scount_5_D, + I1 => scount_5_Q, + O => scount_5_tsimcreated_xor_Q + ); + scount_5_tsimcreated_prld_Q_109 : X_OR2 + port map ( + I0 => FSRIO_1, + I1 => PRLD, + O => scount_5_tsimcreated_prld_Q + ); + scount_5_REG : X_FF + port map ( + I => scount_5_tsimcreated_xor_Q, + CE => Vcc, + CLK => scount_5_CLKF, + SET => Gnd, + RST => scount_5_tsimcreated_prld_Q, + O => scount_5_Q + ); + scount_5_D_110 : X_XOR2 + port map ( + I0 => scount_5_D1, + I1 => scount_5_D2, + O => scount_5_D + ); + scount_5_D1_111 : X_ZERO + port map ( + O => scount_5_D1 + ); + scount_5_D2_112 : X_AND6 + port map ( + I0 => NlwInverterSignal_scount_5_D2_IN0, + I1 => NlwInverterSignal_scount_5_D2_IN1, + I2 => NlwInverterSignal_scount_5_D2_IN2, + I3 => NlwInverterSignal_scount_5_D2_IN3, + I4 => NlwInverterSignal_scount_5_D2_IN4, + I5 => scount(5), + O => scount_5_D2 + ); + scount_5_CLKF_113 : X_AND2 + port map ( + I0 => SCLK1, + I1 => SCLK1, + O => scount_5_CLKF + ); + SCLK_OBUF_BUF0_114 : X_BUF + port map ( + I => SCLK_OBUF_BUF0_Q, + O => SCLK_OBUF_BUF0 + ); + SCLK_OBUF_BUF0_Q_115 : X_BUF + port map ( + I => SCLK_OBUF_BUF0_D, + O => SCLK_OBUF_BUF0_Q + ); + SCLK_OBUF_BUF0_D_116 : X_XOR2 + port map ( + I0 => SCLK_OBUF_BUF0_D1, + I1 => SCLK_OBUF_BUF0_D2, + O => SCLK_OBUF_BUF0_D + ); + SCLK_OBUF_BUF0_D1_117 : X_ZERO + port map ( + O => SCLK_OBUF_BUF0_D1 + ); + SCLK_OBUF_BUF0_D2_118 : X_AND2 + port map ( + I0 => SCLK_OBUF, + I1 => SCLK_OBUF, + O => SCLK_OBUF_BUF0_D2 + ); + NlwInverterBlock_dummy_out_OBUF_CE_IN0 : X_INV + port map ( + I => scount(0), + O => NlwInverterSignal_dummy_out_OBUF_CE_IN0 + ); + NlwInverterBlock_dummy_out_OBUF_CE_IN1 : X_INV + port map ( + I => scount(4), + O => NlwInverterSignal_dummy_out_OBUF_CE_IN1 + ); + NlwInverterBlock_dummy_out_OBUF_CE_IN2 : X_INV + port map ( + I => scount(1), + O => NlwInverterSignal_dummy_out_OBUF_CE_IN2 + ); + NlwInverterBlock_dummy_out_OBUF_CE_IN3 : X_INV + port map ( + I => scount(2), + O => NlwInverterSignal_dummy_out_OBUF_CE_IN3 + ); + NlwInverterBlock_dummy_out_OBUF_CE_IN4 : X_INV + port map ( + I => scount(3), + O => NlwInverterSignal_dummy_out_OBUF_CE_IN4 + ); + NlwInverterBlock_dummy_out_OBUF_CE_IN5 : X_INV + port map ( + I => scount(5), + O => NlwInverterSignal_dummy_out_OBUF_CE_IN5 + ); + NlwInverterBlock_SCLK1_CE_IN0 : X_INV + port map ( + I => count(0), + O => NlwInverterSignal_SCLK1_CE_IN0 + ); + NlwInverterBlock_SCLK1_CE_IN1 : X_INV + port map ( + I => count(4), + O => NlwInverterSignal_SCLK1_CE_IN1 + ); + NlwInverterBlock_SCLK1_CE_IN2 : X_INV + port map ( + I => count(1), + O => NlwInverterSignal_SCLK1_CE_IN2 + ); + NlwInverterBlock_SCLK1_CE_IN3 : X_INV + port map ( + I => count(2), + O => NlwInverterSignal_SCLK1_CE_IN3 + ); + NlwInverterBlock_SCLK1_CE_IN4 : X_INV + port map ( + I => count(3), + O => NlwInverterSignal_SCLK1_CE_IN4 + ); + NlwInverterBlock_SCLK1_CE_IN5 : X_INV + port map ( + I => count(5), + O => NlwInverterSignal_SCLK1_CE_IN5 + ); + NlwInverterBlock_count_0_D_IN0 : X_INV + port map ( + I => count_0_D1, + O => NlwInverterSignal_count_0_D_IN0 + ); + NlwInverterBlock_count_0_D2_IN0 : X_INV + port map ( + I => count(0), + O => NlwInverterSignal_count_0_D2_IN0 + ); + NlwInverterBlock_count_0_D2_IN1 : X_INV + port map ( + I => count(4), + O => NlwInverterSignal_count_0_D2_IN1 + ); + NlwInverterBlock_count_0_D2_IN2 : X_INV + port map ( + I => count(1), + O => NlwInverterSignal_count_0_D2_IN2 + ); + NlwInverterBlock_count_0_D2_IN3 : X_INV + port map ( + I => count(2), + O => NlwInverterSignal_count_0_D2_IN3 + ); + NlwInverterBlock_count_0_D2_IN4 : X_INV + port map ( + I => count(3), + O => NlwInverterSignal_count_0_D2_IN4 + ); + NlwInverterBlock_count_0_D2_IN5 : X_INV + port map ( + I => count(5), + O => NlwInverterSignal_count_0_D2_IN5 + ); + NlwInverterBlock_count_4_D2_PT_0_IN0 : X_INV + port map ( + I => count(0), + O => NlwInverterSignal_count_4_D2_PT_0_IN0 + ); + NlwInverterBlock_count_4_D2_PT_0_IN2 : X_INV + port map ( + I => count(1), + O => NlwInverterSignal_count_4_D2_PT_0_IN2 + ); + NlwInverterBlock_count_4_D2_PT_0_IN3 : X_INV + port map ( + I => count(2), + O => NlwInverterSignal_count_4_D2_PT_0_IN3 + ); + NlwInverterBlock_count_4_D2_PT_0_IN4 : X_INV + port map ( + I => count(3), + O => NlwInverterSignal_count_4_D2_PT_0_IN4 + ); + NlwInverterBlock_count_4_D2_PT_1_IN0 : X_INV + port map ( + I => count(0), + O => NlwInverterSignal_count_4_D2_PT_1_IN0 + ); + NlwInverterBlock_count_4_D2_PT_1_IN1 : X_INV + port map ( + I => count(1), + O => NlwInverterSignal_count_4_D2_PT_1_IN1 + ); + NlwInverterBlock_count_4_D2_PT_1_IN2 : X_INV + port map ( + I => count(2), + O => NlwInverterSignal_count_4_D2_PT_1_IN2 + ); + NlwInverterBlock_count_4_D2_PT_1_IN3 : X_INV + port map ( + I => count(3), + O => NlwInverterSignal_count_4_D2_PT_1_IN3 + ); + NlwInverterBlock_scount_0_D_IN0 : X_INV + port map ( + I => scount_0_D1, + O => NlwInverterSignal_scount_0_D_IN0 + ); + NlwInverterBlock_scount_0_D2_IN0 : X_INV + port map ( + I => scount(0), + O => NlwInverterSignal_scount_0_D2_IN0 + ); + NlwInverterBlock_scount_0_D2_IN1 : X_INV + port map ( + I => scount(4), + O => NlwInverterSignal_scount_0_D2_IN1 + ); + NlwInverterBlock_scount_0_D2_IN2 : X_INV + port map ( + I => scount(1), + O => NlwInverterSignal_scount_0_D2_IN2 + ); + NlwInverterBlock_scount_0_D2_IN3 : X_INV + port map ( + I => scount(2), + O => NlwInverterSignal_scount_0_D2_IN3 + ); + NlwInverterBlock_scount_0_D2_IN4 : X_INV + port map ( + I => scount(3), + O => NlwInverterSignal_scount_0_D2_IN4 + ); + NlwInverterBlock_scount_0_D2_IN5 : X_INV + port map ( + I => scount(5), + O => NlwInverterSignal_scount_0_D2_IN5 + ); + NlwInverterBlock_scount_4_D2_PT_0_IN0 : X_INV + port map ( + I => scount(0), + O => NlwInverterSignal_scount_4_D2_PT_0_IN0 + ); + NlwInverterBlock_scount_4_D2_PT_0_IN2 : X_INV + port map ( + I => scount(1), + O => NlwInverterSignal_scount_4_D2_PT_0_IN2 + ); + NlwInverterBlock_scount_4_D2_PT_0_IN3 : X_INV + port map ( + I => scount(2), + O => NlwInverterSignal_scount_4_D2_PT_0_IN3 + ); + NlwInverterBlock_scount_4_D2_PT_0_IN4 : X_INV + port map ( + I => scount(3), + O => NlwInverterSignal_scount_4_D2_PT_0_IN4 + ); + NlwInverterBlock_scount_4_D2_PT_1_IN0 : X_INV + port map ( + I => scount(0), + O => NlwInverterSignal_scount_4_D2_PT_1_IN0 + ); + NlwInverterBlock_scount_4_D2_PT_1_IN1 : X_INV + port map ( + I => scount(1), + O => NlwInverterSignal_scount_4_D2_PT_1_IN1 + ); + NlwInverterBlock_scount_4_D2_PT_1_IN2 : X_INV + port map ( + I => scount(2), + O => NlwInverterSignal_scount_4_D2_PT_1_IN2 + ); + NlwInverterBlock_scount_4_D2_PT_1_IN3 : X_INV + port map ( + I => scount(3), + O => NlwInverterSignal_scount_4_D2_PT_1_IN3 + ); + NlwInverterBlock_count_1_D_IN0 : X_INV + port map ( + I => count_1_D1, + O => NlwInverterSignal_count_1_D_IN0 + ); + NlwInverterBlock_count_1_D2_PT_1_IN0 : X_INV + port map ( + I => count(4), + O => NlwInverterSignal_count_1_D2_PT_1_IN0 + ); + NlwInverterBlock_count_1_D2_PT_1_IN1 : X_INV + port map ( + I => count(1), + O => NlwInverterSignal_count_1_D2_PT_1_IN1 + ); + NlwInverterBlock_count_1_D2_PT_1_IN2 : X_INV + port map ( + I => count(2), + O => NlwInverterSignal_count_1_D2_PT_1_IN2 + ); + NlwInverterBlock_count_1_D2_PT_1_IN3 : X_INV + port map ( + I => count(3), + O => NlwInverterSignal_count_1_D2_PT_1_IN3 + ); + NlwInverterBlock_count_1_D2_PT_1_IN4 : X_INV + port map ( + I => count(5), + O => NlwInverterSignal_count_1_D2_PT_1_IN4 + ); + NlwInverterBlock_count_2_D2_IN0 : X_INV + port map ( + I => count(0), + O => NlwInverterSignal_count_2_D2_IN0 + ); + NlwInverterBlock_count_2_D2_IN1 : X_INV + port map ( + I => count(1), + O => NlwInverterSignal_count_2_D2_IN1 + ); + NlwInverterBlock_count_3_D2_PT_0_IN0 : X_INV + port map ( + I => count(0), + O => NlwInverterSignal_count_3_D2_PT_0_IN0 + ); + NlwInverterBlock_count_3_D2_PT_0_IN2 : X_INV + port map ( + I => count(1), + O => NlwInverterSignal_count_3_D2_PT_0_IN2 + ); + NlwInverterBlock_count_3_D2_PT_0_IN3 : X_INV + port map ( + I => count(2), + O => NlwInverterSignal_count_3_D2_PT_0_IN3 + ); + NlwInverterBlock_count_3_D2_PT_1_IN0 : X_INV + port map ( + I => count(0), + O => NlwInverterSignal_count_3_D2_PT_1_IN0 + ); + NlwInverterBlock_count_3_D2_PT_1_IN1 : X_INV + port map ( + I => count(1), + O => NlwInverterSignal_count_3_D2_PT_1_IN1 + ); + NlwInverterBlock_count_3_D2_PT_1_IN2 : X_INV + port map ( + I => count(2), + O => NlwInverterSignal_count_3_D2_PT_1_IN2 + ); + NlwInverterBlock_count_3_D2_PT_2_IN0 : X_INV + port map ( + I => count(0), + O => NlwInverterSignal_count_3_D2_PT_2_IN0 + ); + NlwInverterBlock_count_3_D2_PT_2_IN1 : X_INV + port map ( + I => count(1), + O => NlwInverterSignal_count_3_D2_PT_2_IN1 + ); + NlwInverterBlock_count_3_D2_PT_2_IN2 : X_INV + port map ( + I => count(2), + O => NlwInverterSignal_count_3_D2_PT_2_IN2 + ); + NlwInverterBlock_scount_1_D_IN0 : X_INV + port map ( + I => scount_1_D1, + O => NlwInverterSignal_scount_1_D_IN0 + ); + NlwInverterBlock_scount_2_D_IN0 : X_INV + port map ( + I => scount_2_D1, + O => NlwInverterSignal_scount_2_D_IN0 + ); + NlwInverterBlock_scount_2_D2_PT_2_IN0 : X_INV + port map ( + I => scount(4), + O => NlwInverterSignal_scount_2_D2_PT_2_IN0 + ); + NlwInverterBlock_scount_2_D2_PT_2_IN1 : X_INV + port map ( + I => scount(2), + O => NlwInverterSignal_scount_2_D2_PT_2_IN1 + ); + NlwInverterBlock_scount_2_D2_PT_2_IN2 : X_INV + port map ( + I => scount(3), + O => NlwInverterSignal_scount_2_D2_PT_2_IN2 + ); + NlwInverterBlock_scount_2_D2_PT_2_IN3 : X_INV + port map ( + I => scount(5), + O => NlwInverterSignal_scount_2_D2_PT_2_IN3 + ); + NlwInverterBlock_scount_3_D2_PT_0_IN0 : X_INV + port map ( + I => scount(0), + O => NlwInverterSignal_scount_3_D2_PT_0_IN0 + ); + NlwInverterBlock_scount_3_D2_PT_0_IN2 : X_INV + port map ( + I => scount(1), + O => NlwInverterSignal_scount_3_D2_PT_0_IN2 + ); + NlwInverterBlock_scount_3_D2_PT_0_IN3 : X_INV + port map ( + I => scount(2), + O => NlwInverterSignal_scount_3_D2_PT_0_IN3 + ); + NlwInverterBlock_scount_3_D2_PT_1_IN0 : X_INV + port map ( + I => scount(0), + O => NlwInverterSignal_scount_3_D2_PT_1_IN0 + ); + NlwInverterBlock_scount_3_D2_PT_1_IN1 : X_INV + port map ( + I => scount(1), + O => NlwInverterSignal_scount_3_D2_PT_1_IN1 + ); + NlwInverterBlock_scount_3_D2_PT_1_IN2 : X_INV + port map ( + I => scount(2), + O => NlwInverterSignal_scount_3_D2_PT_1_IN2 + ); + NlwInverterBlock_scount_3_D2_PT_2_IN0 : X_INV + port map ( + I => scount(0), + O => NlwInverterSignal_scount_3_D2_PT_2_IN0 + ); + NlwInverterBlock_scount_3_D2_PT_2_IN1 : X_INV + port map ( + I => scount(1), + O => NlwInverterSignal_scount_3_D2_PT_2_IN1 + ); + NlwInverterBlock_scount_3_D2_PT_2_IN2 : X_INV + port map ( + I => scount(2), + O => NlwInverterSignal_scount_3_D2_PT_2_IN2 + ); + NlwInverterBlock_count_5_D2_IN0 : X_INV + port map ( + I => count(0), + O => NlwInverterSignal_count_5_D2_IN0 + ); + NlwInverterBlock_count_5_D2_IN1 : X_INV + port map ( + I => count(4), + O => NlwInverterSignal_count_5_D2_IN1 + ); + NlwInverterBlock_count_5_D2_IN2 : X_INV + port map ( + I => count(1), + O => NlwInverterSignal_count_5_D2_IN2 + ); + NlwInverterBlock_count_5_D2_IN3 : X_INV + port map ( + I => count(2), + O => NlwInverterSignal_count_5_D2_IN3 + ); + NlwInverterBlock_count_5_D2_IN4 : X_INV + port map ( + I => count(3), + O => NlwInverterSignal_count_5_D2_IN4 + ); + NlwInverterBlock_scount_5_D2_IN0 : X_INV + port map ( + I => scount(0), + O => NlwInverterSignal_scount_5_D2_IN0 + ); + NlwInverterBlock_scount_5_D2_IN1 : X_INV + port map ( + I => scount(4), + O => NlwInverterSignal_scount_5_D2_IN1 + ); + NlwInverterBlock_scount_5_D2_IN2 : X_INV + port map ( + I => scount(1), + O => NlwInverterSignal_scount_5_D2_IN2 + ); + NlwInverterBlock_scount_5_D2_IN3 : X_INV + port map ( + I => scount(2), + O => NlwInverterSignal_scount_5_D2_IN3 + ); + NlwInverterBlock_scount_5_D2_IN4 : X_INV + port map ( + I => scount(3), + O => NlwInverterSignal_scount_5_D2_IN4 + ); + NlwBlockROC : X_ROC + generic map (ROC_WIDTH => 100 ns) + port map (O => PRLD); + +end Structure; + diff --git a/projects/eval_twoclocks/pepExtractor.prj b/projects/eval_twoclocks/pepExtractor.prj new file mode 100644 index 0000000..bae7e2a --- /dev/null +++ b/projects/eval_twoclocks/pepExtractor.prj @@ -0,0 +1 @@ +work vconfig.vhdl diff --git a/projects/eval_twoclocks/vconfig.vhdl b/projects/eval_twoclocks/vconfig.vhdl new file mode 100644 index 0000000..523a63c --- /dev/null +++ b/projects/eval_twoclocks/vconfig.vhdl @@ -0,0 +1,62 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following lines to use the declarations that are +-- provided for instantiating Xilinx primitive components. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity eval2clk is + Port ( RES : in std_logic; + CLK : in std_logic; + SCLK : inout std_logic; + dummy_out : inout std_logic); +end eval2clk; + +architecture Behavioral of eval2clk is +signal count, scount : integer range 0 to 63; +signal SCLK1 : std_logic; +begin + +process (RES, SCLK1) +begin + if (RES = '1') then + dummy_out <= '1'; + scount <= 2; + + elsif SCLK1='1' and SCLK1'event then + + if (scount = 0) then + scount <= 2; + dummy_out <= not dummy_out; + + else + scount <= scount - 1; + end if; + end if; +end process; + +process (RES, CLK) +begin + if (RES = '1') then + SCLK1 <= '1'; + COUNT <= 4; + + elsif CLK='1' and CLK'event then + + if (COUNT = 0) then + COUNT <= 4; + SCLK1 <= not SCLK1; + + else + COUNT <= COUNT - 1; + end if; + end if; +end process; + +SCLK <= RES; + +end Behavioral; + diff --git a/projects/eval_twoclocks/vconfig_tb.vhd b/projects/eval_twoclocks/vconfig_tb.vhd new file mode 100644 index 0000000..beccd16 --- /dev/null +++ b/projects/eval_twoclocks/vconfig_tb.vhd @@ -0,0 +1,67 @@ + +-- VHDL Test Bench Created from source file vconfig.vhd -- 20:20:01 05/01/2004 +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY eval2clk_tb IS +END eval2clk_tb; + +ARCHITECTURE behavior OF eval2clk_tb IS + + COMPONENT eval2clk + PORT( + RES : IN std_logic; + CLK : IN std_logic; + SCLK : INOUT std_logic; + dummy_out : OUT std_logic + ); + END COMPONENT; + + + SIGNAL RES : std_logic := '1'; + SIGNAL CLK : std_logic := '0'; + SIGNAL SCLK : std_logic; + SIGNAL dummy_out : std_logic := '0'; + + constant ClockPeriod : Time := 16.667 ns; + +BEGIN + + uut: eval2clk PORT MAP( + RES => RES, + CLK => CLK, + SCLK => SCLK, + dummy_out => dummy_out + ); + + busclock: process + begin + CLK <= '1'; + loop + wait for (ClockPeriod / 2); + CLK <= not CLK; + end loop; + end process; + +-- *** Test Bench - User Defined Section *** + tb : PROCESS + BEGIN + + wait for 20*ClockPeriod; + RES <= '0'; + + + wait; -- will wait forever + END PROCESS; +-- *** End Test Bench - User Defined Section *** + +END; diff --git a/projects/hpi_reg/ise/bitgen.ut b/projects/hpi_reg/ise/bitgen.ut new file mode 100644 index 0000000..1d23f16 --- /dev/null +++ b/projects/hpi_reg/ise/bitgen.ut @@ -0,0 +1,34 @@ + +-w +-g DebugBitstream:No +-g Binary:no +-g CRC:Enable +-g ConfigRate:4 +-g CclkPin:PullUp +-g M0Pin:PullUp +-g M1Pin:PullUp +-g M2Pin:PullUp +-g ProgPin:PullUp +-g DonePin:PullUp +-g InitPin:Pullup +-g CsPin:Pullup +-g DinPin:Pullup +-g BusyPin:Pullup +-g RdWrPin:Pullup +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g DCMShutDown:Disable +-g DCIUpdateMode:AsRequired +-g StartUpClk:JtagClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:No +-g DriveDone:No +-g Encrypt:No diff --git a/projects/hpi_reg/ise/hpi_reg.ise b/projects/hpi_reg/ise/hpi_reg.ise new file mode 100644 index 0000000..26d5bd8 Binary files /dev/null and b/projects/hpi_reg/ise/hpi_reg.ise differ diff --git a/projects/hpi_reg/ise/hpi_reg_top.lso b/projects/hpi_reg/ise/hpi_reg_top.lso new file mode 100644 index 0000000..22de730 --- /dev/null +++ b/projects/hpi_reg/ise/hpi_reg_top.lso @@ -0,0 +1 @@ +work diff --git a/projects/hpi_reg/ise/hpi_reg_top.prj b/projects/hpi_reg/ise/hpi_reg_top.prj new file mode 100644 index 0000000..56d64fe --- /dev/null +++ b/projects/hpi_reg/ise/hpi_reg_top.prj @@ -0,0 +1,2 @@ +vhdl work "E:/work/XilinxISE/Common/oneshot.vhd" +vhdl work "hpi_reg_top.vhd" diff --git a/projects/hpi_reg/ise/hpi_reg_top.ut b/projects/hpi_reg/ise/hpi_reg_top.ut new file mode 100644 index 0000000..1d23f16 --- /dev/null +++ b/projects/hpi_reg/ise/hpi_reg_top.ut @@ -0,0 +1,34 @@ + +-w +-g DebugBitstream:No +-g Binary:no +-g CRC:Enable +-g ConfigRate:4 +-g CclkPin:PullUp +-g M0Pin:PullUp +-g M1Pin:PullUp +-g M2Pin:PullUp +-g ProgPin:PullUp +-g DonePin:PullUp +-g InitPin:Pullup +-g CsPin:Pullup +-g DinPin:Pullup +-g BusyPin:Pullup +-g RdWrPin:Pullup +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g DCMShutDown:Disable +-g DCIUpdateMode:AsRequired +-g StartUpClk:JtagClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:No +-g DriveDone:No +-g Encrypt:No diff --git a/projects/hpi_reg/ise/hpi_reg_top.xst b/projects/hpi_reg/ise/hpi_reg_top.xst new file mode 100644 index 0000000..1ea503c --- /dev/null +++ b/projects/hpi_reg/ise/hpi_reg_top.xst @@ -0,0 +1,55 @@ +set -tmpdir ./xst/projnav.tmp +set -xsthdpdir ./xst +run +-ifn hpi_reg_top.prj +-ifmt mixed +-ofn hpi_reg_top +-ofmt NGC +-p xc4vsx35-10-ff668 +-top hpi_reg_top +-opt_mode Speed +-opt_level 1 +-iuc NO +-lso hpi_reg_top.lso +-keep_hierarchy NO +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case maintain +-slice_utilization_ratio 100 +-dsp_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style lut +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract YES +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-mux_extract YES +-resource_sharing YES +-use_dsp48 auto +-iobuf YES +-max_fanout 500 +-bufg 32 +-bufr 24 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-use_clock_enable Auto +-use_sync_set Auto +-use_sync_reset Auto +-iob auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/projects/hpi_reg/ise/oneshot.lso b/projects/hpi_reg/ise/oneshot.lso new file mode 100644 index 0000000..22de730 --- /dev/null +++ b/projects/hpi_reg/ise/oneshot.lso @@ -0,0 +1 @@ +work diff --git a/projects/hpi_reg/ise/oneshot.prj b/projects/hpi_reg/ise/oneshot.prj new file mode 100644 index 0000000..3d6f1ca --- /dev/null +++ b/projects/hpi_reg/ise/oneshot.prj @@ -0,0 +1 @@ +vhdl work "../Common/oneshot.vhd" diff --git a/projects/hpi_reg/ise/pepExtractor.prj b/projects/hpi_reg/ise/pepExtractor.prj new file mode 100644 index 0000000..6fe7e10 --- /dev/null +++ b/projects/hpi_reg/ise/pepExtractor.prj @@ -0,0 +1 @@ +work "../Common/oneshot.vhd" diff --git a/projects/hpi_reg/ise/system.ucf b/projects/hpi_reg/ise/system.ucf new file mode 100644 index 0000000..02abe8c --- /dev/null +++ b/projects/hpi_reg/ise/system.ucf @@ -0,0 +1,112 @@ +# +# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" +# SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR +# XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION +# AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION +# OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS +# IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, +# AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE +# FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY +# WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE +# IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +# REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF +# INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE. +# +# (c) Copyright 2005 Xilinx, Inc. +# All rights reserved. +# + +# Bus clock nets +#NET sys_clk TNM_NET = "sys_clk"; +#TIMESPEC "TSSYSCLK" = PERIOD "sys_clk" 9.9 ns HIGH 50 %; + +NET sys_clk LOC = AE14; +NET sys_clk IOSTANDARD = LVCMOS33; +NET sys_rst_n LOC = D6; +NET sys_rst_n PULLUP; +NET sys_rst_n TIG; + +# GPLED 0-3 +NET sys_led<0> LOC = G5; #GPLED0 +NET sys_led<1> LOC = G6; #GPLED1 +NET sys_led<2> LOC = A11; #GPLED2 +NET sys_led<3> LOC = A12; #GPLED3 + +#NET "led<*>" SLEW = SLOW; +#NET "led<*>" DRIVE = 2; + + +# Dip Switches 1-8 +#NET sys_test_in<0> LOC = U24; # DIP SW 8 +#NET sys_test_in<1> LOC = U25; # DIP SW 7 +#NET sys_test_in<2> LOC = V23; # DIP SW 6 +#NET sys_test_in<3> LOC = U23; # DIP SW 5 +#NET sys_test_in<4> LOC = U26; # DIP SW 4 +#NET sys_test_in<5> LOC = T26; # DIP SW 3 +#NET sys_test_in<6> LOC = R19; # DIP SW 2 +#NET sys_test_in<7> LOC = R20; # DIP SW 1 +#NET sys_test_in<0> IOSTANDARD = LVCMOS33; +#NET sys_test_in<1> IOSTANDARD = LVCMOS33; +#NET sys_test_in<2> IOSTANDARD = LVCMOS33; +#NET sys_test_in<3> IOSTANDARD = LVCMOS33; +#NET sys_test_in<4> IOSTANDARD = LVCMOS33; +#NET sys_test_in<5> IOSTANDARD = LVCMOS33; +#NET sys_test_in<6> IOSTANDARD = LVCMOS33; +#NET sys_test_in<7> IOSTANDARD = LVCMOS33; + +#NET "sys_test_in<*>" PULLDOWN; +#NET "sys_test_in<*>" TIG; +#NET "sys_test_in<*>" SLEW = SLOW; +#NET "sys_test_in<*>" DRIVE = 2; + +NET sys_hpi_a<0> LOC = U22; +NET sys_hpi_a<1> LOC = Y10; +NET sys_hpi_a<*> IOSTANDARD = LVCMOS33; +NET sys_hpi_a<*> SLEW = FAST; +NET sys_hpi_a<*> DRIVE = 8; +NET sys_hpi_d<0> LOC = AB7; +NET sys_hpi_d<1> LOC = AC9; +NET sys_hpi_d<2> LOC = AB9; +NET sys_hpi_d<3> LOC = AE6; +NET sys_hpi_d<4> LOC = AD6; +NET sys_hpi_d<5> LOC = AF9; +NET sys_hpi_d<6> LOC = AE9; +NET sys_hpi_d<7> LOC = AD8; +NET sys_hpi_d<8> LOC = AC8; +NET sys_hpi_d<9> LOC = AF4; +NET sys_hpi_d<10> LOC = AE4; +NET sys_hpi_d<11> LOC = AD3; +NET sys_hpi_d<12> LOC = AC3; +NET sys_hpi_d<13> LOC = AF6; +NET sys_hpi_d<14> LOC = AF5; +NET sys_hpi_d<15> LOC = AA7; +NET sys_hpi_d<*> IOSTANDARD = LVCMOS33; +NET sys_hpi_d<*> SLEW = FAST; +NET sys_hpi_d<*> DRIVE = 8; +NET sys_hpi_d<*> PULLUP; +NET sys_hpi_rd_n LOC = AA8; +NET sys_hpi_rd_n IOSTANDARD = LVCMOS33; +NET sys_hpi_rd_n SLEW = FAST; +NET sys_hpi_rd_n DRIVE = 8; +NET sys_hpi_wr_n LOC = Y8; +NET sys_hpi_wr_n IOSTANDARD = LVCMOS33; +NET sys_hpi_wr_n SLEW = FAST; +NET sys_hpi_wr_n DRIVE = 8; + +NET sys_hpi_cs_n LOC = AF10; +NET sys_hpi_cs_n IOSTANDARD = LVCMOS33; +NET sys_hpi_cs_n SLEW = FAST; +NET sys_hpi_cs_n DRIVE = 8; +NET sys_hpi_rst_n LOC = A7; +NET sys_hpi_rst_n IOSTANDARD = LVCMOS25; +NET sys_hpi_rst_n TIG; +NET sys_hpi_int LOC = V5; +NET sys_hpi_int IOSTANDARD = LVCMOS33; +NET sys_hpi_int TIG; +NET sys_hpi_int PULLUP; + +NET sys_sace_mpce_n LOC = AD5; +NET sys_sace_mpce_n IOSTANDARD = LVCMOS33; +NET sys_sace_mpce_n SLEW = FAST; +NET sys_sace_mpce_n DRIVE = 8; diff --git a/projects/hpi_reg/src/hpi_reg_top.vhd b/projects/hpi_reg/src/hpi_reg_top.vhd new file mode 100644 index 0000000..c148d08 --- /dev/null +++ b/projects/hpi_reg/src/hpi_reg_top.vhd @@ -0,0 +1,117 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 17:07:37 11/13/05 +-- Design Name: +-- Module Name: hpi_reg_top - Behavioral +-- Project Name: +-- Target Device: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity hpi_reg_top is + Port ( sys_rst_n : in std_logic; + sys_clk : in std_logic; + sys_hpi_a : in std_logic_vector(1 downto 0); + sys_hpi_d : inout std_logic_vector(15 downto 0); + sys_hpi_rd_n : in std_logic; + sys_hpi_wr_n : in std_logic; + sys_hpi_cs_n : in std_logic; + sys_hpi_rst_n : in std_logic; + sys_hpi_int : in std_logic; + sys_led : out std_logic_vector(3 downto 0); + sys_sace_mpce_n : out std_logic); +end hpi_reg_top; + +architecture Behavioral of hpi_reg_top is + + COMPONENT oneshot + Generic ( mode : integer range 0 to 2); + PORT( + rst : IN std_logic; + clk : IN std_logic; + input : IN std_logic; + output : OUT std_logic + ); + END COMPONENT; + + signal reg : std_logic_vector(15 downto 0); + signal wr_n : std_logic; + +begin + +sys_sace_mpce_n <= '1'; +sys_led(0) <= sys_hpi_cs_n; +sys_led(1) <= sys_hpi_rd_n; +sys_led(2) <= sys_hpi_wr_n; +sys_led(3) <= sys_hpi_int; + + Inst_oneshot_wr: oneshot + GENERIC MAP (mode => 1) + PORT MAP( + rst => sys_rst_n, + clk => sys_clk, + input => sys_hpi_wr_n, + output => wr_n + ); + +reg_in: process(sys_clk, sys_hpi_rst_n, wr_n, sys_hpi_cs_n, sys_hpi_a, sys_hpi_d) +begin + if (sys_hpi_rst_n = '0') then + reg <= (others => '0'); + else + if (sys_hpi_cs_n = '0') then + if (wr_n = '0' and rising_edge(sys_clk)) then + case (sys_hpi_a) is + when "00" => + reg <= sys_hpi_d; + + when others => null; + end case; + end if; + end if; + end if; +end process; + +reg_out: process(sys_hpi_rst_n, sys_hpi_rd_n, sys_hpi_cs_n, sys_hpi_a, reg) +begin + if (sys_hpi_rst_n = '0') then + sys_hpi_d <= (others => 'Z'); + else + if (sys_hpi_cs_n = '0' and sys_hpi_rd_n = '0') then + case (sys_hpi_a) is + when "00" => + sys_hpi_d <= reg; + when "01" => + sys_hpi_d <= X"AAAA"; + when "10" => + sys_hpi_d <= X"5555"; + when "11" => + sys_hpi_d <= X"1234"; + when others => null; + end case; + else + sys_hpi_d <= (others => 'Z'); + end if; + end if; +end process; + +end Behavioral; diff --git a/projects/jtag_test/ise/_impact.cmd b/projects/jtag_test/ise/_impact.cmd new file mode 100644 index 0000000..3114c18 --- /dev/null +++ b/projects/jtag_test/ise/_impact.cmd @@ -0,0 +1,27 @@ +setPreference -pref StartupClock:AUTO_CORRECTION +setPreference -pref AutoSignature:FALSE +setPreference -pref KeepSVF:FALSE +setPreference -pref ConcurrentMode:FALSE +setPreference -pref UseHighz:FALSE +setPreference -pref ConfigOnFailure:STOP +setPreference -pref UserLevel:NOVICE +setPreference -pref MessageLevel:DETAILED +setPreference -pref svfUseTime:FALSE +setMode -bs +setMode -bs +setCable -port auto +Identify +identifyMPM +assignFile -p 3 -file "H:/work/vhdl/projects/jtag_test/ise/jtag_test.bit" +Program -p 3 -prog -defaultVersion 0 +Program -p 3 -prog -defaultVersion 0 +Program -p 3 -prog -defaultVersion 0 +Program -p 3 -prog -defaultVersion 0 +Program -p 3 -prog -defaultVersion 0 +Program -p 3 -prog -defaultVersion 0 +Program -p 3 -prog -defaultVersion 0 +Program -p 3 -prog -defaultVersion 0 +Program -p 3 -prog -defaultVersion 0 +Program -p 3 -prog -defaultVersion 0 +Program -p 3 -prog -defaultVersion 0 +saveProjectFile -file "H:/work/vhdl/projects/jtag_test/ise/jtag_test.ipf" diff --git a/projects/jtag_test/ise/jtag_test.ipf b/projects/jtag_test/ise/jtag_test.ipf new file mode 100644 index 0000000..9ecaeb8 Binary files /dev/null and b/projects/jtag_test/ise/jtag_test.ipf differ diff --git a/projects/jtag_test/ise/jtag_test.ise b/projects/jtag_test/ise/jtag_test.ise new file mode 100644 index 0000000..909468b Binary files /dev/null and b/projects/jtag_test/ise/jtag_test.ise differ diff --git a/projects/jtag_test/ise/jtag_test.lso b/projects/jtag_test/ise/jtag_test.lso new file mode 100644 index 0000000..22de730 --- /dev/null +++ b/projects/jtag_test/ise/jtag_test.lso @@ -0,0 +1 @@ +work diff --git a/projects/jtag_test/ise/jtag_test.prj b/projects/jtag_test/ise/jtag_test.prj new file mode 100644 index 0000000..f496b0c --- /dev/null +++ b/projects/jtag_test/ise/jtag_test.prj @@ -0,0 +1 @@ +vhdl work "jtag_test.vhd" diff --git a/projects/jtag_test/ise/jtag_test.ut b/projects/jtag_test/ise/jtag_test.ut new file mode 100644 index 0000000..0cd02ae --- /dev/null +++ b/projects/jtag_test/ise/jtag_test.ut @@ -0,0 +1,34 @@ +-w +-g DebugBitstream:No +-g Binary:no +-g CRC:Enable +-g ConfigRate:4 +-g CclkPin:PullUp +-g M0Pin:PullUp +-g M1Pin:PullUp +-g M2Pin:PullUp +-g ProgPin:PullUp +-g DonePin:PullUp +-g InitPin:Pullup +-g CsPin:Pullup +-g DinPin:Pullup +-g BusyPin:Pullup +-g RdWrPin:Pullup +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g DCMShutdown:Disable +-g DisableBandgap:No +-g DCIUpdateMode:AsRequired +-g StartUpClk:JtagClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:No +-g DriveDone:No +-g Encrypt:No diff --git a/projects/jtag_test/ise/jtag_test.vhd b/projects/jtag_test/ise/jtag_test.vhd new file mode 100644 index 0000000..fdb4fa3 --- /dev/null +++ b/projects/jtag_test/ise/jtag_test.vhd @@ -0,0 +1,122 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09:44:00 03/07/2007 +-- Design Name: +-- Module Name: jtag_test - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + +entity jtag_test is + Port ( + sys_rstn_in : in STD_LOGIC; + sys_led : out unsigned(8 downto 0) + ); +end jtag_test; + +architecture Behavioral of jtag_test is + + signal rst, bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; + signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; + signal user_regi, user_rego : unsigned (7 downto 0); + constant id : unsigned (7 downto 0) := "11010101"; +begin + + BSCAN_VIRTEX4_inst : BSCAN_VIRTEX4 + generic map ( + JTAG_CHAIN => 2) -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) + port map ( + CAPTURE => bs_capture, -- CAPTURE output from TAP controller + DRCK => bs_clk0, -- Data register output for USER functions + RESET => bs_rst, -- Reset output from TAP controller + SEL => bs_sel, -- USER active output + SHIFT => bs_shift, -- SHIFT output from TAP controller + TDI => bs_tdi, -- TDI output from TAP controller + UPDATE => bs_update0, -- UPDATE output from TAP controller + TDO => bs_tdo -- Data input for USER function + ); + + i00_BUFG : BUFG + port map ( + O => bs_clk1, + I => bs_clk0 + ); + i01_BUFG : BUFG + port map ( + O => bs_update1, + I => bs_update0 + ); + + rst <= not sys_rstn_in; + +led_out: + process (rst, bs_clk1, bs_update1, user_regi) + begin + if rst = '1' then + sys_led(7 downto 0) <= (others => '0'); + elsif rising_edge(bs_update1) then + if bs_sel = '1' then + sys_led(7 downto 0) <= user_regi; + end if; + end if; + end process; + +cled_out: + process (rst, bs_clk1, bs_update1, user_regi) + begin + if rst = '1' then + sys_led(8) <= '0'; + elsif rising_edge(bs_update1) then + sys_led(8) <= bs_sel; + end if; + end process; + +sipo: + process (bs_rst, bs_clk1, bs_tdi, bs_shift) + begin + if bs_rst = '1' then + user_regi <= (others => '0'); + elsif rising_edge(bs_clk1) then + if bs_shift = '1' then + user_regi <= bs_tdi & user_regi(user_regi'left downto 1); + end if; + end if; + end process; + +piso: + process (rst, bs_clk1, bs_shift, user_rego) + begin + bs_tdo <= user_rego(0); + if rst = '1' then + user_rego <= (others => '0'); + elsif rising_edge(bs_clk1) then + if bs_shift = '1' then + user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); + else + user_rego <= id; + end if; + end if; + end process; + + +end Behavioral; + diff --git a/projects/jtag_test/ise/jtag_test.xst b/projects/jtag_test/ise/jtag_test.xst new file mode 100644 index 0000000..6792a5f --- /dev/null +++ b/projects/jtag_test/ise/jtag_test.xst @@ -0,0 +1,55 @@ +set -tmpdir ./xst/projnav.tmp +set -xsthdpdir ./xst +run +-ifn jtag_test.prj +-ifmt mixed +-ofn jtag_test +-ofmt NGC +-p xc4vsx35-10-ff668 +-top jtag_test +-opt_mode Speed +-opt_level 1 +-iuc NO +-lso jtag_test.lso +-keep_hierarchy NO +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case maintain +-slice_utilization_ratio 100 +-dsp_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style lut +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract YES +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-mux_extract YES +-resource_sharing YES +-use_dsp48 auto +-iobuf YES +-max_fanout 500 +-bufg 32 +-bufr 24 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-use_clock_enable Auto +-use_sync_set Auto +-use_sync_reset Auto +-iob auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/projects/jtag_test/ise/system.ucf b/projects/jtag_test/ise/system.ucf new file mode 100644 index 0000000..9df3360 --- /dev/null +++ b/projects/jtag_test/ise/system.ucf @@ -0,0 +1,40 @@ +# +# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" +# SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR +# XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION +# AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION +# OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS +# IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, +# AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE +# FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY +# WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE +# IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +# REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF +# INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE. +# +# (c) Copyright 2005 Xilinx, Inc. +# All rights reserved. +# + +NET "sys_rstn_in" LOC = "D6"; +NET sys_rstn_in PULLUP; +NET "sys_rstn_in" TIG; +//////////////////////////////////////////////////////////////////////////// +// Buttons, LEDs, and DIP Switches +//////////////////////////////////////////////////////////////////////////// +# GPLED 0-3 +NET sys_led<0> LOC = G5; #GPLED0 +NET sys_led<1> LOC = G6; #GPLED1 +NET sys_led<2> LOC = A11; #GPLED2 +NET sys_led<3> LOC = A12; #GPLED3 +# North-East-South-West-Center LEDs +NET sys_led<4> LOC = F9; # W LED +NET sys_led<5> LOC = A5; # S LED +NET sys_led<6> LOC = E10; # E LED +NET sys_led<7> LOC = E2; # N LED +NET sys_led<8> LOC = "C6"; # C LED + +NET "sys_led<*>" TIG; +NET "sys_led<*>" SLEW = SLOW; +NET "sys_led<*>" DRIVE = 2; diff --git a/projects/jtag_test/v4_test.tcl b/projects/jtag_test/v4_test.tcl new file mode 100644 index 0000000..73a6702 --- /dev/null +++ b/projects/jtag_test/v4_test.tcl @@ -0,0 +1,43 @@ +# Source JTAG/TCL frame work +cd $env(CHIPSCOPE)/bin/nt +source $env(CHIPSCOPE)/bin/nt/tcljtag.tcl + +# Open JTAG +set handle [jtag_open type=xilinx_platformusb frequency=750000] +jtag_lock $handle +set devlist [jtag_autodetect $handle] +puts $devlist + +# Scan chain +set idcode_list [jtag_scanchain $handle] +puts $idcode_list + +# Get number of devices in chain +set devcount [jtag_devicecount $handle] +puts "Number of devices in the chain: $devcount" + +# Get Device ID +set devtype "Virtex-4SX" +set devid 2 + + +puts "IR Length of device $devid is [jtag_irlength $handle $devid]" +#jtag_navigate $handle TLR + + +# --------------------------------------------------------------- +# Shift the USER1 Instruction (b1111000010) into the Instruction Register of FPGA +# User 1 +puts [jtag_shiftir $handle -buffer "1100001111" -endstate RTI -device $devid] + +# DevIDCode +#puts [jtag_shiftir $handle -buffer "1001001111" -endstate RTI -device $devid] + +# Write LED <= 0x55 +puts [jtag_shiftdr $handle -buffer "10101010" -endstate RTI -device $devid] + +# --------------------------------------------------------------- + +jtag_unlock $handle +jtag_close $handle +exit