- added

git-svn-id: http://moon:8086/svn/vhdl/trunk@1429 cc03376c-175c-47c8-b038-4cd826a8556b
2021-03-21 12:04:37 +00:00
parent 9edf6a70af
commit 2f7ab91e0d
116 changed files with 50542 additions and 0 deletions
@@ -0,0 +1,117 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:    17:07:37 11/13/05
+-- Design Name:    
+-- Module Name:    hpi_reg_top - Behavioral
+-- Project Name:   
+-- Target Device:  
+-- Tool versions:  
+-- Description:
+--
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity hpi_reg_top is
+    Port ( sys_rst_n : in std_logic;
+           sys_clk : in std_logic;
+           sys_hpi_a : in std_logic_vector(1 downto 0);
+           sys_hpi_d : inout std_logic_vector(15 downto 0);
+           sys_hpi_rd_n : in std_logic;
+           sys_hpi_wr_n : in std_logic;
+           sys_hpi_cs_n : in std_logic;
+           sys_hpi_rst_n : in std_logic;
+           sys_hpi_int : in std_logic;
+           sys_led : out std_logic_vector(3 downto 0);
+           sys_sace_mpce_n : out std_logic);
+end hpi_reg_top;
+
+architecture Behavioral of hpi_reg_top is
+
+	COMPONENT oneshot
+   Generic ( mode : integer range 0 to 2);
+	PORT(
+		rst : IN std_logic;
+		clk : IN std_logic;
+		input : IN std_logic;          
+		output : OUT std_logic
+		);
+	END COMPONENT;
+
+	signal reg : std_logic_vector(15 downto 0);
+   signal wr_n : std_logic;
+
+begin
+
+sys_sace_mpce_n <= '1';
+sys_led(0)      <=  sys_hpi_cs_n;
+sys_led(1)      <=  sys_hpi_rd_n;
+sys_led(2)      <=  sys_hpi_wr_n;
+sys_led(3)      <=  sys_hpi_int;
+
+	Inst_oneshot_wr: oneshot 
+	GENERIC MAP (mode => 1)
+	PORT MAP(
+		rst => sys_rst_n,
+		clk => sys_clk,
+		input => sys_hpi_wr_n,
+		output => wr_n
+	);
+
+reg_in: process(sys_clk, sys_hpi_rst_n, wr_n, sys_hpi_cs_n, sys_hpi_a, sys_hpi_d)
+begin
+	if (sys_hpi_rst_n = '0') then
+		reg <= (others => '0');
+	else
+		if (sys_hpi_cs_n = '0') then
+			if (wr_n = '0' and rising_edge(sys_clk)) then
+			   case (sys_hpi_a) is 
+					when "00" =>
+					reg <= sys_hpi_d;
+
+	   	   	when others => null;
+		   	end case;
+			end if;
+		end if;
+	end if;
+end process;
+
+reg_out: process(sys_hpi_rst_n, sys_hpi_rd_n, sys_hpi_cs_n, sys_hpi_a, reg)
+begin
+	if (sys_hpi_rst_n = '0') then
+		sys_hpi_d <= (others => 'Z');
+	else
+		if (sys_hpi_cs_n = '0' and sys_hpi_rd_n = '0') then
+		   case (sys_hpi_a) is 
+				when "00" =>
+				sys_hpi_d <= reg;
+				when "01" =>
+				sys_hpi_d <= X"AAAA";
+				when "10" =>
+				sys_hpi_d <= X"5555";
+				when "11" =>
+				sys_hpi_d <= X"1234";
+	   	   when others => null;
+		   end case;
+		else
+			sys_hpi_d <= (others => 'Z');
+		end if;
+	end if;
+end process;
+
+end Behavioral;