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git-svn-id: http://moon:8086/svn/vhdl/trunk@1429 cc03376c-175c-47c8-b038-4cd826a8556b
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jens
2021-03-21 12:04:37 +00:00
parent 9edf6a70af
commit 2f7ab91e0d
116 changed files with 50542 additions and 0 deletions
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projects/hpi_reg/ise/bitgen.ut
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-w
-g DebugBitstream:No
-g Binary:no
-g CRC:Enable
-g ConfigRate:4
-g CclkPin:PullUp
-g M0Pin:PullUp
-g M1Pin:PullUp
-g M2Pin:PullUp
-g ProgPin:PullUp
-g DonePin:PullUp
-g InitPin:Pullup
-g CsPin:Pullup
-g DinPin:Pullup
-g BusyPin:Pullup
-g RdWrPin:Pullup
-g TckPin:PullUp
-g TdiPin:PullUp
-g TdoPin:PullUp
-g TmsPin:PullUp
-g UnusedPin:PullDown
-g UserID:0xFFFFFFFF
-g DCMShutDown:Disable
-g DCIUpdateMode:AsRequired
-g StartUpClk:JtagClk
-g DONE_cycle:4
-g GTS_cycle:5
-g GWE_cycle:6
-g LCK_cycle:NoWait
-g Security:None
-g DonePipe:No
-g DriveDone:No
-g Encrypt:No
projects/hpi_reg/ise/hpi_reg.ise
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projects/hpi_reg/ise/hpi_reg_top.lso
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work
projects/hpi_reg/ise/hpi_reg_top.prj
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vhdl work "E:/work/XilinxISE/Common/oneshot.vhd"
vhdl work "hpi_reg_top.vhd"
projects/hpi_reg/ise/hpi_reg_top.ut
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-w
-g DebugBitstream:No
-g Binary:no
-g CRC:Enable
-g ConfigRate:4
-g CclkPin:PullUp
-g M0Pin:PullUp
-g M1Pin:PullUp
-g M2Pin:PullUp
-g ProgPin:PullUp
-g DonePin:PullUp
-g InitPin:Pullup
-g CsPin:Pullup
-g DinPin:Pullup
-g BusyPin:Pullup
-g RdWrPin:Pullup
-g TckPin:PullUp
-g TdiPin:PullUp
-g TdoPin:PullUp
-g TmsPin:PullUp
-g UnusedPin:PullDown
-g UserID:0xFFFFFFFF
-g DCMShutDown:Disable
-g DCIUpdateMode:AsRequired
-g StartUpClk:JtagClk
-g DONE_cycle:4
-g GTS_cycle:5
-g GWE_cycle:6
-g LCK_cycle:NoWait
-g Security:None
-g DonePipe:No
-g DriveDone:No
-g Encrypt:No
projects/hpi_reg/ise/hpi_reg_top.xst
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set -tmpdir ./xst/projnav.tmp
set -xsthdpdir ./xst
run
-ifn hpi_reg_top.prj
-ifmt mixed
-ofn hpi_reg_top
-ofmt NGC
-p xc4vsx35-10-ff668
-top hpi_reg_top
-opt_mode Speed
-opt_level 1
-iuc NO
-lso hpi_reg_top.lso
-keep_hierarchy NO
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case maintain
-slice_utilization_ratio 100
-dsp_utilization_ratio 100
-verilog2001 YES
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style lut
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-mux_style Auto
-decoder_extract YES
-priority_extract YES
-shreg_extract YES
-shift_extract YES
-xor_collapse YES
-rom_style Auto
-mux_extract YES
-resource_sharing YES
-use_dsp48 auto
-iobuf YES
-max_fanout 500
-bufg 32
-bufr 24
-register_duplication YES
-register_balancing No
-slice_packing YES
-optimize_primitives NO
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5
projects/hpi_reg/ise/oneshot.lso
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work
projects/hpi_reg/ise/oneshot.prj
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vhdl work "../Common/oneshot.vhd"
projects/hpi_reg/ise/pepExtractor.prj
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work "../Common/oneshot.vhd"
projects/hpi_reg/ise/system.ucf
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#
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
# SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
# XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
# AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
# OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
# IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
# AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
# FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
# WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
# IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
# REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
# INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
# FOR A PARTICULAR PURPOSE.
#
# (c) Copyright 2005 Xilinx, Inc.
# All rights reserved.
#
# Bus clock nets
#NET sys_clk TNM_NET = "sys_clk";
#TIMESPEC "TSSYSCLK" = PERIOD "sys_clk" 9.9 ns HIGH 50 %;
NET sys_clk LOC = AE14;
NET sys_clk IOSTANDARD = LVCMOS33;
NET sys_rst_n LOC = D6;
NET sys_rst_n PULLUP;
NET sys_rst_n TIG;
# GPLED 0-3
NET sys_led<0> LOC = G5; #GPLED0
NET sys_led<1> LOC = G6; #GPLED1
NET sys_led<2> LOC = A11; #GPLED2
NET sys_led<3> LOC = A12; #GPLED3
#NET "led<*>" SLEW = SLOW;
#NET "led<*>" DRIVE = 2;
# Dip Switches 1-8
#NET sys_test_in<0> LOC = U24; # DIP SW 8
#NET sys_test_in<1> LOC = U25; # DIP SW 7
#NET sys_test_in<2> LOC = V23; # DIP SW 6
#NET sys_test_in<3> LOC = U23; # DIP SW 5
#NET sys_test_in<4> LOC = U26; # DIP SW 4
#NET sys_test_in<5> LOC = T26; # DIP SW 3
#NET sys_test_in<6> LOC = R19; # DIP SW 2
#NET sys_test_in<7> LOC = R20; # DIP SW 1
#NET sys_test_in<0> IOSTANDARD = LVCMOS33;
#NET sys_test_in<1> IOSTANDARD = LVCMOS33;
#NET sys_test_in<2> IOSTANDARD = LVCMOS33;
#NET sys_test_in<3> IOSTANDARD = LVCMOS33;
#NET sys_test_in<4> IOSTANDARD = LVCMOS33;
#NET sys_test_in<5> IOSTANDARD = LVCMOS33;
#NET sys_test_in<6> IOSTANDARD = LVCMOS33;
#NET sys_test_in<7> IOSTANDARD = LVCMOS33;
#NET "sys_test_in<*>" PULLDOWN;
#NET "sys_test_in<*>" TIG;
#NET "sys_test_in<*>" SLEW = SLOW;
#NET "sys_test_in<*>" DRIVE = 2;
NET sys_hpi_a<0> LOC = U22;
NET sys_hpi_a<1> LOC = Y10;
NET sys_hpi_a<*> IOSTANDARD = LVCMOS33;
NET sys_hpi_a<*> SLEW = FAST;
NET sys_hpi_a<*> DRIVE = 8;
NET sys_hpi_d<0> LOC = AB7;
NET sys_hpi_d<1> LOC = AC9;
NET sys_hpi_d<2> LOC = AB9;
NET sys_hpi_d<3> LOC = AE6;
NET sys_hpi_d<4> LOC = AD6;
NET sys_hpi_d<5> LOC = AF9;
NET sys_hpi_d<6> LOC = AE9;
NET sys_hpi_d<7> LOC = AD8;
NET sys_hpi_d<8> LOC = AC8;
NET sys_hpi_d<9> LOC = AF4;
NET sys_hpi_d<10> LOC = AE4;
NET sys_hpi_d<11> LOC = AD3;
NET sys_hpi_d<12> LOC = AC3;
NET sys_hpi_d<13> LOC = AF6;
NET sys_hpi_d<14> LOC = AF5;
NET sys_hpi_d<15> LOC = AA7;
NET sys_hpi_d<*> IOSTANDARD = LVCMOS33;
NET sys_hpi_d<*> SLEW = FAST;
NET sys_hpi_d<*> DRIVE = 8;
NET sys_hpi_d<*> PULLUP;
NET sys_hpi_rd_n LOC = AA8;
NET sys_hpi_rd_n IOSTANDARD = LVCMOS33;
NET sys_hpi_rd_n SLEW = FAST;
NET sys_hpi_rd_n DRIVE = 8;
NET sys_hpi_wr_n LOC = Y8;
NET sys_hpi_wr_n IOSTANDARD = LVCMOS33;
NET sys_hpi_wr_n SLEW = FAST;
NET sys_hpi_wr_n DRIVE = 8;
NET sys_hpi_cs_n LOC = AF10;
NET sys_hpi_cs_n IOSTANDARD = LVCMOS33;
NET sys_hpi_cs_n SLEW = FAST;
NET sys_hpi_cs_n DRIVE = 8;
NET sys_hpi_rst_n LOC = A7;
NET sys_hpi_rst_n IOSTANDARD = LVCMOS25;
NET sys_hpi_rst_n TIG;
NET sys_hpi_int LOC = V5;
NET sys_hpi_int IOSTANDARD = LVCMOS33;
NET sys_hpi_int TIG;
NET sys_hpi_int PULLUP;
NET sys_sace_mpce_n LOC = AD5;
NET sys_sace_mpce_n IOSTANDARD = LVCMOS33;
NET sys_sace_mpce_n SLEW = FAST;
NET sys_sace_mpce_n DRIVE = 8;
projects/hpi_reg/src/hpi_reg_top.vhd
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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:07:37 11/13/05
-- Design Name:
-- Module Name: hpi_reg_top - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity hpi_reg_top is
Port ( sys_rst_n : in std_logic;
sys_clk : in std_logic;
sys_hpi_a : in std_logic_vector(1 downto 0);
sys_hpi_d : inout std_logic_vector(15 downto 0);
sys_hpi_rd_n : in std_logic;
sys_hpi_wr_n : in std_logic;
sys_hpi_cs_n : in std_logic;
sys_hpi_rst_n : in std_logic;
sys_hpi_int : in std_logic;
sys_led : out std_logic_vector(3 downto 0);
sys_sace_mpce_n : out std_logic);
end hpi_reg_top;
architecture Behavioral of hpi_reg_top is
COMPONENT oneshot
Generic ( mode : integer range 0 to 2);
PORT(
rst : IN std_logic;
clk : IN std_logic;
input : IN std_logic;
output : OUT std_logic
);
END COMPONENT;
signal reg : std_logic_vector(15 downto 0);
signal wr_n : std_logic;
begin
sys_sace_mpce_n <= '1';
sys_led(0) <= sys_hpi_cs_n;
sys_led(1) <= sys_hpi_rd_n;
sys_led(2) <= sys_hpi_wr_n;
sys_led(3) <= sys_hpi_int;
Inst_oneshot_wr: oneshot
GENERIC MAP (mode => 1)
PORT MAP(
rst => sys_rst_n,
clk => sys_clk,
input => sys_hpi_wr_n,
output => wr_n
);
reg_in: process(sys_clk, sys_hpi_rst_n, wr_n, sys_hpi_cs_n, sys_hpi_a, sys_hpi_d)
begin
if (sys_hpi_rst_n = '0') then
reg <= (others => '0');
else
if (sys_hpi_cs_n = '0') then
if (wr_n = '0' and rising_edge(sys_clk)) then
case (sys_hpi_a) is
when "00" =>
reg <= sys_hpi_d;
when others => null;
end case;
end if;
end if;
end if;
end process;
reg_out: process(sys_hpi_rst_n, sys_hpi_rd_n, sys_hpi_cs_n, sys_hpi_a, reg)
begin
if (sys_hpi_rst_n = '0') then
sys_hpi_d <= (others => 'Z');
else
if (sys_hpi_cs_n = '0' and sys_hpi_rd_n = '0') then
case (sys_hpi_a) is
when "00" =>
sys_hpi_d <= reg;
when "01" =>
sys_hpi_d <= X"AAAA";
when "10" =>
sys_hpi_d <= X"5555";
when "11" =>
sys_hpi_d <= X"1234";
when others => null;
end case;
else
sys_hpi_d <= (others => 'Z');
end if;
end if;
end process;
end Behavioral;