- added

git-svn-id: http://moon:8086/svn/vhdl/trunk@1429 cc03376c-175c-47c8-b038-4cd826a8556b

projects/eval_twoclocks/vconfig.vhdl

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+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+--  Uncomment the following lines to use the declarations that are
+--  provided for instantiating Xilinx primitive components.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity eval2clk is
+    Port ( RES : in std_logic;
+           CLK : in std_logic;
+			  SCLK : inout std_logic;
+			  dummy_out : inout std_logic);
+end eval2clk;
+
+architecture Behavioral of eval2clk is
+signal count, scount : integer range 0 to 63;
+signal SCLK1 : std_logic;
+begin
+
+process (RES, SCLK1) 
+begin
+      if (RES = '1') then
+        dummy_out <= '1';
+	     scount <= 2;
+
+	   elsif SCLK1='1' and SCLK1'event then
+
+		if (scount = 0) then
+         scount <= 2;
+		  	dummy_out <= not dummy_out;
+
+      else
+         scount <= scount - 1;
+      end if;
+   end if;
+end process;
+
+process (RES, CLK) 
+begin
+      if (RES = '1') then
+        SCLK1 <= '1';
+	     COUNT <= 4;
+
+	   elsif CLK='1' and CLK'event then
+
+		if (COUNT = 0) then
+         COUNT <= 4;
+		  	SCLK1 <= not SCLK1;
+
+      else
+         COUNT <= COUNT - 1;
+      end if;
+   end if;
+end process;
+
+SCLK <= RES;
+
+end Behavioral;
+