- added

git-svn-id: http://moon:8086/svn/vhdl/trunk@1429 cc03376c-175c-47c8-b038-4cd826a8556b

projects/eval_twoclocks/eval2clk.lso

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+work

projects/eval_twoclocks/eval2clk.prj

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+vhdl work vconfig.vhdl

projects/eval_twoclocks/eval2clk_tb.fdo

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+## NOTE:  Do not edit this file.
+## Autogenerated by ProjNav (creatfdo.tcl) on Wed Jun 02 00:12:48 Westeuropäische Sommerzeit 2004
+##
+vlib work
+vcom -93 -explicit  vconfig.vhdl
+vcom -93 -explicit  eval2clk_tb.vhd
+vsim -t 1ps   -lib work eval2clk_tb
+do eval2clk_tb.udo
+view wave
+add wave *
+view structure
+view signals
+run 2000ns

projects/eval_twoclocks/eval2clk_tb.tdo

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+## NOTE: Do not edit this file.
+## Auto generated by Project Navigator for VHDL Post-PAR Simulation
+##
+vlib work
+## Compile Post-PAR Model for Module eval2clk
+vcom -87 -explicit  eval2clk_timesim.vhd
+vcom -93 -explicit  eval2clk_tb.vhd
+vsim -t 1ps -sdfmax /UUT=eval2clk_timesim.sdf  -lib work eval2clk_tb
+do eval2clk_tb.udo
+view wave
+add wave *
+view structure
+view signals
+run 2000ns
+## End

projects/eval_twoclocks/eval2clk_tb.udo

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+-- ProjNav VHDL simulation template: eval2clk_tb.udo
+-- You may edit this file after the line that starts with
+-- '-- START' to customize your simulation
+-- START user-defined simulation commands

projects/eval_twoclocks/eval2clk_tb.vhd

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+
+-- VHDL Test Bench Created from source file vconfig.vhd -- 20:20:01 05/01/2004
+--
+-- Notes: 
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
+-- that these types always be used for the top-level I/O of a design in order 
+-- to guarantee that the testbench will bind correctly to the post-implementation 
+-- simulation model.
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY eval2clk_tb IS
+END eval2clk_tb;
+
+ARCHITECTURE behavior OF eval2clk_tb IS 
+
+	COMPONENT eval2clk
+	PORT(
+		RES : IN std_logic;
+		CLK : IN std_logic;    
+		SCLK : INOUT std_logic;      
+		dummy_out : INOUT std_logic
+		);
+	END COMPONENT;
+
+
+	SIGNAL RES :  std_logic := '1';
+	SIGNAL CLK :  std_logic := '0';
+	SIGNAL SCLK :  std_logic;
+	SIGNAL dummy_out :  std_logic := '0';
+
+	constant ClockPeriod : Time := 16.667 ns;
+
+BEGIN
+
+	uut: eval2clk PORT MAP(
+		RES => RES,
+		CLK => CLK,
+		SCLK => SCLK,
+		dummy_out => dummy_out
+	);
+
+	busclock: process
+	begin
+		CLK <= '1';
+		loop
+			wait for (ClockPeriod / 2);
+			CLK <= not CLK;
+		end loop;  
+	end process;
+
+-- *** Test Bench - User Defined Section ***
+   tb : PROCESS
+   BEGIN
+
+	   wait for 20*ClockPeriod;
+		RES <= '0';
+
+
+      wait; -- will wait forever
+   END PROCESS;
+-- *** End Test Bench - User Defined Section ***
+
+END;

projects/eval_twoclocks/pepExtractor.prj

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+work	vconfig.vhdl

projects/eval_twoclocks/vconfig.vhdl

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+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+--  Uncomment the following lines to use the declarations that are
+--  provided for instantiating Xilinx primitive components.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity eval2clk is
+    Port ( RES : in std_logic;
+           CLK : in std_logic;
+			  SCLK : inout std_logic;
+			  dummy_out : inout std_logic);
+end eval2clk;
+
+architecture Behavioral of eval2clk is
+signal count, scount : integer range 0 to 63;
+signal SCLK1 : std_logic;
+begin
+
+process (RES, SCLK1) 
+begin
+      if (RES = '1') then
+        dummy_out <= '1';
+	     scount <= 2;
+
+	   elsif SCLK1='1' and SCLK1'event then
+
+		if (scount = 0) then
+         scount <= 2;
+		  	dummy_out <= not dummy_out;
+
+      else
+         scount <= scount - 1;
+      end if;
+   end if;
+end process;
+
+process (RES, CLK) 
+begin
+      if (RES = '1') then
+        SCLK1 <= '1';
+	     COUNT <= 4;
+
+	   elsif CLK='1' and CLK'event then
+
+		if (COUNT = 0) then
+         COUNT <= 4;
+		  	SCLK1 <= not SCLK1;
+
+      else
+         COUNT <= COUNT - 1;
+      end if;
+   end if;
+end process;
+
+SCLK <= RES;
+
+end Behavioral;
+

projects/eval_twoclocks/vconfig_tb.vhd

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+
+-- VHDL Test Bench Created from source file vconfig.vhd -- 20:20:01 05/01/2004
+--
+-- Notes: 
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
+-- that these types always be used for the top-level I/O of a design in order 
+-- to guarantee that the testbench will bind correctly to the post-implementation 
+-- simulation model.
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY eval2clk_tb IS
+END eval2clk_tb;
+
+ARCHITECTURE behavior OF eval2clk_tb IS 
+
+	COMPONENT eval2clk
+	PORT(
+		RES : IN std_logic;
+		CLK : IN std_logic;    
+		SCLK : INOUT std_logic;      
+		dummy_out : OUT std_logic
+		);
+	END COMPONENT;
+
+
+	SIGNAL RES :  std_logic := '1';
+	SIGNAL CLK :  std_logic := '0';
+	SIGNAL SCLK :  std_logic;
+	SIGNAL dummy_out :  std_logic := '0';
+
+	constant ClockPeriod : Time := 16.667 ns;
+
+BEGIN
+
+	uut: eval2clk PORT MAP(
+		RES => RES,
+		CLK => CLK,
+		SCLK => SCLK,
+		dummy_out => dummy_out
+	);
+
+	busclock: process
+	begin
+		CLK <= '1';
+		loop
+			wait for (ClockPeriod / 2);
+			CLK <= not CLK;
+		end loop;  
+	end process;
+
+-- *** Test Bench - User Defined Section ***
+   tb : PROCESS
+   BEGIN
+
+	   wait for 20*ClockPeriod;
+		RES <= '0';
+
+
+      wait; -- will wait forever
+   END PROCESS;
+-- *** End Test Bench - User Defined Section ***
+
+END;