- added

git-svn-id: http://moon:8086/svn/vhdl/trunk@1429 cc03376c-175c-47c8-b038-4cd826a8556b

projects/eval_timingconstraint/main_top_tb.vhd

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+
+-- VHDL Test Bench Created from source file main_top.vhd -- 22:41:27 06/08/2004
+--
+-- Notes: 
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
+-- that these types always be used for the top-level I/O of a design in order 
+-- to guarantee that the testbench will bind correctly to the post-implementation 
+-- simulation model.
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY main_top_main_top_tb_vhd_tb IS
+END main_top_main_top_tb_vhd_tb;
+
+ARCHITECTURE behavior OF main_top_main_top_tb_vhd_tb IS 
+
+	COMPONENT main_top
+	PORT(
+		res : IN std_logic;
+		clki : IN std_logic;
+		di : IN std_logic;          
+		clko : OUT std_logic;
+		do : OUT std_logic
+		);
+	END COMPONENT;
+
+	constant ClockPeriod : Time := 20 ns;
+	SIGNAL res :  std_logic := '1';
+	SIGNAL clki :  std_logic;
+	SIGNAL clko :  std_logic;
+	SIGNAL di :  std_logic := '0';
+	SIGNAL do :  std_logic;
+
+BEGIN
+
+	uut: main_top PORT MAP(
+		res => res,
+		clki => clki,
+		clko => clko,
+		di => di,
+		do => do
+	);
+
+	clkgen: process
+	begin
+		clki <= '1';
+		loop
+			wait for (ClockPeriod / 2);
+			clki <= not clki;
+		end loop;  
+	end process;
+
+-- *** Test Bench - User Defined Section ***
+   tb : PROCESS
+   BEGIN
+		res <= '1';
+
+		wait for 5*ClockPeriod;
+		res <= '0';
+
+		wait for 5*ClockPeriod;
+		di <= '1';
+
+		wait for 14.5*ClockPeriod;
+		di <= '0';
+
+      wait; -- will wait forever
+   END PROCESS;
+-- *** End Test Bench - User Defined Section ***
+
+END;