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git-svn-id: http://moon:8086/svn/vhdl/trunk@1429 cc03376c-175c-47c8-b038-4cd826a8556b
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jens
2021-03-21 12:04:37 +00:00
parent 9edf6a70af
commit 2f7ab91e0d
116 changed files with 50542 additions and 0 deletions
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projects/eval_timingconstraint/main_top.lso
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work
projects/eval_timingconstraint/main_top.prj
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vhdl work main_top.vhdl
projects/eval_timingconstraint/main_top.ucf
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INST "clki" TNM = "TNM_clk";
NET "clki" PERIOD = 20 ns LOW 50 %;
INST "di" TNM = "testgrp_in";
INST "do" TNM = "testgrp_out";
TIMEGRP "testgrp_in" OFFSET = IN 10 ns BEFORE "clki" ;
TIMEGRP "testgrp_out" OFFSET = OUT 25 ns AFTER "clki" ;
#OFFSET = OUT 2 ns BEFORE "clk" TIMEGRP "TNM_clk" ;
projects/eval_timingconstraint/main_top.vhdl
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity main_top is
Port ( res : in std_logic;
clki : in std_logic;
clko : out std_logic;
di : in std_logic;
do : out std_logic);
end main_top;
architecture Behavioral of main_top is
type state_type is (idle, active, release);
signal state, nextstate : state_type;
signal clk : std_logic;
shared variable test : std_logic;
component BUFG
port (I: in std_logic; O: out std_logic);
end component;
--**Insert the following after the 'begin' keyword**
begin
--U1: BUFG port map (I => clki, O => clk);
clk <= clki;
process (res, clk, di, state)
begin
if (res = '1') then
clko <= '0';
else
clko <= '1';
case state is
when idle =>
if (di = '1') then
nextstate <= active;
else
nextstate <= idle;
end if;
when active =>
if (di = '1') then
nextstate <= active;
else
nextstate <= idle;
end if;
when release =>
nextstate <= idle;
end case;
end if;
end process;
process (res, clk, state)
begin
if (res = '1') then
do <= '0';
else
do <= '0';
case state is
when active =>
do <= '1';
when others =>
end case;
end if;
end process;
process (res, clk)
begin
if (res = '1') then
state <= idle;
elsif clk'event and clk = '1' then
state <= nextstate;
end if;
end process;
end Behavioral;
projects/eval_timingconstraint/main_top_main_top_tb_vhd_tb.fdo
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## NOTE: Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Tue Jun 08 23:46:14 Westeuropäische Sommerzeit 2004
##
vlib work
vcom -93 -explicit main_top.vhdl
vcom -93 -explicit main_top_tb.vhd
vsim -t 1ps -lib work main_top_main_top_tb_vhd_tb
do main_top_main_top_tb_vhd_tb.udo
view wave
add wave *
view structure
view signals
run 1000ns
projects/eval_timingconstraint/main_top_main_top_tb_vhd_tb.tdo
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## NOTE: Do not edit this file.
## Auto generated by Project Navigator for VHDL Post-PAR Simulation
##
vlib work
## Compile Post-PAR Model for Module main_top
vcom -87 -explicit main_top_timesim.vhd
vcom -93 -explicit main_top_tb.vhd
vsim -t 1ps -sdfmax /UUT=main_top_timesim.sdf -lib work main_top_main_top_tb_vhd_tb
do main_top_main_top_tb_vhd_tb.udo
view wave
add wave *
view structure
view signals
run 1000ns
## End
projects/eval_timingconstraint/main_top_main_top_tb_vhd_tb.udo
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-- ProjNav VHDL simulation template: main_top_main_top_tb_vhd_tb.udo
-- You may edit this file after the line that starts with
-- '-- START' to customize your simulation
-- START user-defined simulation commands
projects/eval_timingconstraint/main_top_tb.vhd
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-- VHDL Test Bench Created from source file main_top.vhd -- 22:41:27 06/08/2004
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY main_top_main_top_tb_vhd_tb IS
END main_top_main_top_tb_vhd_tb;
ARCHITECTURE behavior OF main_top_main_top_tb_vhd_tb IS
COMPONENT main_top
PORT(
res : IN std_logic;
clki : IN std_logic;
di : IN std_logic;
clko : OUT std_logic;
do : OUT std_logic
);
END COMPONENT;
constant ClockPeriod : Time := 20 ns;
SIGNAL res : std_logic := '1';
SIGNAL clki : std_logic;
SIGNAL clko : std_logic;
SIGNAL di : std_logic := '0';
SIGNAL do : std_logic;
BEGIN
uut: main_top PORT MAP(
res => res,
clki => clki,
clko => clko,
di => di,
do => do
);
clkgen: process
begin
clki <= '1';
loop
wait for (ClockPeriod / 2);
clki <= not clki;
end loop;
end process;
-- *** Test Bench - User Defined Section ***
tb : PROCESS
BEGIN
res <= '1';
wait for 5*ClockPeriod;
res <= '0';
wait for 5*ClockPeriod;
di <= '1';
wait for 14.5*ClockPeriod;
di <= '0';
wait; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***
END;
projects/eval_timingconstraint/main_top_timesim.vhd
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-- Xilinx Vhdl netlist produced by netgen application (version G.30)
-- Command : -intstyle ise -s 6 -pcf main_top.pcf -ngm main_top.ngm -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim main_top.ncd main_top_timesim.vhd
-- Input file : main_top.ncd
-- Output file : main_top_timesim.vhd
-- Design name : main_top
-- # of Entities : 1
-- Xilinx : D:/Xilinx
-- Device : 2v250cs144-6 (PRODUCTION 1.118 2004-03-12, STEPPING 1)
-- This vhdl netlist is a simulation model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity main_top is
port (
clko : out STD_LOGIC;
do : out STD_LOGIC;
res : in STD_LOGIC := 'X';
clki : in STD_LOGIC := 'X';
di : in STD_LOGIC := 'X'
);
end main_top;
architecture Structure of main_top is
signal di_IBUF : STD_LOGIC;
signal do_OBUF : STD_LOGIC;
signal clki_IBUFG : STD_LOGIC;
signal clko_OBUF : STD_LOGIC;
signal res_BUFGP_IBUFG : STD_LOGIC;
signal GLOBAL_LOGIC1 : STD_LOGIC;
signal res_BUFGP : STD_LOGIC;
signal GLOBAL_LOGIC1_0 : STD_LOGIC;
signal GSR : STD_LOGIC;
signal GTS : STD_LOGIC;
signal di_INBUF : STD_LOGIC;
signal do_ENABLE : STD_LOGIC;
signal do_GTS_OR_T : STD_LOGIC;
signal do_O : STD_LOGIC;
signal clki_INBUF : STD_LOGIC;
signal clko_ENABLE : STD_LOGIC;
signal clko_GTS_OR_T : STD_LOGIC;
signal clko_O : STD_LOGIC;
signal res_INBUF : STD_LOGIC;
signal U1_S_INVNOT : STD_LOGIC;
signal res_BUFGP_BUFG_S_INVNOT : STD_LOGIC;
signal nextstate_1_DXMUX : STD_LOGIC;
signal nextstate_1_F : STD_LOGIC;
signal nextstate_1_DYMUX : STD_LOGIC;
signal nextstate_1_G : STD_LOGIC;
signal nextstate_1_CLKINV : STD_LOGIC;
signal state_1_DXMUX : STD_LOGIC;
signal state_1_DYMUX : STD_LOGIC;
signal state_1_SRFFMUX : STD_LOGIC;
signal state_1_CLKINV : STD_LOGIC;
signal do_OBUF_G : STD_LOGIC;
signal nextstate_1_FFY_SET : STD_LOGIC;
signal nextstate_1_FFX_RST : STD_LOGIC;
signal state_1_FFY_SET : STD_LOGIC;
signal state_1_FFX_RST : STD_LOGIC;
signal GND : STD_LOGIC;
signal VCC : STD_LOGIC;
signal NlwInverterSignal_nextstate_0_CLK : STD_LOGIC;
signal NlwInverterSignal_nextstate_1_CLK : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal Q_n0003 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal nextstate : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
di_IBUF_0 : X_BUF_PP
generic map(
PATHPULSE => 605 ps
)
port map (
I => di,
O => di_INBUF
);
do_OBUF_1 : X_TRI_PP
generic map(
PATHPULSE => 605 ps
)
port map (
I => do_O,
CTL => do_ENABLE,
O => do
);
do_ENABLEINV : X_INV
port map (
I => do_GTS_OR_T,
O => do_ENABLE
);
do_GTS_OR_T_2 : X_BUF_PP
generic map(
PATHPULSE => 605 ps
)
port map (
I => GTS,
O => do_GTS_OR_T
);
clki_IBUFG_3 : X_BUF_PP
generic map(
PATHPULSE => 605 ps
)
port map (
I => clki,
O => clki_INBUF
);
clko_OBUF_4 : X_TRI_PP
generic map(
PATHPULSE => 605 ps
)
port map (
I => clko_O,
CTL => clko_ENABLE,
O => clko
);
clko_ENABLEINV : X_INV
port map (
I => clko_GTS_OR_T,
O => clko_ENABLE
);
clko_GTS_OR_T_5 : X_BUF_PP
generic map(
PATHPULSE => 605 ps
)
port map (
I => GTS,
O => clko_GTS_OR_T
);
res_BUFGP_IBUFG_6 : X_BUF_PP
generic map(
PATHPULSE => 605 ps
)
port map (
I => res,
O => res_INBUF
);
U1 : X_BUFGMUX
port map (
I0 => clki_IBUFG,
I1 => GND,
S => U1_S_INVNOT,
O => clko_OBUF,
GSR => GSR
);
U1_SINV : X_INV
port map (
I => GLOBAL_LOGIC1,
O => U1_S_INVNOT
);
res_BUFGP_BUFG : X_BUFGMUX
port map (
I0 => res_BUFGP_IBUFG,
I1 => GND,
S => res_BUFGP_BUFG_S_INVNOT,
O => res_BUFGP,
GSR => GSR
);
res_BUFGP_BUFG_SINV : X_INV
port map (
I => GLOBAL_LOGIC1_0,
O => res_BUFGP_BUFG_S_INVNOT
);
nextstate_1_DXMUX_7 : X_BUF_PP
generic map(
PATHPULSE => 605 ps
)
port map (
I => Q_n0003(1),
O => nextstate_1_DXMUX
);
nextstate_1_XUSED : X_BUF_PP
generic map(
PATHPULSE => 605 ps
)
port map (
I => nextstate_1_F,
O => Q_n0003(1)
);
nextstate_1_DYMUX_8 : X_BUF_PP
generic map(
PATHPULSE => 605 ps
)
port map (
I => Q_n0003(0),
O => nextstate_1_DYMUX
);
nextstate_1_YUSED : X_BUF_PP
generic map(
PATHPULSE => 605 ps
)
port map (
I => nextstate_1_G,
O => Q_n0003(0)
);
nextstate_1_CLKINV_9 : X_BUF_PP
generic map(
PATHPULSE => 605 ps
)
port map (
I => res_BUFGP,
O => nextstate_1_CLKINV
);
state_1_DXMUX_10 : X_BUF_PP
generic map(
PATHPULSE => 605 ps
)
port map (
I => nextstate(1),
O => state_1_DXMUX
);
state_1_DYMUX_11 : X_BUF_PP
generic map(
PATHPULSE => 605 ps
)
port map (
I => nextstate(0),
O => state_1_DYMUX
);
state_1_SRFFMUX_12 : X_BUF_PP
generic map(
PATHPULSE => 605 ps
)
port map (
I => res_BUFGP,
O => state_1_SRFFMUX
);
state_1_CLKINV_13 : X_BUF_PP
generic map(
PATHPULSE => 605 ps
)
port map (
I => clko_OBUF,
O => state_1_CLKINV
);
do_OBUF_YUSED : X_BUF_PP
generic map(
PATHPULSE => 605 ps
)
port map (
I => do_OBUF_G,
O => do_OBUF
);
Q_n0003_0_1 : X_LUT4
generic map(
INIT => X"5544"
)
port map (
ADR0 => di_IBUF,
ADR1 => state(1),
ADR2 => VCC,
ADR3 => state(0),
O => nextstate_1_G
);
nextstate_0 : X_LATCHE
generic map(
INIT => '1'
)
port map (
I => nextstate_1_DYMUX,
GE => VCC,
CLK => NlwInverterSignal_nextstate_0_CLK,
SET => nextstate_1_FFY_SET,
RST => GND,
O => nextstate(0)
);
nextstate_1_FFY_SETOR : X_BUF_PP
generic map(
PATHPULSE => 605 ps
)
port map (
I => GSR,
O => nextstate_1_FFY_SET
);
Q_n0003_1_1 : X_LUT4
generic map(
INIT => X"AA88"
)
port map (
ADR0 => di_IBUF,
ADR1 => state(1),
ADR2 => VCC,
ADR3 => state(0),
O => nextstate_1_F
);
nextstate_1 : X_LATCHE
generic map(
INIT => '0'
)
port map (
I => nextstate_1_DXMUX,
GE => VCC,
CLK => NlwInverterSignal_nextstate_1_CLK,
SET => GND,
RST => nextstate_1_FFX_RST,
O => nextstate(1)
);
nextstate_1_FFX_RSTOR : X_BUF_PP
generic map(
PATHPULSE => 605 ps
)
port map (
I => GSR,
O => nextstate_1_FFX_RST
);
state_0 : X_FF
generic map(
INIT => '1'
)
port map (
I => state_1_DYMUX,
CE => VCC,
CLK => state_1_CLKINV,
SET => state_1_FFY_SET,
RST => GND,
O => state(0)
);
state_1_FFY_SETOR : X_OR2
port map (
I0 => GSR,
I1 => state_1_SRFFMUX,
O => state_1_FFY_SET
);
Q_n00061 : X_LUT4
generic map(
INIT => X"4444"
)
port map (
ADR0 => res_BUFGP,
ADR1 => state(1),
ADR2 => VCC,
ADR3 => VCC,
O => do_OBUF_G
);
state_1 : X_FF
generic map(
INIT => '0'
)
port map (
I => state_1_DXMUX,
CE => VCC,
CLK => state_1_CLKINV,
SET => GND,
RST => state_1_FFX_RST,
O => state(1)
);
state_1_FFX_RSTOR : X_OR2
port map (
I0 => state_1_SRFFMUX,
I1 => GSR,
O => state_1_FFX_RST
);
PWR_VCC_0_LOGICAL_ONE : X_ONE
port map (
O => GLOBAL_LOGIC1
);
PWR_VCC_1_LOGICAL_ONE : X_ONE
port map (
O => GLOBAL_LOGIC1_0
);
di_IFF_IMUX : X_BUF_PP
generic map(
PATHPULSE => 605 ps
)
port map (
I => di_INBUF,
O => di_IBUF
);
do_OUTPUT_OFF_OMUX : X_BUF_PP
generic map(
PATHPULSE => 605 ps
)
port map (
I => do_OBUF,
O => do_O
);
clki_IFF_IMUX : X_BUF_PP
generic map(
PATHPULSE => 605 ps
)
port map (
I => clki_INBUF,
O => clki_IBUFG
);
clko_OUTPUT_OFF_OMUX : X_BUF_PP
generic map(
PATHPULSE => 605 ps
)
port map (
I => clko_OBUF,
O => clko_O
);
res_IFF_IMUX : X_BUF_PP
generic map(
PATHPULSE => 605 ps
)
port map (
I => res_INBUF,
O => res_BUFGP_IBUFG
);
NlwBlock_main_top_GND : X_ZERO
port map (
O => GND
);
NlwBlock_main_top_VCC : X_ONE
port map (
O => VCC
);
NlwInverterBlock_nextstate_0_CLK : X_INV
port map (
I => nextstate_1_CLKINV,
O => NlwInverterSignal_nextstate_0_CLK
);
NlwInverterBlock_nextstate_1_CLK : X_INV
port map (
I => nextstate_1_CLKINV,
O => NlwInverterSignal_nextstate_1_CLK
);
NlwBlockROC : X_ROC
generic map (ROC_WIDTH => 100 ns)
port map (O => GSR);
NlwBlockTOC : X_TOC
port map (O => GTS);
end Structure;
projects/eval_timingconstraint/main_top_vhdl.prj
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work main_top.vhdl
projects/eval_timingconstraint/pepExtractor.prj
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work main_top.vhdl