- added

git-svn-id: http://moon:8086/svn/vhdl/trunk@1429 cc03376c-175c-47c8-b038-4cd826a8556b

projects/eval_sync/src/d_ff.vhd

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+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:    13:19:14 10/08/05
+-- Design Name:    
+-- Module Name:    d_ff - Behavioral
+-- Project Name:   
+-- Target Device:  
+-- Tool versions:  
+-- Description:
+--
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity d_ff is
+	Generic (
+	   tpd : time := 1 ns
+		);
+    Port ( rst : in std_logic;
+           clk : in std_logic;
+           din : in std_logic;
+           dout : out std_logic);
+end d_ff;
+
+architecture Behavioral of d_ff is
+
+begin
+
+d_ff_proc : process(rst, clk, din)
+begin
+	if (rst = '1') then
+		dout <= '0' after tpd;
+	elsif rising_edge(clk) then
+		dout <= din after tpd;
+	end if;
+end process;
+
+end Behavioral;