- added

git-svn-id: http://moon:8086/svn/vhdl/trunk@1429 cc03376c-175c-47c8-b038-4cd826a8556b
2021-03-21 12:04:37 +00:00
parent 9edf6a70af
commit 2f7ab91e0d
116 changed files with 50542 additions and 0 deletions
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+vhdl work "d_ff.vhd"
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+work
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+vhdl work "d_ff.vhd"
+vhdl work "eval_synch_top.vhd"
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+## NOTE:  Do not edit this file.
+## Autogenerated by ProjNav (creatfdo.tcl) on Sat Oct 08 13:45:11 Westeuropäische Sommerzeit 2005
+##
+vlib work
+vcom -93 -explicit  d_ff.vhd
+vcom -93 -explicit  eval_synch_top.vhd
+vcom -93 -explicit  tb_eval_synch.vhd
+vsim -t 1ps   -lib work tb_eval_synch_vhd
+do {tb_eval_synch_vhd.udo}
+view wave
+add wave *
+view structure
+view signals
+run 1000ns
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+-- ProjNav VHDL simulation template: tb_eval_synch_vhd.udo
+-- You may edit this file after the line that starts with
+-- '-- START' to customize your simulation
+-- START user-defined simulation commands
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+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:    13:19:14 10/08/05
+-- Design Name:    
+-- Module Name:    d_ff - Behavioral
+-- Project Name:   
+-- Target Device:  
+-- Tool versions:  
+-- Description:
+--
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity d_ff is
+	Generic (
+	   tpd : time := 1 ns
+		);
+    Port ( rst : in std_logic;
+           clk : in std_logic;
+           din : in std_logic;
+           dout : out std_logic);
+end d_ff;
+
+architecture Behavioral of d_ff is
+
+begin
+
+d_ff_proc : process(rst, clk, din)
+begin
+	if (rst = '1') then
+		dout <= '0' after tpd;
+	elsif rising_edge(clk) then
+		dout <= din after tpd;
+	end if;
+end process;
+
+end Behavioral;
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+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:    12:33:39 10/08/05
+-- Design Name:    
+-- Module Name:    eval_synch_top - Behavioral
+-- Project Name:   
+-- Target Device:  
+-- Tool versions:  
+-- Description:
+--
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity eval_synch_top is
+	 Generic (N : integer := 8);
+    Port ( rst : in std_logic;
+           clk : in std_logic;
+           din : in std_logic;
+           dout : out std_logic_vector(0 to N-1));
+end eval_synch_top;
+
+architecture Behavioral of eval_synch_top is
+
+	COMPONENT d_ff
+	GENERIC(tpd : time);
+	PORT(
+		rst : IN std_logic;
+		clk : IN std_logic;
+		din : IN std_logic;          
+		dout : OUT std_logic
+		);
+	END COMPONENT;
+
+-------------------------------------------------
+signal d_i : std_logic_vector(0 to N);
+
+begin
+
+d_i(0) <= din;
+dout <= d_i(1 to N);
+
+inst_shift_reg : for i in 1 to N generate 
+
+		Inst_d_ff: d_ff 
+		GENERIC MAP(tpd => 2.5 ns)
+		PORT MAP(
+			rst => rst,
+			clk => clk,
+			din => d_i(i-1),
+			dout => d_i(i)
+		);
+
+end generate;
+
+end Behavioral;
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+
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:   13:42:54 10/08/2005
+-- Design Name:   eval_synch_top
+-- Module Name:   tb_eval_synch.vhd
+-- Project Name:  eval_sync
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+-- VHDL Test Bench Created by ISE for module: eval_synch_top
+--
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes: 
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
+-- that these types always be used for the top-level I/O of a design in order 
+-- to guarantee that the testbench will bind correctly to the post-implementation 
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE ieee.numeric_std.ALL;
+
+ENTITY tb_eval_synch_vhd IS
+END tb_eval_synch_vhd;
+
+ARCHITECTURE behavior OF tb_eval_synch_vhd IS 
+
+	-- Component Declaration for the Unit Under Test (UUT)
+	COMPONENT eval_synch_top
+	PORT(
+		rst : IN std_logic;
+		clk : IN std_logic;
+		din : IN std_logic;          
+		dout : OUT std_logic_vector(0 to 7)
+		);
+	END COMPONENT;
+
+	--Constants
+	constant PERIOD : time := 10 ns;
+
+	--Inputs
+	SIGNAL rst :  std_logic := '1';
+	SIGNAL clk :  std_logic := '0';
+	SIGNAL din :  std_logic := '0';
+
+	--Outputs
+	SIGNAL dout :  std_logic_vector(0 to 7);
+
+BEGIN
+
+	-- Instantiate the Unit Under Test (UUT)
+	uut: eval_synch_top PORT MAP(
+		rst => rst,
+		clk => clk,
+		din => din,
+		dout => dout
+	);
+
+ 	tb_clk : PROCESS
+	BEGIN
+		clk <= not clk;
+		wait for PERIOD/2;
+	END PROCESS;
+
+	tb : PROCESS
+	BEGIN
+
+		-- Wait 100 ns for global reset to finish
+		wait for 2*PERIOD;
+		rst <= '0';
+
+		wait for 1.0*PERIOD + 0 ns;
+		din <= '1';
+
+		wait for PERIOD;
+		din <= '0';
+
+		wait for PERIOD;
+		din <= '1';
+
+		wait for PERIOD;
+		din <= '1';
+
+		wait for PERIOD;
+		din <= '0';
+
+		-- Wait 100 ns for global reset to finish
+		wait for 100 ns;
+
+		-- Place stimulus here
+
+		wait; -- will wait forever
+	END PROCESS;
+
+END;