- added

git-svn-id: http://moon:8086/svn/vhdl/trunk@1429 cc03376c-175c-47c8-b038-4cd826a8556b
2021-03-21 12:04:37 +00:00
parent 9edf6a70af
commit 2f7ab91e0d
116 changed files with 50542 additions and 0 deletions
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+work
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+vhdl work "W:/vhdl/lib/src/fixed_ja/fixed_ja.vhd"
+vhdl work "W:/vhdl/projects/eval_fixed_ja/src/eval_fixed_ja_syn.vhd"
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+set -tmpdir ./xst/projnav.tmp
+set -xsthdpdir ./xst
+run
+-ifn eval_fixed_ja.prj
+-ifmt mixed
+-ofn eval_fixed_ja
+-ofmt NGC
+-p xc4vsx35-10-ff668
+-top eval_fixed_ja
+-opt_mode Speed
+-opt_level 1
+-iuc NO
+-lso eval_fixed_ja.lso
+-keep_hierarchy NO
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case maintain
+-slice_utilization_ratio 100
+-dsp_utilization_ratio 100
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style lut
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-mux_style Auto
+-decoder_extract YES
+-priority_extract YES
+-shreg_extract YES
+-shift_extract YES
+-xor_collapse YES
+-rom_style Auto
+-mux_extract YES
+-resource_sharing YES
+-use_dsp48 auto
+-iobuf YES
+-max_fanout 500
+-bufg 32
+-bufr 24
+-register_duplication YES
+-register_balancing No
+-slice_packing YES
+-optimize_primitives NO
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
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+## NOTE:  Do not edit this file.
+## Autogenerated by ProjNav (creatfdo.tcl) on Tue May 22 21:51:13 Westeuropäische Sommerzeit 2007
+##
+vlib work
+vcom -explicit  -93 "W:/vhdl/lib/src/fixed_ja/fixed_ja.vhd"
+vcom -explicit  -93 "W:/vhdl/lib/src/fixed_ja/fixed_ja_body.vhd"
+vcom -explicit  -93 "W:/vhdl/projects/eval_fixed_ja/src/eval_fixed_ja_syn.vhd"
+vcom -explicit  -93 "W:/vhdl/projects/eval_fixed_ja/src/tb_eval_fixed_ja_syn.vhd"
+vsim -t 1ps   -lib work tb_eval_fixed_ja_vhd
+do {tb_eval_fixed_ja_vhd.udo}
+view wave
+add wave *
+view structure
+view signals
+run 1000ns
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+-- ProjNav VHDL simulation template: tb_eval_fixed_ja_vhd.udo
+-- You may edit this file after the line that starts with
+-- '-- START' to customize your simulation
+-- START user-defined simulation commands