- added

git-svn-id: http://moon:8086/svn/vhdl/trunk@1429 cc03376c-175c-47c8-b038-4cd826a8556b
2021-03-21 12:04:37 +00:00
parent 9edf6a70af
commit 2f7ab91e0d
116 changed files with 50542 additions and 0 deletions
@@ -0,0 +1,50 @@
+# -------------------------------------------------
+# Global options
+# -------------------------------------------------
+LANG_STD := 93c
+IEEE_STD := standard
+WORK_PATH := work
+SOURCE_PATH := src
+LIB_PATH := ../lib
+
+# -------------------------------------------------
+# Target options
+# -------------------------------------------------
+TARGET := tb_eval_fixed_ja
+SOURCES := 
+
+# -------------------------------------------------
+GHDL_OPT := --workdir=$(WORK_PATH) --std=$(LANG_STD) --ieee=$(IEEE_STD)
+
+# -------------------------------------------------
+all: elaborate
+
+.PHONY: syntax
+syntax: 
+	ghdl -s $(GHDL_OPT) $(SOURCE_PATH)/*.vhd
+
+import:
+	ghdl -i $(GHDL_OPT) $(LIB_PATH)/*.vhd
+
+analyze: import
+	ghdl -a $(GHDL_OPT) $(LIB_PATH)/*.vhd $(SOURCE_PATH)/*.vhd
+
+anaborate: import
+	ghdl -c $(GHDL_OPT) $(LIB_PATH)/*.vhd $(SOURCE_PATH)/*.vhd -e $(TARGET)
+
+makeunit: import
+	ghdl -m $(GHDL_OPT) $(TARGET)
+
+elaborate: analyze
+	ghdl -e $(GHDL_OPT) $(TARGET)
+
+run: elaborate
+	ghdl -r $(GHDL_OPT) $(TARGET)
+
+# -------------------------------------------------
+.PHONY: clean
+clean:
+	rm -rf $(TARGET)
+	cd $(WORK_PATH); rm -rf *.o *.cf
+	
+# -------------------------------------------------
@@ -0,0 +1 @@
+work
@@ -0,0 +1,2 @@
+vhdl work "W:/vhdl/lib/src/fixed_ja/fixed_ja.vhd"
+vhdl work "W:/vhdl/projects/eval_fixed_ja/src/eval_fixed_ja_syn.vhd"
@@ -0,0 +1,55 @@
+set -tmpdir ./xst/projnav.tmp
+set -xsthdpdir ./xst
+run
+-ifn eval_fixed_ja.prj
+-ifmt mixed
+-ofn eval_fixed_ja
+-ofmt NGC
+-p xc4vsx35-10-ff668
+-top eval_fixed_ja
+-opt_mode Speed
+-opt_level 1
+-iuc NO
+-lso eval_fixed_ja.lso
+-keep_hierarchy NO
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case maintain
+-slice_utilization_ratio 100
+-dsp_utilization_ratio 100
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style lut
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-mux_style Auto
+-decoder_extract YES
+-priority_extract YES
+-shreg_extract YES
+-shift_extract YES
+-xor_collapse YES
+-rom_style Auto
+-mux_extract YES
+-resource_sharing YES
+-use_dsp48 auto
+-iobuf YES
+-max_fanout 500
+-bufg 32
+-bufr 24
+-register_duplication YES
+-register_balancing No
+-slice_packing YES
+-optimize_primitives NO
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
@@ -0,0 +1,15 @@
+## NOTE:  Do not edit this file.
+## Autogenerated by ProjNav (creatfdo.tcl) on Tue May 22 21:51:13 Westeuropäische Sommerzeit 2007
+##
+vlib work
+vcom -explicit  -93 "W:/vhdl/lib/src/fixed_ja/fixed_ja.vhd"
+vcom -explicit  -93 "W:/vhdl/lib/src/fixed_ja/fixed_ja_body.vhd"
+vcom -explicit  -93 "W:/vhdl/projects/eval_fixed_ja/src/eval_fixed_ja_syn.vhd"
+vcom -explicit  -93 "W:/vhdl/projects/eval_fixed_ja/src/tb_eval_fixed_ja_syn.vhd"
+vsim -t 1ps   -lib work tb_eval_fixed_ja_vhd
+do {tb_eval_fixed_ja_vhd.udo}
+view wave
+add wave *
+view structure
+view signals
+run 1000ns
@@ -0,0 +1,4 @@
+-- ProjNav VHDL simulation template: tb_eval_fixed_ja_vhd.udo
+-- You may edit this file after the line that starts with
+-- '-- START' to customize your simulation
+-- START user-defined simulation commands
@@ -0,0 +1 @@
+work
@@ -0,0 +1,2 @@
+vhdl ieee_proposed "C:/Programme/Xilinx9/vhdl/src/ieee_proposed/fixed_pkg_c.vhd"
+vhdl work "../src/eval_fixed_ja_syn.vhd"
@@ -0,0 +1,59 @@
+set -tmpdir "./xst/projnav.tmp"
+set -xsthdpdir "./xst"
+run
+-ifn eval_fixed_ja.prj
+-ifmt mixed
+-ofn eval_fixed_ja
+-ofmt NGC
+-p xc4vsx35-10-ff668
+-top eval_fixed_ja
+-opt_mode Speed
+-opt_level 1
+-power NO
+-iuc NO
+-lso eval_fixed_ja.lso
+-keep_hierarchy NO
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-dsp_utilization_ratio 100
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style lut
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-mux_style Auto
+-decoder_extract YES
+-priority_extract YES
+-shreg_extract YES
+-shift_extract YES
+-xor_collapse YES
+-rom_style Auto
+-auto_bram_packing NO
+-mux_extract YES
+-resource_sharing YES
+-async_to_sync NO
+-use_dsp48 auto
+-iobuf YES
+-max_fanout 500
+-bufg 32
+-bufr 24
+-register_duplication YES
+-register_balancing No
+-slice_packing YES
+-optimize_primitives NO
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
@@ -0,0 +1,2 @@
+vhdl ieee_proposed "C:\Programme\Xilinx9\vhdl\src\ieee_proposed\fixed_pkg_c.vhd"
+vhdl work "H:\vhdl\projects\eval_fixed_ja\src\eval_fixed_ja_syn.vhd"
@@ -0,0 +1,15 @@
+## NOTE:  Do not edit this file.
+## Autogenerated by ProjNav (creatfdo.tcl) on Thu May 24 11:58:33 Westeuropäische Normalzeit 2007
+##
+vlib work
+vlib ieee_proposed
+vcom -explicit  -93 -work ieee_proposed "C:/Programme/Xilinx9/vhdl/src/ieee_proposed/fixed_pkg_c.vhd"
+vcom -explicit  -93 "../src/eval_fixed_ja_syn.vhd"
+vcom -explicit  -93 "../src/tb_eval_fixed_ja_syn.vhd"
+vsim -t 1ps   -lib work tb_eval_fixed_ja_vhd
+view wave
+add wave *
+do {tb_eval_fixed_ja_vhd.udo}
+view structure
+view signals
+run 1000ns
@@ -0,0 +1,15 @@
+## NOTE: Do not edit this file.
+## Auto generated by Project Navigator for Post-Translate Simulation
+##
+vlib work
+## Compile Post-Translate Model
+vcom -explicit  -93 "netgen/translate/eval_fixed_ja_translate.vhd"
+vcom -explicit  -93 "../src/tb_eval_fixed_ja_syn.vhd"
+vsim -t 1ps  -lib work tb_eval_fixed_ja_vhd
+do {tb_eval_fixed_ja_vhd.udo}
+view wave
+add wave *
+view structure
+view signals
+run 1000ns
+## End
@@ -0,0 +1,4 @@
+-- ProjNav VHDL simulation template: tb_eval_fixed_ja_vhd.udo
+-- You may edit this file after the line that starts with
+-- '-- START' to customize your simulation
+-- START user-defined simulation commands
@@ -0,0 +1,12 @@
+vlib work
+vcom -explicit  -93 "../lib/fixed_ja.vhd"
+vcom -explicit  -93 "../lib/fixed_ja_body.vhd"
+vcom -explicit  -93 "../lib/PCK_FIO_1993.vhd"
+vcom -explicit  -93 "../lib/PCK_FIO_1993_BODY.vhd"
+vcom -explicit  -93 "src/tb_eval_fixed_ja.vhd"
+vsim -t 1ps   -lib work tb_eval_fixed_ja
+#do {wave.do}
+view wave
+view structure
+view signals
+run 1000ns
@@ -0,0 +1,107 @@
+## Generated SDC file "eval_fixed_ja.out.sdc"
+
+## Copyright (C) 1991-2008 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions 
+## and other software and tools, and its AMPP partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Altera Program License 
+## Subscription Agreement, Altera MegaCore Function License 
+## Agreement, or other applicable license agreement, including, 
+## without limitation, that your use is for the sole purpose of 
+## programming logic devices manufactured by Altera and sold by 
+## Altera or its authorized distributors.  Please refer to the 
+## applicable agreement for further details.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 8.1 Build 163 10/28/2008 SJ Web Edition"
+
+## DATE    "Thu Dec 18 22:26:14 2008"
+
+##
+## DEVICE  "EP3C25Q240C8"
+##
+
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {ccc} -period 10.000 -waveform { 0.000 5.000 } [get_ports {clk}]
+
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
@@ -0,0 +1,23 @@
+# Copyright (C) 1991-2008 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+
+
+QUARTUS_VERSION = "8.1"
+DATE = "10:27:40  December 18, 2008"
+
+
+# Revisions
+
+PROJECT_REVISION = "eval_fixed_ja"
@@ -0,0 +1,47 @@
+# Copyright (C) 1991-2008 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+
+# The default values for assignments are stored in the file
+#		eval_fixed_ja_assignment_defaults.qdf
+# If this file doesn't exist, and for assignments not listed, see file
+#		assignment_defaults.qdf
+
+# Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C25Q240C8
+set_global_assignment -name TOP_LEVEL_ENTITY eval_fixed_ja
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:27:40  DECEMBER 18, 2008"
+set_global_assignment -name LAST_QUARTUS_VERSION 8.1
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER clk -section_id clock
+set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON
+set_global_assignment -name SDC_FILE eval_fixed_ja.out.sdc
+set_global_assignment -name VHDL_FILE ../../../lib/fixed/fixed_pkg_c.vhd
+set_global_assignment -name VHDL_FILE ../src/eval_fixed_ja_syn.vhd
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
@@ -0,0 +1,29 @@
+[ProjectWorkspace]
+ptn_Child1=Frames
+[ProjectWorkspace.Frames]
+ptn_Child1=ChildFrames
+[ProjectWorkspace.Frames.ChildFrames]
+ptn_Child1=Document-0
+ptn_Child2=Document-1
+ptn_Child3=Document-2
+ptn_Child4=Document-3
+[ProjectWorkspace.Frames.ChildFrames.Document-2]
+ptn_Child1=ViewFrame-0
+[ProjectWorkspace.Frames.ChildFrames.Document-2.ViewFrame-0]
+DocPathName=eval_fixed_ja.sdc
+DocumentCLSID={c5dd978f-562d-48b1-a72f-0e9994df79df}
+IsChildFrameDetached=False
+IsActiveChildFrame=False
+ptn_Child1=StateMap
+[ProjectWorkspace.Frames.ChildFrames.Document-2.ViewFrame-0.StateMap]
+AFC_IN_REPORT=False
+[ProjectWorkspace.Frames.ChildFrames.Document-3]
+ptn_Child1=ViewFrame-0
+[ProjectWorkspace.Frames.ChildFrames.Document-3.ViewFrame-0]
+DocPathName=eval_fixed_ja.out.sdc
+DocumentCLSID={c5dd978f-562d-48b1-a72f-0e9994df79df}
+IsChildFrameDetached=False
+IsActiveChildFrame=False
+ptn_Child1=StateMap
+[ProjectWorkspace.Frames.ChildFrames.Document-3.ViewFrame-0.StateMap]
+AFC_IN_REPORT=False
@@ -0,0 +1,56 @@
+###########################################################################
+#
+# Generated by : Version 8.1 Build 163 10/28/2008 SJ Web Edition
+#
+# Project      : eval_fixed_ja
+# Revision     : eval_fixed_ja
+#
+# Date         : Thu Dec 18 22:17:10 Westeuropäische Normalzeit 2008
+#
+###########################################################################
+ 
+ 
+# WARNING: Expected ENABLE_CLOCK_LATENCY to be set to 'ON', but it is set to 'OFF'
+#          In SDC, create_generated_clock auto-generates clock latency
+#
+# ------------------------------------------
+#
+# Create generated clocks based on PLLs
+derive_pll_clocks -use_tan_name
+#
+# ------------------------------------------
+
+# ** Clock Latency
+#    -------------
+
+# ** Clock Uncertainty
+#    -----------------
+
+# ** Multicycles
+#    -----------
+# ** Cuts
+#    ----
+
+# ** Input/Output Delays
+#    -------------------
+
+
+
+
+# ** Tpd requirements
+#    ----------------
+
+# ** Setup/Hold Relationships
+#    ------------------------
+
+# ** Tsu/Th requirements
+#    -------------------
+
+
+# ** Tco/MinTco requirements
+#    -----------------------
+
+
+
+# ---------------------------------------------
+
@@ -0,0 +1,876 @@
+Fixed Point Library Testbench 0.1
+----------------------
+ Without saturation   
+----------------------
+
+* No rounding
+
+U: 101.0011 => 01.0011 ...passed
+U: 1.001101 => 001. ...passed
+U: 101.01 => 1.0 ...passed
+U: 1010.1 => 10. ...passed
+U: 101.11 => 101. ...passed
+U: .11 => 0. ...passed
+U: .1011 => 0.10 ...passed
+U: 0.0000000001 => 0. ...passed
+U: 1.0000000001 => 1.0 ...passed
+U: 1.0000000001 => 1. ...passed
+U: 10.000000001 => 10.000 ...passed
+U: 1. => 1.00000000000000000 ...passed
+U: 0. => 0.00000000000000000 ...passed
+U: 1. => .000000000000000000 ...passed
+U: 0. => .000000000000000000 ...passed
+U: 10.101 => 010.1010 ...passed
+U: 10.101 => 10.10 ...passed
+U: 10.101 => 10.1010 ...passed
+S: 101.0011 => 01.0011 ...passed
+S: -1.001101 => -001. ...passed
+S: -101.01 => -1.0 ...passed
+S: 1010.1 => 10. ...passed
+S: 101.11 => 101. ...passed
+S: -.11 => 0. ...passed
+S: -.1011 => -0.10 ...passed
+S: 0.0000000001 => 0. ...passed
+S: -1.0000000001 => -1.0 ...passed
+S: -1.0000000001 => -1. ...passed
+S: -10.000000001 => -10.000 ...passed
+S: 1. => 1.00000000000000000 ...passed
+S: 0. => 0.00000000000000000 ...passed
+S: 1. => .000000000000000000 ...passed
+S: 0. => .000000000000000000 ...passed
+S: 10.101 => 010.1010 ...passed
+S: -10.101 => -10.10 ...passed
+S: 10.101 => 10.1010 ...passed
+
+* Round to zero
+
+U: 101.0011 => 01.0011 ...passed
+U: 1.001101 => 001. ...passed
+U: 101.01 => 1.0 ...passed
+U: 1010.1 => 10. ...passed
+U: 101.11 => 101. ...passed
+U: .11 => 0. ...passed
+U: .1011 => 0.10 ...passed
+U: 0.0000000001 => 0. ...passed
+U: 1.0000000001 => 1.0 ...passed
+U: 1.0000000001 => 1. ...passed
+U: 10.000000001 => 10.000 ...passed
+U: 1. => 1.00000000000000000 ...passed
+U: 0. => 0.00000000000000000 ...passed
+U: 1. => .000000000000000000 ...passed
+U: 0. => .000000000000000000 ...passed
+U: 10.101 => 010.1010 ...passed
+U: 10.101 => 10.10 ...passed
+U: 10.101 => 10.1010 ...passed
+S: 101.0011 => 01.0011 ...passed
+S: -1.001101 => -001. ...passed
+S: -101.01 => -1.0 ...passed
+S: 1010.1 => 10. ...passed
+S: 101.11 => 101. ...passed
+S: -.11 => 0. ...passed
+S: -.1011 => -0.10 ...passed
+S: 0.0000000001 => 0. ...passed
+S: -1.0000000001 => -1.0 ...passed
+S: -1.0000000001 => -1. ...passed
+S: -10.000000001 => -10.000 ...passed
+S: 1. => 1.00000000000000000 ...passed
+S: 0. => 0.00000000000000000 ...passed
+S: 1. => .000000000000000000 ...passed
+S: 0. => .000000000000000000 ...passed
+S: 10.101 => 010.1010 ...passed
+S: -10.101 => -10.10 ...passed
+S: 10.101 => 10.1010 ...passed
+
+* Round to infinity
+
+U: 101.0011 => 01.0011 ...passed
+U: 1.001101 => 010. ...passed
+U: 101.01 => 1.1 ...passed
+U: 1010.1 => 11. ...passed
+U: 101.11 => 110. ...passed
+U: .11 => 1. ...passed
+U: .1011 => 0.11 ...passed
+U: 0.0000000001 => 1. ...passed
+U: 1.0000000001 => 1.1 ...passed
+U: 1.0000000001 => 0. ...passed
+U: 10.000000001 => 10.001 ...passed
+U: 1. => 1.00000000000000000 ...passed
+U: 0. => 0.00000000000000000 ...passed
+U: 1. => .000000000000000000 ...passed
+U: 0. => .000000000000000000 ...passed
+U: 10.101 => 010.1010 ...passed
+U: 10.101 => 10.11 ...passed
+U: 10.101 => 10.1010 ...passed
+S: 101.0011 => 01.0011 ...passed
+S: -10.001101 => -010. ...passed
+S: -101.01 => -1.0 ...passed
+S: 1010.1 => 11. ...passed
+S: 101.11 => 110. ...passed
+S: -.11 => 0. ...passed
+S: -.1011 => -0.10 ...passed
+S: 0.0000000001 => 1. ...passed
+S: -1.0000000001 => -1.0 ...passed
+S: 1.0000000001 => 0. ...passed
+S: -10.000000001 => -10.000 ...passed
+S: 1. => 1.00000000000000000 ...passed
+S: 0. => 0.00000000000000000 ...passed
+S: 1. => .000000000000000000 ...passed
+S: 0. => .000000000000000000 ...passed
+S: 10.101 => 010.1010 ...passed
+S: -10.101 => -10.10 ...passed
+S: 10.101 => 10.1010 ...passed
+
+* Round half up
+
+U: 101.0011 => 01.0011 ...passed
+U: 1.001101 => 001. ...passed
+U: 101.01 => 1.1 ...passed
+U: 1010.1 => 11. ...passed
+U: 101.11 => 110. ...passed
+U: .11 => 1. ...passed
+U: .1011 => 0.11 ...passed
+U: 0.0000000001 => 0. ...passed
+U: 1.0000000001 => 1.0 ...passed
+U: 1.0000000001 => 1. ...passed
+U: 10.000000001 => 10.000 ...passed
+U: 1. => 1.00000000000000000 ...passed
+U: 0. => 0.00000000000000000 ...passed
+U: 1. => .000000000000000000 ...passed
+U: 0. => .000000000000000000 ...passed
+U: 10.101 => 010.1010 ...passed
+U: 10.101 => 10.11 ...passed
+U: 10.101 => 10.1010 ...passed
+S: 101.0011 => 01.0011 ...passed
+S: -10.001101 => -010. ...passed
+S: -101.01 => -1.0 ...passed
+S: 1010.1 => 11. ...passed
+S: 101.11 => 110. ...passed
+S: -.11 => -1. ...passed
+S: -.1011 => -0.11 ...passed
+S: 0.0000000001 => 0. ...passed
+S: -1.0000000001 => -1.0 ...passed
+S: 1.0000000001 => 1. ...passed
+S: -10.000000001 => -10.000 ...passed
+S: 1. => 1.00000000000000000 ...passed
+S: 0. => 0.00000000000000000 ...passed
+S: 1. => .000000000000000000 ...passed
+S: 0. => .000000000000000000 ...passed
+S: 10.101 => 010.1010 ...passed
+S: -10.1011 => -10.11 ...passed
+S: -10.101 => -10.10 ...passed
+S: -0.1111 => -0.111 ...passed
+S: -0.11110 => -0.111 ...passed
+S: -0.11111 => -1.000 ...passed
+
+* Round convergent
+
+U: 01.001 => 01.00 ...passed
+U: 01.0010 => 01.00 ...passed
+U: 01.0011 => 01.01 ...passed
+U: 01.011 => 01.10 ...passed
+U: 01.0110 => 01.10 ...passed
+U: 01.0111 => 01.10 ...passed
+S: 01.001 => 01.00 ...passed
+S: 01.0010 => 01.00 ...passed
+S: 01.0011 => 01.01 ...passed
+S: 01.011 => 01.10 ...passed
+S: 01.0110 => 01.10 ...passed
+S: 01.0111 => 01.10 ...passed
+S: -01.001 => -01.00 ...passed
+S: -01.0010 => -01.00 ...passed
+S: -01.0011 => -01.01 ...passed
+S: -01.011 => -01.10 ...passed
+S: -01.0110 => -01.10 ...passed
+S: -01.0111 => -01.10 ...passed
+
+----------------------
+ With saturation      
+----------------------
+
+* No rounding
+
+U: 101.0011 => 11.1111 ...passed
+U: 1.001101 => 001. ...passed
+U: 101.01 => 1.1 ...passed
+U: 1010.1 => 11. ...passed
+U: 101.11 => 101. ...passed
+U: .11 => 0. ...passed
+U: .1011 => 0.10 ...passed
+U: 0.0000000001 => 0. ...passed
+U: 1.0000000001 => 1.0 ...passed
+U: 1.0000000001 => 1. ...passed
+U: 10.000000001 => 10.000 ...passed
+U: 1. => 1.00000000000000000 ...passed
+U: 0. => 0.00000000000000000 ...passed
+U: 1. => .111111111111111111 ...passed
+U: 0. => .000000000000000000 ...passed
+U: 10.101 => 010.1010 ...passed
+U: 10.101 => 10.10 ...passed
+U: 10.101 => 10.1010 ...passed
+U: 1.0000 => .11111 ...passed
+U: 01.000 => .11111 ...passed
+U: 11.000 => .11111 ...passed
+U: 0.1000 => .10000 ...passed
+U: 00.100 => .10000 ...passed
+U: 1.0001 => .11111 ...passed
+U: 01.001 => .11111 ...passed
+U: 01.010 => .11111 ...passed
+U: 11.001 => .11111 ...passed
+U: 0.1001 => .10010 ...passed
+U: 00.101 => .10100 ...passed
+U: 1.000000000000000001 => .111111111111111 ...passed
+U: 01.00000000000000001 => .111111111111111 ...passed
+U: 1.00000000000000 => .111111111111111 ...passed
+S: -101.0011 => -11.1111 ...passed
+S: 1.001101 => 001. ...passed
+S: 101.01 => 1.1 ...passed
+S: 1010.1 => 11. ...passed
+S: 101.11 => 101. ...passed
+S: .11 => 0. ...passed
+S: .1011 => 0.10 ...passed
+S: -0.0000000001 => 0. ...passed
+S: -1.0000000001 => -1.0 ...passed
+S: 1.0000000001 => 1. ...passed
+S: 10.000000001 => 10.000 ...passed
+S: 1. => 1.00000000000000000 ...passed
+S: 0. => 0.00000000000000000 ...passed
+S: -1. => -.111111111111111111 ...passed
+S: 0. => .000000000000000000 ...passed
+S: -10.101 => -010.1010 ...passed
+S: -10.101 => -10.10 ...passed
+S: -10.101 => -10.1010 ...passed
+S: -1.0000 => -.11111 ...passed
+S: -01.000 => -.11111 ...passed
+S: -11.000 => -.11111 ...passed
+S: -0.1000 => -.10000 ...passed
+S: -00.100 => -.10000 ...passed
+S: -1.0001 => -.11111 ...passed
+S: -01.001 => -.11111 ...passed
+S: -01.010 => -.11111 ...passed
+S: -11.001 => -.11111 ...passed
+S: -0.1001 => -.10010 ...passed
+S: -00.101 => -.10100 ...passed
+S: -1.000000000000000001 => -.111111111111111 ...passed
+S: -01.00000000000000001 => -.111111111111111 ...passed
+S: -1.00000000000000 => -.111111111111111 ...passed
+S: 1.000000000000000001 => .111111111111111 ...passed
+S: 01.00000000000000001 => .111111111111111 ...passed
+S: 1.00000000000000 => .111111111111111 ...passed
+S: 1.0000 => .11111 ...passed
+S: 01.000 => .11111 ...passed
+S: 0.1000 => .10000 ...passed
+S: 00.100 => .10000 ...passed
+
+* Round to zero
+
+U: 101.0011 => 11.1111 ...passed
+U: 1.001101 => 001. ...passed
+U: 101.01 => 1.1 ...passed
+U: 1010.1 => 11. ...passed
+U: 101.11 => 101. ...passed
+U: .11 => 0. ...passed
+U: .1011 => 0.10 ...passed
+U: 0.0000000001 => 0. ...passed
+U: 1.0000000001 => 1.0 ...passed
+U: 1.0000000001 => 1. ...passed
+U: 10.000000001 => 10.000 ...passed
+U: 1. => 1.00000000000000000 ...passed
+U: 0. => 0.00000000000000000 ...passed
+U: 1. => .111111111111111111 ...passed
+U: 0. => .000000000000000000 ...passed
+U: 10.101 => 010.1010 ...passed
+U: 10.101 => 10.10 ...passed
+U: 10.101 => 10.1010 ...passed
+U: 1.000000000000000001 => .111111111111111 ...passed
+U: 01.00000000000000001 => .111111111111111 ...passed
+U: 1.00000000000000 => .111111111111111 ...passed
+S: 101.0011 => 11.1111 ...passed
+S: 1.001101 => 001. ...passed
+S: 101.01 => 1.1 ...passed
+S: 1010.1 => 11. ...passed
+S: 101.11 => 101. ...passed
+S: .11 => 0. ...passed
+S: .1011 => 0.10 ...passed
+S: 0.0000000001 => 0. ...passed
+S: 1.0000000001 => 1.0 ...passed
+S: 1.0000000001 => 1. ...passed
+S: 10.000000001 => 10.000 ...passed
+S: 1. => 1.00000000000000000 ...passed
+S: 0. => 0.00000000000000000 ...passed
+S: 1. => .111111111111111111 ...passed
+S: 0. => .000000000000000000 ...passed
+S: 10.101 => 010.1010 ...passed
+S: 10.101 => 10.10 ...passed
+S: 10.101 => 10.1010 ...passed
+S: -1.000000000000000001 => -.111111111111111 ...passed
+S: -01.00000000000000001 => -.111111111111111 ...passed
+S: -1.00000000000000 => -.111111111111111 ...passed
+S: 1.000000000000000001 => .111111111111111 ...passed
+S: 01.00000000000000001 => .111111111111111 ...passed
+S: 1.00000000000000 => .111111111111111 ...passed
+S: 1.0000 => .11111 ...passed
+S: 01.000 => .11111 ...passed
+S: 0.1000 => .10000 ...passed
+S: 00.100 => .10000 ...passed
+
+* Round to infinity
+
+U: 101.0011 => 11.1111 ...passed
+U: 1.001101 => 010. ...passed
+U: 101.01 => 1.1 ...passed
+U: 1010.1 => 11. ...passed
+U: 101.11 => 110. ...passed
+U: .11 => 1. ...passed
+U: .1011 => 0.11 ...passed
+U: 0.0000000001 => 1. ...passed
+U: 1.0000000001 => 1.1 ...passed
+U: 1.0000000001 => 1. ...passed
+U: 10.000000001 => 10.001 ...passed
+U: 1. => 1.00000000000000000 ...passed
+U: 0. => 0.00000000000000000 ...passed
+U: 1. => .111111111111111111 ...passed
+U: 0. => .000000000000000000 ...passed
+U: 10.101 => 010.1010 ...passed
+U: 10.101 => 10.11 ...passed
+U: 10.101 => 10.1010 ...passed
+U: 1.000000000000000001 => .111111111111111 ...passed
+U: 01.00000000000000001 => .111111111111111 ...passed
+U: 1.00000000000000 => .111111111111111 ...passed
+S: 101.0011 => 11.1111 ...passed
+S: 1.001101 => 010. ...passed
+S: 101.01 => 1.1 ...passed
+S: 1010.1 => 11. ...passed
+S: 101.11 => 110. ...passed
+S: .11 => 1. ...passed
+S: .1011 => 0.11 ...passed
+S: 0.0000000001 => 1. ...passed
+S: 1.0000000001 => 1.1 ...passed
+S: 1.0000000001 => 1. ...passed
+S: 10.000000001 => 10.001 ...passed
+S: 1. => 1.00000000000000000 ...passed
+S: 0. => 0.00000000000000000 ...passed
+S: 1. => .111111111111111111 ...passed
+S: 0. => .000000000000000000 ...passed
+S: 10.101 => 010.1010 ...passed
+S: 10.101 => 10.11 ...passed
+S: 10.101 => 10.1010 ...passed
+S: -1.000000000000000001 => -.111111111111111 ...passed
+S: -01.00000000000000001 => -.111111111111111 ...passed
+S: -1.00000000000000 => -.111111111111111 ...passed
+S: 1.000000000000000001 => .111111111111111 ...passed
+S: 01.00000000000000001 => .111111111111111 ...passed
+S: 1.00000000000000 => .111111111111111 ...passed
+S: 1.0000 => .11111 ...passed
+S: 01.000 => .11111 ...passed
+S: 0.1000 => .10000 ...passed
+S: 00.100 => .10000 ...passed
+
+* Round half up
+
+U: 101.0011 => 11.1111 ...passed
+U: 1.001101 => 001. ...passed
+U: 101.01 => 1.1 ...passed
+U: 1010.1 => 11. ...passed
+U: 101.11 => 110. ...passed
+U: .11 => 1. ...passed
+U: .1011 => 0.11 ...passed
+U: 0.0000000001 => 0. ...passed
+U: 1.0000000001 => 1.0 ...passed
+U: 1.0000000001 => 1. ...passed
+U: 10.000000001 => 10.000 ...passed
+U: 1. => 1.00000000000000000 ...passed
+U: 0. => 0.00000000000000000 ...passed
+U: 1. => .111111111111111111 ...passed
+U: 0. => .000000000000000000 ...passed
+U: 10.101 => 010.1010 ...passed
+U: 10.101 => 10.11 ...passed
+U: 10.101 => 10.1010 ...passed
+U: 1.000000000000000001 => .111111111111111 ...passed
+U: 01.00000000000000001 => .111111111111111 ...passed
+U: 1.00000000000000 => .111111111111111 ...passed
+S: 101.0011 => 11.1111 ...passed
+S: 1.001101 => 001. ...passed
+S: 101.01 => 1.1 ...passed
+S: 1010.1 => 11. ...passed
+S: 101.11 => 110. ...passed
+S: -.11 => -1. ...passed
+S: -.1 => 0. ...passed
+S: .1011 => 0.11 ...passed
+S: 0.0000000001 => 0. ...passed
+S: 1.0000000001 => 1.0 ...passed
+S: 1.0000000001 => 1. ...passed
+S: 10.000000001 => 10.000 ...passed
+S: 1. => 1.00000000000000000 ...passed
+S: 0. => 0.00000000000000000 ...passed
+S: 1. => .111111111111111111 ...passed
+S: 0. => .000000000000000000 ...passed
+S: 10.101 => 010.1010 ...passed
+S: 10.101 => 10.11 ...passed
+S: 10.101 => 10.1010 ...passed
+S: -1.000000000000000000 => -.111111111111111 ...passed
+S: -1.000000000000000001 => -.111111111111111 ...passed
+S: -01.00000000000000000 => -.111111111111111 ...passed
+S: -01.00000000000000001 => -.111111111111111 ...passed
+S: -01.0000000000000 => -.111111111111111 ...passed
+S: -01.0000000000001 => -.111111111111111 ...passed
+S: -01.0000000000000 => -.11111111111111 ...passed
+S: -01.0000000000001 => -.11111111111111 ...passed
+S: -01.0000000000000 => -.1111111111111111 ...passed
+S: -01.0000000000001 => -.1111111111111111 ...passed
+S: -00.1111111111111 => -.111111111111100 ...passed
+S: -00.111111111111111 => -.11111111111111 ...passed
+S: -00.111111111111111 => -1.0000000000000 ...passed
+S: -1.000000000000000001 => -.111111111111111 ...passed
+S: -01.00000000000000001 => -.111111111111111 ...passed
+S: -1.0000000000000000001 => -.111111111111111 ...passed
+S: -01.000000000000000001 => -.111111111111111 ...passed
+S: -1.00000000000000000001 => -.111111111111111 ...passed
+S: -01.0000000000000000001 => -.111111111111111 ...passed
+S: -1.000000000000000000001 => -.111111111111111 ...passed
+S: -01.00000000000000000001 => -.111111111111111 ...passed
+S: -1.0000000000000000000001 => -.111111111111111 ...passed
+S: -01.000000000000000000001 => -.111111111111111 ...passed
+S: -1.000000000000000011 => -.111111111111111 ...passed
+S: -01.00000000000000011 => -.111111111111111 ...passed
+S: -1.0000000000000000011 => -.111111111111111 ...passed
+S: -01.000000000000000011 => -.111111111111111 ...passed
+S: -1.00000000000000000011 => -.111111111111111 ...passed
+S: -01.0000000000000000011 => -.111111111111111 ...passed
+S: -1.000000000000000000011 => -.111111111111111 ...passed
+S: -01.00000000000000000011 => -.111111111111111 ...passed
+S: -1.0000000000000000000011 => -.111111111111111 ...passed
+S: -01.000000000000000000011 => -.111111111111111 ...passed
+S: -1.00000000000000 => -.111111111111111 ...passed
+S: 1.0000 => .11111 ...passed
+S: 01.000 => .11111 ...passed
+S: 0.1000 => .10000 ...passed
+S: 00.100 => .10000 ...passed
+
+U: .10000000 + .01000000 = 0.11000000 ...passed
+U: .01100000 + .01000000 = 0.10100000 ...passed
+U: 0.0110000 - .01000000 = 0.00100000 ...passed
+U: .10000000 + .01000000 = 0.11000000 ...passed
+U: .10000000 - .01000000 = .01000000 ...passed
+U: .01000000 + .01000000 = 0.10000000 ...passed
+U: .01000000 - .01000000 = .00000000 ...passed
+U: .0100 + 000.01000 = 000.10000 ...passed
+U: 1.0000 + 1.0000 = 10.0000 ...passed
+U: 0.1001 + 0.0110 = 00.1111 ...passed
+U: 0.0011 + 0.0110 = 00.1001 ...passed
+U: 0.1111 + 1.0001 = 10.0000 ...passed
+U: 10.0000 - 1.0000 = 01.0000 ...passed
+U: 00.1111 - 0.1001 = 00.0110 ...passed
+U: 00.1001 - 0.0011 = 00.0110 ...passed
+U: 10.0000 - 0.1111 = 01.0001 ...passed
+U: .10000000 * 100.10000 = 10.01000000000000 ...passed
+U: .10000000 * .10000000 = .0100000000000000 ...passed
+U: 0.1000000 * .10000000 = .0100000000000000 ...passed
+U: 0.1000000 * 0.1000000 = 00.01000000000000 ...passed
+U: 0.1000000 * .10000000 = .0100000000000000 ...passed
+U: 00.100000 * 0.1000000 = 000.0100000000000 ...passed
+U: 01.1000000 * .10000000 = 0.1100000000000000 ...passed
+U: .10000000 * 01.1000000 = 0.1100000000000000 ...passed
+U: 01.100000 * .100000000 = 0.1100000000000000 ...passed
+U: .100000000 * 01.100000 = 0.1100000000000000 ...passed
+S: .011 + .0100000 = 0.1010000 ...passed
+S: .0110000 - .0100000 = .0010000 ...passed
+S: .1000000 + .0100000 = 0.1100000 ...passed
+S: .1000000 - .0100000 = .0100000 ...passed
+S: .0100000 + .0100000 = 0.1000000 ...passed
+S: .0100000 - .0100000 = .0000000 ...passed
+S: .010 + 000.0100 = 000.1000 ...passed
+S: -.100 * 100.1000 = -10.010000000 ...passed
+S: -.1000000 * .1000000 = -.010000000000000 ...passed
+S: -0.100000 * .1000000 = -.010000000000000 ...passed
+S: -0.100000 * 0.100000 = -00.0100000000000 ...passed
+S: .100 * 100.1000 = 10.010000000 ...passed
+S: .1000000 * .1000000 = .010000000000000 ...passed
+S: 0.100000 * .1000000 = .010000000000000 ...passed
+S: 0.100000 * 0.100000 = 00.0100000000000 ...passed
+----------------------
+ Arithmetic Test      
+----------------------
+Test finished
+
+
+Positive ufixed
+1.000 sla 0 = 1.000
+1.000 sla 1 = 0.000
+1.000 sla 2 = 0.000
+1.000 sla 3 = 0.000
+1.000 sla 4 = 0.000
+
+1.000 sla 0 = 1.000
+1.000 sla -1 = 0.100
+1.000 sla -2 = 0.010
+1.000 sla -3 = 0.001
+1.000 sla -4 = 0.000
+
+1.000 sra 0 = 1.000
+1.000 sra 1 = 0.100
+1.000 sra 2 = 0.010
+1.000 sra 3 = 0.001
+1.000 sra 4 = 0.000
+
+1.000 sra 0 = 1.000
+1.000 sra -1 = 0.000
+1.000 sra -2 = 0.000
+1.000 sra -3 = 0.000
+1.000 sra -4 = 0.000
+
+Positive sfixed
+1.000 sla 0 = 1.000
+1.000 sla 1 = 0.000
+1.000 sla 2 = 0.000
+1.000 sla 3 = 0.000
+1.000 sla 4 = 0.000
+1.000 sla 5 = 0.000
+
+1.000 sla 0 = 1.000
+1.000 sla -1 = 0.100
+1.000 sla -2 = 0.010
+1.000 sla -3 = 0.001
+1.000 sla -4 = 0.000
+1.000 sla -5 = 0.000
+
+1.000 sra 0 = 1.000
+1.000 sra 1 = 0.100
+1.000 sra 2 = 0.010
+1.000 sra 3 = 0.001
+1.000 sra 4 = 0.000
+1.000 sra 5 = 0.000
+
+1.000 sra 0 = 1.000
+1.000 sra -1 = 0.000
+1.000 sra -2 = 0.000
+1.000 sra -3 = 0.000
+1.000 sra -4 = 0.000
+1.000 sra -5 = 0.000
+
+Negative sfixed
+-1.000 sla 0 = -1.000
+-1.000 sla 1 = -0.000
+-1.000 sla 2 = -0.000
+-1.000 sla 3 = -0.000
+-1.000 sla 4 = 0.000
+-1.000 sla 5 = 0.000
+
+-1.000 sla 0 = -1.000
+-1.000 sla -1 = -0.100
+-1.000 sla -2 = -0.010
+-1.000 sla -3 = -0.001
+-1.000 sla -4 = 0.000
+-1.000 sla -5 = 0.000
+
+-1.000 sra 0 = -1.000
+-1.000 sra 1 = -0.100
+-1.000 sra 2 = -0.010
+-1.000 sra 3 = -0.001
+-1.000 sra 4 = 0.000
+-1.000 sra 5 = 0.000
+
+-1.000 sra 0 = -1.000
+-1.000 sra -1 = -0.000
+-1.000 sra -2 = -0.000
+-1.000 sra -3 = -0.000
+-1.000 sra -4 = 0.000
+-1.000 sra -5 = 0.000
+
+Positive ufixed
+1.001 sla 0 = 1.001
+1.001 sla 1 = 0.010
+1.001 sla 2 = 0.100
+1.001 sla 3 = 1.000
+1.001 sla 4 = 0.000
+
+1.001 sla 0 = 1.001
+1.001 sla -1 = 0.100
+1.001 sla -2 = 0.010
+1.001 sla -3 = 0.001
+1.001 sla -4 = 0.000
+
+1.001 sra 0 = 1.001
+1.001 sra 1 = 0.100
+1.001 sra 2 = 0.010
+1.001 sra 3 = 0.001
+1.001 sra 4 = 0.000
+
+1.001 sra 0 = 1.001
+1.001 sra -1 = 0.010
+1.001 sra -2 = 0.100
+1.001 sra -3 = 1.000
+1.001 sra -4 = 0.000
+
+Positive sfixed
+1.001 sla 0 = 1.001
+1.001 sla 1 = 0.010
+1.001 sla 2 = 0.100
+1.001 sla 3 = 1.000
+1.001 sla 4 = 0.000
+1.001 sla 5 = 0.000
+
+1.001 sla 0 = 1.001
+1.001 sla -1 = 0.100
+1.001 sla -2 = 0.010
+1.001 sla -3 = 0.001
+1.001 sla -4 = 0.000
+1.001 sla -5 = 0.000
+
+1.001 sra 0 = 1.001
+1.001 sra 1 = 0.100
+1.001 sra 2 = 0.010
+1.001 sra 3 = 0.001
+1.001 sra 4 = 0.000
+1.001 sra 5 = 0.000
+
+1.001 sra 0 = 1.001
+1.001 sra -1 = 0.010
+1.001 sra -2 = 0.100
+1.001 sra -3 = 1.000
+1.001 sra -4 = 0.000
+1.001 sra -5 = 0.000
+
+Negative sfixed
+-1.001 sla 0 = -1.001
+-1.001 sla 1 = -0.010
+-1.001 sla 2 = -0.100
+-1.001 sla 3 = -1.000
+-1.001 sla 4 = 0.000
+-1.001 sla 5 = 0.000
+
+-1.001 sla 0 = -1.001
+-1.001 sla -1 = -0.100
+-1.001 sla -2 = -0.010
+-1.001 sla -3 = -0.001
+-1.001 sla -4 = 0.000
+-1.001 sla -5 = 0.000
+
+-1.001 sra 0 = -1.001
+-1.001 sra 1 = -0.100
+-1.001 sra 2 = -0.010
+-1.001 sra 3 = -0.001
+-1.001 sra 4 = 0.000
+-1.001 sra 5 = 0.000
+
+-1.001 sra 0 = -1.001
+-1.001 sra -1 = -0.010
+-1.001 sra -2 = -0.100
+-1.001 sra -3 = -1.000
+-1.001 sra -4 = 0.000
+-1.001 sra -5 = 0.000
+Positive ufixed
+U'length     = 10
+U'high(left) = -1(-1)
+U'low(right) = -10(-10)
+U'value      = B.0100000000
+U'value      = 2.5e-1
+
+U'length     = 10
+U'high(left) = -1(-1)
+U'low(right) = -10(-10)
+U'value      = B.0100000000
+U'value      = 2.5e-1
+
+U'length     = 10
+U'high(left) = -1(-1)
+U'low(right) = -10(-10)
+U'value      = B.0100000000
+U'value      = 2.5e-1
+
+U'length     = 10
+U'high(left) = 1(1)
+U'low(right) = -8(-8)
+U'value      = B00.01000000
+U'value      = 2.5e-1
+
+U'length     = 10
+U'high(left) = 0(0)
+U'low(right) = -9(-9)
+U'value      = B0.010000000
+U'value      = 2.5e-1
+
+U'length     = 10
+U'high(left) = 0(0)
+U'low(right) = -9(-9)
+U'value      = B0.010000000
+U'value      = 2.5e-1
+
+Positive sfixed
+S'length     = 10
+S'high(left) = 0(0)
+S'low(right) = -9(-9)
+S'value      = B.010000000
+S'value      = 2.5e-1
+
+S'length     = 10
+S'high(left) = 0(0)
+S'low(right) = -9(-9)
+S'value      = B.010000000
+S'value      = 2.5e-1
+
+S'length     = 10
+S'high(left) = 0(0)
+S'low(right) = -9(-9)
+S'value      = B.010000000
+S'value      = 2.5e-1
+
+S'length     = 10
+S'high(left) = 2(2)
+S'low(right) = -7(-7)
+S'value      = B00.0100000
+S'value      = 2.5e-1
+
+S'length     = 10
+S'high(left) = 1(1)
+S'low(right) = -8(-8)
+S'value      = B0.01000000
+S'value      = 2.5e-1
+
+S'length     = 10
+S'high(left) = 1(1)
+S'low(right) = -8(-8)
+S'value      = B0.01000000
+S'value      = 2.5e-1
+
+Neg/Pos sfixed
+S'length     = 10
+S'high(left) = 0(0)
+S'low(right) = -9(-9)
+S'value      = B-.010000000
+S'value      = -2.5e-1
+
+S'length     = 10
+S'high(left) = 0(0)
+S'low(right) = -9(-9)
+S'value      = B-.010000000
+S'value      = -2.5e-1
+
+S'length     = 10
+S'high(left) = 0(0)
+S'low(right) = -9(-9)
+S'value      = B-.010000000
+S'value      = -2.5e-1
+
+S'length     = 10
+S'high(left) = 2(2)
+S'low(right) = -7(-7)
+S'value      = B-00.0100000
+S'value      = -2.5e-1
+
+S'length     = 10
+S'high(left) = 1(1)
+S'low(right) = -8(-8)
+S'value      = B-0.01000000
+S'value      = -2.5e-1
+
+S'length     = 10
+S'high(left) = 1(1)
+S'low(right) = -8(-8)
+S'value      = B-0.01000000
+S'value      = -2.5e-1
+
+Pos/Neg sfixed
+S'length     = 10
+S'high(left) = 0(0)
+S'low(right) = -9(-9)
+S'value      = B-.010000000
+S'value      = -2.5e-1
+
+S'length     = 10
+S'high(left) = 0(0)
+S'low(right) = -9(-9)
+S'value      = B-.010000000
+S'value      = -2.5e-1
+
+S'length     = 10
+S'high(left) = 0(0)
+S'low(right) = -9(-9)
+S'value      = B-.010000000
+S'value      = -2.5e-1
+
+S'length     = 10
+S'high(left) = 2(2)
+S'low(right) = -7(-7)
+S'value      = B-00.0100000
+S'value      = -2.5e-1
+
+S'length     = 10
+S'high(left) = 1(1)
+S'low(right) = -8(-8)
+S'value      = B-0.01000000
+S'value      = -2.5e-1
+
+S'length     = 10
+S'high(left) = 1(1)
+S'low(right) = -8(-8)
+S'value      = B-0.01000000
+S'value      = -2.5e-1
+
+Neg/Neg sfixed
+S'length     = 10
+S'high(left) = 0(0)
+S'low(right) = -9(-9)
+S'value      = B.010000000
+S'value      = 2.5e-1
+
+S'length     = 10
+S'high(left) = 0(0)
+S'low(right) = -9(-9)
+S'value      = B.010000000
+S'value      = 2.5e-1
+
+S'length     = 10
+S'high(left) = 0(0)
+S'low(right) = -9(-9)
+S'value      = B.010000000
+S'value      = 2.5e-1
+
+S'length     = 10
+S'high(left) = 2(2)
+S'low(right) = -7(-7)
+S'value      = B00.0100000
+S'value      = 2.5e-1
+
+S'length     = 10
+S'high(left) = 1(1)
+S'low(right) = -8(-8)
+S'value      = B0.01000000
+S'value      = 2.5e-1
+
+S'length     = 10
+S'high(left) = 1(1)
+S'low(right) = -8(-8)
+S'value      = B0.01000000
+S'value      = 2.5e-1
+
+Test 1.1001000:
+Test 1.100100:
+Test -1.100100:
+Test 00.011001:
+Test 00.01100:
+Test -00.01100:
+Integer Test 00.00000:
+R: Bit 11.110010:
+U: Bit 11.110010:
+S: Bit 11.110010:
+S: Bit 00.001110:
+S: Bit 3.50:
+S: Bit -242:
+S1'length     = 130
+S1'high(left) = 13(13)
+S1'low(right) = -116(-116)
+S1'value      = B0111101010101.01100010110111010011100101101101011111010101101000110100101010101010111011010000111011000110000101000001010010100111
+S1'value      = 3.925386188115339e3
+
+S2'length     = 130
+S2'high(left) = 13(13)
+S2'low(right) = -116(-116)
+S2'value      = B0010110111011.11100001100111000100101000110101111111101101000100001110010011100111000110110110010100101001010010100111100011000010
+S2'value      = 1.467881291044409e3
+
+R1'length     = 260
+R1'high(left) = 26(26)
+R1'low(right) = -233(-233)
+R1'value      = B00010101111110101111010000.11110010000101101010111100111010001101011101111110010111000100110100001101100001011110100000111111111110100001011011101000011010000101001110100001100100111111111100101000111011011011111100111000001011001111000010101111101110100011100
+R1'value      = 5.762000945658637e6
+
@@ -0,0 +1,89 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date:    00:28:57 07/10/2006 
+-- Design Name: 
+-- Module Name:    adder_registered - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+use IEEE.MATH_REAL.ALL;
+use std.textio.all; --  Imports the standard textio package.
+
+library work;
+use work.fixed_ja.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity eval_fixed_ja is
+	Generic (
+	        nbits : integer := 32;
+	        nbits_int : integer := 2);
+end eval_fixed_ja;
+
+architecture Behavioral of eval_fixed_ja is
+---------------------------------------------------------------------
+
+type my_range is range 0 downto -10;
+
+begin
+
+process
+constant c1 : ufixed_t (0 downto -10) := "11111111000";
+constant c2 : ufixed_t := to_ufixed(3.141592654, nbits, 4);
+constant c3 : ufixed_t := to_ufixed(1.0/3.141592654, nbits, 1);
+variable t1 : ufixed_t (uproto(8,1)'range);
+variable L : line;
+
+variable slv : string (15 downto 1) := (others => '-');
+constant jens : string (10 downto 7) := "JENS";
+
+
+begin
+
+
+--  slv := (1 => '1', 2 => 'J', jens'range => jens(jens'range), others => '1');
+  
+  slv(jens'range) := "Jens";
+  slv(jens'range) := jens;
+  
+  print_info(c2, "c2");
+  print_info(c3, "c3");
+  
+  t1 := to_ufixed(c1, t1, round_to_zero, saturate);
+  print_info(c1, "c1");
+  print_info(t1, "t1");
+  
+  t1 := to_ufixed(c1, t1, round_half_up, saturate);
+  print_info(c1, "c1");
+  print_info(t1, "t1");
+
+  print_info(to_ufixed(c2*c2, 32, 2, none, saturate), "c2*c2");
+  print_info(to_ufixed(c2*c3, 32, 0, round_half_up, none), "c2*c3");
+
+  write (L, slv);
+  writeline (output, L);
+  
+  wait;
+end process;
+
+---------------------------------------------------------------------
+end Behavioral;
+
@@ -0,0 +1,80 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date:    00:28:57 07/10/2006 
+-- Design Name: 
+-- Module Name:    adder_registered - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library ieee_proposed;
+use ieee_proposed.fixed_pkg.all;
+use std.textio.all; --  Imports the standard textio package.
+
+library work;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity eval_fixed_ja is
+	Generic (
+	        nbits : integer := 8;
+	        nbits_int : integer := 0
+			  );
+	Port
+	(
+		srst			: in std_logic;
+		clk			: in std_logic;
+		di1			: in std_logic_vector(nbits-1 downto 0);
+		di2			: in std_logic_vector(nbits-1 downto 0);
+		in_valid		: in std_logic;
+		do				: out std_logic_vector(nbits-1 downto 0);
+		out_valid	: out std_logic
+	);
+			  
+end eval_fixed_ja;
+
+architecture Behavioral of eval_fixed_ja is
+signal op1, op2 : sfixed(nbits_int downto -(nbits-1));
+signal result : sfixed(2*nbits_int downto -(2*nbits-1));
+begin
+
+op1 <= to_sfixed(di1, op1);
+op2 <= to_sfixed(di2, op2);
+
+do <= to_slv(resize(result, op1, false, false));
+
+---------------------------------------------------------------------
+process(srst, clk, in_valid, di1, di2)
+begin
+	if rising_edge(clk) then
+		if srst = '1' then
+			result <= (others => '0');
+		elsif in_valid = '1' then
+			result <= op1 * op2;
+		end if;
+		out_valid <= in_valid;
+	end if;	
+end process;
+
+
+---------------------------------------------------------------------
+end Behavioral;
+
@@ -0,0 +1,104 @@
+
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:   20:01:25 05/22/2007
+-- Design Name:   eval_fixed_ja
+-- Module Name:   H:/vhdl/projects/eval_fixed_ja/ise/tb_eval_fixed_ja.vhd
+-- Project Name:  eval_fixed
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+-- VHDL Test Bench Created by ISE for module: eval_fixed_ja
+--
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes: 
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
+-- that these types always be used for the top-level I/O of a design in order 
+-- to guarantee that the testbench will bind correctly to the post-implementation 
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE ieee.numeric_std.ALL;
+
+ENTITY tb_eval_fixed_ja_vhd IS
+END tb_eval_fixed_ja_vhd;
+
+ARCHITECTURE behavior OF tb_eval_fixed_ja_vhd IS 
+
+	-- Component Declaration for the Unit Under Test (UUT)
+	COMPONENT eval_fixed_ja
+	PORT(
+		srst : IN std_logic;
+		clk : IN std_logic;
+		di1 : IN std_logic_vector(7 downto 0);
+		di2 : IN std_logic_vector(7 downto 0);
+		in_valid : IN std_logic;          
+		do : OUT std_logic_vector(7 downto 0);
+		out_valid : OUT std_logic
+		);
+	END COMPONENT;
+
+	--Inputs
+	SIGNAL srst :  std_logic := '1';
+	SIGNAL clk :  std_logic := '0';
+	SIGNAL in_valid :  std_logic := '0';
+	SIGNAL di1 :  std_logic_vector(7 downto 0) := (others=>'0');
+	SIGNAL di2 :  std_logic_vector(7 downto 0) := (others=>'0');
+
+	--Outputs
+	SIGNAL do :  std_logic_vector(7 downto 0);
+	SIGNAL out_valid :  std_logic;
+
+BEGIN
+
+	-- Instantiate the Unit Under Test (UUT)
+	uut: eval_fixed_ja PORT MAP(
+		srst => srst,
+		clk => clk,
+		di1 => di1,
+		di2 => di2,
+		in_valid => in_valid,
+		do => do,
+		out_valid => out_valid
+	);
+
+	clk_gen : PROCESS
+	BEGIN
+		wait for 10 ns;
+		clk <= not clk;
+	END PROCESS;	
+
+	tb : PROCESS
+	BEGIN
+
+		-- Wait 100 ns for global reset to finish
+		wait for 100 ns;
+		srst <= '0';
+		di1 <= X"40";
+		di2 <= X"20";
+		
+		wait for 20 ns;
+		wait until rising_edge(clk);
+		in_valid <= '1';
+		wait until rising_edge(clk);
+		in_valid <= '0';
+		wait for 20 ns;
+		
+
+		-- Place stimulus here
+
+		wait; -- will wait forever
+	END PROCESS;
+
+END;
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@@ -0,0 +1,12 @@
+vlib work
+vcom -explicit  -93 "../../lib/src/fixed_ja/fixed_ja.vhd"
+vcom -explicit  -93 "../../lib/src/fixed_ja/fixed_ja_body.vhd"
+vcom -explicit  -93 "../../lib/src/PCK_FIO-2002.7/PCK_FIO_1993.vhd"
+vcom -explicit  -93 "../../lib/src/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
+vcom -explicit  -93 "src/tb_eval_fixed_ja.vhd"
+vsim -t 1ps   -lib work tb_eval_fixed_ja
+#do {wave.do}
+view wave
+view structure
+view signals
+run 1000ns
@@ -0,0 +1,14 @@
+% Read data
+[xu,yu] = TEXTREAD('sum_test_u.txt');
+[xs,ys] = TEXTREAD('sum_test_s.txt');
+
+
+close all;
+
+plot(0:length(xu)-1, xu, 0:length(yu)-1, yu);
+grid;
+
+figure;
+
+plot(0:length(xs)-1, xs, 0:length(ys)-1, ys);
+grid;