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git-svn-id: http://moon:8086/svn/vhdl/trunk@1429 cc03376c-175c-47c8-b038-4cd826a8556b
2021-03-21 12:04:37 +00:00
parent 9edf6a70af
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+
+-- VHDL Test Bench Created from source file main_top.vhd -- 00:26:28 06/02/2004
+--
+-- Notes: 
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
+-- that these types always be used for the top-level I/O of a design in order 
+-- to guarantee that the testbench will bind correctly to the post-implementation 
+-- simulation model.
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY main_top_main_top_tb_vhd_tb IS
+END main_top_main_top_tb_vhd_tb;
+
+ARCHITECTURE behavior OF main_top_main_top_tb_vhd_tb IS 
+
+	COMPONENT main_top
+	PORT(
+		clk : IN std_logic;
+		resn : IN std_logic;
+		a : IN std_logic_vector(31 downto 0);
+		wen : IN std_logic;
+		csn : IN std_logic;       
+		d : INOUT std_logic_vector(31 downto 0)
+		);
+	END COMPONENT;
+
+	SIGNAL clk :  std_logic;
+	SIGNAL resn :  std_logic;
+	SIGNAL a :  std_logic_vector(31 downto 0);
+	SIGNAL d :  std_logic_vector(31 downto 0);
+	SIGNAL wen :  std_logic;
+	SIGNAL csn :  std_logic;
+
+	constant ClockPeriod : Time := 25 ns;
+
+BEGIN
+
+	uut: main_top PORT MAP(
+		clk => clk,
+		resn => resn,
+		a => a,
+		d => d,
+		wen => wen,
+		csn => csn
+	);
+
+
+	clockgen: process
+	begin
+		clk <= '1';
+		loop
+			wait for (ClockPeriod / 2);
+			clk <= not clk;
+		end loop;  
+	end process;
+
+-- *** Test Bench - User Defined Section ***
+   tb : PROCESS
+   BEGIN
+      wait for 8*ClockPeriod;
+		
+		resn <= '1';
+		wait for 4*ClockPeriod;
+      
+		wen <= '0';
+		
+		a <= X"00000000";
+		wait for 1*ClockPeriod;
+		d <= X"AAAAAAAA";
+		csn <= '0';
+		wait for 1*ClockPeriod;
+		csn <= '1';
+			   
+		a <= X"00000010";
+		wait for 1*ClockPeriod;
+		d <= X"BBBBBBBB";
+		csn <= '0';
+		wait for 1*ClockPeriod;
+		csn <= '1';
+
+		a <= X"00000020";
+		wait for 1*ClockPeriod;
+		d <= X"CCCCCCCC";
+		csn <= '0';
+		wait for 1*ClockPeriod;
+		csn <= '1';
+
+		a <= X"00000030";
+		wait for 1*ClockPeriod;
+		d <= X"DDDDDDDD";
+		csn <= '0';
+		wait for 1*ClockPeriod;
+		csn <= '1';
+
+		wait for 8*ClockPeriod;
+		wen <= '1';
+		
+		a <= X"00000000";
+		wait for 1*ClockPeriod;
+		d <= (31 downto 0 => 'Z');
+		csn <= '0';
+		wait for 1*ClockPeriod;
+		csn <= '1';
+			   
+		a <= X"00000010";
+		wait for 1*ClockPeriod;
+		d <= (31 downto 0 => 'Z');
+		csn <= '0';
+		wait for 1*ClockPeriod;
+		csn <= '1';
+
+		a <= X"00000020";
+		wait for 1*ClockPeriod;
+		d <= (31 downto 0 => 'Z');
+		csn <= '0';
+		wait for 1*ClockPeriod;
+		csn <= '1';
+
+		a <= X"00000030";
+		wait for 1*ClockPeriod;
+		d <= (31 downto 0 => 'Z');
+		csn <= '0';
+		wait for 1*ClockPeriod;
+		csn <= '1';
+
+      wait; -- will wait forever
+    END PROCESS;
+-- *** End Test Bench - User Defined Section ***
+
+END;