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git-svn-id: http://moon:8086/svn/vhdl/trunk@1429 cc03376c-175c-47c8-b038-4cd826a8556b
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work
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vhdl work "main_top.vhdl"
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- Uncomment the following lines to use the declarations that are
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-- provided for instantiating Xilinx primitive components.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity main_top is
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Port ( clk : in std_logic;
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resn : in std_logic;
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a : in std_logic_vector(31 downto 0);
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d : inout std_logic_vector(31 downto 0);
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wen : in std_logic;
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csn : in std_logic);
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end main_top;
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architecture Behavioral of main_top is
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type t_reg is array (31 downto 0) of std_logic ;
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signal reg_a, reg_b, reg_c : t_reg;
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signal cs_a, cs_b, cs_c, CI, CO : std_logic;
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signal dmuxo : std_logic_vector(31 downto 0);
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signal mux_ctrl : std_logic_vector (3 downto 0);
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signal AA,BB,S31: std_logic_vector(32-1 downto 0);
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signal sum : std_logic_vector(32 downto 0);
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signal zeros: std_logic_vector(32-1 downto 0) := (others => '0');
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begin
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mux_ctrl <= a(7 downto 4);
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dmuxo <= std_logic_vector(reg_a) when (mux_ctrl = X"0") else
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std_logic_vector(reg_b) when (mux_ctrl = X"1") else
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std_logic_vector(reg_c) when (mux_ctrl = X"2") else
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X"12345678";
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cs_a <= '1' when (mux_ctrl = X"0" and csn = '0') else '0';
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cs_b <= '1' when (mux_ctrl = X"1" and csn = '0') else '0';
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cs_c <= '1' when (mux_ctrl = X"2" and csn = '0') else '0';
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CI <= wen;
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AA <= dmuxo when (wen = '1' and csn = '0') else (31 downto 0 => 'Z');
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BB <=a;
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d <= S31;
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write_reg_a: process (clk, wen, cs_a, d)
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begin
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if clk'event and clk = '0' then
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if (wen = '0' and cs_a = '1') then
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reg_a <= t_reg(d);
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end if;
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end if;
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end process;
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write_reg_b: process (clk, wen, cs_b, d)
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begin
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if clk'event and clk = '0' then
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if (wen = '0' and cs_b = '1') then
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reg_b <= t_reg(d);
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end if;
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end if;
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end process;
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write_reg_c: process (clk, wen, cs_c, d)
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begin
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if clk'event and clk = '0' then
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if (wen = '0' and cs_c = '1') then
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reg_c <= t_reg(d);
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end if;
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end if;
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end process;
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process (CI, AA, BB, sum)
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begin
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sum <= ('0' & AA) + ('0' & BB) + (zeros & CI);
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S31 <= sum(32-1 downto 0);
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CO <= sum(32);
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end process;
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end Behavioral;
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set -tmpdir ./xst/projnav.tmp
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set -xsthdpdir ./xst
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run
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-ifn main_top.prj
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-ifmt mixed
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-ofn main_top
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-ofmt NGC
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-p xc3s50-5-tq144
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-top main_top
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-opt_mode Speed
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-opt_level 1
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-iuc NO
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-lso main_top.lso
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-keep_hierarchy NO
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-rtlview Yes
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-glob_opt AllClockNets
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-read_cores YES
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-write_timing_constraints NO
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-cross_clock_analysis NO
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-hierarchy_separator _
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-bus_delimiter <>
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-case maintain
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-slice_utilization_ratio 100
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-verilog2001 YES
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-fsm_extract YES -fsm_encoding Auto
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-safe_implementation No
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-fsm_style lut
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-ram_extract Yes
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-ram_style Auto
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-rom_extract Yes
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-mux_style Auto
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-decoder_extract YES
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-priority_extract YES
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-shreg_extract YES
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-shift_extract YES
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-xor_collapse YES
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-rom_style Auto
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-mux_extract YES
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-resource_sharing YES
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-mult_style auto
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-iobuf YES
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-max_fanout 500
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-bufg 8
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-register_duplication YES
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-register_balancing No
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-slice_packing YES
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-optimize_primitives NO
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-use_clock_enable Yes
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-use_sync_set Yes
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-use_sync_reset Yes
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-iob auto
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-equivalent_register_removal YES
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-slice_utilization_ratio_maxmargin 5
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## NOTE: Do not edit this file.
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## Autogenerated by ProjNav (creatfdo.tcl) on Wed Jun 02 00:28:35 Westeuropäische Sommerzeit 2004
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##
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vlib work
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vcom -93 -explicit main_top.vhdl
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vcom -93 -explicit main_top_tb.vhd
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vsim -t 1ps -lib work main_top_main_top_tb_vhd_tb
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do main_top_main_top_tb_vhd_tb.udo
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view wave
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add wave *
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view structure
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view signals
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run 1000ns
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## NOTE: Do not edit this file.
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## Auto generated by Project Navigator for VHDL Post-Translate Simulation
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##
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vlib work
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## Compile Post-Translate Model for Module main_top
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vcom -87 -explicit main_top_translate.vhd
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vcom -93 -explicit main_top_tb.vhd
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vsim -t 1ps -lib work main_top_main_top_tb_vhd_tb
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do main_top_main_top_tb_vhd_tb.udo
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view wave
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add wave *
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view structure
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view signals
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run 1000ns
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## End
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## NOTE: Do not edit this file.
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## Auto generated by Project Navigator for VHDL Post-PAR Simulation
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##
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vlib work
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## Compile Post-PAR Model for Module main_top
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vcom -87 -explicit main_top_timesim.vhd
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vcom -93 -explicit main_top_tb.vhd
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vsim -t 1ps -sdfmax /UUT=main_top_timesim.sdf -lib work main_top_main_top_tb_vhd_tb
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do main_top_main_top_tb_vhd_tb.udo
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view wave
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add wave *
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view structure
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view signals
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run 1000ns
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## End
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-- ProjNav VHDL simulation template: main_top_main_top_tb_vhd_tb.udo
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-- You may edit this file after the line that starts with
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-- '-- START' to customize your simulation
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-- START user-defined simulation commands
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-- VHDL Test Bench Created from source file main_top.vhd -- 00:26:28 06/02/2004
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--
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY main_top_main_top_tb_vhd_tb IS
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END main_top_main_top_tb_vhd_tb;
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ARCHITECTURE behavior OF main_top_main_top_tb_vhd_tb IS
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COMPONENT main_top
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PORT(
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clk : IN std_logic;
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resn : IN std_logic;
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a : IN std_logic_vector(31 downto 0);
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wen : IN std_logic;
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csn : IN std_logic;
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d : INOUT std_logic_vector(31 downto 0)
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);
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END COMPONENT;
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SIGNAL clk : std_logic;
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SIGNAL resn : std_logic;
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SIGNAL a : std_logic_vector(31 downto 0);
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SIGNAL d : std_logic_vector(31 downto 0);
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SIGNAL wen : std_logic;
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SIGNAL csn : std_logic;
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constant ClockPeriod : Time := 25 ns;
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BEGIN
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uut: main_top PORT MAP(
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clk => clk,
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resn => resn,
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a => a,
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d => d,
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wen => wen,
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csn => csn
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);
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clockgen: process
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begin
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clk <= '1';
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loop
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wait for (ClockPeriod / 2);
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clk <= not clk;
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end loop;
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end process;
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-- *** Test Bench - User Defined Section ***
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tb : PROCESS
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BEGIN
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wait for 8*ClockPeriod;
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resn <= '1';
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wait for 4*ClockPeriod;
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wen <= '0';
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a <= X"00000000";
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wait for 1*ClockPeriod;
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d <= X"AAAAAAAA";
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csn <= '0';
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wait for 1*ClockPeriod;
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csn <= '1';
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a <= X"00000010";
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wait for 1*ClockPeriod;
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d <= X"BBBBBBBB";
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csn <= '0';
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wait for 1*ClockPeriod;
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csn <= '1';
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a <= X"00000020";
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wait for 1*ClockPeriod;
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d <= X"CCCCCCCC";
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csn <= '0';
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wait for 1*ClockPeriod;
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csn <= '1';
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a <= X"00000030";
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wait for 1*ClockPeriod;
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d <= X"DDDDDDDD";
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csn <= '0';
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wait for 1*ClockPeriod;
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csn <= '1';
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wait for 8*ClockPeriod;
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wen <= '1';
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a <= X"00000000";
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wait for 1*ClockPeriod;
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d <= (31 downto 0 => 'Z');
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csn <= '0';
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wait for 1*ClockPeriod;
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csn <= '1';
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a <= X"00000010";
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wait for 1*ClockPeriod;
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d <= (31 downto 0 => 'Z');
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csn <= '0';
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wait for 1*ClockPeriod;
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csn <= '1';
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a <= X"00000020";
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wait for 1*ClockPeriod;
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d <= (31 downto 0 => 'Z');
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csn <= '0';
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wait for 1*ClockPeriod;
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csn <= '1';
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a <= X"00000030";
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wait for 1*ClockPeriod;
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d <= (31 downto 0 => 'Z');
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csn <= '0';
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wait for 1*ClockPeriod;
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csn <= '1';
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wait; -- will wait forever
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END PROCESS;
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-- *** End Test Bench - User Defined Section ***
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END;
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
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work main_top.vhdl
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onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate -format Logic /main_top_main_top_tb_vhd_tb/clk
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add wave -noupdate -format Logic /main_top_main_top_tb_vhd_tb/resn
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add wave -noupdate -format Literal -radix hexadecimal /main_top_main_top_tb_vhd_tb/a
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add wave -noupdate -format Literal -radix hexadecimal /main_top_main_top_tb_vhd_tb/d
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add wave -noupdate -format Logic /main_top_main_top_tb_vhd_tb/wen
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add wave -noupdate -format Logic /main_top_main_top_tb_vhd_tb/csn
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add wave -noupdate -format Literal -radix hexadecimal /main_top_main_top_tb_vhd_tb/uut/reg_a
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add wave -noupdate -format Literal -radix hexadecimal /main_top_main_top_tb_vhd_tb/uut/reg_b
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add wave -noupdate -format Literal -radix hexadecimal /main_top_main_top_tb_vhd_tb/uut/reg_c
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add wave -noupdate -format Literal -radix hexadecimal /main_top_main_top_tb_vhd_tb/uut/dmuxo
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add wave -noupdate -format Literal -radix hexadecimal /main_top_main_top_tb_vhd_tb/uut/mux_ctrl
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 1} {684150 ps} 0}
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WaveRestoreZoom {356007 ps} {1033895 ps}
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configure wave -namecolwidth 150
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configure wave -valuecolwidth 100
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configure wave -justifyvalue left
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configure wave -signalnamewidth 1
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configure wave -snapdistance 10
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configure wave -datasetprefix 0
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configure wave -rowmargin 4
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configure wave -childrowmargin 2
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configure wave -gridoffset 0
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configure wave -gridperiod 1
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configure wave -griddelta 40
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configure wave -timeline 0
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