- added
git-svn-id: http://moon:8086/svn/vhdl/trunk@1429 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -0,0 +1 @@
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work vconfig.vhdl
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@@ -0,0 +1,5 @@
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do vconfig_tb.fdo
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delete wave *
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do wave.do
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restart -force
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run 6000ns -all
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@@ -0,0 +1,10 @@
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# Auto generated by Project Navigator for Modelsim
|
||||
vlib work
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||||
|
||||
vcom -93 -explicit vconfig.vhdl
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||||
## You need to generate your own stimuli
|
||||
vsim -t 1ps vconfig
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||||
view wave
|
||||
add wave *
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||||
view structure
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||||
view signals
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||||
@@ -0,0 +1 @@
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work
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@@ -0,0 +1 @@
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||||
vhdl work vconfig.vhdl
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,183 @@
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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||||
-- Uncomment the following lines to use the declarations that are
|
||||
-- provided for instantiating Xilinx primitive components.
|
||||
--library UNISIM;
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||||
--use UNISIM.VComponents.all;
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||||
|
||||
entity vconfig is
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||||
Port ( RES : in std_logic;
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nINIT_B : in std_logic;
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||||
CLK : in std_logic;
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DONE : in std_logic;
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CCLK : out std_logic;
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CCLK_PRESCALER : in std_logic_vector(5 downto 0);
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||||
LOAD_PRESCALER : in std_logic;
|
||||
DIN : in std_logic_vector(31 downto 0);
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DOUT : out std_logic;
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||||
LOAD_SREG : in std_logic;
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||||
BUF_IS_EMPTY : inout std_logic);
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||||
end vconfig;
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||||
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||||
architecture Behavioral of vconfig is
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constant nbits : integer := 32;
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constant nBufs : integer := 2;
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type t_config_state is (CFG_STOP, CFG_INIT, CFG_RUN);
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type t_buf is array (0 to nBufs-1) of std_logic_vector (nBits-1 downto 0);
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||||
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signal REG: t_buf;
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signal count, CLK_SCALE: integer range 0 to 63;
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signal SHIFT_CNT: integer range 0 to nbits-1;
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signal state, next_state : t_config_state;
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||||
signal SCLK, SHIFT_EN : STD_LOGIC;
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signal buf_depth: integer range 0 to 2;
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signal tempID, readBufId, writeBufId : integer range 0 to nBufs-1;
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||||
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||||
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begin
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||||
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-- 4-bit loadable serial-in and serial-out shift register
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-- CLK: in STD_LOGIC;
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-- DIN: in STD_LOGIC;
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-- LOAD: in STD_LOGIC;
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-- LOAD_DATA: in STD_LOGIC_VECTOR(3 downto 0);
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-- DOUT: out STD_LOGIC;
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||||
process (RES, SCLK, state, nINIT_B, DONE, REG, BUF_IS_EMPTY)
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begin
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if (RES = '1') then
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CCLK <= '1';
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SHIFT_EN <= '0';
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||||
DOUT <= 'Z';
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else
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case state is
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when CFG_STOP =>
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||||
SHIFT_EN <= '0';
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||||
CCLK <= '1';
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||||
if (DONE = '0' and BUF_IS_EMPTY = '0') then
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next_state <= CFG_INIT;
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||||
else
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||||
next_state <= CFG_STOP;
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||||
end if;
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||||
|
||||
when CFG_INIT =>
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||||
CCLK <= SCLK;
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next_state <= CFG_RUN;
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||||
|
||||
when CFG_RUN =>
|
||||
SHIFT_EN <= '1';
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||||
CCLK <= SCLK;
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||||
if (DONE = '1' or nINIT_B = '0' or BUF_IS_EMPTY = '1') then
|
||||
next_state <= CFG_STOP;
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||||
else
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||||
next_state <= CFG_RUN;
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end if;
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||||
end case;
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||||
if (nINIT_B = '1') then
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||||
DOUT <= STD_LOGIC(REG(readBufId)(nbits-1));
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||||
else
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||||
DOUT <= 'Z';
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||||
end if;
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||||
end if;
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||||
|
||||
end process;
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||||
|
||||
sreg:
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||||
process(RES, SCLK, REG, DIN, LOAD_SREG, SHIFT_EN, SHIFT_CNT)
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||||
begin
|
||||
if (RES = '1') then
|
||||
BUF_IS_EMPTY <= '1';
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||||
SHIFT_CNT <= 0;
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||||
writeBufId <= 0;
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||||
readBufId <= 0;
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||||
buf_depth <= 0;
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||||
|
||||
elsif (LOAD_SREG = '1') then
|
||||
REG(writeBufId) <= DIN;
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||||
|
||||
if (SHIFT_EN = '0') then
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||||
SHIFT_CNT <= nbits-1;
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||||
end if;
|
||||
|
||||
if (buf_depth = nbufs) then
|
||||
buf_depth <= buf_depth ;
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||||
else
|
||||
buf_depth <= buf_depth + 1;
|
||||
end if;
|
||||
|
||||
else
|
||||
if SCLK='0' and SCLK'event then
|
||||
if SHIFT_EN = '1' then
|
||||
REG(readBufId)(nbits-1 downto 0) <= REG(readBufId)(nbits-2 downto 0) & '0';
|
||||
if (SHIFT_CNT = 0) then
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||||
if (buf_depth = 0) then
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writeBufId <= 0;
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readBufId <= 0;
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||||
else
|
||||
SHIFT_CNT <= nbits-1;
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tempID <= readBufID;
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||||
readBufID <= writeBufId;
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||||
writeBufId <= tempID;
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||||
buf_depth <= buf_depth - 1;
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||||
end if;
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||||
else
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||||
SHIFT_CNT <= SHIFT_CNT - 1;
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||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
if (SHIFT_CNT = 0 and buf_depth = 1) then
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||||
BUF_IS_EMPTY <= '1';
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||||
else
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||||
BUF_IS_EMPTY <= '0';
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||||
end if;
|
||||
end process;
|
||||
|
||||
-- 4-bit synchronous counter with count enable,
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||||
-- asynchronous reset
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||||
-- CLK: in STD_LOGIC;
|
||||
-- RESET: in STD_LOGIC;
|
||||
-- CE, LOAD, DIR: in STD_LOGIC;
|
||||
-- DIN: in STD_LOGIC_VECTOR(3 downto 0);
|
||||
-- COUNT: inout STD_LOGIC_VECTOR(3 downto 0);
|
||||
cfg_state_gen:
|
||||
process(RES, SCLK, next_state)
|
||||
begin
|
||||
if (RES = '1') then
|
||||
state <= CFG_STOP;
|
||||
elsif SCLK='1' and SCLK'event then
|
||||
state <= next_state;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
clk_prescaler:
|
||||
process (RES, CLK, CCLK_PRESCALER, LOAD_PRESCALER)
|
||||
begin
|
||||
if (RES = '1') then
|
||||
SCLK <= '1';
|
||||
CLK_SCALE <= 1;
|
||||
COUNT <= CLK_SCALE;
|
||||
|
||||
elsif (LOAD_PRESCALER = '1') then
|
||||
CLK_SCALE <= CONV_INTEGER(CCLK_PRESCALER);
|
||||
|
||||
elsif CLK='1' and CLK'event then
|
||||
if (COUNT = 1) then
|
||||
SCLK <= not SCLK;
|
||||
|
||||
COUNT <= CLK_SCALE;
|
||||
else
|
||||
COUNT <= COUNT - 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
@@ -0,0 +1,54 @@
|
||||
|
||||
#PINLOCK_BEGIN
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||||
|
||||
#Sun May 02 01:57:09 2004
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||||
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||||
NET "CLK" LOC = "S:PIN30";
|
||||
NET "DIN<0>" LOC = "S:PIN94";
|
||||
NET "DIN<10>" LOC = "S:PIN132";
|
||||
NET "DIN<11>" LOC = "S:PIN12";
|
||||
NET "DIN<12>" LOC = "S:PIN124";
|
||||
NET "DIN<13>" LOC = "S:PIN85";
|
||||
NET "DIN<14>" LOC = "S:PIN118";
|
||||
NET "DIN<15>" LOC = "S:PIN82";
|
||||
NET "DIN<16>" LOC = "S:PIN139";
|
||||
NET "DIN<17>" LOC = "S:PIN40";
|
||||
NET "DIN<18>" LOC = "S:PIN6";
|
||||
NET "DIN<19>" LOC = "S:PIN115";
|
||||
NET "DIN<1>" LOC = "S:PIN35";
|
||||
NET "DIN<20>" LOC = "S:PIN134";
|
||||
NET "DIN<21>" LOC = "S:PIN76";
|
||||
NET "DIN<22>" LOC = "S:PIN136";
|
||||
NET "DIN<23>" LOC = "S:PIN13";
|
||||
NET "DIN<24>" LOC = "S:PIN103";
|
||||
NET "DIN<25>" LOC = "S:PIN112";
|
||||
NET "DIN<26>" LOC = "S:PIN59";
|
||||
NET "DIN<27>" LOC = "S:PIN88";
|
||||
NET "DIN<28>" LOC = "S:PIN101";
|
||||
NET "DIN<29>" LOC = "S:PIN25";
|
||||
NET "DIN<2>" LOC = "S:PIN93";
|
||||
NET "DIN<30>" LOC = "S:PIN38";
|
||||
NET "DIN<31>" LOC = "S:PIN91";
|
||||
NET "DIN<3>" LOC = "S:PIN21";
|
||||
NET "DIN<4>" LOC = "S:PIN143";
|
||||
NET "DIN<5>" LOC = "S:PIN28";
|
||||
NET "DIN<6>" LOC = "S:PIN24";
|
||||
NET "DIN<7>" LOC = "S:PIN44";
|
||||
NET "DIN<8>" LOC = "S:PIN104";
|
||||
NET "DIN<9>" LOC = "S:PIN140";
|
||||
NET "DONE" LOC = "S:PIN48";
|
||||
NET "LOAD_PRESCALER" LOC = "S:PIN74";
|
||||
NET "LOAD_SREG" LOC = "S:PIN64";
|
||||
NET "RES" LOC = "S:PIN98";
|
||||
NET "VCLK_PRESCALER<0>" LOC = "S:PIN11";
|
||||
NET "VCLK_PRESCALER<1>" LOC = "S:PIN97";
|
||||
NET "VCLK_PRESCALER<2>" LOC = "S:PIN133";
|
||||
NET "VCLK_PRESCALER<3>" LOC = "S:PIN7";
|
||||
NET "VCLK_PRESCALER<4>" LOC = "S:PIN138";
|
||||
NET "VCLK_PRESCALER<5>" LOC = "S:PIN142";
|
||||
NET "nINIT_B" LOC = "S:PIN10";
|
||||
NET "DOUT" LOC = "S:PIN79";
|
||||
NET "SCLK" LOC = "S:PIN9";
|
||||
NET "VCLK" LOC = "S:PIN50";
|
||||
NET "dummy_out" LOC = "S:PIN117";
|
||||
#PINLOCK_END
|
||||
@@ -0,0 +1,13 @@
|
||||
## NOTE: Do not edit this file.
|
||||
## Autogenerated by ProjNav (creatfdo.tcl) on Wed May 05 21:50:05 Westeuropäische Sommerzeit 2004
|
||||
##
|
||||
vlib work
|
||||
vcom -93 -explicit vconfig.vhdl
|
||||
vcom -93 -explicit vconfig_tb.vhd
|
||||
vsim -t 1ps -lib work vconfig_tb
|
||||
do vconfig_tb.udo
|
||||
view wave
|
||||
add wave *
|
||||
view structure
|
||||
view signals
|
||||
run 6000ns
|
||||
@@ -0,0 +1,15 @@
|
||||
## NOTE: Do not edit this file.
|
||||
## Auto generated by Project Navigator for VHDL Post-PAR Simulation
|
||||
##
|
||||
vlib work
|
||||
## Compile Post-PAR Model for Module vconfig
|
||||
vcom -87 -explicit vconfig_timesim.vhd
|
||||
vcom -93 -explicit vconfig_tb.vhd
|
||||
vsim -t 1ps -sdfmax /UUT=vconfig_timesim.sdf -lib work vconfig_tb
|
||||
do vconfig_tb.udo
|
||||
view wave
|
||||
add wave *
|
||||
view structure
|
||||
view signals
|
||||
run 6000ns
|
||||
## End
|
||||
@@ -0,0 +1,4 @@
|
||||
-- ProjNav VHDL simulation template: vconfig_tb.udo
|
||||
-- You may edit this file after the line that starts with
|
||||
-- '-- START' to customize your simulation
|
||||
-- START user-defined simulation commands
|
||||
@@ -0,0 +1,129 @@
|
||||
|
||||
-- VHDL Test Bench Created from source file vconfig.vhd -- 20:20:01 05/01/2004
|
||||
--
|
||||
-- Notes:
|
||||
-- This testbench has been automatically generated using types std_logic and
|
||||
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
|
||||
-- that these types always be used for the top-level I/O of a design in order
|
||||
-- to guarantee that the testbench will bind correctly to the post-implementation
|
||||
-- simulation model.
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.numeric_std.ALL;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
ENTITY vconfig_tb IS
|
||||
END vconfig_tb;
|
||||
|
||||
ARCHITECTURE behavior OF vconfig_tb IS
|
||||
|
||||
COMPONENT vconfig
|
||||
PORT(
|
||||
RES : IN std_logic;
|
||||
nINIT_B : IN std_logic;
|
||||
CLK : IN std_logic;
|
||||
DONE : IN std_logic;
|
||||
CCLK : OUT std_logic;
|
||||
CCLK_PRESCALER : IN std_logic_vector(5 downto 0);
|
||||
LOAD_PRESCALER : in std_logic;
|
||||
DIN : IN std_logic_vector(31 downto 0);
|
||||
DOUT : OUT std_logic;
|
||||
BUF_IS_EMPTY : inout std_logic;
|
||||
LOAD_SREG : IN std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
SIGNAL RES : std_logic := '1';
|
||||
SIGNAL nINIT_B : std_logic := '0';
|
||||
SIGNAL CLK : std_logic := '0';
|
||||
SIGNAL DONE : std_logic := '1';
|
||||
SIGNAL CCLK : std_logic;
|
||||
SIGNAL CCLK_PRESCALER : std_logic_vector(5 downto 0);
|
||||
SIGNAL LOAD_PRESCALER : std_logic := '0';
|
||||
SIGNAL DOUT : std_logic;
|
||||
SIGNAL DIN : std_logic_vector(31 downto 0);
|
||||
SIGNAL LOAD_SREG : std_logic := '0';
|
||||
SIGNAL BUF_IS_EMPTY : std_logic;
|
||||
|
||||
constant ClockPeriod : Time := 16.667 ns;
|
||||
constant CFG_PRESCALE: integer range 0 to 63 := 2;
|
||||
|
||||
BEGIN
|
||||
|
||||
uut: vconfig PORT MAP(
|
||||
RES => RES,
|
||||
nINIT_B => nINIT_B,
|
||||
CLK => CLK,
|
||||
DONE => DONE,
|
||||
CCLK => CCLK,
|
||||
CCLK_PRESCALER => CCLK_PRESCALER,
|
||||
LOAD_PRESCALER => LOAD_PRESCALER,
|
||||
DOUT => DOUT,
|
||||
DIN => DIN,
|
||||
BUF_IS_EMPTY => BUF_IS_EMPTY,
|
||||
LOAD_SREG => LOAD_SREG
|
||||
);
|
||||
|
||||
busclock: process
|
||||
begin
|
||||
CLK <= '1';
|
||||
loop
|
||||
wait for (ClockPeriod / 2);
|
||||
CLK <= not CLK;
|
||||
end loop;
|
||||
end process;
|
||||
|
||||
-- *** Test Bench - User Defined Section ***
|
||||
tb : PROCESS
|
||||
BEGIN
|
||||
|
||||
wait for 5*ClockPeriod;
|
||||
RES <= '0';
|
||||
|
||||
wait for 5*ClockPeriod;
|
||||
CCLK_PRESCALER <= CONV_STD_LOGIC_VECTOR(CFG_PRESCALE,6);
|
||||
|
||||
wait for 1.5*ClockPeriod;
|
||||
LOAD_PRESCALER <= '1';
|
||||
|
||||
wait for 1*ClockPeriod;
|
||||
LOAD_PRESCALER <= '0';
|
||||
|
||||
wait for 1*ClockPeriod;
|
||||
DIN <= X"BAA34569";
|
||||
|
||||
wait for 1.5*ClockPeriod;
|
||||
LOAD_SREG <= '1';
|
||||
|
||||
wait for 1.0*ClockPeriod;
|
||||
LOAD_SREG <= '0';
|
||||
|
||||
wait for 5*ClockPeriod;
|
||||
DONE <= '0';
|
||||
|
||||
wait for 2*ClockPeriod;
|
||||
nINIT_B <= '1';
|
||||
|
||||
wait for 30.0*real(CFG_PRESCALE)*ClockPeriod*2;
|
||||
|
||||
DIN <= X"8654F41B";
|
||||
|
||||
wait for 1.5*ClockPeriod;
|
||||
LOAD_SREG <= '1';
|
||||
|
||||
wait for 2.0*ClockPeriod;
|
||||
LOAD_SREG <= '0';
|
||||
|
||||
wait for 29.0*real(CFG_PRESCALE)*ClockPeriod*2;
|
||||
DONE <= '1';
|
||||
|
||||
wait for 10.0*ClockPeriod;
|
||||
nINIT_B <= '0';
|
||||
|
||||
wait; -- will wait forever
|
||||
END PROCESS;
|
||||
-- *** End Test Bench - User Defined Section ***
|
||||
|
||||
END;
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,40 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -format Logic /vconfig_tb/uut/res
|
||||
add wave -noupdate -format Logic /vconfig_tb/uut/ninit_b
|
||||
add wave -noupdate -format Logic /vconfig_tb/uut/clk
|
||||
add wave -noupdate -format Logic /vconfig_tb/uut/done
|
||||
add wave -noupdate -format Logic /vconfig_tb/uut/cclk
|
||||
add wave -noupdate -format Literal /vconfig_tb/uut/cclk_prescaler
|
||||
add wave -noupdate -format Logic /vconfig_tb/uut/load_prescaler
|
||||
add wave -noupdate -format Literal /vconfig_tb/uut/din
|
||||
add wave -noupdate -format Logic /vconfig_tb/uut/dout
|
||||
add wave -noupdate -format Logic /vconfig_tb/uut/load_sreg
|
||||
add wave -noupdate -format Logic /vconfig_tb/uut/buf_is_empty
|
||||
add wave -noupdate -format Literal /vconfig_tb/uut/reg
|
||||
add wave -noupdate -format Literal /vconfig_tb/uut/count
|
||||
add wave -noupdate -format Literal /vconfig_tb/uut/clk_scale
|
||||
add wave -noupdate -format Literal /vconfig_tb/uut/shift_cnt
|
||||
add wave -noupdate -format Literal /vconfig_tb/uut/state
|
||||
add wave -noupdate -format Literal /vconfig_tb/uut/next_state
|
||||
add wave -noupdate -format Logic /vconfig_tb/uut/sclk
|
||||
add wave -noupdate -format Logic /vconfig_tb/uut/shift_en
|
||||
add wave -noupdate -format Literal /vconfig_tb/uut/buf_depth
|
||||
add wave -noupdate -format Literal /vconfig_tb/uut/tempid
|
||||
add wave -noupdate -format Literal /vconfig_tb/uut/readbufid
|
||||
add wave -noupdate -format Literal /vconfig_tb/uut/writebufid
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {2809539 ps} 0}
|
||||
WaveRestoreZoom {1356698 ps} {12202906 ps}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
Reference in New Issue
Block a user