From 288ed8d40cf20a57f1f0853105bece3349cdbb28 Mon Sep 17 00:00:00 2001
From: jens <jens@jayfield.org>
Date: Thu, 30 Jun 2022 23:16:01 +0200
Subject: [PATCH] tb_mips_sys_sim compile clean

---
 projects/mips_sys/ghdl/tb_mips_sys.make | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/projects/mips_sys/ghdl/tb_mips_sys.make b/projects/mips_sys/ghdl/tb_mips_sys.make
index 0de6c0e..e0a4153 100644
--- a/projects/mips_sys/ghdl/tb_mips_sys.make
+++ b/projects/mips_sys/ghdl/tb_mips_sys.make
@@ -14,7 +14,7 @@ SRCS += $(LIB_PATH)/models/memory/sdram/mt46v16m16/mt46v16m16.vhd
 SRCS += ../src/sdram_config_sim.vhd
 
 # Clock Generator
-SRCS += ../src/clockgen.vhd
+SRCS += $(LIB_PATH)/clock/xilinx/src/clockgen.vhd
 
 # MIPS
 SRCS += $(MIPS_CORE_SRCS)
@@ -62,8 +62,8 @@ SRCS += $(LIB_PATH)/SSRAM/src/ssram_port_wb.vhd
 
 # SDRAM
 SRCS += $(LIB_PATH)/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd
-SRCS += $(LIB_PATH)/SDRAM/ddr_sdr_v1_5/src/ddr_clk_virtex4.vhd
-SRCS += $(LIB_PATH)/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd
+SRCS += $(LIB_PATH)/SDRAM/ddr_sdr_v1_5/src/clock/xilinx/ddr_clk_virtex4.vhd
+SRCS += $(LIB_PATH)/SDRAM/ddr_sdr_v1_5/src/phy/xilinx/ddr_phy_virtex4.vhd
 SRCS += $(LIB_PATH)/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd
 SRCS += $(LIB_PATH)/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd
 SRCS += $(LIB_PATH)/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd
@@ -89,7 +89,7 @@ TARGET := tb_mips_sys
 ENTITY = tb_mips_sys
 RUN_TIME := 10ms
 
-GHDL_OPTS := -P$(VHDL_HOME)/Common/sim/build/unisim/unisim -fsynopsys -fexplicit
+GHDL_OPTS := -P$(VHDL_HOME)/Common/sim/build/ghdl/unisim -fsynopsys -fexplicit
 
 include $(VHDL_HOME)/make/ghdl.mk