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- avoid of undefined data in forwarding logic during simulation.

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git-svn-id: http://moon:8086/svn/vhdl/trunk@982 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2013-07-20 18:41:32 +00:00
parent f002777772
commit 1926d23b44
1 changed files with 18 additions and 2 deletions
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lib/CPUs/MIPS/src/core/mips_pipeline.vhd
+18 -2
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@@ -394,7 +394,15 @@ proc_stage_fwd_a:
elsif hdu.alu_fwd_a_wb then elsif hdu.alu_fwd_a_wb then
data := WB_stage.data; data := WB_stage.data;
end if; end if;
ID_stage.reg_a <= to_01(data) after 2 ns;
for i in 0 to 31 loop
if data(i) = '1' then
ID_stage.reg_a(i) <= '1' after 2 ns;
else
ID_stage.reg_a(i) <= '0' after 2 ns;
end if;
end loop;
end process; end process;
proc_stage_fwd_b: proc_stage_fwd_b:
@@ -409,7 +417,15 @@ proc_stage_fwd_b:
elsif hdu.alu_fwd_b_wb then elsif hdu.alu_fwd_b_wb then
data := WB_stage.data; data := WB_stage.data;
end if; end if;
ID_stage.reg_b <= to_01(data) after 2 ns;
for i in 0 to 31 loop
if data(i) = '1' then
ID_stage.reg_b(i) <= '1' after 2 ns;
else
ID_stage.reg_b(i) <= '0' after 2 ns;
end if;
end loop;
end process; end process;
proc_imm_mux: proc_imm_mux: