From 1926d23b445cb177fa9e2b8d1976b6679866810c Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sat, 20 Jul 2013 18:41:32 +0000 Subject: [PATCH] - avoid of undefined data in forwarding logic during simulation. Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@982 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/CPUs/MIPS/src/core/mips_pipeline.vhd | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd b/lib/CPUs/MIPS/src/core/mips_pipeline.vhd index 2cc39e8..0dc3689 100644 --- a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd +++ b/lib/CPUs/MIPS/src/core/mips_pipeline.vhd @@ -394,7 +394,15 @@ proc_stage_fwd_a: elsif hdu.alu_fwd_a_wb then data := WB_stage.data; end if; - ID_stage.reg_a <= to_01(data) after 2 ns; + + for i in 0 to 31 loop + if data(i) = '1' then + ID_stage.reg_a(i) <= '1' after 2 ns; + else + ID_stage.reg_a(i) <= '0' after 2 ns; + end if; + end loop; + end process; proc_stage_fwd_b: @@ -409,7 +417,15 @@ proc_stage_fwd_b: elsif hdu.alu_fwd_b_wb then data := WB_stage.data; end if; - ID_stage.reg_b <= to_01(data) after 2 ns; + + for i in 0 to 31 loop + if data(i) = '1' then + ID_stage.reg_b(i) <= '1' after 2 ns; + else + ID_stage.reg_b(i) <= '0' after 2 ns; + end if; + end loop; + end process; proc_imm_mux: