diff --git a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd b/lib/CPUs/MIPS/src/core/mips_pipeline.vhd
index 2cc39e8..0dc3689 100644
--- a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd
+++ b/lib/CPUs/MIPS/src/core/mips_pipeline.vhd
@@ -394,7 +394,15 @@ proc_stage_fwd_a:
 		elsif hdu.alu_fwd_a_wb then
 			data 	:= WB_stage.data;
 		end if;
-		ID_stage.reg_a	<= to_01(data) after 2 ns;
+		
+		for i in 0 to 31 loop
+			if data(i) = '1' then
+				ID_stage.reg_a(i)	<= '1' after 2 ns;
+			else 
+				ID_stage.reg_a(i)	<= '0' after 2 ns;
+			end if;
+		end loop;
+
 	end process;
 
 proc_stage_fwd_b:
@@ -409,7 +417,15 @@ proc_stage_fwd_b:
 		elsif hdu.alu_fwd_b_wb then
 			data	:= WB_stage.data;
 		end if;
-		ID_stage.reg_b	<= to_01(data) after 2 ns;
+
+		for i in 0 to 31 loop
+			if data(i) = '1' then
+				ID_stage.reg_b(i)	<= '1' after 2 ns;
+			else 
+				ID_stage.reg_b(i)	<= '0' after 2 ns;
+			end if;
+		end loop;
+
 	end process;
 	
 proc_imm_mux: