jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

- use dpram_xxx_ra for synthesis

Browse Source 
- fixed do file for post synthesis simulation


git-svn-id: http://moon:8086/svn/vhdl/trunk@1083 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-14 20:45:05 +00:00
parent 5c6c1fd1cd
commit 182e68126e
5 changed files with 26 additions and 38 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/CPUs/MIPS/sim/modelsim.ini
+1 -1
View File
@@ -11,7 +11,7 @@ others = $MODEL_TECH/../modelsim.ini
;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release
;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release
unisim = ../../../Common/sim/unisim
unisim = W:/SVN/vhdl/trunk/Common/sim/unisim
[vcom]
; VHDL93 variable selects language version as the default.
; Default is VHDL-2002.