diff --git a/lib/CPUs/MIPS/sim/ModelSim SE .lnk b/lib/CPUs/MIPS/sim/ModelSim SE .lnk
index a92f29f..7b83436 100644
Binary files a/lib/CPUs/MIPS/sim/ModelSim SE .lnk and b/lib/CPUs/MIPS/sim/ModelSim SE .lnk differ
diff --git a/lib/CPUs/MIPS/sim/modelsim.ini b/lib/CPUs/MIPS/sim/modelsim.ini
index 5fb74a9..bb852ba 100644
--- a/lib/CPUs/MIPS/sim/modelsim.ini
+++ b/lib/CPUs/MIPS/sim/modelsim.ini
@@ -11,7 +11,7 @@ others = $MODEL_TECH/../modelsim.ini
 ;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers       // Source files only for this release
 ;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release
 
-unisim = ../../../Common/sim/unisim
+unisim = W:/SVN/vhdl/trunk/Common/sim/unisim
 [vcom]
 ; VHDL93 variable selects language version as the default. 
 ; Default is VHDL-2002.
diff --git a/lib/CPUs/MIPS/sim/tb_mips_top_syn.fdo b/lib/CPUs/MIPS/sim/tb_mips_top_syn.fdo
index 4c72deb..a1e316a 100644
--- a/lib/CPUs/MIPS/sim/tb_mips_top_syn.fdo
+++ b/lib/CPUs/MIPS/sim/tb_mips_top_syn.fdo
@@ -3,15 +3,8 @@
 vlib work
 
 # RAMS
-vcom -explicit  -93 "../../../misc/dpram_2w2r1c_sim.vhd"
-vcom -explicit  -93 "../../../misc/dpram_2w2r.vhd"
-vcom -explicit  -93 "../../../misc/dpram_1w2r1c_sim.vhd"
-vcom -explicit  -93 "../../../misc/dpram_1w1r.vhd"
-vcom -explicit  -93 "../../../misc/dpram_1w1r1c_sim.vhd"
-
-vcom -explicit  -93 "../../../misc/dpram_1w1r2c_sim.vhd"
-vcom -explicit  -93 "../../../misc/dpram_2w2r2c_sim.vhd"
-
+vcom -explicit  -93 "../../../rams/dpram_2w2r2c_ra_sim.vhd"
+vcom -explicit  -93 "../../../rams/dpram_1w1r2c_ra_sim.vhd"
 
 # FIFOS
 vcom -explicit  -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
@@ -22,11 +15,8 @@ vcom -explicit  -93 "../../../FIFO/src/fifo_async_ctrl.vhd"
 vcom -explicit  -93 "../../../FIFO/src/fifo_async.vhd"
 
 # UART
-vcom -explicit  -93 "../../../uart/bbfifo_16x8.vhd"
-vcom -explicit  -93 "../../../uart/kcuart_rx.vhd"
-vcom -explicit  -93 "../../../uart/kcuart_tx.vhd"
-vcom -explicit  -93 "../../../uart/uart_rx.vhd"
-vcom -explicit  -93 "../../../uart/uart_tx.vhd"
+vcom -explicit  -93 "../../../uart/uart_rx_sim.vhd"
+vcom -explicit  -93 "../../../uart/uart_tx_sim.vhd"
 vcom -explicit  -93 "../../../uart/uart_wb.vhd"
 
 # GPIO
diff --git a/lib/CPUs/MIPS/syn/ise101/mips_top.prj b/lib/CPUs/MIPS/syn/ise101/mips_top.prj
index 6925d0f..8bf3018 100644
--- a/lib/CPUs/MIPS/syn/ise101/mips_top.prj
+++ b/lib/CPUs/MIPS/syn/ise101/mips_top.prj
@@ -1,7 +1,6 @@
 vhdl work "../../../../FIFO/src/fifo_ctrl_pkg.vhd"
 vhdl work "../../../../FIFO/src/gray_counter.vhd"
 vhdl work "../../../../rams/dpram_2w2r2c_ra_xil.vhd"
-vhdl work "../../../../rams/dpram_1w1r2c_ro_xil.vhd"
 vhdl work "../../../../rams/dpram_1w1r2c_ra_xil.vhd"
 vhdl work "../../../../FIFO/src/fifo_sync_ctrl.vhd"
 vhdl work "../../../../FIFO/src/fifo_async_ctrl.vhd"
diff --git a/lib/CPUs/MIPS/syn/ise101/mips_top_vhdl.prj b/lib/CPUs/MIPS/syn/ise101/mips_top_vhdl.prj
index 3ccfc7d..92b7ff7 100644
--- a/lib/CPUs/MIPS/syn/ise101/mips_top_vhdl.prj
+++ b/lib/CPUs/MIPS/syn/ise101/mips_top_vhdl.prj
@@ -1,22 +1,21 @@
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\gray_counter.vhd"
-vhdl work "W:\vhdl\lib\rams\dpram_2w2r2c_ra_xil.vhd"
-vhdl work "W:\vhdl\lib\rams\dpram_1w1r2c_ro_xil.vhd"
-vhdl work "W:\vhdl\lib\rams\dpram_1w1r2c_ra_xil.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync_ctrl.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_async_ctrl.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_async.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_shifter.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_reg.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_muldiv.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_instr.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_icache.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_dcache.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bcu.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_alu.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_pipeline.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_cop.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_biu.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_top.vhd"
+vhdl work "W:\SVN\vhdl\trunk\lib\FIFO\src\fifo_ctrl_pkg.vhd"
+vhdl work "W:\SVN\vhdl\trunk\lib\FIFO\src\gray_counter.vhd"
+vhdl work "W:\SVN\vhdl\trunk\lib\rams\dpram_2w2r2c_ra_xil.vhd"
+vhdl work "W:\SVN\vhdl\trunk\lib\rams\dpram_1w1r2c_ra_xil.vhd"
+vhdl work "W:\SVN\vhdl\trunk\lib\FIFO\src\fifo_sync_ctrl.vhd"
+vhdl work "W:\SVN\vhdl\trunk\lib\FIFO\src\fifo_async_ctrl.vhd"
+vhdl work "W:\SVN\vhdl\trunk\lib\CPUs\MIPS\src\core\mips_types.vhd"
+vhdl work "W:\SVN\vhdl\trunk\lib\FIFO\src\fifo_sync.vhd"
+vhdl work "W:\SVN\vhdl\trunk\lib\FIFO\src\fifo_async.vhd"
+vhdl work "W:\SVN\vhdl\trunk\lib\CPUs\MIPS\src\core\mips_shifter.vhd"
+vhdl work "W:\SVN\vhdl\trunk\lib\CPUs\MIPS\src\core\mips_reg.vhd"
+vhdl work "W:\SVN\vhdl\trunk\lib\CPUs\MIPS\src\core\mips_muldiv.vhd"
+vhdl work "W:\SVN\vhdl\trunk\lib\CPUs\MIPS\src\core\mips_instr.vhd"
+vhdl work "W:\SVN\vhdl\trunk\lib\CPUs\MIPS\src\core\mips_icache.vhd"
+vhdl work "W:\SVN\vhdl\trunk\lib\CPUs\MIPS\src\core\mips_dcache.vhd"
+vhdl work "W:\SVN\vhdl\trunk\lib\CPUs\MIPS\src\core\mips_bcu.vhd"
+vhdl work "W:\SVN\vhdl\trunk\lib\CPUs\MIPS\src\core\mips_alu.vhd"
+vhdl work "W:\SVN\vhdl\trunk\lib\CPUs\MIPS\src\core\mips_pipeline.vhd"
+vhdl work "W:\SVN\vhdl\trunk\lib\CPUs\MIPS\src\core\mips_cop.vhd"
+vhdl work "W:\SVN\vhdl\trunk\lib\CPUs\MIPS\src\core\mips_biu.vhd"
+vhdl work "W:\SVN\vhdl\trunk\lib\CPUs\MIPS\src\core\mips_top.vhd"