From 182e68126ec6292efadcf09ee02f78216607c6c1 Mon Sep 17 00:00:00 2001
From: Jens Ahrensfeld <jens@jayfield.org>
Date: Thu, 14 May 2015 20:45:05 +0000
Subject: [PATCH] - use dpram_xxx_ra for synthesis - fixed do file for post
 synthesis simulation

git-svn-id: http://moon:8086/svn/vhdl/trunk@1083 cc03376c-175c-47c8-b038-4cd826a8556b
---
 lib/CPUs/MIPS/sim/ModelSim SE .lnk         | Bin 1771 -> 1364 bytes
 lib/CPUs/MIPS/sim/modelsim.ini             |   2 +-
 lib/CPUs/MIPS/sim/tb_mips_top_syn.fdo      |  18 ++-------
 lib/CPUs/MIPS/syn/ise101/mips_top.prj      |   1 -
 lib/CPUs/MIPS/syn/ise101/mips_top_vhdl.prj |  43 ++++++++++-----------
 5 files changed, 26 insertions(+), 38 deletions(-)

diff --git a/lib/CPUs/MIPS/sim/ModelSim SE .lnk b/lib/CPUs/MIPS/sim/ModelSim SE .lnk
index a92f29ff49265c8c98d7e9aedc9222fc4e7035eb..7b83436ec6525a1bc377aa252e5fb429599dfe24 100644
GIT binary patch
delta 432
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z*SQI|iU8I5GUPL)Fr+f%Fq8nvWQGiecm^{DJq9Bnn}I<J$cC8~4K%GhGtbzFK?#dF
z<qVk&c?`x3Mn*twA`Cu213=D|GL;HeV93o+NzEzF%+*V+NM&F!fNPJ0IAgK^lVVUX
zP@fDCgFFYKb%7WJf`C{Mh?#-dOTVs107x?c{pt%cvm`Y+Bi>BUC^-h~vKSPLHk&ag
zGKT;qbSnx#njm1_!$~XFZS8ViJJn>{?7KJjoZY*3;kmp=g1cUGFsN(DH4>5snF0V!
C8gPgJ

literal 1771
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zB#WdVx+(|-ArS9Ei1I?H3;UrYf0BZ-ZtFSU=RR#2L3GuD_nh~<=Y5~|J<of-uL6M1
zki;37P-c`3aciPJKX9or`~EXs>_U>VV!UMXa`RIi+zpDSPW9L3cRB<1df#}aOpCTa
z`t27fIGCGza~E<-ZIb4+s(6v7Y?2%|iqqi>M*VF*z=jkg<I}jX3dyF={(>~l`qfZH
z^C5^R{AdHiupOr~yg_?9@(L`uz~P_J2JHgvfP$u8c@;7b1+ai2FrZFD>LrrPQ|hRw
z>|(KH8k)zR<mgq<#)q~rCXtE|TG7PXf`}l15b9ZDgnM8oYBls)qMvcP^R2}K-L9c~
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z$a?6BwOfeasnnjyEG-nViW`eHpCU#xWd}uc$@o05FP&>uYp^}!2ivc9R}xK;;&s*g
zB7UhO5YD&yg023LW>@QVvl|vje>tyx8xr|edn=Kr_4^`WJx+i1k8@#!8C57pDJt08
za(Li^gEoo%2(S+lO5nw5_FUqLlX@jJ^(`1k5!o9ys}IZRsxSAr9Oi`kt7wV!#`BZh
z|6-WQj)yEd$YUjWawV|&`}_CFo!e4z9DTBF<<E64Z20G#WF`J4)?|q16ZvQ6jryW*
zSLI^L+Iq%l7a=ptTo=?cVOXNw&>xePL++~=jQR&-F)cRtvl^GohhqAu>H<d$)7w!L
z(f{c1k*@PgQp~DP=C==QqIhXP$u&L-QHTlhBF^Hv{K2U2ytv#Eqx3Ht^&^aVz2}&s
z&v6y8BFE-92vTv6J`ro5e1(#-Ar)B|&`xK0R-Dr<J1LWvZaHgeRQWRqpE!od(eiQ>
z)66$<y<7Iu_dAD(smm<tI7>8gF<iZZ8u3Nj+rnB3JS=(D*xPW&-Cy%{ckJ=R`@6<#
Wb7>i~TOajArw?UhefiV5K>7i~-Yo_I

diff --git a/lib/CPUs/MIPS/sim/modelsim.ini b/lib/CPUs/MIPS/sim/modelsim.ini
index 5fb74a9..bb852ba 100644
--- a/lib/CPUs/MIPS/sim/modelsim.ini
+++ b/lib/CPUs/MIPS/sim/modelsim.ini
@@ -11,7 +11,7 @@ others = $MODEL_TECH/../modelsim.ini
 ;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers       // Source files only for this release
 ;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release
 
-unisim = ../../../Common/sim/unisim
+unisim = W:/SVN/vhdl/trunk/Common/sim/unisim
 [vcom]
 ; VHDL93 variable selects language version as the default. 
 ; Default is VHDL-2002.
diff --git a/lib/CPUs/MIPS/sim/tb_mips_top_syn.fdo b/lib/CPUs/MIPS/sim/tb_mips_top_syn.fdo
index 4c72deb..a1e316a 100644
--- a/lib/CPUs/MIPS/sim/tb_mips_top_syn.fdo
+++ b/lib/CPUs/MIPS/sim/tb_mips_top_syn.fdo
@@ -3,15 +3,8 @@
 vlib work
 
 # RAMS
-vcom -explicit  -93 "../../../misc/dpram_2w2r1c_sim.vhd"
-vcom -explicit  -93 "../../../misc/dpram_2w2r.vhd"
-vcom -explicit  -93 "../../../misc/dpram_1w2r1c_sim.vhd"
-vcom -explicit  -93 "../../../misc/dpram_1w1r.vhd"
-vcom -explicit  -93 "../../../misc/dpram_1w1r1c_sim.vhd"
-
-vcom -explicit  -93 "../../../misc/dpram_1w1r2c_sim.vhd"
-vcom -explicit  -93 "../../../misc/dpram_2w2r2c_sim.vhd"
-
+vcom -explicit  -93 "../../../rams/dpram_2w2r2c_ra_sim.vhd"
+vcom -explicit  -93 "../../../rams/dpram_1w1r2c_ra_sim.vhd"
 
 # FIFOS
 vcom -explicit  -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
@@ -22,11 +15,8 @@ vcom -explicit  -93 "../../../FIFO/src/fifo_async_ctrl.vhd"
 vcom -explicit  -93 "../../../FIFO/src/fifo_async.vhd"
 
 # UART
-vcom -explicit  -93 "../../../uart/bbfifo_16x8.vhd"
-vcom -explicit  -93 "../../../uart/kcuart_rx.vhd"
-vcom -explicit  -93 "../../../uart/kcuart_tx.vhd"
-vcom -explicit  -93 "../../../uart/uart_rx.vhd"
-vcom -explicit  -93 "../../../uart/uart_tx.vhd"
+vcom -explicit  -93 "../../../uart/uart_rx_sim.vhd"
+vcom -explicit  -93 "../../../uart/uart_tx_sim.vhd"
 vcom -explicit  -93 "../../../uart/uart_wb.vhd"
 
 # GPIO
diff --git a/lib/CPUs/MIPS/syn/ise101/mips_top.prj b/lib/CPUs/MIPS/syn/ise101/mips_top.prj
index 6925d0f..8bf3018 100644
--- a/lib/CPUs/MIPS/syn/ise101/mips_top.prj
+++ b/lib/CPUs/MIPS/syn/ise101/mips_top.prj
@@ -1,7 +1,6 @@
 vhdl work "../../../../FIFO/src/fifo_ctrl_pkg.vhd"
 vhdl work "../../../../FIFO/src/gray_counter.vhd"
 vhdl work "../../../../rams/dpram_2w2r2c_ra_xil.vhd"
-vhdl work "../../../../rams/dpram_1w1r2c_ro_xil.vhd"
 vhdl work "../../../../rams/dpram_1w1r2c_ra_xil.vhd"
 vhdl work "../../../../FIFO/src/fifo_sync_ctrl.vhd"
 vhdl work "../../../../FIFO/src/fifo_async_ctrl.vhd"
diff --git a/lib/CPUs/MIPS/syn/ise101/mips_top_vhdl.prj b/lib/CPUs/MIPS/syn/ise101/mips_top_vhdl.prj
index 3ccfc7d..92b7ff7 100644
--- a/lib/CPUs/MIPS/syn/ise101/mips_top_vhdl.prj
+++ b/lib/CPUs/MIPS/syn/ise101/mips_top_vhdl.prj
@@ -1,22 +1,21 @@
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\gray_counter.vhd"
-vhdl work "W:\vhdl\lib\rams\dpram_2w2r2c_ra_xil.vhd"
-vhdl work "W:\vhdl\lib\rams\dpram_1w1r2c_ro_xil.vhd"
-vhdl work "W:\vhdl\lib\rams\dpram_1w1r2c_ra_xil.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync_ctrl.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_async_ctrl.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_async.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_shifter.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_reg.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_muldiv.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_instr.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_icache.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_dcache.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bcu.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_alu.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_pipeline.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_cop.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_biu.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_top.vhd"
+vhdl work "W:\SVN\vhdl\trunk\lib\FIFO\src\fifo_ctrl_pkg.vhd"
+vhdl work "W:\SVN\vhdl\trunk\lib\FIFO\src\gray_counter.vhd"
+vhdl work "W:\SVN\vhdl\trunk\lib\rams\dpram_2w2r2c_ra_xil.vhd"
+vhdl work "W:\SVN\vhdl\trunk\lib\rams\dpram_1w1r2c_ra_xil.vhd"
+vhdl work "W:\SVN\vhdl\trunk\lib\FIFO\src\fifo_sync_ctrl.vhd"
+vhdl work "W:\SVN\vhdl\trunk\lib\FIFO\src\fifo_async_ctrl.vhd"
+vhdl work "W:\SVN\vhdl\trunk\lib\CPUs\MIPS\src\core\mips_types.vhd"
+vhdl work "W:\SVN\vhdl\trunk\lib\FIFO\src\fifo_sync.vhd"
+vhdl work "W:\SVN\vhdl\trunk\lib\FIFO\src\fifo_async.vhd"
+vhdl work "W:\SVN\vhdl\trunk\lib\CPUs\MIPS\src\core\mips_shifter.vhd"
+vhdl work "W:\SVN\vhdl\trunk\lib\CPUs\MIPS\src\core\mips_reg.vhd"
+vhdl work "W:\SVN\vhdl\trunk\lib\CPUs\MIPS\src\core\mips_muldiv.vhd"
+vhdl work "W:\SVN\vhdl\trunk\lib\CPUs\MIPS\src\core\mips_instr.vhd"
+vhdl work "W:\SVN\vhdl\trunk\lib\CPUs\MIPS\src\core\mips_icache.vhd"
+vhdl work "W:\SVN\vhdl\trunk\lib\CPUs\MIPS\src\core\mips_dcache.vhd"
+vhdl work "W:\SVN\vhdl\trunk\lib\CPUs\MIPS\src\core\mips_bcu.vhd"
+vhdl work "W:\SVN\vhdl\trunk\lib\CPUs\MIPS\src\core\mips_alu.vhd"
+vhdl work "W:\SVN\vhdl\trunk\lib\CPUs\MIPS\src\core\mips_pipeline.vhd"
+vhdl work "W:\SVN\vhdl\trunk\lib\CPUs\MIPS\src\core\mips_cop.vhd"
+vhdl work "W:\SVN\vhdl\trunk\lib\CPUs\MIPS\src\core\mips_biu.vhd"
+vhdl work "W:\SVN\vhdl\trunk\lib\CPUs\MIPS\src\core\mips_top.vhd"