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- use dpram_xxx_ra for synthesis

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- fixed do file for post synthesis simulation


git-svn-id: http://moon:8086/svn/vhdl/trunk@1083 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-14 20:45:05 +00:00
parent 5c6c1fd1cd
commit 182e68126e
5 changed files with 26 additions and 38 deletions
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lib/CPUs/MIPS/sim/ModelSim SE .lnk
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lib/CPUs/MIPS/sim/modelsim.ini
+1 -1
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@@ -11,7 +11,7 @@ others = $MODEL_TECH/../modelsim.ini
;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release
;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release
unisim = ../../../Common/sim/unisim
unisim = W:/SVN/vhdl/trunk/Common/sim/unisim
[vcom]
; VHDL93 variable selects language version as the default.
; Default is VHDL-2002.
lib/CPUs/MIPS/sim/tb_mips_top_syn.fdo
+4 -14
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@@ -3,15 +3,8 @@
vlib work
# RAMS
vcom -explicit -93 "../../../misc/dpram_2w2r1c_sim.vhd"
vcom -explicit -93 "../../../misc/dpram_2w2r.vhd"
vcom -explicit -93 "../../../misc/dpram_1w2r1c_sim.vhd"
vcom -explicit -93 "../../../misc/dpram_1w1r.vhd"
vcom -explicit -93 "../../../misc/dpram_1w1r1c_sim.vhd"
vcom -explicit -93 "../../../misc/dpram_1w1r2c_sim.vhd"
vcom -explicit -93 "../../../misc/dpram_2w2r2c_sim.vhd"
vcom -explicit -93 "../../../rams/dpram_2w2r2c_ra_sim.vhd"
vcom -explicit -93 "../../../rams/dpram_1w1r2c_ra_sim.vhd"
# FIFOS
vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
@@ -22,11 +15,8 @@ vcom -explicit -93 "../../../FIFO/src/fifo_async_ctrl.vhd"
vcom -explicit -93 "../../../FIFO/src/fifo_async.vhd"
# UART
vcom -explicit -93 "../../../uart/bbfifo_16x8.vhd"
vcom -explicit -93 "../../../uart/kcuart_rx.vhd"
vcom -explicit -93 "../../../uart/kcuart_tx.vhd"
vcom -explicit -93 "../../../uart/uart_rx.vhd"
vcom -explicit -93 "../../../uart/uart_tx.vhd"
vcom -explicit -93 "../../../uart/uart_rx_sim.vhd"
vcom -explicit -93 "../../../uart/uart_tx_sim.vhd"
vcom -explicit -93 "../../../uart/uart_wb.vhd"
# GPIO
lib/CPUs/MIPS/syn/ise101/mips_top.prj
-1
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@@ -1,7 +1,6 @@
vhdl work "../../../../FIFO/src/fifo_ctrl_pkg.vhd"
vhdl work "../../../../FIFO/src/gray_counter.vhd"
vhdl work "../../../../rams/dpram_2w2r2c_ra_xil.vhd"
vhdl work "../../../../rams/dpram_1w1r2c_ro_xil.vhd"
vhdl work "../../../../rams/dpram_1w1r2c_ra_xil.vhd"
vhdl work "../../../../FIFO/src/fifo_sync_ctrl.vhd"
vhdl work "../../../../FIFO/src/fifo_async_ctrl.vhd"
lib/CPUs/MIPS/syn/ise101/mips_top_vhdl.prj
+21 -22
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@@ -1,22 +1,21 @@
vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\gray_counter.vhd"
vhdl work "W:\vhdl\lib\rams\dpram_2w2r2c_ra_xil.vhd"
vhdl work "W:\vhdl\lib\rams\dpram_1w1r2c_ro_xil.vhd"
vhdl work "W:\vhdl\lib\rams\dpram_1w1r2c_ra_xil.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync_ctrl.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\fifo_async_ctrl.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\fifo_async.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_shifter.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_reg.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_muldiv.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_instr.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_icache.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_dcache.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bcu.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_alu.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_pipeline.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_cop.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_biu.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_top.vhd"
vhdl work "W:\SVN\vhdl\trunk\lib\FIFO\src\fifo_ctrl_pkg.vhd"
vhdl work "W:\SVN\vhdl\trunk\lib\FIFO\src\gray_counter.vhd"
vhdl work "W:\SVN\vhdl\trunk\lib\rams\dpram_2w2r2c_ra_xil.vhd"
vhdl work "W:\SVN\vhdl\trunk\lib\rams\dpram_1w1r2c_ra_xil.vhd"
vhdl work "W:\SVN\vhdl\trunk\lib\FIFO\src\fifo_sync_ctrl.vhd"
vhdl work "W:\SVN\vhdl\trunk\lib\FIFO\src\fifo_async_ctrl.vhd"
vhdl work "W:\SVN\vhdl\trunk\lib\CPUs\MIPS\src\core\mips_types.vhd"
vhdl work "W:\SVN\vhdl\trunk\lib\FIFO\src\fifo_sync.vhd"
vhdl work "W:\SVN\vhdl\trunk\lib\FIFO\src\fifo_async.vhd"
vhdl work "W:\SVN\vhdl\trunk\lib\CPUs\MIPS\src\core\mips_shifter.vhd"
vhdl work "W:\SVN\vhdl\trunk\lib\CPUs\MIPS\src\core\mips_reg.vhd"
vhdl work "W:\SVN\vhdl\trunk\lib\CPUs\MIPS\src\core\mips_muldiv.vhd"
vhdl work "W:\SVN\vhdl\trunk\lib\CPUs\MIPS\src\core\mips_instr.vhd"
vhdl work "W:\SVN\vhdl\trunk\lib\CPUs\MIPS\src\core\mips_icache.vhd"
vhdl work "W:\SVN\vhdl\trunk\lib\CPUs\MIPS\src\core\mips_dcache.vhd"
vhdl work "W:\SVN\vhdl\trunk\lib\CPUs\MIPS\src\core\mips_bcu.vhd"
vhdl work "W:\SVN\vhdl\trunk\lib\CPUs\MIPS\src\core\mips_alu.vhd"
vhdl work "W:\SVN\vhdl\trunk\lib\CPUs\MIPS\src\core\mips_pipeline.vhd"
vhdl work "W:\SVN\vhdl\trunk\lib\CPUs\MIPS\src\core\mips_cop.vhd"
vhdl work "W:\SVN\vhdl\trunk\lib\CPUs\MIPS\src\core\mips_biu.vhd"
vhdl work "W:\SVN\vhdl\trunk\lib\CPUs\MIPS\src\core\mips_top.vhd"