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- added dedicated sys_clk_out frequency synthesis

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- SDRAM clocks use sys_clk_out for clock generation
- added cpu_clk_out which is the same as sys_clk_in

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git-svn-id: http://moon:8086/svn/vhdl/trunk@727 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-02-07 19:16:11 +00:00
parent c42c0ba5b8
commit 023b7e42a3
5 changed files with 251 additions and 175 deletions
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projects/mips_sys/src/tb_mips_sys.vhd
+1 -1
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@@ -254,7 +254,7 @@ i_mt46v16m16_1 : entity work.mt46v16m16
dm => std_logic_vector(sys_sdr_dm_q(3 downto 2))
);
sys_sdr_clk_fb <= sys_sdr_clk_p after 2300 ps;
sys_sdr_clk_fb <= sys_sdr_clk_p after 1300 ps;
sys_ssram_clk_fb <= sys_ssram_clk after 0.5 ns;
refresh <= true when falling_edge(sys_sdr_ras_qn) and falling_edge(sys_sdr_cas_qn) and sys_sdr_we_qn='1' else false;