jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

- added dedicated sys_clk_out frequency synthesis

Browse Source 
- SDRAM clocks use sys_clk_out for clock generation
- added cpu_clk_out which is the same as sys_clk_in

Committed on the Free edition of March Hare Software CVSNT Server.
Upgrade to CVS Suite for more features and support:
http://march-hare.com/cvsnt/


git-svn-id: http://moon:8086/svn/vhdl/trunk@727 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-02-07 19:16:11 +00:00
parent c42c0ba5b8
commit 023b7e42a3
5 changed files with 251 additions and 175 deletions
Download Patch File Download Diff File Expand all files Collapse all files
projects/mips_sys/src/mips_sys.vhd
+26 -16
View File
@@ -42,9 +42,10 @@ use work.async_defs.all;
ENTITY mips_sys IS
GENERIC
(
sys_freq_in : integer := 100E6;
sys_freq : integer := 100E6;
ddr_phaseshift : integer := 0;
ddr_frequency_hz : integer := 100E6;
ddr_phaseshift : integer := 0;
tsvga : vga_timespec_t := ts_vga_800_600_60
);
@@ -143,6 +144,7 @@ ARCHITECTURE behavior OF mips_sys IS
debug : out unsigned(1 downto 0);
eb : in STD_LOGIC;
nmi : in STD_LOGIC;
cpu_clk : in STD_LOGIC;
RST_I : in STD_LOGIC;
CLK_I : in STD_LOGIC;
ACK_I : in STD_LOGIC;
@@ -193,6 +195,7 @@ ARCHITECTURE behavior OF mips_sys IS
COMPONENT async_port_wb
GENERIC
(
f_sysclk_hz : natural := 100E6;
addr_width : natural := 32;
data_width : natural := 32;
byte_sel_width : natural := 4;
@@ -320,13 +323,14 @@ ARCHITECTURE behavior OF mips_sys IS
);
END COMPONENT;
signal cpu_clk : std_logic;
signal nmi : std_logic;
signal eb : std_logic;
signal sdram_clk0 : std_logic;
signal sdram_clk270 : std_logic;
signal sdram_clk270var : std_logic;
signal vga_clk : std_logic;
signal dcm_lock : std_logic;
signal vga_ce : std_logic;
signal rst_in : std_logic;
signal int_timer : std_logic;
signal int_uart0 : std_logic;
@@ -473,6 +477,9 @@ ARCHITECTURE behavior OF mips_sys IS
attribute KEEP : string;
attribute KEEP of vga_clk : signal is "TRUE";
attribute KEEP of sdram_clk0 : signal is "TRUE";
attribute KEEP of cpu_clk : signal is "TRUE";
attribute KEEP of CLK_O : signal is "TRUE";
attribute KEEP of RST_O : signal is "TRUE";
BEGIN
@@ -496,8 +503,6 @@ BEGIN
sys_flash_a <= '0' & flash_addr(24 downto 2) & '0';
flash_page_mode_en <= not mem_mapped_io;
RST_O <= not dcm_lock;
sys_flash_ac97_rstn <= ac97_rstn and flash_rstn;
sys_uart1_tx <= uart1_tx;
sys_uart2_tx <= uart1_tx;
@@ -505,6 +510,7 @@ BEGIN
sys_uart3_tx <= sys_uart3_rx;
sys_vga_clk <= vga_clk;
vga_ce <= not RST_O;
---------------------------------------------------------------
-- Arbiter
@@ -671,6 +677,7 @@ inst_mips_top: mips_top
debug => debug,
eb => eb,
nmi => nmi,
cpu_clk => cpu_clk,
RST_I => RST_O,
CLK_I => CLK_O,
ACK_I => ACK_I_cpu,
@@ -741,6 +748,7 @@ inst_gpio_wb : gpio_wb
inst_flash_port : async_port_wb
GENERIC MAP
(
f_sysclk_hz => sys_freq,
addr_width => 25,
data_width => 32,
byte_sel_width => 1,
@@ -773,6 +781,7 @@ inst_flash_port : async_port_wb
inst_usb_port : async_port_wb
GENERIC MAP
(
f_sysclk_hz => sys_freq,
addr_width => 4,
data_width => 16,
byte_sel_width => 1,
@@ -846,25 +855,26 @@ inst_uart_wb_1 : uart_wb
inst_clockgen : entity work.clockgen
GENERIC MAP
(
clk_in_freq_hz => sys_freq,
clk_in_freq_hz => sys_freq_in,
sys_clk_out_freq_hz => sys_freq,
vga_clk_out_freq_hz => tsvga.f_pxl_clk,
sdr_clk0_out_phaseshift => 0,
sdr_clk1_out_phaseshift => 0
sdr0_clk_out_phaseshift => 0,
sdr1_clk_out_phaseshift => 0
)
PORT MAP
(
-- Clocks and Reset
rst => rst_in, -- external async reset, low active
rst_in => rst_in, -- external async reset, low active
clk_in => sys_clk_in, -- system clock (e.g. 100MHz), from board
sys_rst_out => RST_O,
sys_clk_out => CLK_O,
vga_clk_out => vga_clk,
sdr_clk0_fb_in => sys_sdr_clk_fb, -- feedback clock
sdr_clk0_0_out => sdram_clk0, -- System clock #0, dcm#0 output 0°
sdr_clk0_270_out => sdram_clk270, -- System clock #0, dcm#0 output 270°
sdr_clk1_0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
sdr_clk1_270_out => sdram_clk270var, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
locked_out => dcm_lock, -- DCM locked status
error_out => open
cpu_clk_out => cpu_clk,
sdr0_clk_fb_in => sys_sdr_clk_fb, -- feedback clock
sdr0_clk0_out => sdram_clk0, -- System clock #0, dcm#0 output 0°
sdr0_clk270_out => sdram_clk270, -- System clock #0, dcm#0 output 270°
sdr1_clk0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
sdr1_clk270_out => sdram_clk270var -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
);
inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb
@@ -952,7 +962,7 @@ inst_vga_frontend : vga_frontend64
-- VGA signals
vga_clk_in => vga_clk,
vga_clk_ce => dcm_lock,
vga_clk_ce => vga_ce,
vga_red => sys_vga_red,
vga_green => sys_vga_green,
vga_blue => sys_vga_blue,